1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 29 struct amd_vce_state { 30 /* vce clocks */ 31 u32 evclk; 32 u32 ecclk; 33 /* gpu clocks */ 34 u32 sclk; 35 u32 mclk; 36 u8 clk_idx; 37 u8 pstate; 38 }; 39 40 41 enum amd_dpm_forced_level { 42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 44 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 51 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 52 }; 53 54 enum amd_pm_state_type { 55 /* not used for dpm */ 56 POWER_STATE_TYPE_DEFAULT, 57 POWER_STATE_TYPE_POWERSAVE, 58 /* user selectable states */ 59 POWER_STATE_TYPE_BATTERY, 60 POWER_STATE_TYPE_BALANCED, 61 POWER_STATE_TYPE_PERFORMANCE, 62 /* internal states */ 63 POWER_STATE_TYPE_INTERNAL_UVD, 64 POWER_STATE_TYPE_INTERNAL_UVD_SD, 65 POWER_STATE_TYPE_INTERNAL_UVD_HD, 66 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 67 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 68 POWER_STATE_TYPE_INTERNAL_BOOT, 69 POWER_STATE_TYPE_INTERNAL_THERMAL, 70 POWER_STATE_TYPE_INTERNAL_ACPI, 71 POWER_STATE_TYPE_INTERNAL_ULV, 72 POWER_STATE_TYPE_INTERNAL_3DPERF, 73 }; 74 75 #define AMD_MAX_VCE_LEVELS 6 76 77 enum amd_vce_level { 78 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 79 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 80 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 81 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 82 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 83 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 84 }; 85 86 enum amd_fan_ctrl_mode { 87 AMD_FAN_CTRL_NONE = 0, 88 AMD_FAN_CTRL_MANUAL = 1, 89 AMD_FAN_CTRL_AUTO = 2, 90 }; 91 92 enum pp_clock_type { 93 PP_SCLK, 94 PP_MCLK, 95 PP_PCIE, 96 PP_SOCCLK, 97 PP_FCLK, 98 PP_DCEFCLK, 99 PP_VCLK, 100 PP_DCLK, 101 OD_SCLK, 102 OD_MCLK, 103 OD_VDDC_CURVE, 104 OD_RANGE, 105 OD_VDDGFX_OFFSET, 106 OD_CCLK, 107 }; 108 109 enum amd_pp_sensors { 110 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 111 AMDGPU_PP_SENSOR_CPU_CLK, 112 AMDGPU_PP_SENSOR_VDDNB, 113 AMDGPU_PP_SENSOR_VDDGFX, 114 AMDGPU_PP_SENSOR_UVD_VCLK, 115 AMDGPU_PP_SENSOR_UVD_DCLK, 116 AMDGPU_PP_SENSOR_VCE_ECCLK, 117 AMDGPU_PP_SENSOR_GPU_LOAD, 118 AMDGPU_PP_SENSOR_MEM_LOAD, 119 AMDGPU_PP_SENSOR_GFX_MCLK, 120 AMDGPU_PP_SENSOR_GPU_TEMP, 121 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 122 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 123 AMDGPU_PP_SENSOR_MEM_TEMP, 124 AMDGPU_PP_SENSOR_VCE_POWER, 125 AMDGPU_PP_SENSOR_UVD_POWER, 126 AMDGPU_PP_SENSOR_GPU_POWER, 127 AMDGPU_PP_SENSOR_SS_APU_SHARE, 128 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 129 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 130 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 131 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 132 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 133 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 134 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 135 }; 136 137 enum amd_pp_task { 138 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 139 AMD_PP_TASK_ENABLE_USER_STATE, 140 AMD_PP_TASK_READJUST_POWER_STATE, 141 AMD_PP_TASK_COMPLETE_INIT, 142 AMD_PP_TASK_MAX 143 }; 144 145 enum PP_SMC_POWER_PROFILE { 146 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 147 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 148 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 149 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 150 PP_SMC_POWER_PROFILE_VR = 0x4, 151 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 152 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 153 PP_SMC_POWER_PROFILE_COUNT, 154 }; 155 156 enum { 157 PP_GROUP_UNKNOWN = 0, 158 PP_GROUP_GFX = 1, 159 PP_GROUP_SYS, 160 PP_GROUP_MAX 161 }; 162 163 enum PP_OD_DPM_TABLE_COMMAND { 164 PP_OD_EDIT_SCLK_VDDC_TABLE, 165 PP_OD_EDIT_MCLK_VDDC_TABLE, 166 PP_OD_EDIT_CCLK_VDDC_TABLE, 167 PP_OD_EDIT_VDDC_CURVE, 168 PP_OD_RESTORE_DEFAULT_TABLE, 169 PP_OD_COMMIT_DPM_TABLE, 170 PP_OD_EDIT_VDDGFX_OFFSET 171 }; 172 173 struct pp_states_info { 174 uint32_t nums; 175 uint32_t states[16]; 176 }; 177 178 enum PP_HWMON_TEMP { 179 PP_TEMP_EDGE = 0, 180 PP_TEMP_JUNCTION, 181 PP_TEMP_MEM, 182 PP_TEMP_MAX 183 }; 184 185 enum pp_mp1_state { 186 PP_MP1_STATE_NONE, 187 PP_MP1_STATE_SHUTDOWN, 188 PP_MP1_STATE_UNLOAD, 189 PP_MP1_STATE_RESET, 190 }; 191 192 enum pp_df_cstate { 193 DF_CSTATE_DISALLOW = 0, 194 DF_CSTATE_ALLOW, 195 }; 196 197 #define PP_GROUP_MASK 0xF0000000 198 #define PP_GROUP_SHIFT 28 199 200 #define PP_BLOCK_MASK 0x0FFFFF00 201 #define PP_BLOCK_SHIFT 8 202 203 #define PP_BLOCK_GFX_CG 0x01 204 #define PP_BLOCK_GFX_MG 0x02 205 #define PP_BLOCK_GFX_3D 0x04 206 #define PP_BLOCK_GFX_RLC 0x08 207 #define PP_BLOCK_GFX_CP 0x10 208 #define PP_BLOCK_SYS_BIF 0x01 209 #define PP_BLOCK_SYS_MC 0x02 210 #define PP_BLOCK_SYS_ROM 0x04 211 #define PP_BLOCK_SYS_DRM 0x08 212 #define PP_BLOCK_SYS_HDP 0x10 213 #define PP_BLOCK_SYS_SDMA 0x20 214 215 #define PP_STATE_MASK 0x0000000F 216 #define PP_STATE_SHIFT 0 217 #define PP_STATE_SUPPORT_MASK 0x000000F0 218 #define PP_STATE_SUPPORT_SHIFT 0 219 220 #define PP_STATE_CG 0x01 221 #define PP_STATE_LS 0x02 222 #define PP_STATE_DS 0x04 223 #define PP_STATE_SD 0x08 224 #define PP_STATE_SUPPORT_CG 0x10 225 #define PP_STATE_SUPPORT_LS 0x20 226 #define PP_STATE_SUPPORT_DS 0x40 227 #define PP_STATE_SUPPORT_SD 0x80 228 229 #define PP_CG_MSG_ID(group, block, support, state) \ 230 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 231 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 232 233 #define XGMI_MODE_PSTATE_D3 0 234 #define XGMI_MODE_PSTATE_D0 1 235 236 #define NUM_HBM_INSTANCES 4 237 238 struct seq_file; 239 enum amd_pp_clock_type; 240 struct amd_pp_simple_clock_info; 241 struct amd_pp_display_configuration; 242 struct amd_pp_clock_info; 243 struct pp_display_clock_request; 244 struct pp_clock_levels_with_voltage; 245 struct pp_clock_levels_with_latency; 246 struct amd_pp_clocks; 247 struct pp_smu_wm_range_sets; 248 struct pp_smu_nv_clock_table; 249 struct dpm_clocks; 250 251 struct amd_pm_funcs { 252 /* export for dpm on ci and si */ 253 int (*pre_set_power_state)(void *handle); 254 int (*set_power_state)(void *handle); 255 void (*post_set_power_state)(void *handle); 256 void (*display_configuration_changed)(void *handle); 257 void (*print_power_state)(void *handle, void *ps); 258 bool (*vblank_too_short)(void *handle); 259 void (*enable_bapm)(void *handle, bool enable); 260 int (*check_state_equal)(void *handle, 261 void *cps, 262 void *rps, 263 bool *equal); 264 /* export for sysfs */ 265 void (*set_fan_control_mode)(void *handle, u32 mode); 266 u32 (*get_fan_control_mode)(void *handle); 267 int (*set_fan_speed_percent)(void *handle, u32 speed); 268 int (*get_fan_speed_percent)(void *handle, u32 *speed); 269 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 270 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 271 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 272 int (*get_sclk_od)(void *handle); 273 int (*set_sclk_od)(void *handle, uint32_t value); 274 int (*get_mclk_od)(void *handle); 275 int (*set_mclk_od)(void *handle, uint32_t value); 276 int (*read_sensor)(void *handle, int idx, void *value, int *size); 277 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 278 enum amd_pm_state_type (*get_current_power_state)(void *handle); 279 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 280 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 281 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 282 int (*get_pp_table)(void *handle, char **table); 283 int (*set_pp_table)(void *handle, const char *buf, size_t size); 284 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 285 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 286 /* export to amdgpu */ 287 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 288 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 289 enum amd_pm_state_type *user_state); 290 int (*load_firmware)(void *handle); 291 int (*wait_for_fw_loading_complete)(void *handle); 292 int (*set_powergating_by_smu)(void *handle, 293 uint32_t block_type, bool gate); 294 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 295 int (*set_power_limit)(void *handle, uint32_t n); 296 int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit, 297 bool default_limit); 298 int (*get_power_profile_mode)(void *handle, char *buf); 299 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 300 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 301 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 302 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 303 int (*smu_i2c_bus_access)(void *handle, bool acquire); 304 int (*gfx_state_change_set)(void *handle, uint32_t state); 305 /* export to DC */ 306 u32 (*get_sclk)(void *handle, bool low); 307 u32 (*get_mclk)(void *handle, bool low); 308 int (*display_configuration_change)(void *handle, 309 const struct amd_pp_display_configuration *input); 310 int (*get_display_power_level)(void *handle, 311 struct amd_pp_simple_clock_info *output); 312 int (*get_current_clocks)(void *handle, 313 struct amd_pp_clock_info *clocks); 314 int (*get_clock_by_type)(void *handle, 315 enum amd_pp_clock_type type, 316 struct amd_pp_clocks *clocks); 317 int (*get_clock_by_type_with_latency)(void *handle, 318 enum amd_pp_clock_type type, 319 struct pp_clock_levels_with_latency *clocks); 320 int (*get_clock_by_type_with_voltage)(void *handle, 321 enum amd_pp_clock_type type, 322 struct pp_clock_levels_with_voltage *clocks); 323 int (*set_watermarks_for_clocks_ranges)(void *handle, 324 void *clock_ranges); 325 int (*display_clock_voltage_request)(void *handle, 326 struct pp_display_clock_request *clock); 327 int (*get_display_mode_validation_clocks)(void *handle, 328 struct amd_pp_simple_clock_info *clocks); 329 int (*notify_smu_enable_pwe)(void *handle); 330 int (*enable_mgpu_fan_boost)(void *handle); 331 int (*set_active_display_count)(void *handle, uint32_t count); 332 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 333 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 334 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 335 int (*get_asic_baco_capability)(void *handle, bool *cap); 336 int (*get_asic_baco_state)(void *handle, int *state); 337 int (*set_asic_baco_state)(void *handle, int state); 338 int (*get_ppfeature_status)(void *handle, char *buf); 339 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 340 int (*asic_reset_mode_2)(void *handle); 341 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 342 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 343 ssize_t (*get_gpu_metrics)(void *handle, void **table); 344 int (*set_watermarks_for_clock_ranges)(void *handle, 345 struct pp_smu_wm_range_sets *ranges); 346 int (*display_disable_memory_clock_switch)(void *handle, 347 bool disable_memory_clock_switch); 348 int (*get_max_sustainable_clocks_by_dc)(void *handle, 349 struct pp_smu_nv_clock_table *max_clocks); 350 int (*get_uclk_dpm_states)(void *handle, 351 unsigned int *clock_values_in_khz, 352 unsigned int *num_states); 353 int (*get_dpm_clock_table)(void *handle, 354 struct dpm_clocks *clock_table); 355 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 356 }; 357 358 struct metrics_table_header { 359 uint16_t structure_size; 360 uint8_t format_revision; 361 uint8_t content_revision; 362 }; 363 364 /* 365 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 366 * Use gpu_metrics_v1_1 or later instead. 367 */ 368 struct gpu_metrics_v1_0 { 369 struct metrics_table_header common_header; 370 371 /* Driver attached timestamp (in ns) */ 372 uint64_t system_clock_counter; 373 374 /* Temperature */ 375 uint16_t temperature_edge; 376 uint16_t temperature_hotspot; 377 uint16_t temperature_mem; 378 uint16_t temperature_vrgfx; 379 uint16_t temperature_vrsoc; 380 uint16_t temperature_vrmem; 381 382 /* Utilization */ 383 uint16_t average_gfx_activity; 384 uint16_t average_umc_activity; // memory controller 385 uint16_t average_mm_activity; // UVD or VCN 386 387 /* Power/Energy */ 388 uint16_t average_socket_power; 389 uint32_t energy_accumulator; 390 391 /* Average clocks */ 392 uint16_t average_gfxclk_frequency; 393 uint16_t average_socclk_frequency; 394 uint16_t average_uclk_frequency; 395 uint16_t average_vclk0_frequency; 396 uint16_t average_dclk0_frequency; 397 uint16_t average_vclk1_frequency; 398 uint16_t average_dclk1_frequency; 399 400 /* Current clocks */ 401 uint16_t current_gfxclk; 402 uint16_t current_socclk; 403 uint16_t current_uclk; 404 uint16_t current_vclk0; 405 uint16_t current_dclk0; 406 uint16_t current_vclk1; 407 uint16_t current_dclk1; 408 409 /* Throttle status */ 410 uint32_t throttle_status; 411 412 /* Fans */ 413 uint16_t current_fan_speed; 414 415 /* Link width/speed */ 416 uint8_t pcie_link_width; 417 uint8_t pcie_link_speed; // in 0.1 GT/s 418 }; 419 420 struct gpu_metrics_v1_1 { 421 struct metrics_table_header common_header; 422 423 /* Temperature */ 424 uint16_t temperature_edge; 425 uint16_t temperature_hotspot; 426 uint16_t temperature_mem; 427 uint16_t temperature_vrgfx; 428 uint16_t temperature_vrsoc; 429 uint16_t temperature_vrmem; 430 431 /* Utilization */ 432 uint16_t average_gfx_activity; 433 uint16_t average_umc_activity; // memory controller 434 uint16_t average_mm_activity; // UVD or VCN 435 436 /* Power/Energy */ 437 uint16_t average_socket_power; 438 uint64_t energy_accumulator; 439 440 /* Driver attached timestamp (in ns) */ 441 uint64_t system_clock_counter; 442 443 /* Average clocks */ 444 uint16_t average_gfxclk_frequency; 445 uint16_t average_socclk_frequency; 446 uint16_t average_uclk_frequency; 447 uint16_t average_vclk0_frequency; 448 uint16_t average_dclk0_frequency; 449 uint16_t average_vclk1_frequency; 450 uint16_t average_dclk1_frequency; 451 452 /* Current clocks */ 453 uint16_t current_gfxclk; 454 uint16_t current_socclk; 455 uint16_t current_uclk; 456 uint16_t current_vclk0; 457 uint16_t current_dclk0; 458 uint16_t current_vclk1; 459 uint16_t current_dclk1; 460 461 /* Throttle status */ 462 uint32_t throttle_status; 463 464 /* Fans */ 465 uint16_t current_fan_speed; 466 467 /* Link width/speed */ 468 uint16_t pcie_link_width; 469 uint16_t pcie_link_speed; // in 0.1 GT/s 470 471 uint16_t padding; 472 473 uint32_t gfx_activity_acc; 474 uint32_t mem_activity_acc; 475 476 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 477 }; 478 479 struct gpu_metrics_v1_2 { 480 struct metrics_table_header common_header; 481 482 /* Temperature */ 483 uint16_t temperature_edge; 484 uint16_t temperature_hotspot; 485 uint16_t temperature_mem; 486 uint16_t temperature_vrgfx; 487 uint16_t temperature_vrsoc; 488 uint16_t temperature_vrmem; 489 490 /* Utilization */ 491 uint16_t average_gfx_activity; 492 uint16_t average_umc_activity; // memory controller 493 uint16_t average_mm_activity; // UVD or VCN 494 495 /* Power/Energy */ 496 uint16_t average_socket_power; 497 uint64_t energy_accumulator; 498 499 /* Driver attached timestamp (in ns) */ 500 uint64_t system_clock_counter; 501 502 /* Average clocks */ 503 uint16_t average_gfxclk_frequency; 504 uint16_t average_socclk_frequency; 505 uint16_t average_uclk_frequency; 506 uint16_t average_vclk0_frequency; 507 uint16_t average_dclk0_frequency; 508 uint16_t average_vclk1_frequency; 509 uint16_t average_dclk1_frequency; 510 511 /* Current clocks */ 512 uint16_t current_gfxclk; 513 uint16_t current_socclk; 514 uint16_t current_uclk; 515 uint16_t current_vclk0; 516 uint16_t current_dclk0; 517 uint16_t current_vclk1; 518 uint16_t current_dclk1; 519 520 /* Throttle status */ 521 uint32_t throttle_status; 522 523 /* Fans */ 524 uint16_t current_fan_speed; 525 526 /* Link width/speed */ 527 uint16_t pcie_link_width; 528 uint16_t pcie_link_speed; // in 0.1 GT/s 529 530 uint16_t padding; 531 532 uint32_t gfx_activity_acc; 533 uint32_t mem_activity_acc; 534 535 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 536 537 /* PMFW attached timestamp (10ns resolution) */ 538 uint64_t firmware_timestamp; 539 }; 540 541 struct gpu_metrics_v1_3 { 542 struct metrics_table_header common_header; 543 544 /* Temperature */ 545 uint16_t temperature_edge; 546 uint16_t temperature_hotspot; 547 uint16_t temperature_mem; 548 uint16_t temperature_vrgfx; 549 uint16_t temperature_vrsoc; 550 uint16_t temperature_vrmem; 551 552 /* Utilization */ 553 uint16_t average_gfx_activity; 554 uint16_t average_umc_activity; // memory controller 555 uint16_t average_mm_activity; // UVD or VCN 556 557 /* Power/Energy */ 558 uint16_t average_socket_power; 559 uint64_t energy_accumulator; 560 561 /* Driver attached timestamp (in ns) */ 562 uint64_t system_clock_counter; 563 564 /* Average clocks */ 565 uint16_t average_gfxclk_frequency; 566 uint16_t average_socclk_frequency; 567 uint16_t average_uclk_frequency; 568 uint16_t average_vclk0_frequency; 569 uint16_t average_dclk0_frequency; 570 uint16_t average_vclk1_frequency; 571 uint16_t average_dclk1_frequency; 572 573 /* Current clocks */ 574 uint16_t current_gfxclk; 575 uint16_t current_socclk; 576 uint16_t current_uclk; 577 uint16_t current_vclk0; 578 uint16_t current_dclk0; 579 uint16_t current_vclk1; 580 uint16_t current_dclk1; 581 582 /* Throttle status */ 583 uint32_t throttle_status; 584 585 /* Fans */ 586 uint16_t current_fan_speed; 587 588 /* Link width/speed */ 589 uint16_t pcie_link_width; 590 uint16_t pcie_link_speed; // in 0.1 GT/s 591 592 uint16_t padding; 593 594 uint32_t gfx_activity_acc; 595 uint32_t mem_activity_acc; 596 597 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 598 599 /* PMFW attached timestamp (10ns resolution) */ 600 uint64_t firmware_timestamp; 601 602 /* Voltage (mV) */ 603 uint16_t voltage_soc; 604 uint16_t voltage_gfx; 605 uint16_t voltage_mem; 606 607 uint16_t padding1; 608 }; 609 610 /* 611 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 612 * Use gpu_metrics_v2_1 or later instead. 613 */ 614 struct gpu_metrics_v2_0 { 615 struct metrics_table_header common_header; 616 617 /* Driver attached timestamp (in ns) */ 618 uint64_t system_clock_counter; 619 620 /* Temperature */ 621 uint16_t temperature_gfx; // gfx temperature on APUs 622 uint16_t temperature_soc; // soc temperature on APUs 623 uint16_t temperature_core[8]; // CPU core temperature on APUs 624 uint16_t temperature_l3[2]; 625 626 /* Utilization */ 627 uint16_t average_gfx_activity; 628 uint16_t average_mm_activity; // UVD or VCN 629 630 /* Power/Energy */ 631 uint16_t average_socket_power; // dGPU + APU power on A + A platform 632 uint16_t average_cpu_power; 633 uint16_t average_soc_power; 634 uint16_t average_gfx_power; 635 uint16_t average_core_power[8]; // CPU core power on APUs 636 637 /* Average clocks */ 638 uint16_t average_gfxclk_frequency; 639 uint16_t average_socclk_frequency; 640 uint16_t average_uclk_frequency; 641 uint16_t average_fclk_frequency; 642 uint16_t average_vclk_frequency; 643 uint16_t average_dclk_frequency; 644 645 /* Current clocks */ 646 uint16_t current_gfxclk; 647 uint16_t current_socclk; 648 uint16_t current_uclk; 649 uint16_t current_fclk; 650 uint16_t current_vclk; 651 uint16_t current_dclk; 652 uint16_t current_coreclk[8]; // CPU core clocks 653 uint16_t current_l3clk[2]; 654 655 /* Throttle status */ 656 uint32_t throttle_status; 657 658 /* Fans */ 659 uint16_t fan_pwm; 660 661 uint16_t padding; 662 }; 663 664 struct gpu_metrics_v2_1 { 665 struct metrics_table_header common_header; 666 667 /* Temperature */ 668 uint16_t temperature_gfx; // gfx temperature on APUs 669 uint16_t temperature_soc; // soc temperature on APUs 670 uint16_t temperature_core[8]; // CPU core temperature on APUs 671 uint16_t temperature_l3[2]; 672 673 /* Utilization */ 674 uint16_t average_gfx_activity; 675 uint16_t average_mm_activity; // UVD or VCN 676 677 /* Driver attached timestamp (in ns) */ 678 uint64_t system_clock_counter; 679 680 /* Power/Energy */ 681 uint16_t average_socket_power; // dGPU + APU power on A + A platform 682 uint16_t average_cpu_power; 683 uint16_t average_soc_power; 684 uint16_t average_gfx_power; 685 uint16_t average_core_power[8]; // CPU core power on APUs 686 687 /* Average clocks */ 688 uint16_t average_gfxclk_frequency; 689 uint16_t average_socclk_frequency; 690 uint16_t average_uclk_frequency; 691 uint16_t average_fclk_frequency; 692 uint16_t average_vclk_frequency; 693 uint16_t average_dclk_frequency; 694 695 /* Current clocks */ 696 uint16_t current_gfxclk; 697 uint16_t current_socclk; 698 uint16_t current_uclk; 699 uint16_t current_fclk; 700 uint16_t current_vclk; 701 uint16_t current_dclk; 702 uint16_t current_coreclk[8]; // CPU core clocks 703 uint16_t current_l3clk[2]; 704 705 /* Throttle status */ 706 uint32_t throttle_status; 707 708 /* Fans */ 709 uint16_t fan_pwm; 710 711 uint16_t padding[3]; 712 }; 713 714 #endif 715