1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 OD_FAN_ZERO_RPM_ENABLE, 123 OD_FAN_ZERO_RPM_STOP_TEMP, 124 }; 125 126 enum amd_pp_sensors { 127 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 128 AMDGPU_PP_SENSOR_CPU_CLK, 129 AMDGPU_PP_SENSOR_VDDNB, 130 AMDGPU_PP_SENSOR_VDDGFX, 131 AMDGPU_PP_SENSOR_UVD_VCLK, 132 AMDGPU_PP_SENSOR_UVD_DCLK, 133 AMDGPU_PP_SENSOR_VCE_ECCLK, 134 AMDGPU_PP_SENSOR_GPU_LOAD, 135 AMDGPU_PP_SENSOR_MEM_LOAD, 136 AMDGPU_PP_SENSOR_GFX_MCLK, 137 AMDGPU_PP_SENSOR_GPU_TEMP, 138 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 139 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 140 AMDGPU_PP_SENSOR_MEM_TEMP, 141 AMDGPU_PP_SENSOR_VCE_POWER, 142 AMDGPU_PP_SENSOR_UVD_POWER, 143 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 144 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 145 AMDGPU_PP_SENSOR_SS_APU_SHARE, 146 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 147 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 148 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 149 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 150 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 151 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 152 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 153 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 154 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 155 AMDGPU_PP_SENSOR_VCN_LOAD, 156 }; 157 158 enum amd_pp_task { 159 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 160 AMD_PP_TASK_ENABLE_USER_STATE, 161 AMD_PP_TASK_READJUST_POWER_STATE, 162 AMD_PP_TASK_COMPLETE_INIT, 163 AMD_PP_TASK_MAX 164 }; 165 166 enum PP_SMC_POWER_PROFILE { 167 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 168 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 169 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 170 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 171 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 172 PP_SMC_POWER_PROFILE_VR = 0x4, 173 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 174 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 175 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 176 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 177 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 178 PP_SMC_POWER_PROFILE_COUNT, 179 }; 180 181 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 182 183 184 185 enum { 186 PP_GROUP_UNKNOWN = 0, 187 PP_GROUP_GFX = 1, 188 PP_GROUP_SYS, 189 PP_GROUP_MAX 190 }; 191 192 enum PP_OD_DPM_TABLE_COMMAND { 193 PP_OD_EDIT_SCLK_VDDC_TABLE, 194 PP_OD_EDIT_MCLK_VDDC_TABLE, 195 PP_OD_EDIT_CCLK_VDDC_TABLE, 196 PP_OD_EDIT_VDDC_CURVE, 197 PP_OD_RESTORE_DEFAULT_TABLE, 198 PP_OD_COMMIT_DPM_TABLE, 199 PP_OD_EDIT_VDDGFX_OFFSET, 200 PP_OD_EDIT_FAN_CURVE, 201 PP_OD_EDIT_ACOUSTIC_LIMIT, 202 PP_OD_EDIT_ACOUSTIC_TARGET, 203 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 204 PP_OD_EDIT_FAN_MINIMUM_PWM, 205 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 206 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 207 }; 208 209 struct pp_states_info { 210 uint32_t nums; 211 uint32_t states[16]; 212 }; 213 214 enum PP_HWMON_TEMP { 215 PP_TEMP_EDGE = 0, 216 PP_TEMP_JUNCTION, 217 PP_TEMP_MEM, 218 PP_TEMP_MAX 219 }; 220 221 enum pp_mp1_state { 222 PP_MP1_STATE_NONE, 223 PP_MP1_STATE_SHUTDOWN, 224 PP_MP1_STATE_UNLOAD, 225 PP_MP1_STATE_RESET, 226 PP_MP1_STATE_FLR, 227 }; 228 229 enum pp_df_cstate { 230 DF_CSTATE_DISALLOW = 0, 231 DF_CSTATE_ALLOW, 232 }; 233 234 /** 235 * DOC: amdgpu_pp_power 236 * 237 * APU power is managed to system-level requirements through the PPT 238 * (package power tracking) feature. PPT is intended to limit power to the 239 * requirements of the power source and could be dynamically updated to 240 * maximize APU performance within the system power budget. 241 * 242 * Two types of power measurement can be requested, where supported, with 243 * :c:type:`enum pp_power_type <pp_power_type>`. 244 */ 245 246 /** 247 * enum pp_power_limit_level - Used to query the power limits 248 * 249 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 250 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 251 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 252 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 253 */ 254 enum pp_power_limit_level { 255 PP_PWR_LIMIT_MIN = -1, 256 PP_PWR_LIMIT_CURRENT, 257 PP_PWR_LIMIT_DEFAULT, 258 PP_PWR_LIMIT_MAX, 259 }; 260 261 /** 262 * enum pp_power_type - Used to specify the type of the requested power 263 * 264 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 265 * moving average of APU power (default ~5000 ms). 266 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 267 * where supported. 268 */ 269 enum pp_power_type { 270 PP_PWR_TYPE_SUSTAINED, 271 PP_PWR_TYPE_FAST, 272 }; 273 274 enum pp_xgmi_plpd_mode { 275 XGMI_PLPD_NONE = -1, 276 XGMI_PLPD_DISALLOW, 277 XGMI_PLPD_DEFAULT, 278 XGMI_PLPD_OPTIMIZED, 279 XGMI_PLPD_COUNT, 280 }; 281 282 enum pp_pm_policy { 283 PP_PM_POLICY_NONE = -1, 284 PP_PM_POLICY_SOC_PSTATE = 0, 285 PP_PM_POLICY_XGMI_PLPD, 286 PP_PM_POLICY_NUM, 287 }; 288 289 enum pp_policy_soc_pstate { 290 SOC_PSTATE_DEFAULT = 0, 291 SOC_PSTATE_0, 292 SOC_PSTATE_1, 293 SOC_PSTATE_2, 294 SOC_PSTAT_COUNT, 295 }; 296 297 #define PP_POLICY_MAX_LEVELS 5 298 299 #define PP_GROUP_MASK 0xF0000000 300 #define PP_GROUP_SHIFT 28 301 302 #define PP_BLOCK_MASK 0x0FFFFF00 303 #define PP_BLOCK_SHIFT 8 304 305 #define PP_BLOCK_GFX_CG 0x01 306 #define PP_BLOCK_GFX_MG 0x02 307 #define PP_BLOCK_GFX_3D 0x04 308 #define PP_BLOCK_GFX_RLC 0x08 309 #define PP_BLOCK_GFX_CP 0x10 310 #define PP_BLOCK_SYS_BIF 0x01 311 #define PP_BLOCK_SYS_MC 0x02 312 #define PP_BLOCK_SYS_ROM 0x04 313 #define PP_BLOCK_SYS_DRM 0x08 314 #define PP_BLOCK_SYS_HDP 0x10 315 #define PP_BLOCK_SYS_SDMA 0x20 316 317 #define PP_STATE_MASK 0x0000000F 318 #define PP_STATE_SHIFT 0 319 #define PP_STATE_SUPPORT_MASK 0x000000F0 320 #define PP_STATE_SUPPORT_SHIFT 0 321 322 #define PP_STATE_CG 0x01 323 #define PP_STATE_LS 0x02 324 #define PP_STATE_DS 0x04 325 #define PP_STATE_SD 0x08 326 #define PP_STATE_SUPPORT_CG 0x10 327 #define PP_STATE_SUPPORT_LS 0x20 328 #define PP_STATE_SUPPORT_DS 0x40 329 #define PP_STATE_SUPPORT_SD 0x80 330 331 #define PP_CG_MSG_ID(group, block, support, state) \ 332 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 333 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 334 335 #define XGMI_MODE_PSTATE_D3 0 336 #define XGMI_MODE_PSTATE_D0 1 337 338 #define NUM_HBM_INSTANCES 4 339 #define NUM_XGMI_LINKS 8 340 #define MAX_GFX_CLKS 8 341 #define MAX_CLKS 4 342 #define NUM_VCN 4 343 #define NUM_JPEG_ENG 32 344 #define NUM_JPEG_ENG_V1 40 345 #define MAX_XCC 8 346 #define NUM_XCP 8 347 struct seq_file; 348 enum amd_pp_clock_type; 349 struct amd_pp_simple_clock_info; 350 struct amd_pp_display_configuration; 351 struct amd_pp_clock_info; 352 struct pp_display_clock_request; 353 struct pp_clock_levels_with_voltage; 354 struct pp_clock_levels_with_latency; 355 struct amd_pp_clocks; 356 struct pp_smu_wm_range_sets; 357 struct pp_smu_nv_clock_table; 358 struct dpm_clocks; 359 360 struct amdgpu_xcp_metrics { 361 /* Utilization Instantaneous (%) */ 362 uint32_t gfx_busy_inst[MAX_XCC]; 363 uint16_t jpeg_busy[NUM_JPEG_ENG]; 364 uint16_t vcn_busy[NUM_VCN]; 365 /* Utilization Accumulated (%) */ 366 uint64_t gfx_busy_acc[MAX_XCC]; 367 }; 368 369 struct amdgpu_xcp_metrics_v1_1 { 370 /* Utilization Instantaneous (%) */ 371 uint32_t gfx_busy_inst[MAX_XCC]; 372 uint16_t jpeg_busy[NUM_JPEG_ENG]; 373 uint16_t vcn_busy[NUM_VCN]; 374 /* Utilization Accumulated (%) */ 375 uint64_t gfx_busy_acc[MAX_XCC]; 376 /* Total App Clock Counter Accumulated */ 377 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 378 }; 379 380 struct amdgpu_xcp_metrics_v1_2 { 381 /* Utilization Instantaneous (%) */ 382 uint32_t gfx_busy_inst[MAX_XCC]; 383 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 384 uint16_t vcn_busy[NUM_VCN]; 385 /* Utilization Accumulated (%) */ 386 uint64_t gfx_busy_acc[MAX_XCC]; 387 /* Total App Clock Counter Accumulated */ 388 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 389 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 390 uint64_t gfx_low_utilization_acc[MAX_XCC]; 391 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 392 }; 393 394 struct amd_pm_funcs { 395 /* export for dpm on ci and si */ 396 int (*pre_set_power_state)(void *handle); 397 int (*set_power_state)(void *handle); 398 void (*post_set_power_state)(void *handle); 399 void (*display_configuration_changed)(void *handle); 400 void (*print_power_state)(void *handle, void *ps); 401 bool (*vblank_too_short)(void *handle); 402 void (*enable_bapm)(void *handle, bool enable); 403 int (*check_state_equal)(void *handle, 404 void *cps, 405 void *rps, 406 bool *equal); 407 /* export for sysfs */ 408 int (*set_fan_control_mode)(void *handle, u32 mode); 409 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 410 int (*set_fan_speed_pwm)(void *handle, u32 speed); 411 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 412 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 413 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 414 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 415 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 416 int (*get_sclk_od)(void *handle); 417 int (*set_sclk_od)(void *handle, uint32_t value); 418 int (*get_mclk_od)(void *handle); 419 int (*set_mclk_od)(void *handle, uint32_t value); 420 int (*read_sensor)(void *handle, int idx, void *value, int *size); 421 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 422 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 423 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 424 enum amd_pm_state_type (*get_current_power_state)(void *handle); 425 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 426 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 427 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 428 int (*get_pp_table)(void *handle, char **table); 429 int (*set_pp_table)(void *handle, const char *buf, size_t size); 430 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 431 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 432 /* export to amdgpu */ 433 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 434 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 435 enum amd_pm_state_type *user_state); 436 int (*load_firmware)(void *handle); 437 int (*wait_for_fw_loading_complete)(void *handle); 438 int (*set_powergating_by_smu)(void *handle, 439 uint32_t block_type, 440 bool gate, 441 int inst); 442 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 443 int (*set_power_limit)(void *handle, uint32_t n); 444 int (*get_power_limit)(void *handle, uint32_t *limit, 445 enum pp_power_limit_level pp_limit_level, 446 enum pp_power_type power_type); 447 int (*get_power_profile_mode)(void *handle, char *buf); 448 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 449 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 450 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 451 long *input, uint32_t size); 452 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 453 int (*smu_i2c_bus_access)(void *handle, bool acquire); 454 int (*gfx_state_change_set)(void *handle, uint32_t state); 455 /* export to DC */ 456 u32 (*get_sclk)(void *handle, bool low); 457 u32 (*get_mclk)(void *handle, bool low); 458 int (*display_configuration_change)(void *handle, 459 const struct amd_pp_display_configuration *input); 460 int (*get_display_power_level)(void *handle, 461 struct amd_pp_simple_clock_info *output); 462 int (*get_current_clocks)(void *handle, 463 struct amd_pp_clock_info *clocks); 464 int (*get_clock_by_type)(void *handle, 465 enum amd_pp_clock_type type, 466 struct amd_pp_clocks *clocks); 467 int (*get_clock_by_type_with_latency)(void *handle, 468 enum amd_pp_clock_type type, 469 struct pp_clock_levels_with_latency *clocks); 470 int (*get_clock_by_type_with_voltage)(void *handle, 471 enum amd_pp_clock_type type, 472 struct pp_clock_levels_with_voltage *clocks); 473 int (*set_watermarks_for_clocks_ranges)(void *handle, 474 void *clock_ranges); 475 int (*display_clock_voltage_request)(void *handle, 476 struct pp_display_clock_request *clock); 477 int (*get_display_mode_validation_clocks)(void *handle, 478 struct amd_pp_simple_clock_info *clocks); 479 int (*notify_smu_enable_pwe)(void *handle); 480 int (*enable_mgpu_fan_boost)(void *handle); 481 int (*set_active_display_count)(void *handle, uint32_t count); 482 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 483 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 484 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 485 int (*get_asic_baco_capability)(void *handle); 486 int (*get_asic_baco_state)(void *handle, int *state); 487 int (*set_asic_baco_state)(void *handle, int state); 488 int (*get_ppfeature_status)(void *handle, char *buf); 489 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 490 int (*asic_reset_mode_2)(void *handle); 491 int (*asic_reset_enable_gfx_features)(void *handle); 492 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 493 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 494 ssize_t (*get_gpu_metrics)(void *handle, void **table); 495 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 496 int (*set_watermarks_for_clock_ranges)(void *handle, 497 struct pp_smu_wm_range_sets *ranges); 498 int (*display_disable_memory_clock_switch)(void *handle, 499 bool disable_memory_clock_switch); 500 int (*get_max_sustainable_clocks_by_dc)(void *handle, 501 struct pp_smu_nv_clock_table *max_clocks); 502 int (*get_uclk_dpm_states)(void *handle, 503 unsigned int *clock_values_in_khz, 504 unsigned int *num_states); 505 int (*get_dpm_clock_table)(void *handle, 506 struct dpm_clocks *clock_table); 507 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 508 void (*pm_compute_clocks)(void *handle); 509 int (*notify_rlc_state)(void *handle, bool en); 510 }; 511 512 struct metrics_table_header { 513 uint16_t structure_size; 514 uint8_t format_revision; 515 uint8_t content_revision; 516 }; 517 518 /* 519 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 520 * Use gpu_metrics_v1_1 or later instead. 521 */ 522 struct gpu_metrics_v1_0 { 523 struct metrics_table_header common_header; 524 525 /* Driver attached timestamp (in ns) */ 526 uint64_t system_clock_counter; 527 528 /* Temperature */ 529 uint16_t temperature_edge; 530 uint16_t temperature_hotspot; 531 uint16_t temperature_mem; 532 uint16_t temperature_vrgfx; 533 uint16_t temperature_vrsoc; 534 uint16_t temperature_vrmem; 535 536 /* Utilization */ 537 uint16_t average_gfx_activity; 538 uint16_t average_umc_activity; // memory controller 539 uint16_t average_mm_activity; // UVD or VCN 540 541 /* Power/Energy */ 542 uint16_t average_socket_power; 543 uint32_t energy_accumulator; 544 545 /* Average clocks */ 546 uint16_t average_gfxclk_frequency; 547 uint16_t average_socclk_frequency; 548 uint16_t average_uclk_frequency; 549 uint16_t average_vclk0_frequency; 550 uint16_t average_dclk0_frequency; 551 uint16_t average_vclk1_frequency; 552 uint16_t average_dclk1_frequency; 553 554 /* Current clocks */ 555 uint16_t current_gfxclk; 556 uint16_t current_socclk; 557 uint16_t current_uclk; 558 uint16_t current_vclk0; 559 uint16_t current_dclk0; 560 uint16_t current_vclk1; 561 uint16_t current_dclk1; 562 563 /* Throttle status */ 564 uint32_t throttle_status; 565 566 /* Fans */ 567 uint16_t current_fan_speed; 568 569 /* Link width/speed */ 570 uint8_t pcie_link_width; 571 uint8_t pcie_link_speed; // in 0.1 GT/s 572 }; 573 574 struct gpu_metrics_v1_1 { 575 struct metrics_table_header common_header; 576 577 /* Temperature */ 578 uint16_t temperature_edge; 579 uint16_t temperature_hotspot; 580 uint16_t temperature_mem; 581 uint16_t temperature_vrgfx; 582 uint16_t temperature_vrsoc; 583 uint16_t temperature_vrmem; 584 585 /* Utilization */ 586 uint16_t average_gfx_activity; 587 uint16_t average_umc_activity; // memory controller 588 uint16_t average_mm_activity; // UVD or VCN 589 590 /* Power/Energy */ 591 uint16_t average_socket_power; 592 uint64_t energy_accumulator; 593 594 /* Driver attached timestamp (in ns) */ 595 uint64_t system_clock_counter; 596 597 /* Average clocks */ 598 uint16_t average_gfxclk_frequency; 599 uint16_t average_socclk_frequency; 600 uint16_t average_uclk_frequency; 601 uint16_t average_vclk0_frequency; 602 uint16_t average_dclk0_frequency; 603 uint16_t average_vclk1_frequency; 604 uint16_t average_dclk1_frequency; 605 606 /* Current clocks */ 607 uint16_t current_gfxclk; 608 uint16_t current_socclk; 609 uint16_t current_uclk; 610 uint16_t current_vclk0; 611 uint16_t current_dclk0; 612 uint16_t current_vclk1; 613 uint16_t current_dclk1; 614 615 /* Throttle status */ 616 uint32_t throttle_status; 617 618 /* Fans */ 619 uint16_t current_fan_speed; 620 621 /* Link width/speed */ 622 uint16_t pcie_link_width; 623 uint16_t pcie_link_speed; // in 0.1 GT/s 624 625 uint16_t padding; 626 627 uint32_t gfx_activity_acc; 628 uint32_t mem_activity_acc; 629 630 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 631 }; 632 633 struct gpu_metrics_v1_2 { 634 struct metrics_table_header common_header; 635 636 /* Temperature */ 637 uint16_t temperature_edge; 638 uint16_t temperature_hotspot; 639 uint16_t temperature_mem; 640 uint16_t temperature_vrgfx; 641 uint16_t temperature_vrsoc; 642 uint16_t temperature_vrmem; 643 644 /* Utilization */ 645 uint16_t average_gfx_activity; 646 uint16_t average_umc_activity; // memory controller 647 uint16_t average_mm_activity; // UVD or VCN 648 649 /* Power/Energy */ 650 uint16_t average_socket_power; 651 uint64_t energy_accumulator; 652 653 /* Driver attached timestamp (in ns) */ 654 uint64_t system_clock_counter; 655 656 /* Average clocks */ 657 uint16_t average_gfxclk_frequency; 658 uint16_t average_socclk_frequency; 659 uint16_t average_uclk_frequency; 660 uint16_t average_vclk0_frequency; 661 uint16_t average_dclk0_frequency; 662 uint16_t average_vclk1_frequency; 663 uint16_t average_dclk1_frequency; 664 665 /* Current clocks */ 666 uint16_t current_gfxclk; 667 uint16_t current_socclk; 668 uint16_t current_uclk; 669 uint16_t current_vclk0; 670 uint16_t current_dclk0; 671 uint16_t current_vclk1; 672 uint16_t current_dclk1; 673 674 /* Throttle status (ASIC dependent) */ 675 uint32_t throttle_status; 676 677 /* Fans */ 678 uint16_t current_fan_speed; 679 680 /* Link width/speed */ 681 uint16_t pcie_link_width; 682 uint16_t pcie_link_speed; // in 0.1 GT/s 683 684 uint16_t padding; 685 686 uint32_t gfx_activity_acc; 687 uint32_t mem_activity_acc; 688 689 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 690 691 /* PMFW attached timestamp (10ns resolution) */ 692 uint64_t firmware_timestamp; 693 }; 694 695 struct gpu_metrics_v1_3 { 696 struct metrics_table_header common_header; 697 698 /* Temperature */ 699 uint16_t temperature_edge; 700 uint16_t temperature_hotspot; 701 uint16_t temperature_mem; 702 uint16_t temperature_vrgfx; 703 uint16_t temperature_vrsoc; 704 uint16_t temperature_vrmem; 705 706 /* Utilization */ 707 uint16_t average_gfx_activity; 708 uint16_t average_umc_activity; // memory controller 709 uint16_t average_mm_activity; // UVD or VCN 710 711 /* Power/Energy */ 712 uint16_t average_socket_power; 713 uint64_t energy_accumulator; 714 715 /* Driver attached timestamp (in ns) */ 716 uint64_t system_clock_counter; 717 718 /* Average clocks */ 719 uint16_t average_gfxclk_frequency; 720 uint16_t average_socclk_frequency; 721 uint16_t average_uclk_frequency; 722 uint16_t average_vclk0_frequency; 723 uint16_t average_dclk0_frequency; 724 uint16_t average_vclk1_frequency; 725 uint16_t average_dclk1_frequency; 726 727 /* Current clocks */ 728 uint16_t current_gfxclk; 729 uint16_t current_socclk; 730 uint16_t current_uclk; 731 uint16_t current_vclk0; 732 uint16_t current_dclk0; 733 uint16_t current_vclk1; 734 uint16_t current_dclk1; 735 736 /* Throttle status */ 737 uint32_t throttle_status; 738 739 /* Fans */ 740 uint16_t current_fan_speed; 741 742 /* Link width/speed */ 743 uint16_t pcie_link_width; 744 uint16_t pcie_link_speed; // in 0.1 GT/s 745 746 uint16_t padding; 747 748 uint32_t gfx_activity_acc; 749 uint32_t mem_activity_acc; 750 751 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 752 753 /* PMFW attached timestamp (10ns resolution) */ 754 uint64_t firmware_timestamp; 755 756 /* Voltage (mV) */ 757 uint16_t voltage_soc; 758 uint16_t voltage_gfx; 759 uint16_t voltage_mem; 760 761 uint16_t padding1; 762 763 /* Throttle status (ASIC independent) */ 764 uint64_t indep_throttle_status; 765 }; 766 767 struct gpu_metrics_v1_4 { 768 struct metrics_table_header common_header; 769 770 /* Temperature (Celsius) */ 771 uint16_t temperature_hotspot; 772 uint16_t temperature_mem; 773 uint16_t temperature_vrsoc; 774 775 /* Power (Watts) */ 776 uint16_t curr_socket_power; 777 778 /* Utilization (%) */ 779 uint16_t average_gfx_activity; 780 uint16_t average_umc_activity; // memory controller 781 uint16_t vcn_activity[NUM_VCN]; 782 783 /* Energy (15.259uJ (2^-16) units) */ 784 uint64_t energy_accumulator; 785 786 /* Driver attached timestamp (in ns) */ 787 uint64_t system_clock_counter; 788 789 /* Throttle status */ 790 uint32_t throttle_status; 791 792 /* Clock Lock Status. Each bit corresponds to clock instance */ 793 uint32_t gfxclk_lock_status; 794 795 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 796 uint16_t pcie_link_width; 797 uint16_t pcie_link_speed; 798 799 /* XGMI bus width and bitrate (in Gbps) */ 800 uint16_t xgmi_link_width; 801 uint16_t xgmi_link_speed; 802 803 /* Utilization Accumulated (%) */ 804 uint32_t gfx_activity_acc; 805 uint32_t mem_activity_acc; 806 807 /*PCIE accumulated bandwidth (GB/sec) */ 808 uint64_t pcie_bandwidth_acc; 809 810 /*PCIE instantaneous bandwidth (GB/sec) */ 811 uint64_t pcie_bandwidth_inst; 812 813 /* PCIE L0 to recovery state transition accumulated count */ 814 uint64_t pcie_l0_to_recov_count_acc; 815 816 /* PCIE replay accumulated count */ 817 uint64_t pcie_replay_count_acc; 818 819 /* PCIE replay rollover accumulated count */ 820 uint64_t pcie_replay_rover_count_acc; 821 822 /* XGMI accumulated data transfer size(KiloBytes) */ 823 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 824 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 825 826 /* PMFW attached timestamp (10ns resolution) */ 827 uint64_t firmware_timestamp; 828 829 /* Current clocks (Mhz) */ 830 uint16_t current_gfxclk[MAX_GFX_CLKS]; 831 uint16_t current_socclk[MAX_CLKS]; 832 uint16_t current_vclk0[MAX_CLKS]; 833 uint16_t current_dclk0[MAX_CLKS]; 834 uint16_t current_uclk; 835 836 uint16_t padding; 837 }; 838 839 struct gpu_metrics_v1_5 { 840 struct metrics_table_header common_header; 841 842 /* Temperature (Celsius) */ 843 uint16_t temperature_hotspot; 844 uint16_t temperature_mem; 845 uint16_t temperature_vrsoc; 846 847 /* Power (Watts) */ 848 uint16_t curr_socket_power; 849 850 /* Utilization (%) */ 851 uint16_t average_gfx_activity; 852 uint16_t average_umc_activity; // memory controller 853 uint16_t vcn_activity[NUM_VCN]; 854 uint16_t jpeg_activity[NUM_JPEG_ENG]; 855 856 /* Energy (15.259uJ (2^-16) units) */ 857 uint64_t energy_accumulator; 858 859 /* Driver attached timestamp (in ns) */ 860 uint64_t system_clock_counter; 861 862 /* Throttle status */ 863 uint32_t throttle_status; 864 865 /* Clock Lock Status. Each bit corresponds to clock instance */ 866 uint32_t gfxclk_lock_status; 867 868 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 869 uint16_t pcie_link_width; 870 uint16_t pcie_link_speed; 871 872 /* XGMI bus width and bitrate (in Gbps) */ 873 uint16_t xgmi_link_width; 874 uint16_t xgmi_link_speed; 875 876 /* Utilization Accumulated (%) */ 877 uint32_t gfx_activity_acc; 878 uint32_t mem_activity_acc; 879 880 /*PCIE accumulated bandwidth (GB/sec) */ 881 uint64_t pcie_bandwidth_acc; 882 883 /*PCIE instantaneous bandwidth (GB/sec) */ 884 uint64_t pcie_bandwidth_inst; 885 886 /* PCIE L0 to recovery state transition accumulated count */ 887 uint64_t pcie_l0_to_recov_count_acc; 888 889 /* PCIE replay accumulated count */ 890 uint64_t pcie_replay_count_acc; 891 892 /* PCIE replay rollover accumulated count */ 893 uint64_t pcie_replay_rover_count_acc; 894 895 /* PCIE NAK sent accumulated count */ 896 uint32_t pcie_nak_sent_count_acc; 897 898 /* PCIE NAK received accumulated count */ 899 uint32_t pcie_nak_rcvd_count_acc; 900 901 /* XGMI accumulated data transfer size(KiloBytes) */ 902 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 903 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 904 905 /* PMFW attached timestamp (10ns resolution) */ 906 uint64_t firmware_timestamp; 907 908 /* Current clocks (Mhz) */ 909 uint16_t current_gfxclk[MAX_GFX_CLKS]; 910 uint16_t current_socclk[MAX_CLKS]; 911 uint16_t current_vclk0[MAX_CLKS]; 912 uint16_t current_dclk0[MAX_CLKS]; 913 uint16_t current_uclk; 914 915 uint16_t padding; 916 }; 917 918 struct gpu_metrics_v1_6 { 919 struct metrics_table_header common_header; 920 921 /* Temperature (Celsius) */ 922 uint16_t temperature_hotspot; 923 uint16_t temperature_mem; 924 uint16_t temperature_vrsoc; 925 926 /* Power (Watts) */ 927 uint16_t curr_socket_power; 928 929 /* Utilization (%) */ 930 uint16_t average_gfx_activity; 931 uint16_t average_umc_activity; // memory controller 932 933 /* Energy (15.259uJ (2^-16) units) */ 934 uint64_t energy_accumulator; 935 936 /* Driver attached timestamp (in ns) */ 937 uint64_t system_clock_counter; 938 939 /* Accumulation cycle counter */ 940 uint32_t accumulation_counter; 941 942 /* Accumulated throttler residencies */ 943 uint32_t prochot_residency_acc; 944 uint32_t ppt_residency_acc; 945 uint32_t socket_thm_residency_acc; 946 uint32_t vr_thm_residency_acc; 947 uint32_t hbm_thm_residency_acc; 948 949 /* Clock Lock Status. Each bit corresponds to clock instance */ 950 uint32_t gfxclk_lock_status; 951 952 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 953 uint16_t pcie_link_width; 954 uint16_t pcie_link_speed; 955 956 /* XGMI bus width and bitrate (in Gbps) */ 957 uint16_t xgmi_link_width; 958 uint16_t xgmi_link_speed; 959 960 /* Utilization Accumulated (%) */ 961 uint32_t gfx_activity_acc; 962 uint32_t mem_activity_acc; 963 964 /*PCIE accumulated bandwidth (GB/sec) */ 965 uint64_t pcie_bandwidth_acc; 966 967 /*PCIE instantaneous bandwidth (GB/sec) */ 968 uint64_t pcie_bandwidth_inst; 969 970 /* PCIE L0 to recovery state transition accumulated count */ 971 uint64_t pcie_l0_to_recov_count_acc; 972 973 /* PCIE replay accumulated count */ 974 uint64_t pcie_replay_count_acc; 975 976 /* PCIE replay rollover accumulated count */ 977 uint64_t pcie_replay_rover_count_acc; 978 979 /* PCIE NAK sent accumulated count */ 980 uint32_t pcie_nak_sent_count_acc; 981 982 /* PCIE NAK received accumulated count */ 983 uint32_t pcie_nak_rcvd_count_acc; 984 985 /* XGMI accumulated data transfer size(KiloBytes) */ 986 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 987 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 988 989 /* PMFW attached timestamp (10ns resolution) */ 990 uint64_t firmware_timestamp; 991 992 /* Current clocks (Mhz) */ 993 uint16_t current_gfxclk[MAX_GFX_CLKS]; 994 uint16_t current_socclk[MAX_CLKS]; 995 uint16_t current_vclk0[MAX_CLKS]; 996 uint16_t current_dclk0[MAX_CLKS]; 997 uint16_t current_uclk; 998 999 /* Number of current partition */ 1000 uint16_t num_partition; 1001 1002 /* XCP metrics stats */ 1003 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1004 1005 /* PCIE other end recovery counter */ 1006 uint32_t pcie_lc_perf_other_end_recovery; 1007 }; 1008 1009 struct gpu_metrics_v1_7 { 1010 struct metrics_table_header common_header; 1011 1012 /* Temperature (Celsius) */ 1013 uint16_t temperature_hotspot; 1014 uint16_t temperature_mem; 1015 uint16_t temperature_vrsoc; 1016 1017 /* Power (Watts) */ 1018 uint16_t curr_socket_power; 1019 1020 /* Utilization (%) */ 1021 uint16_t average_gfx_activity; 1022 uint16_t average_umc_activity; // memory controller 1023 1024 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1025 uint64_t mem_max_bandwidth; 1026 1027 /* Energy (15.259uJ (2^-16) units) */ 1028 uint64_t energy_accumulator; 1029 1030 /* Driver attached timestamp (in ns) */ 1031 uint64_t system_clock_counter; 1032 1033 /* Accumulation cycle counter */ 1034 uint32_t accumulation_counter; 1035 1036 /* Accumulated throttler residencies */ 1037 uint32_t prochot_residency_acc; 1038 uint32_t ppt_residency_acc; 1039 uint32_t socket_thm_residency_acc; 1040 uint32_t vr_thm_residency_acc; 1041 uint32_t hbm_thm_residency_acc; 1042 1043 /* Clock Lock Status. Each bit corresponds to clock instance */ 1044 uint32_t gfxclk_lock_status; 1045 1046 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1047 uint16_t pcie_link_width; 1048 uint16_t pcie_link_speed; 1049 1050 /* XGMI bus width and bitrate (in Gbps) */ 1051 uint16_t xgmi_link_width; 1052 uint16_t xgmi_link_speed; 1053 1054 /* Utilization Accumulated (%) */ 1055 uint32_t gfx_activity_acc; 1056 uint32_t mem_activity_acc; 1057 1058 /*PCIE accumulated bandwidth (GB/sec) */ 1059 uint64_t pcie_bandwidth_acc; 1060 1061 /*PCIE instantaneous bandwidth (GB/sec) */ 1062 uint64_t pcie_bandwidth_inst; 1063 1064 /* PCIE L0 to recovery state transition accumulated count */ 1065 uint64_t pcie_l0_to_recov_count_acc; 1066 1067 /* PCIE replay accumulated count */ 1068 uint64_t pcie_replay_count_acc; 1069 1070 /* PCIE replay rollover accumulated count */ 1071 uint64_t pcie_replay_rover_count_acc; 1072 1073 /* PCIE NAK sent accumulated count */ 1074 uint32_t pcie_nak_sent_count_acc; 1075 1076 /* PCIE NAK received accumulated count */ 1077 uint32_t pcie_nak_rcvd_count_acc; 1078 1079 /* XGMI accumulated data transfer size(KiloBytes) */ 1080 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1081 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1082 1083 /* XGMI link status(active/inactive) */ 1084 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1085 1086 uint16_t padding; 1087 1088 /* PMFW attached timestamp (10ns resolution) */ 1089 uint64_t firmware_timestamp; 1090 1091 /* Current clocks (Mhz) */ 1092 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1093 uint16_t current_socclk[MAX_CLKS]; 1094 uint16_t current_vclk0[MAX_CLKS]; 1095 uint16_t current_dclk0[MAX_CLKS]; 1096 uint16_t current_uclk; 1097 1098 /* Number of current partition */ 1099 uint16_t num_partition; 1100 1101 /* XCP metrics stats */ 1102 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1103 1104 /* PCIE other end recovery counter */ 1105 uint32_t pcie_lc_perf_other_end_recovery; 1106 }; 1107 1108 struct gpu_metrics_v1_8 { 1109 struct metrics_table_header common_header; 1110 1111 /* Temperature (Celsius) */ 1112 uint16_t temperature_hotspot; 1113 uint16_t temperature_mem; 1114 uint16_t temperature_vrsoc; 1115 1116 /* Power (Watts) */ 1117 uint16_t curr_socket_power; 1118 1119 /* Utilization (%) */ 1120 uint16_t average_gfx_activity; 1121 uint16_t average_umc_activity; // memory controller 1122 1123 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1124 uint64_t mem_max_bandwidth; 1125 1126 /* Energy (15.259uJ (2^-16) units) */ 1127 uint64_t energy_accumulator; 1128 1129 /* Driver attached timestamp (in ns) */ 1130 uint64_t system_clock_counter; 1131 1132 /* Accumulation cycle counter */ 1133 uint32_t accumulation_counter; 1134 1135 /* Accumulated throttler residencies */ 1136 uint32_t prochot_residency_acc; 1137 uint32_t ppt_residency_acc; 1138 uint32_t socket_thm_residency_acc; 1139 uint32_t vr_thm_residency_acc; 1140 uint32_t hbm_thm_residency_acc; 1141 1142 /* Clock Lock Status. Each bit corresponds to clock instance */ 1143 uint32_t gfxclk_lock_status; 1144 1145 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1146 uint16_t pcie_link_width; 1147 uint16_t pcie_link_speed; 1148 1149 /* XGMI bus width and bitrate (in Gbps) */ 1150 uint16_t xgmi_link_width; 1151 uint16_t xgmi_link_speed; 1152 1153 /* Utilization Accumulated (%) */ 1154 uint32_t gfx_activity_acc; 1155 uint32_t mem_activity_acc; 1156 1157 /*PCIE accumulated bandwidth (GB/sec) */ 1158 uint64_t pcie_bandwidth_acc; 1159 1160 /*PCIE instantaneous bandwidth (GB/sec) */ 1161 uint64_t pcie_bandwidth_inst; 1162 1163 /* PCIE L0 to recovery state transition accumulated count */ 1164 uint64_t pcie_l0_to_recov_count_acc; 1165 1166 /* PCIE replay accumulated count */ 1167 uint64_t pcie_replay_count_acc; 1168 1169 /* PCIE replay rollover accumulated count */ 1170 uint64_t pcie_replay_rover_count_acc; 1171 1172 /* PCIE NAK sent accumulated count */ 1173 uint32_t pcie_nak_sent_count_acc; 1174 1175 /* PCIE NAK received accumulated count */ 1176 uint32_t pcie_nak_rcvd_count_acc; 1177 1178 /* XGMI accumulated data transfer size(KiloBytes) */ 1179 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1180 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1181 1182 /* XGMI link status(active/inactive) */ 1183 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1184 1185 uint16_t padding; 1186 1187 /* PMFW attached timestamp (10ns resolution) */ 1188 uint64_t firmware_timestamp; 1189 1190 /* Current clocks (Mhz) */ 1191 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1192 uint16_t current_socclk[MAX_CLKS]; 1193 uint16_t current_vclk0[MAX_CLKS]; 1194 uint16_t current_dclk0[MAX_CLKS]; 1195 uint16_t current_uclk; 1196 1197 /* Number of current partition */ 1198 uint16_t num_partition; 1199 1200 /* XCP metrics stats */ 1201 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1202 1203 /* PCIE other end recovery counter */ 1204 uint32_t pcie_lc_perf_other_end_recovery; 1205 }; 1206 1207 /* 1208 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1209 * Use gpu_metrics_v2_1 or later instead. 1210 */ 1211 struct gpu_metrics_v2_0 { 1212 struct metrics_table_header common_header; 1213 1214 /* Driver attached timestamp (in ns) */ 1215 uint64_t system_clock_counter; 1216 1217 /* Temperature */ 1218 uint16_t temperature_gfx; // gfx temperature on APUs 1219 uint16_t temperature_soc; // soc temperature on APUs 1220 uint16_t temperature_core[8]; // CPU core temperature on APUs 1221 uint16_t temperature_l3[2]; 1222 1223 /* Utilization */ 1224 uint16_t average_gfx_activity; 1225 uint16_t average_mm_activity; // UVD or VCN 1226 1227 /* Power/Energy */ 1228 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1229 uint16_t average_cpu_power; 1230 uint16_t average_soc_power; 1231 uint16_t average_gfx_power; 1232 uint16_t average_core_power[8]; // CPU core power on APUs 1233 1234 /* Average clocks */ 1235 uint16_t average_gfxclk_frequency; 1236 uint16_t average_socclk_frequency; 1237 uint16_t average_uclk_frequency; 1238 uint16_t average_fclk_frequency; 1239 uint16_t average_vclk_frequency; 1240 uint16_t average_dclk_frequency; 1241 1242 /* Current clocks */ 1243 uint16_t current_gfxclk; 1244 uint16_t current_socclk; 1245 uint16_t current_uclk; 1246 uint16_t current_fclk; 1247 uint16_t current_vclk; 1248 uint16_t current_dclk; 1249 uint16_t current_coreclk[8]; // CPU core clocks 1250 uint16_t current_l3clk[2]; 1251 1252 /* Throttle status */ 1253 uint32_t throttle_status; 1254 1255 /* Fans */ 1256 uint16_t fan_pwm; 1257 1258 uint16_t padding; 1259 }; 1260 1261 struct gpu_metrics_v2_1 { 1262 struct metrics_table_header common_header; 1263 1264 /* Temperature */ 1265 uint16_t temperature_gfx; // gfx temperature on APUs 1266 uint16_t temperature_soc; // soc temperature on APUs 1267 uint16_t temperature_core[8]; // CPU core temperature on APUs 1268 uint16_t temperature_l3[2]; 1269 1270 /* Utilization */ 1271 uint16_t average_gfx_activity; 1272 uint16_t average_mm_activity; // UVD or VCN 1273 1274 /* Driver attached timestamp (in ns) */ 1275 uint64_t system_clock_counter; 1276 1277 /* Power/Energy */ 1278 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1279 uint16_t average_cpu_power; 1280 uint16_t average_soc_power; 1281 uint16_t average_gfx_power; 1282 uint16_t average_core_power[8]; // CPU core power on APUs 1283 1284 /* Average clocks */ 1285 uint16_t average_gfxclk_frequency; 1286 uint16_t average_socclk_frequency; 1287 uint16_t average_uclk_frequency; 1288 uint16_t average_fclk_frequency; 1289 uint16_t average_vclk_frequency; 1290 uint16_t average_dclk_frequency; 1291 1292 /* Current clocks */ 1293 uint16_t current_gfxclk; 1294 uint16_t current_socclk; 1295 uint16_t current_uclk; 1296 uint16_t current_fclk; 1297 uint16_t current_vclk; 1298 uint16_t current_dclk; 1299 uint16_t current_coreclk[8]; // CPU core clocks 1300 uint16_t current_l3clk[2]; 1301 1302 /* Throttle status */ 1303 uint32_t throttle_status; 1304 1305 /* Fans */ 1306 uint16_t fan_pwm; 1307 1308 uint16_t padding[3]; 1309 }; 1310 1311 struct gpu_metrics_v2_2 { 1312 struct metrics_table_header common_header; 1313 1314 /* Temperature */ 1315 uint16_t temperature_gfx; // gfx temperature on APUs 1316 uint16_t temperature_soc; // soc temperature on APUs 1317 uint16_t temperature_core[8]; // CPU core temperature on APUs 1318 uint16_t temperature_l3[2]; 1319 1320 /* Utilization */ 1321 uint16_t average_gfx_activity; 1322 uint16_t average_mm_activity; // UVD or VCN 1323 1324 /* Driver attached timestamp (in ns) */ 1325 uint64_t system_clock_counter; 1326 1327 /* Power/Energy */ 1328 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1329 uint16_t average_cpu_power; 1330 uint16_t average_soc_power; 1331 uint16_t average_gfx_power; 1332 uint16_t average_core_power[8]; // CPU core power on APUs 1333 1334 /* Average clocks */ 1335 uint16_t average_gfxclk_frequency; 1336 uint16_t average_socclk_frequency; 1337 uint16_t average_uclk_frequency; 1338 uint16_t average_fclk_frequency; 1339 uint16_t average_vclk_frequency; 1340 uint16_t average_dclk_frequency; 1341 1342 /* Current clocks */ 1343 uint16_t current_gfxclk; 1344 uint16_t current_socclk; 1345 uint16_t current_uclk; 1346 uint16_t current_fclk; 1347 uint16_t current_vclk; 1348 uint16_t current_dclk; 1349 uint16_t current_coreclk[8]; // CPU core clocks 1350 uint16_t current_l3clk[2]; 1351 1352 /* Throttle status (ASIC dependent) */ 1353 uint32_t throttle_status; 1354 1355 /* Fans */ 1356 uint16_t fan_pwm; 1357 1358 uint16_t padding[3]; 1359 1360 /* Throttle status (ASIC independent) */ 1361 uint64_t indep_throttle_status; 1362 }; 1363 1364 struct gpu_metrics_v2_3 { 1365 struct metrics_table_header common_header; 1366 1367 /* Temperature */ 1368 uint16_t temperature_gfx; // gfx temperature on APUs 1369 uint16_t temperature_soc; // soc temperature on APUs 1370 uint16_t temperature_core[8]; // CPU core temperature on APUs 1371 uint16_t temperature_l3[2]; 1372 1373 /* Utilization */ 1374 uint16_t average_gfx_activity; 1375 uint16_t average_mm_activity; // UVD or VCN 1376 1377 /* Driver attached timestamp (in ns) */ 1378 uint64_t system_clock_counter; 1379 1380 /* Power/Energy */ 1381 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1382 uint16_t average_cpu_power; 1383 uint16_t average_soc_power; 1384 uint16_t average_gfx_power; 1385 uint16_t average_core_power[8]; // CPU core power on APUs 1386 1387 /* Average clocks */ 1388 uint16_t average_gfxclk_frequency; 1389 uint16_t average_socclk_frequency; 1390 uint16_t average_uclk_frequency; 1391 uint16_t average_fclk_frequency; 1392 uint16_t average_vclk_frequency; 1393 uint16_t average_dclk_frequency; 1394 1395 /* Current clocks */ 1396 uint16_t current_gfxclk; 1397 uint16_t current_socclk; 1398 uint16_t current_uclk; 1399 uint16_t current_fclk; 1400 uint16_t current_vclk; 1401 uint16_t current_dclk; 1402 uint16_t current_coreclk[8]; // CPU core clocks 1403 uint16_t current_l3clk[2]; 1404 1405 /* Throttle status (ASIC dependent) */ 1406 uint32_t throttle_status; 1407 1408 /* Fans */ 1409 uint16_t fan_pwm; 1410 1411 uint16_t padding[3]; 1412 1413 /* Throttle status (ASIC independent) */ 1414 uint64_t indep_throttle_status; 1415 1416 /* Average Temperature */ 1417 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1418 uint16_t average_temperature_soc; // average soc temperature on APUs 1419 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1420 uint16_t average_temperature_l3[2]; 1421 }; 1422 1423 struct gpu_metrics_v2_4 { 1424 struct metrics_table_header common_header; 1425 1426 /* Temperature (unit: centi-Celsius) */ 1427 uint16_t temperature_gfx; 1428 uint16_t temperature_soc; 1429 uint16_t temperature_core[8]; 1430 uint16_t temperature_l3[2]; 1431 1432 /* Utilization (unit: centi) */ 1433 uint16_t average_gfx_activity; 1434 uint16_t average_mm_activity; 1435 1436 /* Driver attached timestamp (in ns) */ 1437 uint64_t system_clock_counter; 1438 1439 /* Power/Energy (unit: mW) */ 1440 uint16_t average_socket_power; 1441 uint16_t average_cpu_power; 1442 uint16_t average_soc_power; 1443 uint16_t average_gfx_power; 1444 uint16_t average_core_power[8]; 1445 1446 /* Average clocks (unit: MHz) */ 1447 uint16_t average_gfxclk_frequency; 1448 uint16_t average_socclk_frequency; 1449 uint16_t average_uclk_frequency; 1450 uint16_t average_fclk_frequency; 1451 uint16_t average_vclk_frequency; 1452 uint16_t average_dclk_frequency; 1453 1454 /* Current clocks (unit: MHz) */ 1455 uint16_t current_gfxclk; 1456 uint16_t current_socclk; 1457 uint16_t current_uclk; 1458 uint16_t current_fclk; 1459 uint16_t current_vclk; 1460 uint16_t current_dclk; 1461 uint16_t current_coreclk[8]; 1462 uint16_t current_l3clk[2]; 1463 1464 /* Throttle status (ASIC dependent) */ 1465 uint32_t throttle_status; 1466 1467 /* Fans */ 1468 uint16_t fan_pwm; 1469 1470 uint16_t padding[3]; 1471 1472 /* Throttle status (ASIC independent) */ 1473 uint64_t indep_throttle_status; 1474 1475 /* Average Temperature (unit: centi-Celsius) */ 1476 uint16_t average_temperature_gfx; 1477 uint16_t average_temperature_soc; 1478 uint16_t average_temperature_core[8]; 1479 uint16_t average_temperature_l3[2]; 1480 1481 /* Power/Voltage (unit: mV) */ 1482 uint16_t average_cpu_voltage; 1483 uint16_t average_soc_voltage; 1484 uint16_t average_gfx_voltage; 1485 1486 /* Power/Current (unit: mA) */ 1487 uint16_t average_cpu_current; 1488 uint16_t average_soc_current; 1489 uint16_t average_gfx_current; 1490 }; 1491 1492 struct gpu_metrics_v3_0 { 1493 struct metrics_table_header common_header; 1494 1495 /* Temperature */ 1496 /* gfx temperature on APUs */ 1497 uint16_t temperature_gfx; 1498 /* soc temperature on APUs */ 1499 uint16_t temperature_soc; 1500 /* CPU core temperature on APUs */ 1501 uint16_t temperature_core[16]; 1502 /* skin temperature on APUs */ 1503 uint16_t temperature_skin; 1504 1505 /* Utilization */ 1506 /* time filtered GFX busy % [0-100] */ 1507 uint16_t average_gfx_activity; 1508 /* time filtered VCN busy % [0-100] */ 1509 uint16_t average_vcn_activity; 1510 /* time filtered IPU per-column busy % [0-100] */ 1511 uint16_t average_ipu_activity[8]; 1512 /* time filtered per-core C0 residency % [0-100]*/ 1513 uint16_t average_core_c0_activity[16]; 1514 /* time filtered DRAM read bandwidth [MB/sec] */ 1515 uint16_t average_dram_reads; 1516 /* time filtered DRAM write bandwidth [MB/sec] */ 1517 uint16_t average_dram_writes; 1518 /* time filtered IPU read bandwidth [MB/sec] */ 1519 uint16_t average_ipu_reads; 1520 /* time filtered IPU write bandwidth [MB/sec] */ 1521 uint16_t average_ipu_writes; 1522 1523 /* Driver attached timestamp (in ns) */ 1524 uint64_t system_clock_counter; 1525 1526 /* Power/Energy */ 1527 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1528 uint32_t average_socket_power; 1529 /* time filtered IPU power [mW] */ 1530 uint16_t average_ipu_power; 1531 /* time filtered APU power [mW] */ 1532 uint32_t average_apu_power; 1533 /* time filtered GFX power [mW] */ 1534 uint32_t average_gfx_power; 1535 /* time filtered dGPU power [mW] */ 1536 uint32_t average_dgpu_power; 1537 /* time filtered sum of core power across all cores in the socket [mW] */ 1538 uint32_t average_all_core_power; 1539 /* calculated core power [mW] */ 1540 uint16_t average_core_power[16]; 1541 /* time filtered total system power [mW] */ 1542 uint16_t average_sys_power; 1543 /* maximum IRM defined STAPM power limit [mW] */ 1544 uint16_t stapm_power_limit; 1545 /* time filtered STAPM power limit [mW] */ 1546 uint16_t current_stapm_power_limit; 1547 1548 /* time filtered clocks [MHz] */ 1549 uint16_t average_gfxclk_frequency; 1550 uint16_t average_socclk_frequency; 1551 uint16_t average_vpeclk_frequency; 1552 uint16_t average_ipuclk_frequency; 1553 uint16_t average_fclk_frequency; 1554 uint16_t average_vclk_frequency; 1555 uint16_t average_uclk_frequency; 1556 uint16_t average_mpipu_frequency; 1557 1558 /* Current clocks */ 1559 /* target core frequency [MHz] */ 1560 uint16_t current_coreclk[16]; 1561 /* CCLK frequency limit enforced on classic cores [MHz] */ 1562 uint16_t current_core_maxfreq; 1563 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1564 uint16_t current_gfx_maxfreq; 1565 1566 /* Throttle Residency (ASIC dependent) */ 1567 uint32_t throttle_residency_prochot; 1568 uint32_t throttle_residency_spl; 1569 uint32_t throttle_residency_fppt; 1570 uint32_t throttle_residency_sppt; 1571 uint32_t throttle_residency_thm_core; 1572 uint32_t throttle_residency_thm_gfx; 1573 uint32_t throttle_residency_thm_soc; 1574 1575 /* Metrics table alpha filter time constant [us] */ 1576 uint32_t time_filter_alphavalue; 1577 }; 1578 1579 struct amdgpu_pmmetrics_header { 1580 uint16_t structure_size; 1581 uint16_t pad; 1582 uint32_t mp1_ip_discovery_version; 1583 uint32_t pmfw_version; 1584 uint32_t pmmetrics_version; 1585 }; 1586 1587 struct amdgpu_pm_metrics { 1588 struct amdgpu_pmmetrics_header common_header; 1589 1590 uint8_t data[]; 1591 }; 1592 1593 #endif 1594