1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 }; 123 124 enum amd_pp_sensors { 125 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 126 AMDGPU_PP_SENSOR_CPU_CLK, 127 AMDGPU_PP_SENSOR_VDDNB, 128 AMDGPU_PP_SENSOR_VDDGFX, 129 AMDGPU_PP_SENSOR_UVD_VCLK, 130 AMDGPU_PP_SENSOR_UVD_DCLK, 131 AMDGPU_PP_SENSOR_VCE_ECCLK, 132 AMDGPU_PP_SENSOR_GPU_LOAD, 133 AMDGPU_PP_SENSOR_MEM_LOAD, 134 AMDGPU_PP_SENSOR_GFX_MCLK, 135 AMDGPU_PP_SENSOR_GPU_TEMP, 136 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 137 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 138 AMDGPU_PP_SENSOR_MEM_TEMP, 139 AMDGPU_PP_SENSOR_VCE_POWER, 140 AMDGPU_PP_SENSOR_UVD_POWER, 141 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 142 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 143 AMDGPU_PP_SENSOR_SS_APU_SHARE, 144 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 145 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 146 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 147 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 148 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 149 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 150 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 151 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 152 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 153 AMDGPU_PP_SENSOR_VCN_LOAD, 154 }; 155 156 enum amd_pp_task { 157 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 158 AMD_PP_TASK_ENABLE_USER_STATE, 159 AMD_PP_TASK_READJUST_POWER_STATE, 160 AMD_PP_TASK_COMPLETE_INIT, 161 AMD_PP_TASK_MAX 162 }; 163 164 enum PP_SMC_POWER_PROFILE { 165 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 166 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 167 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 168 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 169 PP_SMC_POWER_PROFILE_VR = 0x4, 170 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 171 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 172 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 173 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 174 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 175 PP_SMC_POWER_PROFILE_COUNT, 176 }; 177 178 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 179 180 181 182 enum { 183 PP_GROUP_UNKNOWN = 0, 184 PP_GROUP_GFX = 1, 185 PP_GROUP_SYS, 186 PP_GROUP_MAX 187 }; 188 189 enum PP_OD_DPM_TABLE_COMMAND { 190 PP_OD_EDIT_SCLK_VDDC_TABLE, 191 PP_OD_EDIT_MCLK_VDDC_TABLE, 192 PP_OD_EDIT_CCLK_VDDC_TABLE, 193 PP_OD_EDIT_VDDC_CURVE, 194 PP_OD_RESTORE_DEFAULT_TABLE, 195 PP_OD_COMMIT_DPM_TABLE, 196 PP_OD_EDIT_VDDGFX_OFFSET, 197 PP_OD_EDIT_FAN_CURVE, 198 PP_OD_EDIT_ACOUSTIC_LIMIT, 199 PP_OD_EDIT_ACOUSTIC_TARGET, 200 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 201 PP_OD_EDIT_FAN_MINIMUM_PWM, 202 }; 203 204 struct pp_states_info { 205 uint32_t nums; 206 uint32_t states[16]; 207 }; 208 209 enum PP_HWMON_TEMP { 210 PP_TEMP_EDGE = 0, 211 PP_TEMP_JUNCTION, 212 PP_TEMP_MEM, 213 PP_TEMP_MAX 214 }; 215 216 enum pp_mp1_state { 217 PP_MP1_STATE_NONE, 218 PP_MP1_STATE_SHUTDOWN, 219 PP_MP1_STATE_UNLOAD, 220 PP_MP1_STATE_RESET, 221 PP_MP1_STATE_FLR, 222 }; 223 224 enum pp_df_cstate { 225 DF_CSTATE_DISALLOW = 0, 226 DF_CSTATE_ALLOW, 227 }; 228 229 /** 230 * DOC: amdgpu_pp_power 231 * 232 * APU power is managed to system-level requirements through the PPT 233 * (package power tracking) feature. PPT is intended to limit power to the 234 * requirements of the power source and could be dynamically updated to 235 * maximize APU performance within the system power budget. 236 * 237 * Two types of power measurement can be requested, where supported, with 238 * :c:type:`enum pp_power_type <pp_power_type>`. 239 */ 240 241 /** 242 * enum pp_power_limit_level - Used to query the power limits 243 * 244 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 245 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 246 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 247 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 248 */ 249 enum pp_power_limit_level { 250 PP_PWR_LIMIT_MIN = -1, 251 PP_PWR_LIMIT_CURRENT, 252 PP_PWR_LIMIT_DEFAULT, 253 PP_PWR_LIMIT_MAX, 254 }; 255 256 /** 257 * enum pp_power_type - Used to specify the type of the requested power 258 * 259 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 260 * moving average of APU power (default ~5000 ms). 261 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 262 * where supported. 263 */ 264 enum pp_power_type { 265 PP_PWR_TYPE_SUSTAINED, 266 PP_PWR_TYPE_FAST, 267 }; 268 269 enum pp_xgmi_plpd_mode { 270 XGMI_PLPD_NONE = -1, 271 XGMI_PLPD_DISALLOW, 272 XGMI_PLPD_DEFAULT, 273 XGMI_PLPD_OPTIMIZED, 274 XGMI_PLPD_COUNT, 275 }; 276 277 enum pp_pm_policy { 278 PP_PM_POLICY_NONE = -1, 279 PP_PM_POLICY_SOC_PSTATE = 0, 280 PP_PM_POLICY_XGMI_PLPD, 281 PP_PM_POLICY_NUM, 282 }; 283 284 enum pp_policy_soc_pstate { 285 SOC_PSTATE_DEFAULT = 0, 286 SOC_PSTATE_0, 287 SOC_PSTATE_1, 288 SOC_PSTATE_2, 289 SOC_PSTAT_COUNT, 290 }; 291 292 #define PP_POLICY_MAX_LEVELS 5 293 294 #define PP_GROUP_MASK 0xF0000000 295 #define PP_GROUP_SHIFT 28 296 297 #define PP_BLOCK_MASK 0x0FFFFF00 298 #define PP_BLOCK_SHIFT 8 299 300 #define PP_BLOCK_GFX_CG 0x01 301 #define PP_BLOCK_GFX_MG 0x02 302 #define PP_BLOCK_GFX_3D 0x04 303 #define PP_BLOCK_GFX_RLC 0x08 304 #define PP_BLOCK_GFX_CP 0x10 305 #define PP_BLOCK_SYS_BIF 0x01 306 #define PP_BLOCK_SYS_MC 0x02 307 #define PP_BLOCK_SYS_ROM 0x04 308 #define PP_BLOCK_SYS_DRM 0x08 309 #define PP_BLOCK_SYS_HDP 0x10 310 #define PP_BLOCK_SYS_SDMA 0x20 311 312 #define PP_STATE_MASK 0x0000000F 313 #define PP_STATE_SHIFT 0 314 #define PP_STATE_SUPPORT_MASK 0x000000F0 315 #define PP_STATE_SUPPORT_SHIFT 0 316 317 #define PP_STATE_CG 0x01 318 #define PP_STATE_LS 0x02 319 #define PP_STATE_DS 0x04 320 #define PP_STATE_SD 0x08 321 #define PP_STATE_SUPPORT_CG 0x10 322 #define PP_STATE_SUPPORT_LS 0x20 323 #define PP_STATE_SUPPORT_DS 0x40 324 #define PP_STATE_SUPPORT_SD 0x80 325 326 #define PP_CG_MSG_ID(group, block, support, state) \ 327 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 328 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 329 330 #define XGMI_MODE_PSTATE_D3 0 331 #define XGMI_MODE_PSTATE_D0 1 332 333 #define NUM_HBM_INSTANCES 4 334 #define NUM_XGMI_LINKS 8 335 #define MAX_GFX_CLKS 8 336 #define MAX_CLKS 4 337 #define NUM_VCN 4 338 #define NUM_JPEG_ENG 32 339 #define MAX_XCC 8 340 #define NUM_XCP 8 341 struct seq_file; 342 enum amd_pp_clock_type; 343 struct amd_pp_simple_clock_info; 344 struct amd_pp_display_configuration; 345 struct amd_pp_clock_info; 346 struct pp_display_clock_request; 347 struct pp_clock_levels_with_voltage; 348 struct pp_clock_levels_with_latency; 349 struct amd_pp_clocks; 350 struct pp_smu_wm_range_sets; 351 struct pp_smu_nv_clock_table; 352 struct dpm_clocks; 353 354 struct amdgpu_xcp_metrics { 355 /* Utilization Instantaneous (%) */ 356 u32 gfx_busy_inst[MAX_XCC]; 357 u16 jpeg_busy[NUM_JPEG_ENG]; 358 u16 vcn_busy[NUM_VCN]; 359 /* Utilization Accumulated (%) */ 360 u64 gfx_busy_acc[MAX_XCC]; 361 }; 362 363 struct amd_pm_funcs { 364 /* export for dpm on ci and si */ 365 int (*pre_set_power_state)(void *handle); 366 int (*set_power_state)(void *handle); 367 void (*post_set_power_state)(void *handle); 368 void (*display_configuration_changed)(void *handle); 369 void (*print_power_state)(void *handle, void *ps); 370 bool (*vblank_too_short)(void *handle); 371 void (*enable_bapm)(void *handle, bool enable); 372 int (*check_state_equal)(void *handle, 373 void *cps, 374 void *rps, 375 bool *equal); 376 /* export for sysfs */ 377 int (*set_fan_control_mode)(void *handle, u32 mode); 378 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 379 int (*set_fan_speed_pwm)(void *handle, u32 speed); 380 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 381 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 382 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 383 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 384 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 385 int (*get_sclk_od)(void *handle); 386 int (*set_sclk_od)(void *handle, uint32_t value); 387 int (*get_mclk_od)(void *handle); 388 int (*set_mclk_od)(void *handle, uint32_t value); 389 int (*read_sensor)(void *handle, int idx, void *value, int *size); 390 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 391 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 392 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 393 enum amd_pm_state_type (*get_current_power_state)(void *handle); 394 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 395 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 396 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 397 int (*get_pp_table)(void *handle, char **table); 398 int (*set_pp_table)(void *handle, const char *buf, size_t size); 399 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 400 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 401 /* export to amdgpu */ 402 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 403 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 404 enum amd_pm_state_type *user_state); 405 int (*load_firmware)(void *handle); 406 int (*wait_for_fw_loading_complete)(void *handle); 407 int (*set_powergating_by_smu)(void *handle, 408 uint32_t block_type, bool gate); 409 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 410 int (*set_power_limit)(void *handle, uint32_t n); 411 int (*get_power_limit)(void *handle, uint32_t *limit, 412 enum pp_power_limit_level pp_limit_level, 413 enum pp_power_type power_type); 414 int (*get_power_profile_mode)(void *handle, char *buf); 415 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 416 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 417 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 418 long *input, uint32_t size); 419 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 420 int (*smu_i2c_bus_access)(void *handle, bool acquire); 421 int (*gfx_state_change_set)(void *handle, uint32_t state); 422 /* export to DC */ 423 u32 (*get_sclk)(void *handle, bool low); 424 u32 (*get_mclk)(void *handle, bool low); 425 int (*display_configuration_change)(void *handle, 426 const struct amd_pp_display_configuration *input); 427 int (*get_display_power_level)(void *handle, 428 struct amd_pp_simple_clock_info *output); 429 int (*get_current_clocks)(void *handle, 430 struct amd_pp_clock_info *clocks); 431 int (*get_clock_by_type)(void *handle, 432 enum amd_pp_clock_type type, 433 struct amd_pp_clocks *clocks); 434 int (*get_clock_by_type_with_latency)(void *handle, 435 enum amd_pp_clock_type type, 436 struct pp_clock_levels_with_latency *clocks); 437 int (*get_clock_by_type_with_voltage)(void *handle, 438 enum amd_pp_clock_type type, 439 struct pp_clock_levels_with_voltage *clocks); 440 int (*set_watermarks_for_clocks_ranges)(void *handle, 441 void *clock_ranges); 442 int (*display_clock_voltage_request)(void *handle, 443 struct pp_display_clock_request *clock); 444 int (*get_display_mode_validation_clocks)(void *handle, 445 struct amd_pp_simple_clock_info *clocks); 446 int (*notify_smu_enable_pwe)(void *handle); 447 int (*enable_mgpu_fan_boost)(void *handle); 448 int (*set_active_display_count)(void *handle, uint32_t count); 449 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 450 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 451 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 452 int (*get_asic_baco_capability)(void *handle); 453 int (*get_asic_baco_state)(void *handle, int *state); 454 int (*set_asic_baco_state)(void *handle, int state); 455 int (*get_ppfeature_status)(void *handle, char *buf); 456 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 457 int (*asic_reset_mode_2)(void *handle); 458 int (*asic_reset_enable_gfx_features)(void *handle); 459 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 460 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 461 ssize_t (*get_gpu_metrics)(void *handle, void **table); 462 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 463 int (*set_watermarks_for_clock_ranges)(void *handle, 464 struct pp_smu_wm_range_sets *ranges); 465 int (*display_disable_memory_clock_switch)(void *handle, 466 bool disable_memory_clock_switch); 467 int (*get_max_sustainable_clocks_by_dc)(void *handle, 468 struct pp_smu_nv_clock_table *max_clocks); 469 int (*get_uclk_dpm_states)(void *handle, 470 unsigned int *clock_values_in_khz, 471 unsigned int *num_states); 472 int (*get_dpm_clock_table)(void *handle, 473 struct dpm_clocks *clock_table); 474 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 475 void (*pm_compute_clocks)(void *handle); 476 int (*notify_rlc_state)(void *handle, bool en); 477 }; 478 479 struct metrics_table_header { 480 uint16_t structure_size; 481 uint8_t format_revision; 482 uint8_t content_revision; 483 }; 484 485 /* 486 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 487 * Use gpu_metrics_v1_1 or later instead. 488 */ 489 struct gpu_metrics_v1_0 { 490 struct metrics_table_header common_header; 491 492 /* Driver attached timestamp (in ns) */ 493 uint64_t system_clock_counter; 494 495 /* Temperature */ 496 uint16_t temperature_edge; 497 uint16_t temperature_hotspot; 498 uint16_t temperature_mem; 499 uint16_t temperature_vrgfx; 500 uint16_t temperature_vrsoc; 501 uint16_t temperature_vrmem; 502 503 /* Utilization */ 504 uint16_t average_gfx_activity; 505 uint16_t average_umc_activity; // memory controller 506 uint16_t average_mm_activity; // UVD or VCN 507 508 /* Power/Energy */ 509 uint16_t average_socket_power; 510 uint32_t energy_accumulator; 511 512 /* Average clocks */ 513 uint16_t average_gfxclk_frequency; 514 uint16_t average_socclk_frequency; 515 uint16_t average_uclk_frequency; 516 uint16_t average_vclk0_frequency; 517 uint16_t average_dclk0_frequency; 518 uint16_t average_vclk1_frequency; 519 uint16_t average_dclk1_frequency; 520 521 /* Current clocks */ 522 uint16_t current_gfxclk; 523 uint16_t current_socclk; 524 uint16_t current_uclk; 525 uint16_t current_vclk0; 526 uint16_t current_dclk0; 527 uint16_t current_vclk1; 528 uint16_t current_dclk1; 529 530 /* Throttle status */ 531 uint32_t throttle_status; 532 533 /* Fans */ 534 uint16_t current_fan_speed; 535 536 /* Link width/speed */ 537 uint8_t pcie_link_width; 538 uint8_t pcie_link_speed; // in 0.1 GT/s 539 }; 540 541 struct gpu_metrics_v1_1 { 542 struct metrics_table_header common_header; 543 544 /* Temperature */ 545 uint16_t temperature_edge; 546 uint16_t temperature_hotspot; 547 uint16_t temperature_mem; 548 uint16_t temperature_vrgfx; 549 uint16_t temperature_vrsoc; 550 uint16_t temperature_vrmem; 551 552 /* Utilization */ 553 uint16_t average_gfx_activity; 554 uint16_t average_umc_activity; // memory controller 555 uint16_t average_mm_activity; // UVD or VCN 556 557 /* Power/Energy */ 558 uint16_t average_socket_power; 559 uint64_t energy_accumulator; 560 561 /* Driver attached timestamp (in ns) */ 562 uint64_t system_clock_counter; 563 564 /* Average clocks */ 565 uint16_t average_gfxclk_frequency; 566 uint16_t average_socclk_frequency; 567 uint16_t average_uclk_frequency; 568 uint16_t average_vclk0_frequency; 569 uint16_t average_dclk0_frequency; 570 uint16_t average_vclk1_frequency; 571 uint16_t average_dclk1_frequency; 572 573 /* Current clocks */ 574 uint16_t current_gfxclk; 575 uint16_t current_socclk; 576 uint16_t current_uclk; 577 uint16_t current_vclk0; 578 uint16_t current_dclk0; 579 uint16_t current_vclk1; 580 uint16_t current_dclk1; 581 582 /* Throttle status */ 583 uint32_t throttle_status; 584 585 /* Fans */ 586 uint16_t current_fan_speed; 587 588 /* Link width/speed */ 589 uint16_t pcie_link_width; 590 uint16_t pcie_link_speed; // in 0.1 GT/s 591 592 uint16_t padding; 593 594 uint32_t gfx_activity_acc; 595 uint32_t mem_activity_acc; 596 597 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 598 }; 599 600 struct gpu_metrics_v1_2 { 601 struct metrics_table_header common_header; 602 603 /* Temperature */ 604 uint16_t temperature_edge; 605 uint16_t temperature_hotspot; 606 uint16_t temperature_mem; 607 uint16_t temperature_vrgfx; 608 uint16_t temperature_vrsoc; 609 uint16_t temperature_vrmem; 610 611 /* Utilization */ 612 uint16_t average_gfx_activity; 613 uint16_t average_umc_activity; // memory controller 614 uint16_t average_mm_activity; // UVD or VCN 615 616 /* Power/Energy */ 617 uint16_t average_socket_power; 618 uint64_t energy_accumulator; 619 620 /* Driver attached timestamp (in ns) */ 621 uint64_t system_clock_counter; 622 623 /* Average clocks */ 624 uint16_t average_gfxclk_frequency; 625 uint16_t average_socclk_frequency; 626 uint16_t average_uclk_frequency; 627 uint16_t average_vclk0_frequency; 628 uint16_t average_dclk0_frequency; 629 uint16_t average_vclk1_frequency; 630 uint16_t average_dclk1_frequency; 631 632 /* Current clocks */ 633 uint16_t current_gfxclk; 634 uint16_t current_socclk; 635 uint16_t current_uclk; 636 uint16_t current_vclk0; 637 uint16_t current_dclk0; 638 uint16_t current_vclk1; 639 uint16_t current_dclk1; 640 641 /* Throttle status (ASIC dependent) */ 642 uint32_t throttle_status; 643 644 /* Fans */ 645 uint16_t current_fan_speed; 646 647 /* Link width/speed */ 648 uint16_t pcie_link_width; 649 uint16_t pcie_link_speed; // in 0.1 GT/s 650 651 uint16_t padding; 652 653 uint32_t gfx_activity_acc; 654 uint32_t mem_activity_acc; 655 656 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 657 658 /* PMFW attached timestamp (10ns resolution) */ 659 uint64_t firmware_timestamp; 660 }; 661 662 struct gpu_metrics_v1_3 { 663 struct metrics_table_header common_header; 664 665 /* Temperature */ 666 uint16_t temperature_edge; 667 uint16_t temperature_hotspot; 668 uint16_t temperature_mem; 669 uint16_t temperature_vrgfx; 670 uint16_t temperature_vrsoc; 671 uint16_t temperature_vrmem; 672 673 /* Utilization */ 674 uint16_t average_gfx_activity; 675 uint16_t average_umc_activity; // memory controller 676 uint16_t average_mm_activity; // UVD or VCN 677 678 /* Power/Energy */ 679 uint16_t average_socket_power; 680 uint64_t energy_accumulator; 681 682 /* Driver attached timestamp (in ns) */ 683 uint64_t system_clock_counter; 684 685 /* Average clocks */ 686 uint16_t average_gfxclk_frequency; 687 uint16_t average_socclk_frequency; 688 uint16_t average_uclk_frequency; 689 uint16_t average_vclk0_frequency; 690 uint16_t average_dclk0_frequency; 691 uint16_t average_vclk1_frequency; 692 uint16_t average_dclk1_frequency; 693 694 /* Current clocks */ 695 uint16_t current_gfxclk; 696 uint16_t current_socclk; 697 uint16_t current_uclk; 698 uint16_t current_vclk0; 699 uint16_t current_dclk0; 700 uint16_t current_vclk1; 701 uint16_t current_dclk1; 702 703 /* Throttle status */ 704 uint32_t throttle_status; 705 706 /* Fans */ 707 uint16_t current_fan_speed; 708 709 /* Link width/speed */ 710 uint16_t pcie_link_width; 711 uint16_t pcie_link_speed; // in 0.1 GT/s 712 713 uint16_t padding; 714 715 uint32_t gfx_activity_acc; 716 uint32_t mem_activity_acc; 717 718 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 719 720 /* PMFW attached timestamp (10ns resolution) */ 721 uint64_t firmware_timestamp; 722 723 /* Voltage (mV) */ 724 uint16_t voltage_soc; 725 uint16_t voltage_gfx; 726 uint16_t voltage_mem; 727 728 uint16_t padding1; 729 730 /* Throttle status (ASIC independent) */ 731 uint64_t indep_throttle_status; 732 }; 733 734 struct gpu_metrics_v1_4 { 735 struct metrics_table_header common_header; 736 737 /* Temperature (Celsius) */ 738 uint16_t temperature_hotspot; 739 uint16_t temperature_mem; 740 uint16_t temperature_vrsoc; 741 742 /* Power (Watts) */ 743 uint16_t curr_socket_power; 744 745 /* Utilization (%) */ 746 uint16_t average_gfx_activity; 747 uint16_t average_umc_activity; // memory controller 748 uint16_t vcn_activity[NUM_VCN]; 749 750 /* Energy (15.259uJ (2^-16) units) */ 751 uint64_t energy_accumulator; 752 753 /* Driver attached timestamp (in ns) */ 754 uint64_t system_clock_counter; 755 756 /* Throttle status */ 757 uint32_t throttle_status; 758 759 /* Clock Lock Status. Each bit corresponds to clock instance */ 760 uint32_t gfxclk_lock_status; 761 762 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 763 uint16_t pcie_link_width; 764 uint16_t pcie_link_speed; 765 766 /* XGMI bus width and bitrate (in Gbps) */ 767 uint16_t xgmi_link_width; 768 uint16_t xgmi_link_speed; 769 770 /* Utilization Accumulated (%) */ 771 uint32_t gfx_activity_acc; 772 uint32_t mem_activity_acc; 773 774 /*PCIE accumulated bandwidth (GB/sec) */ 775 uint64_t pcie_bandwidth_acc; 776 777 /*PCIE instantaneous bandwidth (GB/sec) */ 778 uint64_t pcie_bandwidth_inst; 779 780 /* PCIE L0 to recovery state transition accumulated count */ 781 uint64_t pcie_l0_to_recov_count_acc; 782 783 /* PCIE replay accumulated count */ 784 uint64_t pcie_replay_count_acc; 785 786 /* PCIE replay rollover accumulated count */ 787 uint64_t pcie_replay_rover_count_acc; 788 789 /* XGMI accumulated data transfer size(KiloBytes) */ 790 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 791 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 792 793 /* PMFW attached timestamp (10ns resolution) */ 794 uint64_t firmware_timestamp; 795 796 /* Current clocks (Mhz) */ 797 uint16_t current_gfxclk[MAX_GFX_CLKS]; 798 uint16_t current_socclk[MAX_CLKS]; 799 uint16_t current_vclk0[MAX_CLKS]; 800 uint16_t current_dclk0[MAX_CLKS]; 801 uint16_t current_uclk; 802 803 uint16_t padding; 804 }; 805 806 struct gpu_metrics_v1_5 { 807 struct metrics_table_header common_header; 808 809 /* Temperature (Celsius) */ 810 uint16_t temperature_hotspot; 811 uint16_t temperature_mem; 812 uint16_t temperature_vrsoc; 813 814 /* Power (Watts) */ 815 uint16_t curr_socket_power; 816 817 /* Utilization (%) */ 818 uint16_t average_gfx_activity; 819 uint16_t average_umc_activity; // memory controller 820 uint16_t vcn_activity[NUM_VCN]; 821 uint16_t jpeg_activity[NUM_JPEG_ENG]; 822 823 /* Energy (15.259uJ (2^-16) units) */ 824 uint64_t energy_accumulator; 825 826 /* Driver attached timestamp (in ns) */ 827 uint64_t system_clock_counter; 828 829 /* Throttle status */ 830 uint32_t throttle_status; 831 832 /* Clock Lock Status. Each bit corresponds to clock instance */ 833 uint32_t gfxclk_lock_status; 834 835 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 836 uint16_t pcie_link_width; 837 uint16_t pcie_link_speed; 838 839 /* XGMI bus width and bitrate (in Gbps) */ 840 uint16_t xgmi_link_width; 841 uint16_t xgmi_link_speed; 842 843 /* Utilization Accumulated (%) */ 844 uint32_t gfx_activity_acc; 845 uint32_t mem_activity_acc; 846 847 /*PCIE accumulated bandwidth (GB/sec) */ 848 uint64_t pcie_bandwidth_acc; 849 850 /*PCIE instantaneous bandwidth (GB/sec) */ 851 uint64_t pcie_bandwidth_inst; 852 853 /* PCIE L0 to recovery state transition accumulated count */ 854 uint64_t pcie_l0_to_recov_count_acc; 855 856 /* PCIE replay accumulated count */ 857 uint64_t pcie_replay_count_acc; 858 859 /* PCIE replay rollover accumulated count */ 860 uint64_t pcie_replay_rover_count_acc; 861 862 /* PCIE NAK sent accumulated count */ 863 uint32_t pcie_nak_sent_count_acc; 864 865 /* PCIE NAK received accumulated count */ 866 uint32_t pcie_nak_rcvd_count_acc; 867 868 /* XGMI accumulated data transfer size(KiloBytes) */ 869 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 870 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 871 872 /* PMFW attached timestamp (10ns resolution) */ 873 uint64_t firmware_timestamp; 874 875 /* Current clocks (Mhz) */ 876 uint16_t current_gfxclk[MAX_GFX_CLKS]; 877 uint16_t current_socclk[MAX_CLKS]; 878 uint16_t current_vclk0[MAX_CLKS]; 879 uint16_t current_dclk0[MAX_CLKS]; 880 uint16_t current_uclk; 881 882 uint16_t padding; 883 }; 884 885 struct gpu_metrics_v1_6 { 886 struct metrics_table_header common_header; 887 888 /* Temperature (Celsius) */ 889 uint16_t temperature_hotspot; 890 uint16_t temperature_mem; 891 uint16_t temperature_vrsoc; 892 893 /* Power (Watts) */ 894 uint16_t curr_socket_power; 895 896 /* Utilization (%) */ 897 uint16_t average_gfx_activity; 898 uint16_t average_umc_activity; // memory controller 899 900 /* Energy (15.259uJ (2^-16) units) */ 901 uint64_t energy_accumulator; 902 903 /* Driver attached timestamp (in ns) */ 904 uint64_t system_clock_counter; 905 906 /* Accumulation cycle counter */ 907 uint32_t accumulation_counter; 908 909 /* Accumulated throttler residencies */ 910 uint32_t prochot_residency_acc; 911 uint32_t ppt_residency_acc; 912 uint32_t socket_thm_residency_acc; 913 uint32_t vr_thm_residency_acc; 914 uint32_t hbm_thm_residency_acc; 915 916 /* Clock Lock Status. Each bit corresponds to clock instance */ 917 uint32_t gfxclk_lock_status; 918 919 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 920 uint16_t pcie_link_width; 921 uint16_t pcie_link_speed; 922 923 /* XGMI bus width and bitrate (in Gbps) */ 924 uint16_t xgmi_link_width; 925 uint16_t xgmi_link_speed; 926 927 /* Utilization Accumulated (%) */ 928 uint32_t gfx_activity_acc; 929 uint32_t mem_activity_acc; 930 931 /*PCIE accumulated bandwidth (GB/sec) */ 932 uint64_t pcie_bandwidth_acc; 933 934 /*PCIE instantaneous bandwidth (GB/sec) */ 935 uint64_t pcie_bandwidth_inst; 936 937 /* PCIE L0 to recovery state transition accumulated count */ 938 uint64_t pcie_l0_to_recov_count_acc; 939 940 /* PCIE replay accumulated count */ 941 uint64_t pcie_replay_count_acc; 942 943 /* PCIE replay rollover accumulated count */ 944 uint64_t pcie_replay_rover_count_acc; 945 946 /* PCIE NAK sent accumulated count */ 947 uint32_t pcie_nak_sent_count_acc; 948 949 /* PCIE NAK received accumulated count */ 950 uint32_t pcie_nak_rcvd_count_acc; 951 952 /* XGMI accumulated data transfer size(KiloBytes) */ 953 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 954 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 955 956 /* PMFW attached timestamp (10ns resolution) */ 957 uint64_t firmware_timestamp; 958 959 /* Current clocks (Mhz) */ 960 uint16_t current_gfxclk[MAX_GFX_CLKS]; 961 uint16_t current_socclk[MAX_CLKS]; 962 uint16_t current_vclk0[MAX_CLKS]; 963 uint16_t current_dclk0[MAX_CLKS]; 964 uint16_t current_uclk; 965 966 /* Number of current partition */ 967 uint16_t num_partition; 968 969 /* XCP metrics stats */ 970 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 971 972 /* PCIE other end recovery counter */ 973 uint32_t pcie_lc_perf_other_end_recovery; 974 }; 975 976 /* 977 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 978 * Use gpu_metrics_v2_1 or later instead. 979 */ 980 struct gpu_metrics_v2_0 { 981 struct metrics_table_header common_header; 982 983 /* Driver attached timestamp (in ns) */ 984 uint64_t system_clock_counter; 985 986 /* Temperature */ 987 uint16_t temperature_gfx; // gfx temperature on APUs 988 uint16_t temperature_soc; // soc temperature on APUs 989 uint16_t temperature_core[8]; // CPU core temperature on APUs 990 uint16_t temperature_l3[2]; 991 992 /* Utilization */ 993 uint16_t average_gfx_activity; 994 uint16_t average_mm_activity; // UVD or VCN 995 996 /* Power/Energy */ 997 uint16_t average_socket_power; // dGPU + APU power on A + A platform 998 uint16_t average_cpu_power; 999 uint16_t average_soc_power; 1000 uint16_t average_gfx_power; 1001 uint16_t average_core_power[8]; // CPU core power on APUs 1002 1003 /* Average clocks */ 1004 uint16_t average_gfxclk_frequency; 1005 uint16_t average_socclk_frequency; 1006 uint16_t average_uclk_frequency; 1007 uint16_t average_fclk_frequency; 1008 uint16_t average_vclk_frequency; 1009 uint16_t average_dclk_frequency; 1010 1011 /* Current clocks */ 1012 uint16_t current_gfxclk; 1013 uint16_t current_socclk; 1014 uint16_t current_uclk; 1015 uint16_t current_fclk; 1016 uint16_t current_vclk; 1017 uint16_t current_dclk; 1018 uint16_t current_coreclk[8]; // CPU core clocks 1019 uint16_t current_l3clk[2]; 1020 1021 /* Throttle status */ 1022 uint32_t throttle_status; 1023 1024 /* Fans */ 1025 uint16_t fan_pwm; 1026 1027 uint16_t padding; 1028 }; 1029 1030 struct gpu_metrics_v2_1 { 1031 struct metrics_table_header common_header; 1032 1033 /* Temperature */ 1034 uint16_t temperature_gfx; // gfx temperature on APUs 1035 uint16_t temperature_soc; // soc temperature on APUs 1036 uint16_t temperature_core[8]; // CPU core temperature on APUs 1037 uint16_t temperature_l3[2]; 1038 1039 /* Utilization */ 1040 uint16_t average_gfx_activity; 1041 uint16_t average_mm_activity; // UVD or VCN 1042 1043 /* Driver attached timestamp (in ns) */ 1044 uint64_t system_clock_counter; 1045 1046 /* Power/Energy */ 1047 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1048 uint16_t average_cpu_power; 1049 uint16_t average_soc_power; 1050 uint16_t average_gfx_power; 1051 uint16_t average_core_power[8]; // CPU core power on APUs 1052 1053 /* Average clocks */ 1054 uint16_t average_gfxclk_frequency; 1055 uint16_t average_socclk_frequency; 1056 uint16_t average_uclk_frequency; 1057 uint16_t average_fclk_frequency; 1058 uint16_t average_vclk_frequency; 1059 uint16_t average_dclk_frequency; 1060 1061 /* Current clocks */ 1062 uint16_t current_gfxclk; 1063 uint16_t current_socclk; 1064 uint16_t current_uclk; 1065 uint16_t current_fclk; 1066 uint16_t current_vclk; 1067 uint16_t current_dclk; 1068 uint16_t current_coreclk[8]; // CPU core clocks 1069 uint16_t current_l3clk[2]; 1070 1071 /* Throttle status */ 1072 uint32_t throttle_status; 1073 1074 /* Fans */ 1075 uint16_t fan_pwm; 1076 1077 uint16_t padding[3]; 1078 }; 1079 1080 struct gpu_metrics_v2_2 { 1081 struct metrics_table_header common_header; 1082 1083 /* Temperature */ 1084 uint16_t temperature_gfx; // gfx temperature on APUs 1085 uint16_t temperature_soc; // soc temperature on APUs 1086 uint16_t temperature_core[8]; // CPU core temperature on APUs 1087 uint16_t temperature_l3[2]; 1088 1089 /* Utilization */ 1090 uint16_t average_gfx_activity; 1091 uint16_t average_mm_activity; // UVD or VCN 1092 1093 /* Driver attached timestamp (in ns) */ 1094 uint64_t system_clock_counter; 1095 1096 /* Power/Energy */ 1097 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1098 uint16_t average_cpu_power; 1099 uint16_t average_soc_power; 1100 uint16_t average_gfx_power; 1101 uint16_t average_core_power[8]; // CPU core power on APUs 1102 1103 /* Average clocks */ 1104 uint16_t average_gfxclk_frequency; 1105 uint16_t average_socclk_frequency; 1106 uint16_t average_uclk_frequency; 1107 uint16_t average_fclk_frequency; 1108 uint16_t average_vclk_frequency; 1109 uint16_t average_dclk_frequency; 1110 1111 /* Current clocks */ 1112 uint16_t current_gfxclk; 1113 uint16_t current_socclk; 1114 uint16_t current_uclk; 1115 uint16_t current_fclk; 1116 uint16_t current_vclk; 1117 uint16_t current_dclk; 1118 uint16_t current_coreclk[8]; // CPU core clocks 1119 uint16_t current_l3clk[2]; 1120 1121 /* Throttle status (ASIC dependent) */ 1122 uint32_t throttle_status; 1123 1124 /* Fans */ 1125 uint16_t fan_pwm; 1126 1127 uint16_t padding[3]; 1128 1129 /* Throttle status (ASIC independent) */ 1130 uint64_t indep_throttle_status; 1131 }; 1132 1133 struct gpu_metrics_v2_3 { 1134 struct metrics_table_header common_header; 1135 1136 /* Temperature */ 1137 uint16_t temperature_gfx; // gfx temperature on APUs 1138 uint16_t temperature_soc; // soc temperature on APUs 1139 uint16_t temperature_core[8]; // CPU core temperature on APUs 1140 uint16_t temperature_l3[2]; 1141 1142 /* Utilization */ 1143 uint16_t average_gfx_activity; 1144 uint16_t average_mm_activity; // UVD or VCN 1145 1146 /* Driver attached timestamp (in ns) */ 1147 uint64_t system_clock_counter; 1148 1149 /* Power/Energy */ 1150 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1151 uint16_t average_cpu_power; 1152 uint16_t average_soc_power; 1153 uint16_t average_gfx_power; 1154 uint16_t average_core_power[8]; // CPU core power on APUs 1155 1156 /* Average clocks */ 1157 uint16_t average_gfxclk_frequency; 1158 uint16_t average_socclk_frequency; 1159 uint16_t average_uclk_frequency; 1160 uint16_t average_fclk_frequency; 1161 uint16_t average_vclk_frequency; 1162 uint16_t average_dclk_frequency; 1163 1164 /* Current clocks */ 1165 uint16_t current_gfxclk; 1166 uint16_t current_socclk; 1167 uint16_t current_uclk; 1168 uint16_t current_fclk; 1169 uint16_t current_vclk; 1170 uint16_t current_dclk; 1171 uint16_t current_coreclk[8]; // CPU core clocks 1172 uint16_t current_l3clk[2]; 1173 1174 /* Throttle status (ASIC dependent) */ 1175 uint32_t throttle_status; 1176 1177 /* Fans */ 1178 uint16_t fan_pwm; 1179 1180 uint16_t padding[3]; 1181 1182 /* Throttle status (ASIC independent) */ 1183 uint64_t indep_throttle_status; 1184 1185 /* Average Temperature */ 1186 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1187 uint16_t average_temperature_soc; // average soc temperature on APUs 1188 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1189 uint16_t average_temperature_l3[2]; 1190 }; 1191 1192 struct gpu_metrics_v2_4 { 1193 struct metrics_table_header common_header; 1194 1195 /* Temperature (unit: centi-Celsius) */ 1196 uint16_t temperature_gfx; 1197 uint16_t temperature_soc; 1198 uint16_t temperature_core[8]; 1199 uint16_t temperature_l3[2]; 1200 1201 /* Utilization (unit: centi) */ 1202 uint16_t average_gfx_activity; 1203 uint16_t average_mm_activity; 1204 1205 /* Driver attached timestamp (in ns) */ 1206 uint64_t system_clock_counter; 1207 1208 /* Power/Energy (unit: mW) */ 1209 uint16_t average_socket_power; 1210 uint16_t average_cpu_power; 1211 uint16_t average_soc_power; 1212 uint16_t average_gfx_power; 1213 uint16_t average_core_power[8]; 1214 1215 /* Average clocks (unit: MHz) */ 1216 uint16_t average_gfxclk_frequency; 1217 uint16_t average_socclk_frequency; 1218 uint16_t average_uclk_frequency; 1219 uint16_t average_fclk_frequency; 1220 uint16_t average_vclk_frequency; 1221 uint16_t average_dclk_frequency; 1222 1223 /* Current clocks (unit: MHz) */ 1224 uint16_t current_gfxclk; 1225 uint16_t current_socclk; 1226 uint16_t current_uclk; 1227 uint16_t current_fclk; 1228 uint16_t current_vclk; 1229 uint16_t current_dclk; 1230 uint16_t current_coreclk[8]; 1231 uint16_t current_l3clk[2]; 1232 1233 /* Throttle status (ASIC dependent) */ 1234 uint32_t throttle_status; 1235 1236 /* Fans */ 1237 uint16_t fan_pwm; 1238 1239 uint16_t padding[3]; 1240 1241 /* Throttle status (ASIC independent) */ 1242 uint64_t indep_throttle_status; 1243 1244 /* Average Temperature (unit: centi-Celsius) */ 1245 uint16_t average_temperature_gfx; 1246 uint16_t average_temperature_soc; 1247 uint16_t average_temperature_core[8]; 1248 uint16_t average_temperature_l3[2]; 1249 1250 /* Power/Voltage (unit: mV) */ 1251 uint16_t average_cpu_voltage; 1252 uint16_t average_soc_voltage; 1253 uint16_t average_gfx_voltage; 1254 1255 /* Power/Current (unit: mA) */ 1256 uint16_t average_cpu_current; 1257 uint16_t average_soc_current; 1258 uint16_t average_gfx_current; 1259 }; 1260 1261 struct gpu_metrics_v3_0 { 1262 struct metrics_table_header common_header; 1263 1264 /* Temperature */ 1265 /* gfx temperature on APUs */ 1266 uint16_t temperature_gfx; 1267 /* soc temperature on APUs */ 1268 uint16_t temperature_soc; 1269 /* CPU core temperature on APUs */ 1270 uint16_t temperature_core[16]; 1271 /* skin temperature on APUs */ 1272 uint16_t temperature_skin; 1273 1274 /* Utilization */ 1275 /* time filtered GFX busy % [0-100] */ 1276 uint16_t average_gfx_activity; 1277 /* time filtered VCN busy % [0-100] */ 1278 uint16_t average_vcn_activity; 1279 /* time filtered IPU per-column busy % [0-100] */ 1280 uint16_t average_ipu_activity[8]; 1281 /* time filtered per-core C0 residency % [0-100]*/ 1282 uint16_t average_core_c0_activity[16]; 1283 /* time filtered DRAM read bandwidth [MB/sec] */ 1284 uint16_t average_dram_reads; 1285 /* time filtered DRAM write bandwidth [MB/sec] */ 1286 uint16_t average_dram_writes; 1287 /* time filtered IPU read bandwidth [MB/sec] */ 1288 uint16_t average_ipu_reads; 1289 /* time filtered IPU write bandwidth [MB/sec] */ 1290 uint16_t average_ipu_writes; 1291 1292 /* Driver attached timestamp (in ns) */ 1293 uint64_t system_clock_counter; 1294 1295 /* Power/Energy */ 1296 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1297 uint32_t average_socket_power; 1298 /* time filtered IPU power [mW] */ 1299 uint16_t average_ipu_power; 1300 /* time filtered APU power [mW] */ 1301 uint32_t average_apu_power; 1302 /* time filtered GFX power [mW] */ 1303 uint32_t average_gfx_power; 1304 /* time filtered dGPU power [mW] */ 1305 uint32_t average_dgpu_power; 1306 /* time filtered sum of core power across all cores in the socket [mW] */ 1307 uint32_t average_all_core_power; 1308 /* calculated core power [mW] */ 1309 uint16_t average_core_power[16]; 1310 /* time filtered total system power [mW] */ 1311 uint16_t average_sys_power; 1312 /* maximum IRM defined STAPM power limit [mW] */ 1313 uint16_t stapm_power_limit; 1314 /* time filtered STAPM power limit [mW] */ 1315 uint16_t current_stapm_power_limit; 1316 1317 /* time filtered clocks [MHz] */ 1318 uint16_t average_gfxclk_frequency; 1319 uint16_t average_socclk_frequency; 1320 uint16_t average_vpeclk_frequency; 1321 uint16_t average_ipuclk_frequency; 1322 uint16_t average_fclk_frequency; 1323 uint16_t average_vclk_frequency; 1324 uint16_t average_uclk_frequency; 1325 uint16_t average_mpipu_frequency; 1326 1327 /* Current clocks */ 1328 /* target core frequency [MHz] */ 1329 uint16_t current_coreclk[16]; 1330 /* CCLK frequency limit enforced on classic cores [MHz] */ 1331 uint16_t current_core_maxfreq; 1332 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1333 uint16_t current_gfx_maxfreq; 1334 1335 /* Throttle Residency (ASIC dependent) */ 1336 uint32_t throttle_residency_prochot; 1337 uint32_t throttle_residency_spl; 1338 uint32_t throttle_residency_fppt; 1339 uint32_t throttle_residency_sppt; 1340 uint32_t throttle_residency_thm_core; 1341 uint32_t throttle_residency_thm_gfx; 1342 uint32_t throttle_residency_thm_soc; 1343 1344 /* Metrics table alpha filter time constant [us] */ 1345 uint32_t time_filter_alphavalue; 1346 }; 1347 1348 struct amdgpu_pmmetrics_header { 1349 uint16_t structure_size; 1350 uint16_t pad; 1351 uint32_t mp1_ip_discovery_version; 1352 uint32_t pmfw_version; 1353 uint32_t pmmetrics_version; 1354 }; 1355 1356 struct amdgpu_pm_metrics { 1357 struct amdgpu_pmmetrics_header common_header; 1358 1359 uint8_t data[]; 1360 }; 1361 1362 #endif 1363