1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 29 struct amd_vce_state { 30 /* vce clocks */ 31 u32 evclk; 32 u32 ecclk; 33 /* gpu clocks */ 34 u32 sclk; 35 u32 mclk; 36 u8 clk_idx; 37 u8 pstate; 38 }; 39 40 41 enum amd_dpm_forced_level { 42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 44 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 51 }; 52 53 enum amd_pm_state_type { 54 /* not used for dpm */ 55 POWER_STATE_TYPE_DEFAULT, 56 POWER_STATE_TYPE_POWERSAVE, 57 /* user selectable states */ 58 POWER_STATE_TYPE_BATTERY, 59 POWER_STATE_TYPE_BALANCED, 60 POWER_STATE_TYPE_PERFORMANCE, 61 /* internal states */ 62 POWER_STATE_TYPE_INTERNAL_UVD, 63 POWER_STATE_TYPE_INTERNAL_UVD_SD, 64 POWER_STATE_TYPE_INTERNAL_UVD_HD, 65 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 66 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 67 POWER_STATE_TYPE_INTERNAL_BOOT, 68 POWER_STATE_TYPE_INTERNAL_THERMAL, 69 POWER_STATE_TYPE_INTERNAL_ACPI, 70 POWER_STATE_TYPE_INTERNAL_ULV, 71 POWER_STATE_TYPE_INTERNAL_3DPERF, 72 }; 73 74 #define AMD_MAX_VCE_LEVELS 6 75 76 enum amd_vce_level { 77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 83 }; 84 85 enum amd_fan_ctrl_mode { 86 AMD_FAN_CTRL_NONE = 0, 87 AMD_FAN_CTRL_MANUAL = 1, 88 AMD_FAN_CTRL_AUTO = 2, 89 }; 90 91 enum pp_clock_type { 92 PP_SCLK, 93 PP_MCLK, 94 PP_PCIE, 95 PP_SOCCLK, 96 PP_FCLK, 97 PP_DCEFCLK, 98 OD_SCLK, 99 OD_MCLK, 100 OD_VDDC_CURVE, 101 OD_RANGE, 102 }; 103 104 enum amd_pp_sensors { 105 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 106 AMDGPU_PP_SENSOR_CPU_CLK, 107 AMDGPU_PP_SENSOR_VDDNB, 108 AMDGPU_PP_SENSOR_VDDGFX, 109 AMDGPU_PP_SENSOR_UVD_VCLK, 110 AMDGPU_PP_SENSOR_UVD_DCLK, 111 AMDGPU_PP_SENSOR_VCE_ECCLK, 112 AMDGPU_PP_SENSOR_GPU_LOAD, 113 AMDGPU_PP_SENSOR_MEM_LOAD, 114 AMDGPU_PP_SENSOR_GFX_MCLK, 115 AMDGPU_PP_SENSOR_GPU_TEMP, 116 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 117 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 118 AMDGPU_PP_SENSOR_MEM_TEMP, 119 AMDGPU_PP_SENSOR_VCE_POWER, 120 AMDGPU_PP_SENSOR_UVD_POWER, 121 AMDGPU_PP_SENSOR_GPU_POWER, 122 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 123 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 124 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 125 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 126 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 127 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 128 }; 129 130 enum amd_pp_task { 131 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 132 AMD_PP_TASK_ENABLE_USER_STATE, 133 AMD_PP_TASK_READJUST_POWER_STATE, 134 AMD_PP_TASK_COMPLETE_INIT, 135 AMD_PP_TASK_MAX 136 }; 137 138 enum PP_SMC_POWER_PROFILE { 139 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 140 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 141 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 142 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 143 PP_SMC_POWER_PROFILE_VR = 0x4, 144 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 145 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 146 PP_SMC_POWER_PROFILE_COUNT, 147 }; 148 149 enum { 150 PP_GROUP_UNKNOWN = 0, 151 PP_GROUP_GFX = 1, 152 PP_GROUP_SYS, 153 PP_GROUP_MAX 154 }; 155 156 enum PP_OD_DPM_TABLE_COMMAND { 157 PP_OD_EDIT_SCLK_VDDC_TABLE, 158 PP_OD_EDIT_MCLK_VDDC_TABLE, 159 PP_OD_EDIT_CCLK_VDDC_TABLE, 160 PP_OD_EDIT_VDDC_CURVE, 161 PP_OD_RESTORE_DEFAULT_TABLE, 162 PP_OD_COMMIT_DPM_TABLE, 163 PP_OD_EDIT_VDDGFX_OFFSET 164 }; 165 166 struct pp_states_info { 167 uint32_t nums; 168 uint32_t states[16]; 169 }; 170 171 enum PP_HWMON_TEMP { 172 PP_TEMP_EDGE = 0, 173 PP_TEMP_JUNCTION, 174 PP_TEMP_MEM, 175 PP_TEMP_MAX 176 }; 177 178 enum pp_mp1_state { 179 PP_MP1_STATE_NONE, 180 PP_MP1_STATE_SHUTDOWN, 181 PP_MP1_STATE_UNLOAD, 182 PP_MP1_STATE_RESET, 183 }; 184 185 enum pp_df_cstate { 186 DF_CSTATE_DISALLOW = 0, 187 DF_CSTATE_ALLOW, 188 }; 189 190 #define PP_GROUP_MASK 0xF0000000 191 #define PP_GROUP_SHIFT 28 192 193 #define PP_BLOCK_MASK 0x0FFFFF00 194 #define PP_BLOCK_SHIFT 8 195 196 #define PP_BLOCK_GFX_CG 0x01 197 #define PP_BLOCK_GFX_MG 0x02 198 #define PP_BLOCK_GFX_3D 0x04 199 #define PP_BLOCK_GFX_RLC 0x08 200 #define PP_BLOCK_GFX_CP 0x10 201 #define PP_BLOCK_SYS_BIF 0x01 202 #define PP_BLOCK_SYS_MC 0x02 203 #define PP_BLOCK_SYS_ROM 0x04 204 #define PP_BLOCK_SYS_DRM 0x08 205 #define PP_BLOCK_SYS_HDP 0x10 206 #define PP_BLOCK_SYS_SDMA 0x20 207 208 #define PP_STATE_MASK 0x0000000F 209 #define PP_STATE_SHIFT 0 210 #define PP_STATE_SUPPORT_MASK 0x000000F0 211 #define PP_STATE_SUPPORT_SHIFT 0 212 213 #define PP_STATE_CG 0x01 214 #define PP_STATE_LS 0x02 215 #define PP_STATE_DS 0x04 216 #define PP_STATE_SD 0x08 217 #define PP_STATE_SUPPORT_CG 0x10 218 #define PP_STATE_SUPPORT_LS 0x20 219 #define PP_STATE_SUPPORT_DS 0x40 220 #define PP_STATE_SUPPORT_SD 0x80 221 222 #define PP_CG_MSG_ID(group, block, support, state) \ 223 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 224 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 225 226 #define XGMI_MODE_PSTATE_D3 0 227 #define XGMI_MODE_PSTATE_D0 1 228 229 struct seq_file; 230 enum amd_pp_clock_type; 231 struct amd_pp_simple_clock_info; 232 struct amd_pp_display_configuration; 233 struct amd_pp_clock_info; 234 struct pp_display_clock_request; 235 struct pp_clock_levels_with_voltage; 236 struct pp_clock_levels_with_latency; 237 struct amd_pp_clocks; 238 239 struct amd_pm_funcs { 240 /* export for dpm on ci and si */ 241 int (*pre_set_power_state)(void *handle); 242 int (*set_power_state)(void *handle); 243 void (*post_set_power_state)(void *handle); 244 void (*display_configuration_changed)(void *handle); 245 void (*print_power_state)(void *handle, void *ps); 246 bool (*vblank_too_short)(void *handle); 247 void (*enable_bapm)(void *handle, bool enable); 248 int (*check_state_equal)(void *handle, 249 void *cps, 250 void *rps, 251 bool *equal); 252 /* export for sysfs */ 253 void (*set_fan_control_mode)(void *handle, u32 mode); 254 u32 (*get_fan_control_mode)(void *handle); 255 int (*set_fan_speed_percent)(void *handle, u32 speed); 256 int (*get_fan_speed_percent)(void *handle, u32 *speed); 257 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 258 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 259 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 260 int (*get_sclk_od)(void *handle); 261 int (*set_sclk_od)(void *handle, uint32_t value); 262 int (*get_mclk_od)(void *handle); 263 int (*set_mclk_od)(void *handle, uint32_t value); 264 int (*read_sensor)(void *handle, int idx, void *value, int *size); 265 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 266 enum amd_pm_state_type (*get_current_power_state)(void *handle); 267 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 268 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 269 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 270 int (*get_pp_table)(void *handle, char **table); 271 int (*set_pp_table)(void *handle, const char *buf, size_t size); 272 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 273 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 274 /* export to amdgpu */ 275 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 276 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 277 enum amd_pm_state_type *user_state); 278 int (*load_firmware)(void *handle); 279 int (*wait_for_fw_loading_complete)(void *handle); 280 int (*set_powergating_by_smu)(void *handle, 281 uint32_t block_type, bool gate); 282 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 283 int (*set_power_limit)(void *handle, uint32_t n); 284 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit); 285 int (*get_power_profile_mode)(void *handle, char *buf); 286 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 287 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 288 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 289 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 290 int (*smu_i2c_bus_access)(void *handle, bool acquire); 291 int (*gfx_state_change_set)(void *handle, uint32_t state); 292 /* export to DC */ 293 u32 (*get_sclk)(void *handle, bool low); 294 u32 (*get_mclk)(void *handle, bool low); 295 int (*display_configuration_change)(void *handle, 296 const struct amd_pp_display_configuration *input); 297 int (*get_display_power_level)(void *handle, 298 struct amd_pp_simple_clock_info *output); 299 int (*get_current_clocks)(void *handle, 300 struct amd_pp_clock_info *clocks); 301 int (*get_clock_by_type)(void *handle, 302 enum amd_pp_clock_type type, 303 struct amd_pp_clocks *clocks); 304 int (*get_clock_by_type_with_latency)(void *handle, 305 enum amd_pp_clock_type type, 306 struct pp_clock_levels_with_latency *clocks); 307 int (*get_clock_by_type_with_voltage)(void *handle, 308 enum amd_pp_clock_type type, 309 struct pp_clock_levels_with_voltage *clocks); 310 int (*set_watermarks_for_clocks_ranges)(void *handle, 311 void *clock_ranges); 312 int (*display_clock_voltage_request)(void *handle, 313 struct pp_display_clock_request *clock); 314 int (*get_display_mode_validation_clocks)(void *handle, 315 struct amd_pp_simple_clock_info *clocks); 316 int (*notify_smu_enable_pwe)(void *handle); 317 int (*enable_mgpu_fan_boost)(void *handle); 318 int (*set_active_display_count)(void *handle, uint32_t count); 319 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 320 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 321 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 322 int (*get_asic_baco_capability)(void *handle, bool *cap); 323 int (*get_asic_baco_state)(void *handle, int *state); 324 int (*set_asic_baco_state)(void *handle, int state); 325 int (*get_ppfeature_status)(void *handle, char *buf); 326 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 327 int (*asic_reset_mode_2)(void *handle); 328 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 329 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 330 ssize_t (*get_gpu_metrics)(void *handle, void **table); 331 }; 332 333 struct metrics_table_header { 334 uint16_t structure_size; 335 uint8_t format_revision; 336 uint8_t content_revision; 337 }; 338 339 struct gpu_metrics_v1_0 { 340 struct metrics_table_header common_header; 341 342 /* Driver attached timestamp (in ns) */ 343 uint64_t system_clock_counter; 344 345 /* Temperature */ 346 uint16_t temperature_edge; 347 uint16_t temperature_hotspot; 348 uint16_t temperature_mem; 349 uint16_t temperature_vrgfx; 350 uint16_t temperature_vrsoc; 351 uint16_t temperature_vrmem; 352 353 /* Utilization */ 354 uint16_t average_gfx_activity; 355 uint16_t average_umc_activity; // memory controller 356 uint16_t average_mm_activity; // UVD or VCN 357 358 /* Power/Energy */ 359 uint16_t average_socket_power; 360 uint32_t energy_accumulator; 361 362 /* Average clocks */ 363 uint16_t average_gfxclk_frequency; 364 uint16_t average_socclk_frequency; 365 uint16_t average_uclk_frequency; 366 uint16_t average_vclk0_frequency; 367 uint16_t average_dclk0_frequency; 368 uint16_t average_vclk1_frequency; 369 uint16_t average_dclk1_frequency; 370 371 /* Current clocks */ 372 uint16_t current_gfxclk; 373 uint16_t current_socclk; 374 uint16_t current_uclk; 375 uint16_t current_vclk0; 376 uint16_t current_dclk0; 377 uint16_t current_vclk1; 378 uint16_t current_dclk1; 379 380 /* Throttle status */ 381 uint32_t throttle_status; 382 383 /* Fans */ 384 uint16_t current_fan_speed; 385 386 /* Link width/speed */ 387 uint8_t pcie_link_width; 388 uint8_t pcie_link_speed; // in 0.1 GT/s 389 }; 390 391 struct gpu_metrics_v2_0 { 392 struct metrics_table_header common_header; 393 394 /* Driver attached timestamp (in ns) */ 395 uint64_t system_clock_counter; 396 397 /* Temperature */ 398 uint16_t temperature_gfx; // gfx temperature on APUs 399 uint16_t temperature_soc; // soc temperature on APUs 400 uint16_t temperature_core[8]; // CPU core temperature on APUs 401 uint16_t temperature_l3[2]; 402 403 /* Utilization */ 404 uint16_t average_gfx_activity; 405 uint16_t average_mm_activity; // UVD or VCN 406 407 /* Power/Energy */ 408 uint16_t average_socket_power; // dGPU + APU power on A + A platform 409 uint16_t average_cpu_power; 410 uint16_t average_soc_power; 411 uint16_t average_gfx_power; 412 uint16_t average_core_power[8]; // CPU core power on APUs 413 414 /* Average clocks */ 415 uint16_t average_gfxclk_frequency; 416 uint16_t average_socclk_frequency; 417 uint16_t average_uclk_frequency; 418 uint16_t average_fclk_frequency; 419 uint16_t average_vclk_frequency; 420 uint16_t average_dclk_frequency; 421 422 /* Current clocks */ 423 uint16_t current_gfxclk; 424 uint16_t current_socclk; 425 uint16_t current_uclk; 426 uint16_t current_fclk; 427 uint16_t current_vclk; 428 uint16_t current_dclk; 429 uint16_t current_coreclk[8]; // CPU core clocks 430 uint16_t current_l3clk[2]; 431 432 /* Throttle status */ 433 uint32_t throttle_status; 434 435 /* Fans */ 436 uint16_t fan_pwm; 437 438 uint16_t padding; 439 }; 440 441 #endif 442