1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_VCLK1, 108 PP_DCLK, 109 PP_DCLK1, 110 OD_SCLK, 111 OD_MCLK, 112 OD_VDDC_CURVE, 113 OD_RANGE, 114 OD_VDDGFX_OFFSET, 115 OD_CCLK, 116 OD_FAN_CURVE, 117 OD_ACOUSTIC_LIMIT, 118 OD_ACOUSTIC_TARGET, 119 OD_FAN_TARGET_TEMPERATURE, 120 OD_FAN_MINIMUM_PWM, 121 }; 122 123 enum amd_pp_sensors { 124 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 125 AMDGPU_PP_SENSOR_CPU_CLK, 126 AMDGPU_PP_SENSOR_VDDNB, 127 AMDGPU_PP_SENSOR_VDDGFX, 128 AMDGPU_PP_SENSOR_UVD_VCLK, 129 AMDGPU_PP_SENSOR_UVD_DCLK, 130 AMDGPU_PP_SENSOR_VCE_ECCLK, 131 AMDGPU_PP_SENSOR_GPU_LOAD, 132 AMDGPU_PP_SENSOR_MEM_LOAD, 133 AMDGPU_PP_SENSOR_GFX_MCLK, 134 AMDGPU_PP_SENSOR_GPU_TEMP, 135 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 136 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 137 AMDGPU_PP_SENSOR_MEM_TEMP, 138 AMDGPU_PP_SENSOR_VCE_POWER, 139 AMDGPU_PP_SENSOR_UVD_POWER, 140 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 141 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 142 AMDGPU_PP_SENSOR_SS_APU_SHARE, 143 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 144 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 145 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 146 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 147 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 148 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 149 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 150 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 151 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 152 }; 153 154 enum amd_pp_task { 155 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 156 AMD_PP_TASK_ENABLE_USER_STATE, 157 AMD_PP_TASK_READJUST_POWER_STATE, 158 AMD_PP_TASK_COMPLETE_INIT, 159 AMD_PP_TASK_MAX 160 }; 161 162 enum PP_SMC_POWER_PROFILE { 163 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 164 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 165 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 166 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 167 PP_SMC_POWER_PROFILE_VR = 0x4, 168 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 169 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 170 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 171 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 172 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 173 PP_SMC_POWER_PROFILE_COUNT, 174 }; 175 176 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 177 178 179 180 enum { 181 PP_GROUP_UNKNOWN = 0, 182 PP_GROUP_GFX = 1, 183 PP_GROUP_SYS, 184 PP_GROUP_MAX 185 }; 186 187 enum PP_OD_DPM_TABLE_COMMAND { 188 PP_OD_EDIT_SCLK_VDDC_TABLE, 189 PP_OD_EDIT_MCLK_VDDC_TABLE, 190 PP_OD_EDIT_CCLK_VDDC_TABLE, 191 PP_OD_EDIT_VDDC_CURVE, 192 PP_OD_RESTORE_DEFAULT_TABLE, 193 PP_OD_COMMIT_DPM_TABLE, 194 PP_OD_EDIT_VDDGFX_OFFSET, 195 PP_OD_EDIT_FAN_CURVE, 196 PP_OD_EDIT_ACOUSTIC_LIMIT, 197 PP_OD_EDIT_ACOUSTIC_TARGET, 198 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 199 PP_OD_EDIT_FAN_MINIMUM_PWM, 200 }; 201 202 struct pp_states_info { 203 uint32_t nums; 204 uint32_t states[16]; 205 }; 206 207 enum PP_HWMON_TEMP { 208 PP_TEMP_EDGE = 0, 209 PP_TEMP_JUNCTION, 210 PP_TEMP_MEM, 211 PP_TEMP_MAX 212 }; 213 214 enum pp_mp1_state { 215 PP_MP1_STATE_NONE, 216 PP_MP1_STATE_SHUTDOWN, 217 PP_MP1_STATE_UNLOAD, 218 PP_MP1_STATE_RESET, 219 }; 220 221 enum pp_df_cstate { 222 DF_CSTATE_DISALLOW = 0, 223 DF_CSTATE_ALLOW, 224 }; 225 226 /** 227 * DOC: amdgpu_pp_power 228 * 229 * APU power is managed to system-level requirements through the PPT 230 * (package power tracking) feature. PPT is intended to limit power to the 231 * requirements of the power source and could be dynamically updated to 232 * maximize APU performance within the system power budget. 233 * 234 * Two types of power measurement can be requested, where supported, with 235 * :c:type:`enum pp_power_type <pp_power_type>`. 236 */ 237 238 /** 239 * enum pp_power_limit_level - Used to query the power limits 240 * 241 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 242 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 243 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 244 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 245 */ 246 enum pp_power_limit_level 247 { 248 PP_PWR_LIMIT_MIN = -1, 249 PP_PWR_LIMIT_CURRENT, 250 PP_PWR_LIMIT_DEFAULT, 251 PP_PWR_LIMIT_MAX, 252 }; 253 254 /** 255 * enum pp_power_type - Used to specify the type of the requested power 256 * 257 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 258 * moving average of APU power (default ~5000 ms). 259 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 260 * where supported. 261 */ 262 enum pp_power_type 263 { 264 PP_PWR_TYPE_SUSTAINED, 265 PP_PWR_TYPE_FAST, 266 }; 267 268 enum pp_xgmi_plpd_mode { 269 XGMI_PLPD_NONE = -1, 270 XGMI_PLPD_DISALLOW, 271 XGMI_PLPD_DEFAULT, 272 XGMI_PLPD_OPTIMIZED, 273 XGMI_PLPD_COUNT, 274 }; 275 276 #define PP_GROUP_MASK 0xF0000000 277 #define PP_GROUP_SHIFT 28 278 279 #define PP_BLOCK_MASK 0x0FFFFF00 280 #define PP_BLOCK_SHIFT 8 281 282 #define PP_BLOCK_GFX_CG 0x01 283 #define PP_BLOCK_GFX_MG 0x02 284 #define PP_BLOCK_GFX_3D 0x04 285 #define PP_BLOCK_GFX_RLC 0x08 286 #define PP_BLOCK_GFX_CP 0x10 287 #define PP_BLOCK_SYS_BIF 0x01 288 #define PP_BLOCK_SYS_MC 0x02 289 #define PP_BLOCK_SYS_ROM 0x04 290 #define PP_BLOCK_SYS_DRM 0x08 291 #define PP_BLOCK_SYS_HDP 0x10 292 #define PP_BLOCK_SYS_SDMA 0x20 293 294 #define PP_STATE_MASK 0x0000000F 295 #define PP_STATE_SHIFT 0 296 #define PP_STATE_SUPPORT_MASK 0x000000F0 297 #define PP_STATE_SUPPORT_SHIFT 0 298 299 #define PP_STATE_CG 0x01 300 #define PP_STATE_LS 0x02 301 #define PP_STATE_DS 0x04 302 #define PP_STATE_SD 0x08 303 #define PP_STATE_SUPPORT_CG 0x10 304 #define PP_STATE_SUPPORT_LS 0x20 305 #define PP_STATE_SUPPORT_DS 0x40 306 #define PP_STATE_SUPPORT_SD 0x80 307 308 #define PP_CG_MSG_ID(group, block, support, state) \ 309 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 310 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 311 312 #define XGMI_MODE_PSTATE_D3 0 313 #define XGMI_MODE_PSTATE_D0 1 314 315 #define NUM_HBM_INSTANCES 4 316 317 struct seq_file; 318 enum amd_pp_clock_type; 319 struct amd_pp_simple_clock_info; 320 struct amd_pp_display_configuration; 321 struct amd_pp_clock_info; 322 struct pp_display_clock_request; 323 struct pp_clock_levels_with_voltage; 324 struct pp_clock_levels_with_latency; 325 struct amd_pp_clocks; 326 struct pp_smu_wm_range_sets; 327 struct pp_smu_nv_clock_table; 328 struct dpm_clocks; 329 330 struct amd_pm_funcs { 331 /* export for dpm on ci and si */ 332 int (*pre_set_power_state)(void *handle); 333 int (*set_power_state)(void *handle); 334 void (*post_set_power_state)(void *handle); 335 void (*display_configuration_changed)(void *handle); 336 void (*print_power_state)(void *handle, void *ps); 337 bool (*vblank_too_short)(void *handle); 338 void (*enable_bapm)(void *handle, bool enable); 339 int (*check_state_equal)(void *handle, 340 void *cps, 341 void *rps, 342 bool *equal); 343 /* export for sysfs */ 344 int (*set_fan_control_mode)(void *handle, u32 mode); 345 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 346 int (*set_fan_speed_pwm)(void *handle, u32 speed); 347 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 348 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 349 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 350 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 351 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 352 int (*get_sclk_od)(void *handle); 353 int (*set_sclk_od)(void *handle, uint32_t value); 354 int (*get_mclk_od)(void *handle); 355 int (*set_mclk_od)(void *handle, uint32_t value); 356 int (*read_sensor)(void *handle, int idx, void *value, int *size); 357 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 358 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 359 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 360 enum amd_pm_state_type (*get_current_power_state)(void *handle); 361 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 362 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 363 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 364 int (*get_pp_table)(void *handle, char **table); 365 int (*set_pp_table)(void *handle, const char *buf, size_t size); 366 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 367 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 368 /* export to amdgpu */ 369 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 370 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 371 enum amd_pm_state_type *user_state); 372 int (*load_firmware)(void *handle); 373 int (*wait_for_fw_loading_complete)(void *handle); 374 int (*set_powergating_by_smu)(void *handle, 375 uint32_t block_type, bool gate); 376 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 377 int (*set_power_limit)(void *handle, uint32_t n); 378 int (*get_power_limit)(void *handle, uint32_t *limit, 379 enum pp_power_limit_level pp_limit_level, 380 enum pp_power_type power_type); 381 int (*get_power_profile_mode)(void *handle, char *buf); 382 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 383 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 384 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 385 long *input, uint32_t size); 386 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 387 int (*smu_i2c_bus_access)(void *handle, bool acquire); 388 int (*gfx_state_change_set)(void *handle, uint32_t state); 389 /* export to DC */ 390 u32 (*get_sclk)(void *handle, bool low); 391 u32 (*get_mclk)(void *handle, bool low); 392 int (*display_configuration_change)(void *handle, 393 const struct amd_pp_display_configuration *input); 394 int (*get_display_power_level)(void *handle, 395 struct amd_pp_simple_clock_info *output); 396 int (*get_current_clocks)(void *handle, 397 struct amd_pp_clock_info *clocks); 398 int (*get_clock_by_type)(void *handle, 399 enum amd_pp_clock_type type, 400 struct amd_pp_clocks *clocks); 401 int (*get_clock_by_type_with_latency)(void *handle, 402 enum amd_pp_clock_type type, 403 struct pp_clock_levels_with_latency *clocks); 404 int (*get_clock_by_type_with_voltage)(void *handle, 405 enum amd_pp_clock_type type, 406 struct pp_clock_levels_with_voltage *clocks); 407 int (*set_watermarks_for_clocks_ranges)(void *handle, 408 void *clock_ranges); 409 int (*display_clock_voltage_request)(void *handle, 410 struct pp_display_clock_request *clock); 411 int (*get_display_mode_validation_clocks)(void *handle, 412 struct amd_pp_simple_clock_info *clocks); 413 int (*notify_smu_enable_pwe)(void *handle); 414 int (*enable_mgpu_fan_boost)(void *handle); 415 int (*set_active_display_count)(void *handle, uint32_t count); 416 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 417 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 418 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 419 int (*get_asic_baco_capability)(void *handle, bool *cap); 420 int (*get_asic_baco_state)(void *handle, int *state); 421 int (*set_asic_baco_state)(void *handle, int state); 422 int (*get_ppfeature_status)(void *handle, char *buf); 423 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 424 int (*asic_reset_mode_2)(void *handle); 425 int (*asic_reset_enable_gfx_features)(void *handle); 426 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 427 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 428 ssize_t (*get_gpu_metrics)(void *handle, void **table); 429 int (*set_watermarks_for_clock_ranges)(void *handle, 430 struct pp_smu_wm_range_sets *ranges); 431 int (*display_disable_memory_clock_switch)(void *handle, 432 bool disable_memory_clock_switch); 433 int (*get_max_sustainable_clocks_by_dc)(void *handle, 434 struct pp_smu_nv_clock_table *max_clocks); 435 int (*get_uclk_dpm_states)(void *handle, 436 unsigned int *clock_values_in_khz, 437 unsigned int *num_states); 438 int (*get_dpm_clock_table)(void *handle, 439 struct dpm_clocks *clock_table); 440 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 441 void (*pm_compute_clocks)(void *handle); 442 }; 443 444 struct metrics_table_header { 445 uint16_t structure_size; 446 uint8_t format_revision; 447 uint8_t content_revision; 448 }; 449 450 /* 451 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 452 * Use gpu_metrics_v1_1 or later instead. 453 */ 454 struct gpu_metrics_v1_0 { 455 struct metrics_table_header common_header; 456 457 /* Driver attached timestamp (in ns) */ 458 uint64_t system_clock_counter; 459 460 /* Temperature */ 461 uint16_t temperature_edge; 462 uint16_t temperature_hotspot; 463 uint16_t temperature_mem; 464 uint16_t temperature_vrgfx; 465 uint16_t temperature_vrsoc; 466 uint16_t temperature_vrmem; 467 468 /* Utilization */ 469 uint16_t average_gfx_activity; 470 uint16_t average_umc_activity; // memory controller 471 uint16_t average_mm_activity; // UVD or VCN 472 473 /* Power/Energy */ 474 uint16_t average_socket_power; 475 uint32_t energy_accumulator; 476 477 /* Average clocks */ 478 uint16_t average_gfxclk_frequency; 479 uint16_t average_socclk_frequency; 480 uint16_t average_uclk_frequency; 481 uint16_t average_vclk0_frequency; 482 uint16_t average_dclk0_frequency; 483 uint16_t average_vclk1_frequency; 484 uint16_t average_dclk1_frequency; 485 486 /* Current clocks */ 487 uint16_t current_gfxclk; 488 uint16_t current_socclk; 489 uint16_t current_uclk; 490 uint16_t current_vclk0; 491 uint16_t current_dclk0; 492 uint16_t current_vclk1; 493 uint16_t current_dclk1; 494 495 /* Throttle status */ 496 uint32_t throttle_status; 497 498 /* Fans */ 499 uint16_t current_fan_speed; 500 501 /* Link width/speed */ 502 uint8_t pcie_link_width; 503 uint8_t pcie_link_speed; // in 0.1 GT/s 504 }; 505 506 struct gpu_metrics_v1_1 { 507 struct metrics_table_header common_header; 508 509 /* Temperature */ 510 uint16_t temperature_edge; 511 uint16_t temperature_hotspot; 512 uint16_t temperature_mem; 513 uint16_t temperature_vrgfx; 514 uint16_t temperature_vrsoc; 515 uint16_t temperature_vrmem; 516 517 /* Utilization */ 518 uint16_t average_gfx_activity; 519 uint16_t average_umc_activity; // memory controller 520 uint16_t average_mm_activity; // UVD or VCN 521 522 /* Power/Energy */ 523 uint16_t average_socket_power; 524 uint64_t energy_accumulator; 525 526 /* Driver attached timestamp (in ns) */ 527 uint64_t system_clock_counter; 528 529 /* Average clocks */ 530 uint16_t average_gfxclk_frequency; 531 uint16_t average_socclk_frequency; 532 uint16_t average_uclk_frequency; 533 uint16_t average_vclk0_frequency; 534 uint16_t average_dclk0_frequency; 535 uint16_t average_vclk1_frequency; 536 uint16_t average_dclk1_frequency; 537 538 /* Current clocks */ 539 uint16_t current_gfxclk; 540 uint16_t current_socclk; 541 uint16_t current_uclk; 542 uint16_t current_vclk0; 543 uint16_t current_dclk0; 544 uint16_t current_vclk1; 545 uint16_t current_dclk1; 546 547 /* Throttle status */ 548 uint32_t throttle_status; 549 550 /* Fans */ 551 uint16_t current_fan_speed; 552 553 /* Link width/speed */ 554 uint16_t pcie_link_width; 555 uint16_t pcie_link_speed; // in 0.1 GT/s 556 557 uint16_t padding; 558 559 uint32_t gfx_activity_acc; 560 uint32_t mem_activity_acc; 561 562 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 563 }; 564 565 struct gpu_metrics_v1_2 { 566 struct metrics_table_header common_header; 567 568 /* Temperature */ 569 uint16_t temperature_edge; 570 uint16_t temperature_hotspot; 571 uint16_t temperature_mem; 572 uint16_t temperature_vrgfx; 573 uint16_t temperature_vrsoc; 574 uint16_t temperature_vrmem; 575 576 /* Utilization */ 577 uint16_t average_gfx_activity; 578 uint16_t average_umc_activity; // memory controller 579 uint16_t average_mm_activity; // UVD or VCN 580 581 /* Power/Energy */ 582 uint16_t average_socket_power; 583 uint64_t energy_accumulator; 584 585 /* Driver attached timestamp (in ns) */ 586 uint64_t system_clock_counter; 587 588 /* Average clocks */ 589 uint16_t average_gfxclk_frequency; 590 uint16_t average_socclk_frequency; 591 uint16_t average_uclk_frequency; 592 uint16_t average_vclk0_frequency; 593 uint16_t average_dclk0_frequency; 594 uint16_t average_vclk1_frequency; 595 uint16_t average_dclk1_frequency; 596 597 /* Current clocks */ 598 uint16_t current_gfxclk; 599 uint16_t current_socclk; 600 uint16_t current_uclk; 601 uint16_t current_vclk0; 602 uint16_t current_dclk0; 603 uint16_t current_vclk1; 604 uint16_t current_dclk1; 605 606 /* Throttle status (ASIC dependent) */ 607 uint32_t throttle_status; 608 609 /* Fans */ 610 uint16_t current_fan_speed; 611 612 /* Link width/speed */ 613 uint16_t pcie_link_width; 614 uint16_t pcie_link_speed; // in 0.1 GT/s 615 616 uint16_t padding; 617 618 uint32_t gfx_activity_acc; 619 uint32_t mem_activity_acc; 620 621 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 622 623 /* PMFW attached timestamp (10ns resolution) */ 624 uint64_t firmware_timestamp; 625 }; 626 627 struct gpu_metrics_v1_3 { 628 struct metrics_table_header common_header; 629 630 /* Temperature */ 631 uint16_t temperature_edge; 632 uint16_t temperature_hotspot; 633 uint16_t temperature_mem; 634 uint16_t temperature_vrgfx; 635 uint16_t temperature_vrsoc; 636 uint16_t temperature_vrmem; 637 638 /* Utilization */ 639 uint16_t average_gfx_activity; 640 uint16_t average_umc_activity; // memory controller 641 uint16_t average_mm_activity; // UVD or VCN 642 643 /* Power/Energy */ 644 uint16_t average_socket_power; 645 uint64_t energy_accumulator; 646 647 /* Driver attached timestamp (in ns) */ 648 uint64_t system_clock_counter; 649 650 /* Average clocks */ 651 uint16_t average_gfxclk_frequency; 652 uint16_t average_socclk_frequency; 653 uint16_t average_uclk_frequency; 654 uint16_t average_vclk0_frequency; 655 uint16_t average_dclk0_frequency; 656 uint16_t average_vclk1_frequency; 657 uint16_t average_dclk1_frequency; 658 659 /* Current clocks */ 660 uint16_t current_gfxclk; 661 uint16_t current_socclk; 662 uint16_t current_uclk; 663 uint16_t current_vclk0; 664 uint16_t current_dclk0; 665 uint16_t current_vclk1; 666 uint16_t current_dclk1; 667 668 /* Throttle status */ 669 uint32_t throttle_status; 670 671 /* Fans */ 672 uint16_t current_fan_speed; 673 674 /* Link width/speed */ 675 uint16_t pcie_link_width; 676 uint16_t pcie_link_speed; // in 0.1 GT/s 677 678 uint16_t padding; 679 680 uint32_t gfx_activity_acc; 681 uint32_t mem_activity_acc; 682 683 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 684 685 /* PMFW attached timestamp (10ns resolution) */ 686 uint64_t firmware_timestamp; 687 688 /* Voltage (mV) */ 689 uint16_t voltage_soc; 690 uint16_t voltage_gfx; 691 uint16_t voltage_mem; 692 693 uint16_t padding1; 694 695 /* Throttle status (ASIC independent) */ 696 uint64_t indep_throttle_status; 697 }; 698 699 /* 700 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 701 * Use gpu_metrics_v2_1 or later instead. 702 */ 703 struct gpu_metrics_v2_0 { 704 struct metrics_table_header common_header; 705 706 /* Driver attached timestamp (in ns) */ 707 uint64_t system_clock_counter; 708 709 /* Temperature */ 710 uint16_t temperature_gfx; // gfx temperature on APUs 711 uint16_t temperature_soc; // soc temperature on APUs 712 uint16_t temperature_core[8]; // CPU core temperature on APUs 713 uint16_t temperature_l3[2]; 714 715 /* Utilization */ 716 uint16_t average_gfx_activity; 717 uint16_t average_mm_activity; // UVD or VCN 718 719 /* Power/Energy */ 720 uint16_t average_socket_power; // dGPU + APU power on A + A platform 721 uint16_t average_cpu_power; 722 uint16_t average_soc_power; 723 uint16_t average_gfx_power; 724 uint16_t average_core_power[8]; // CPU core power on APUs 725 726 /* Average clocks */ 727 uint16_t average_gfxclk_frequency; 728 uint16_t average_socclk_frequency; 729 uint16_t average_uclk_frequency; 730 uint16_t average_fclk_frequency; 731 uint16_t average_vclk_frequency; 732 uint16_t average_dclk_frequency; 733 734 /* Current clocks */ 735 uint16_t current_gfxclk; 736 uint16_t current_socclk; 737 uint16_t current_uclk; 738 uint16_t current_fclk; 739 uint16_t current_vclk; 740 uint16_t current_dclk; 741 uint16_t current_coreclk[8]; // CPU core clocks 742 uint16_t current_l3clk[2]; 743 744 /* Throttle status */ 745 uint32_t throttle_status; 746 747 /* Fans */ 748 uint16_t fan_pwm; 749 750 uint16_t padding; 751 }; 752 753 struct gpu_metrics_v2_1 { 754 struct metrics_table_header common_header; 755 756 /* Temperature */ 757 uint16_t temperature_gfx; // gfx temperature on APUs 758 uint16_t temperature_soc; // soc temperature on APUs 759 uint16_t temperature_core[8]; // CPU core temperature on APUs 760 uint16_t temperature_l3[2]; 761 762 /* Utilization */ 763 uint16_t average_gfx_activity; 764 uint16_t average_mm_activity; // UVD or VCN 765 766 /* Driver attached timestamp (in ns) */ 767 uint64_t system_clock_counter; 768 769 /* Power/Energy */ 770 uint16_t average_socket_power; // dGPU + APU power on A + A platform 771 uint16_t average_cpu_power; 772 uint16_t average_soc_power; 773 uint16_t average_gfx_power; 774 uint16_t average_core_power[8]; // CPU core power on APUs 775 776 /* Average clocks */ 777 uint16_t average_gfxclk_frequency; 778 uint16_t average_socclk_frequency; 779 uint16_t average_uclk_frequency; 780 uint16_t average_fclk_frequency; 781 uint16_t average_vclk_frequency; 782 uint16_t average_dclk_frequency; 783 784 /* Current clocks */ 785 uint16_t current_gfxclk; 786 uint16_t current_socclk; 787 uint16_t current_uclk; 788 uint16_t current_fclk; 789 uint16_t current_vclk; 790 uint16_t current_dclk; 791 uint16_t current_coreclk[8]; // CPU core clocks 792 uint16_t current_l3clk[2]; 793 794 /* Throttle status */ 795 uint32_t throttle_status; 796 797 /* Fans */ 798 uint16_t fan_pwm; 799 800 uint16_t padding[3]; 801 }; 802 803 struct gpu_metrics_v2_2 { 804 struct metrics_table_header common_header; 805 806 /* Temperature */ 807 uint16_t temperature_gfx; // gfx temperature on APUs 808 uint16_t temperature_soc; // soc temperature on APUs 809 uint16_t temperature_core[8]; // CPU core temperature on APUs 810 uint16_t temperature_l3[2]; 811 812 /* Utilization */ 813 uint16_t average_gfx_activity; 814 uint16_t average_mm_activity; // UVD or VCN 815 816 /* Driver attached timestamp (in ns) */ 817 uint64_t system_clock_counter; 818 819 /* Power/Energy */ 820 uint16_t average_socket_power; // dGPU + APU power on A + A platform 821 uint16_t average_cpu_power; 822 uint16_t average_soc_power; 823 uint16_t average_gfx_power; 824 uint16_t average_core_power[8]; // CPU core power on APUs 825 826 /* Average clocks */ 827 uint16_t average_gfxclk_frequency; 828 uint16_t average_socclk_frequency; 829 uint16_t average_uclk_frequency; 830 uint16_t average_fclk_frequency; 831 uint16_t average_vclk_frequency; 832 uint16_t average_dclk_frequency; 833 834 /* Current clocks */ 835 uint16_t current_gfxclk; 836 uint16_t current_socclk; 837 uint16_t current_uclk; 838 uint16_t current_fclk; 839 uint16_t current_vclk; 840 uint16_t current_dclk; 841 uint16_t current_coreclk[8]; // CPU core clocks 842 uint16_t current_l3clk[2]; 843 844 /* Throttle status (ASIC dependent) */ 845 uint32_t throttle_status; 846 847 /* Fans */ 848 uint16_t fan_pwm; 849 850 uint16_t padding[3]; 851 852 /* Throttle status (ASIC independent) */ 853 uint64_t indep_throttle_status; 854 }; 855 856 struct gpu_metrics_v2_3 { 857 struct metrics_table_header common_header; 858 859 /* Temperature */ 860 uint16_t temperature_gfx; // gfx temperature on APUs 861 uint16_t temperature_soc; // soc temperature on APUs 862 uint16_t temperature_core[8]; // CPU core temperature on APUs 863 uint16_t temperature_l3[2]; 864 865 /* Utilization */ 866 uint16_t average_gfx_activity; 867 uint16_t average_mm_activity; // UVD or VCN 868 869 /* Driver attached timestamp (in ns) */ 870 uint64_t system_clock_counter; 871 872 /* Power/Energy */ 873 uint16_t average_socket_power; // dGPU + APU power on A + A platform 874 uint16_t average_cpu_power; 875 uint16_t average_soc_power; 876 uint16_t average_gfx_power; 877 uint16_t average_core_power[8]; // CPU core power on APUs 878 879 /* Average clocks */ 880 uint16_t average_gfxclk_frequency; 881 uint16_t average_socclk_frequency; 882 uint16_t average_uclk_frequency; 883 uint16_t average_fclk_frequency; 884 uint16_t average_vclk_frequency; 885 uint16_t average_dclk_frequency; 886 887 /* Current clocks */ 888 uint16_t current_gfxclk; 889 uint16_t current_socclk; 890 uint16_t current_uclk; 891 uint16_t current_fclk; 892 uint16_t current_vclk; 893 uint16_t current_dclk; 894 uint16_t current_coreclk[8]; // CPU core clocks 895 uint16_t current_l3clk[2]; 896 897 /* Throttle status (ASIC dependent) */ 898 uint32_t throttle_status; 899 900 /* Fans */ 901 uint16_t fan_pwm; 902 903 uint16_t padding[3]; 904 905 /* Throttle status (ASIC independent) */ 906 uint64_t indep_throttle_status; 907 908 /* Average Temperature */ 909 uint16_t average_temperature_gfx; // average gfx temperature on APUs 910 uint16_t average_temperature_soc; // average soc temperature on APUs 911 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 912 uint16_t average_temperature_l3[2]; 913 }; 914 915 struct gpu_metrics_v2_4 { 916 struct metrics_table_header common_header; 917 918 /* Temperature (unit: centi-Celsius) */ 919 uint16_t temperature_gfx; 920 uint16_t temperature_soc; 921 uint16_t temperature_core[8]; 922 uint16_t temperature_l3[2]; 923 924 /* Utilization (unit: centi) */ 925 uint16_t average_gfx_activity; 926 uint16_t average_mm_activity; 927 928 /* Driver attached timestamp (in ns) */ 929 uint64_t system_clock_counter; 930 931 /* Power/Energy (unit: mW) */ 932 uint16_t average_socket_power; 933 uint16_t average_cpu_power; 934 uint16_t average_soc_power; 935 uint16_t average_gfx_power; 936 uint16_t average_core_power[8]; 937 938 /* Average clocks (unit: MHz) */ 939 uint16_t average_gfxclk_frequency; 940 uint16_t average_socclk_frequency; 941 uint16_t average_uclk_frequency; 942 uint16_t average_fclk_frequency; 943 uint16_t average_vclk_frequency; 944 uint16_t average_dclk_frequency; 945 946 /* Current clocks (unit: MHz) */ 947 uint16_t current_gfxclk; 948 uint16_t current_socclk; 949 uint16_t current_uclk; 950 uint16_t current_fclk; 951 uint16_t current_vclk; 952 uint16_t current_dclk; 953 uint16_t current_coreclk[8]; 954 uint16_t current_l3clk[2]; 955 956 /* Throttle status (ASIC dependent) */ 957 uint32_t throttle_status; 958 959 /* Fans */ 960 uint16_t fan_pwm; 961 962 uint16_t padding[3]; 963 964 /* Throttle status (ASIC independent) */ 965 uint64_t indep_throttle_status; 966 967 /* Average Temperature (unit: centi-Celsius) */ 968 uint16_t average_temperature_gfx; 969 uint16_t average_temperature_soc; 970 uint16_t average_temperature_core[8]; 971 uint16_t average_temperature_l3[2]; 972 973 /* Power/Voltage (unit: mV) */ 974 uint16_t average_cpu_voltage; 975 uint16_t average_soc_voltage; 976 uint16_t average_gfx_voltage; 977 978 /* Power/Current (unit: mA) */ 979 uint16_t average_cpu_current; 980 uint16_t average_soc_current; 981 uint16_t average_gfx_current; 982 }; 983 #endif 984