1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 OD_FAN_ZERO_RPM_ENABLE, 123 OD_FAN_ZERO_RPM_STOP_TEMP, 124 }; 125 126 enum amd_pp_sensors { 127 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 128 AMDGPU_PP_SENSOR_CPU_CLK, 129 AMDGPU_PP_SENSOR_VDDNB, 130 AMDGPU_PP_SENSOR_VDDGFX, 131 AMDGPU_PP_SENSOR_UVD_VCLK, 132 AMDGPU_PP_SENSOR_UVD_DCLK, 133 AMDGPU_PP_SENSOR_VCE_ECCLK, 134 AMDGPU_PP_SENSOR_GPU_LOAD, 135 AMDGPU_PP_SENSOR_MEM_LOAD, 136 AMDGPU_PP_SENSOR_GFX_MCLK, 137 AMDGPU_PP_SENSOR_GPU_TEMP, 138 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 139 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 140 AMDGPU_PP_SENSOR_MEM_TEMP, 141 AMDGPU_PP_SENSOR_VCE_POWER, 142 AMDGPU_PP_SENSOR_UVD_POWER, 143 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 144 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 145 AMDGPU_PP_SENSOR_SS_APU_SHARE, 146 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 147 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 148 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 149 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 150 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 151 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 152 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 153 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 154 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 155 AMDGPU_PP_SENSOR_VCN_LOAD, 156 }; 157 158 enum amd_pp_task { 159 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 160 AMD_PP_TASK_ENABLE_USER_STATE, 161 AMD_PP_TASK_READJUST_POWER_STATE, 162 AMD_PP_TASK_COMPLETE_INIT, 163 AMD_PP_TASK_MAX 164 }; 165 166 enum PP_SMC_POWER_PROFILE { 167 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 168 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 169 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 170 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 171 PP_SMC_POWER_PROFILE_VR = 0x4, 172 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 173 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 174 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 175 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 176 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 177 PP_SMC_POWER_PROFILE_COUNT, 178 }; 179 180 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 181 182 183 184 enum { 185 PP_GROUP_UNKNOWN = 0, 186 PP_GROUP_GFX = 1, 187 PP_GROUP_SYS, 188 PP_GROUP_MAX 189 }; 190 191 enum PP_OD_DPM_TABLE_COMMAND { 192 PP_OD_EDIT_SCLK_VDDC_TABLE, 193 PP_OD_EDIT_MCLK_VDDC_TABLE, 194 PP_OD_EDIT_CCLK_VDDC_TABLE, 195 PP_OD_EDIT_VDDC_CURVE, 196 PP_OD_RESTORE_DEFAULT_TABLE, 197 PP_OD_COMMIT_DPM_TABLE, 198 PP_OD_EDIT_VDDGFX_OFFSET, 199 PP_OD_EDIT_FAN_CURVE, 200 PP_OD_EDIT_ACOUSTIC_LIMIT, 201 PP_OD_EDIT_ACOUSTIC_TARGET, 202 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 203 PP_OD_EDIT_FAN_MINIMUM_PWM, 204 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 205 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 206 }; 207 208 struct pp_states_info { 209 uint32_t nums; 210 uint32_t states[16]; 211 }; 212 213 enum PP_HWMON_TEMP { 214 PP_TEMP_EDGE = 0, 215 PP_TEMP_JUNCTION, 216 PP_TEMP_MEM, 217 PP_TEMP_MAX 218 }; 219 220 enum pp_mp1_state { 221 PP_MP1_STATE_NONE, 222 PP_MP1_STATE_SHUTDOWN, 223 PP_MP1_STATE_UNLOAD, 224 PP_MP1_STATE_RESET, 225 PP_MP1_STATE_FLR, 226 }; 227 228 enum pp_df_cstate { 229 DF_CSTATE_DISALLOW = 0, 230 DF_CSTATE_ALLOW, 231 }; 232 233 /** 234 * DOC: amdgpu_pp_power 235 * 236 * APU power is managed to system-level requirements through the PPT 237 * (package power tracking) feature. PPT is intended to limit power to the 238 * requirements of the power source and could be dynamically updated to 239 * maximize APU performance within the system power budget. 240 * 241 * Two types of power measurement can be requested, where supported, with 242 * :c:type:`enum pp_power_type <pp_power_type>`. 243 */ 244 245 /** 246 * enum pp_power_limit_level - Used to query the power limits 247 * 248 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 249 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 250 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 251 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 252 */ 253 enum pp_power_limit_level { 254 PP_PWR_LIMIT_MIN = -1, 255 PP_PWR_LIMIT_CURRENT, 256 PP_PWR_LIMIT_DEFAULT, 257 PP_PWR_LIMIT_MAX, 258 }; 259 260 /** 261 * enum pp_power_type - Used to specify the type of the requested power 262 * 263 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 264 * moving average of APU power (default ~5000 ms). 265 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 266 * where supported. 267 */ 268 enum pp_power_type { 269 PP_PWR_TYPE_SUSTAINED, 270 PP_PWR_TYPE_FAST, 271 }; 272 273 enum pp_xgmi_plpd_mode { 274 XGMI_PLPD_NONE = -1, 275 XGMI_PLPD_DISALLOW, 276 XGMI_PLPD_DEFAULT, 277 XGMI_PLPD_OPTIMIZED, 278 XGMI_PLPD_COUNT, 279 }; 280 281 enum pp_pm_policy { 282 PP_PM_POLICY_NONE = -1, 283 PP_PM_POLICY_SOC_PSTATE = 0, 284 PP_PM_POLICY_XGMI_PLPD, 285 PP_PM_POLICY_NUM, 286 }; 287 288 enum pp_policy_soc_pstate { 289 SOC_PSTATE_DEFAULT = 0, 290 SOC_PSTATE_0, 291 SOC_PSTATE_1, 292 SOC_PSTATE_2, 293 SOC_PSTAT_COUNT, 294 }; 295 296 #define PP_POLICY_MAX_LEVELS 5 297 298 #define PP_GROUP_MASK 0xF0000000 299 #define PP_GROUP_SHIFT 28 300 301 #define PP_BLOCK_MASK 0x0FFFFF00 302 #define PP_BLOCK_SHIFT 8 303 304 #define PP_BLOCK_GFX_CG 0x01 305 #define PP_BLOCK_GFX_MG 0x02 306 #define PP_BLOCK_GFX_3D 0x04 307 #define PP_BLOCK_GFX_RLC 0x08 308 #define PP_BLOCK_GFX_CP 0x10 309 #define PP_BLOCK_SYS_BIF 0x01 310 #define PP_BLOCK_SYS_MC 0x02 311 #define PP_BLOCK_SYS_ROM 0x04 312 #define PP_BLOCK_SYS_DRM 0x08 313 #define PP_BLOCK_SYS_HDP 0x10 314 #define PP_BLOCK_SYS_SDMA 0x20 315 316 #define PP_STATE_MASK 0x0000000F 317 #define PP_STATE_SHIFT 0 318 #define PP_STATE_SUPPORT_MASK 0x000000F0 319 #define PP_STATE_SUPPORT_SHIFT 0 320 321 #define PP_STATE_CG 0x01 322 #define PP_STATE_LS 0x02 323 #define PP_STATE_DS 0x04 324 #define PP_STATE_SD 0x08 325 #define PP_STATE_SUPPORT_CG 0x10 326 #define PP_STATE_SUPPORT_LS 0x20 327 #define PP_STATE_SUPPORT_DS 0x40 328 #define PP_STATE_SUPPORT_SD 0x80 329 330 #define PP_CG_MSG_ID(group, block, support, state) \ 331 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 332 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 333 334 #define XGMI_MODE_PSTATE_D3 0 335 #define XGMI_MODE_PSTATE_D0 1 336 337 #define NUM_HBM_INSTANCES 4 338 #define NUM_XGMI_LINKS 8 339 #define MAX_GFX_CLKS 8 340 #define MAX_CLKS 4 341 #define NUM_VCN 4 342 #define NUM_JPEG_ENG 32 343 #define MAX_XCC 8 344 #define NUM_XCP 8 345 struct seq_file; 346 enum amd_pp_clock_type; 347 struct amd_pp_simple_clock_info; 348 struct amd_pp_display_configuration; 349 struct amd_pp_clock_info; 350 struct pp_display_clock_request; 351 struct pp_clock_levels_with_voltage; 352 struct pp_clock_levels_with_latency; 353 struct amd_pp_clocks; 354 struct pp_smu_wm_range_sets; 355 struct pp_smu_nv_clock_table; 356 struct dpm_clocks; 357 358 struct amdgpu_xcp_metrics { 359 /* Utilization Instantaneous (%) */ 360 uint32_t gfx_busy_inst[MAX_XCC]; 361 uint16_t jpeg_busy[NUM_JPEG_ENG]; 362 uint16_t vcn_busy[NUM_VCN]; 363 /* Utilization Accumulated (%) */ 364 uint64_t gfx_busy_acc[MAX_XCC]; 365 }; 366 367 struct amdgpu_xcp_metrics_v1_1 { 368 /* Utilization Instantaneous (%) */ 369 uint32_t gfx_busy_inst[MAX_XCC]; 370 uint16_t jpeg_busy[NUM_JPEG_ENG]; 371 uint16_t vcn_busy[NUM_VCN]; 372 /* Utilization Accumulated (%) */ 373 uint64_t gfx_busy_acc[MAX_XCC]; 374 /* Total App Clock Counter Accumulated */ 375 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 376 }; 377 378 struct amd_pm_funcs { 379 /* export for dpm on ci and si */ 380 int (*pre_set_power_state)(void *handle); 381 int (*set_power_state)(void *handle); 382 void (*post_set_power_state)(void *handle); 383 void (*display_configuration_changed)(void *handle); 384 void (*print_power_state)(void *handle, void *ps); 385 bool (*vblank_too_short)(void *handle); 386 void (*enable_bapm)(void *handle, bool enable); 387 int (*check_state_equal)(void *handle, 388 void *cps, 389 void *rps, 390 bool *equal); 391 /* export for sysfs */ 392 int (*set_fan_control_mode)(void *handle, u32 mode); 393 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 394 int (*set_fan_speed_pwm)(void *handle, u32 speed); 395 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 396 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 397 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 398 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 399 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 400 int (*get_sclk_od)(void *handle); 401 int (*set_sclk_od)(void *handle, uint32_t value); 402 int (*get_mclk_od)(void *handle); 403 int (*set_mclk_od)(void *handle, uint32_t value); 404 int (*read_sensor)(void *handle, int idx, void *value, int *size); 405 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 406 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 407 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 408 enum amd_pm_state_type (*get_current_power_state)(void *handle); 409 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 410 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 411 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 412 int (*get_pp_table)(void *handle, char **table); 413 int (*set_pp_table)(void *handle, const char *buf, size_t size); 414 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 415 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 416 /* export to amdgpu */ 417 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 418 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 419 enum amd_pm_state_type *user_state); 420 int (*load_firmware)(void *handle); 421 int (*wait_for_fw_loading_complete)(void *handle); 422 int (*set_powergating_by_smu)(void *handle, 423 uint32_t block_type, bool gate); 424 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 425 int (*set_power_limit)(void *handle, uint32_t n); 426 int (*get_power_limit)(void *handle, uint32_t *limit, 427 enum pp_power_limit_level pp_limit_level, 428 enum pp_power_type power_type); 429 int (*get_power_profile_mode)(void *handle, char *buf); 430 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 431 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 432 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 433 long *input, uint32_t size); 434 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 435 int (*smu_i2c_bus_access)(void *handle, bool acquire); 436 int (*gfx_state_change_set)(void *handle, uint32_t state); 437 /* export to DC */ 438 u32 (*get_sclk)(void *handle, bool low); 439 u32 (*get_mclk)(void *handle, bool low); 440 int (*display_configuration_change)(void *handle, 441 const struct amd_pp_display_configuration *input); 442 int (*get_display_power_level)(void *handle, 443 struct amd_pp_simple_clock_info *output); 444 int (*get_current_clocks)(void *handle, 445 struct amd_pp_clock_info *clocks); 446 int (*get_clock_by_type)(void *handle, 447 enum amd_pp_clock_type type, 448 struct amd_pp_clocks *clocks); 449 int (*get_clock_by_type_with_latency)(void *handle, 450 enum amd_pp_clock_type type, 451 struct pp_clock_levels_with_latency *clocks); 452 int (*get_clock_by_type_with_voltage)(void *handle, 453 enum amd_pp_clock_type type, 454 struct pp_clock_levels_with_voltage *clocks); 455 int (*set_watermarks_for_clocks_ranges)(void *handle, 456 void *clock_ranges); 457 int (*display_clock_voltage_request)(void *handle, 458 struct pp_display_clock_request *clock); 459 int (*get_display_mode_validation_clocks)(void *handle, 460 struct amd_pp_simple_clock_info *clocks); 461 int (*notify_smu_enable_pwe)(void *handle); 462 int (*enable_mgpu_fan_boost)(void *handle); 463 int (*set_active_display_count)(void *handle, uint32_t count); 464 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 465 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 466 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 467 int (*get_asic_baco_capability)(void *handle); 468 int (*get_asic_baco_state)(void *handle, int *state); 469 int (*set_asic_baco_state)(void *handle, int state); 470 int (*get_ppfeature_status)(void *handle, char *buf); 471 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 472 int (*asic_reset_mode_2)(void *handle); 473 int (*asic_reset_enable_gfx_features)(void *handle); 474 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 475 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 476 ssize_t (*get_gpu_metrics)(void *handle, void **table); 477 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 478 int (*set_watermarks_for_clock_ranges)(void *handle, 479 struct pp_smu_wm_range_sets *ranges); 480 int (*display_disable_memory_clock_switch)(void *handle, 481 bool disable_memory_clock_switch); 482 int (*get_max_sustainable_clocks_by_dc)(void *handle, 483 struct pp_smu_nv_clock_table *max_clocks); 484 int (*get_uclk_dpm_states)(void *handle, 485 unsigned int *clock_values_in_khz, 486 unsigned int *num_states); 487 int (*get_dpm_clock_table)(void *handle, 488 struct dpm_clocks *clock_table); 489 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 490 void (*pm_compute_clocks)(void *handle); 491 int (*notify_rlc_state)(void *handle, bool en); 492 }; 493 494 struct metrics_table_header { 495 uint16_t structure_size; 496 uint8_t format_revision; 497 uint8_t content_revision; 498 }; 499 500 /* 501 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 502 * Use gpu_metrics_v1_1 or later instead. 503 */ 504 struct gpu_metrics_v1_0 { 505 struct metrics_table_header common_header; 506 507 /* Driver attached timestamp (in ns) */ 508 uint64_t system_clock_counter; 509 510 /* Temperature */ 511 uint16_t temperature_edge; 512 uint16_t temperature_hotspot; 513 uint16_t temperature_mem; 514 uint16_t temperature_vrgfx; 515 uint16_t temperature_vrsoc; 516 uint16_t temperature_vrmem; 517 518 /* Utilization */ 519 uint16_t average_gfx_activity; 520 uint16_t average_umc_activity; // memory controller 521 uint16_t average_mm_activity; // UVD or VCN 522 523 /* Power/Energy */ 524 uint16_t average_socket_power; 525 uint32_t energy_accumulator; 526 527 /* Average clocks */ 528 uint16_t average_gfxclk_frequency; 529 uint16_t average_socclk_frequency; 530 uint16_t average_uclk_frequency; 531 uint16_t average_vclk0_frequency; 532 uint16_t average_dclk0_frequency; 533 uint16_t average_vclk1_frequency; 534 uint16_t average_dclk1_frequency; 535 536 /* Current clocks */ 537 uint16_t current_gfxclk; 538 uint16_t current_socclk; 539 uint16_t current_uclk; 540 uint16_t current_vclk0; 541 uint16_t current_dclk0; 542 uint16_t current_vclk1; 543 uint16_t current_dclk1; 544 545 /* Throttle status */ 546 uint32_t throttle_status; 547 548 /* Fans */ 549 uint16_t current_fan_speed; 550 551 /* Link width/speed */ 552 uint8_t pcie_link_width; 553 uint8_t pcie_link_speed; // in 0.1 GT/s 554 }; 555 556 struct gpu_metrics_v1_1 { 557 struct metrics_table_header common_header; 558 559 /* Temperature */ 560 uint16_t temperature_edge; 561 uint16_t temperature_hotspot; 562 uint16_t temperature_mem; 563 uint16_t temperature_vrgfx; 564 uint16_t temperature_vrsoc; 565 uint16_t temperature_vrmem; 566 567 /* Utilization */ 568 uint16_t average_gfx_activity; 569 uint16_t average_umc_activity; // memory controller 570 uint16_t average_mm_activity; // UVD or VCN 571 572 /* Power/Energy */ 573 uint16_t average_socket_power; 574 uint64_t energy_accumulator; 575 576 /* Driver attached timestamp (in ns) */ 577 uint64_t system_clock_counter; 578 579 /* Average clocks */ 580 uint16_t average_gfxclk_frequency; 581 uint16_t average_socclk_frequency; 582 uint16_t average_uclk_frequency; 583 uint16_t average_vclk0_frequency; 584 uint16_t average_dclk0_frequency; 585 uint16_t average_vclk1_frequency; 586 uint16_t average_dclk1_frequency; 587 588 /* Current clocks */ 589 uint16_t current_gfxclk; 590 uint16_t current_socclk; 591 uint16_t current_uclk; 592 uint16_t current_vclk0; 593 uint16_t current_dclk0; 594 uint16_t current_vclk1; 595 uint16_t current_dclk1; 596 597 /* Throttle status */ 598 uint32_t throttle_status; 599 600 /* Fans */ 601 uint16_t current_fan_speed; 602 603 /* Link width/speed */ 604 uint16_t pcie_link_width; 605 uint16_t pcie_link_speed; // in 0.1 GT/s 606 607 uint16_t padding; 608 609 uint32_t gfx_activity_acc; 610 uint32_t mem_activity_acc; 611 612 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 613 }; 614 615 struct gpu_metrics_v1_2 { 616 struct metrics_table_header common_header; 617 618 /* Temperature */ 619 uint16_t temperature_edge; 620 uint16_t temperature_hotspot; 621 uint16_t temperature_mem; 622 uint16_t temperature_vrgfx; 623 uint16_t temperature_vrsoc; 624 uint16_t temperature_vrmem; 625 626 /* Utilization */ 627 uint16_t average_gfx_activity; 628 uint16_t average_umc_activity; // memory controller 629 uint16_t average_mm_activity; // UVD or VCN 630 631 /* Power/Energy */ 632 uint16_t average_socket_power; 633 uint64_t energy_accumulator; 634 635 /* Driver attached timestamp (in ns) */ 636 uint64_t system_clock_counter; 637 638 /* Average clocks */ 639 uint16_t average_gfxclk_frequency; 640 uint16_t average_socclk_frequency; 641 uint16_t average_uclk_frequency; 642 uint16_t average_vclk0_frequency; 643 uint16_t average_dclk0_frequency; 644 uint16_t average_vclk1_frequency; 645 uint16_t average_dclk1_frequency; 646 647 /* Current clocks */ 648 uint16_t current_gfxclk; 649 uint16_t current_socclk; 650 uint16_t current_uclk; 651 uint16_t current_vclk0; 652 uint16_t current_dclk0; 653 uint16_t current_vclk1; 654 uint16_t current_dclk1; 655 656 /* Throttle status (ASIC dependent) */ 657 uint32_t throttle_status; 658 659 /* Fans */ 660 uint16_t current_fan_speed; 661 662 /* Link width/speed */ 663 uint16_t pcie_link_width; 664 uint16_t pcie_link_speed; // in 0.1 GT/s 665 666 uint16_t padding; 667 668 uint32_t gfx_activity_acc; 669 uint32_t mem_activity_acc; 670 671 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 672 673 /* PMFW attached timestamp (10ns resolution) */ 674 uint64_t firmware_timestamp; 675 }; 676 677 struct gpu_metrics_v1_3 { 678 struct metrics_table_header common_header; 679 680 /* Temperature */ 681 uint16_t temperature_edge; 682 uint16_t temperature_hotspot; 683 uint16_t temperature_mem; 684 uint16_t temperature_vrgfx; 685 uint16_t temperature_vrsoc; 686 uint16_t temperature_vrmem; 687 688 /* Utilization */ 689 uint16_t average_gfx_activity; 690 uint16_t average_umc_activity; // memory controller 691 uint16_t average_mm_activity; // UVD or VCN 692 693 /* Power/Energy */ 694 uint16_t average_socket_power; 695 uint64_t energy_accumulator; 696 697 /* Driver attached timestamp (in ns) */ 698 uint64_t system_clock_counter; 699 700 /* Average clocks */ 701 uint16_t average_gfxclk_frequency; 702 uint16_t average_socclk_frequency; 703 uint16_t average_uclk_frequency; 704 uint16_t average_vclk0_frequency; 705 uint16_t average_dclk0_frequency; 706 uint16_t average_vclk1_frequency; 707 uint16_t average_dclk1_frequency; 708 709 /* Current clocks */ 710 uint16_t current_gfxclk; 711 uint16_t current_socclk; 712 uint16_t current_uclk; 713 uint16_t current_vclk0; 714 uint16_t current_dclk0; 715 uint16_t current_vclk1; 716 uint16_t current_dclk1; 717 718 /* Throttle status */ 719 uint32_t throttle_status; 720 721 /* Fans */ 722 uint16_t current_fan_speed; 723 724 /* Link width/speed */ 725 uint16_t pcie_link_width; 726 uint16_t pcie_link_speed; // in 0.1 GT/s 727 728 uint16_t padding; 729 730 uint32_t gfx_activity_acc; 731 uint32_t mem_activity_acc; 732 733 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 734 735 /* PMFW attached timestamp (10ns resolution) */ 736 uint64_t firmware_timestamp; 737 738 /* Voltage (mV) */ 739 uint16_t voltage_soc; 740 uint16_t voltage_gfx; 741 uint16_t voltage_mem; 742 743 uint16_t padding1; 744 745 /* Throttle status (ASIC independent) */ 746 uint64_t indep_throttle_status; 747 }; 748 749 struct gpu_metrics_v1_4 { 750 struct metrics_table_header common_header; 751 752 /* Temperature (Celsius) */ 753 uint16_t temperature_hotspot; 754 uint16_t temperature_mem; 755 uint16_t temperature_vrsoc; 756 757 /* Power (Watts) */ 758 uint16_t curr_socket_power; 759 760 /* Utilization (%) */ 761 uint16_t average_gfx_activity; 762 uint16_t average_umc_activity; // memory controller 763 uint16_t vcn_activity[NUM_VCN]; 764 765 /* Energy (15.259uJ (2^-16) units) */ 766 uint64_t energy_accumulator; 767 768 /* Driver attached timestamp (in ns) */ 769 uint64_t system_clock_counter; 770 771 /* Throttle status */ 772 uint32_t throttle_status; 773 774 /* Clock Lock Status. Each bit corresponds to clock instance */ 775 uint32_t gfxclk_lock_status; 776 777 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 778 uint16_t pcie_link_width; 779 uint16_t pcie_link_speed; 780 781 /* XGMI bus width and bitrate (in Gbps) */ 782 uint16_t xgmi_link_width; 783 uint16_t xgmi_link_speed; 784 785 /* Utilization Accumulated (%) */ 786 uint32_t gfx_activity_acc; 787 uint32_t mem_activity_acc; 788 789 /*PCIE accumulated bandwidth (GB/sec) */ 790 uint64_t pcie_bandwidth_acc; 791 792 /*PCIE instantaneous bandwidth (GB/sec) */ 793 uint64_t pcie_bandwidth_inst; 794 795 /* PCIE L0 to recovery state transition accumulated count */ 796 uint64_t pcie_l0_to_recov_count_acc; 797 798 /* PCIE replay accumulated count */ 799 uint64_t pcie_replay_count_acc; 800 801 /* PCIE replay rollover accumulated count */ 802 uint64_t pcie_replay_rover_count_acc; 803 804 /* XGMI accumulated data transfer size(KiloBytes) */ 805 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 806 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 807 808 /* PMFW attached timestamp (10ns resolution) */ 809 uint64_t firmware_timestamp; 810 811 /* Current clocks (Mhz) */ 812 uint16_t current_gfxclk[MAX_GFX_CLKS]; 813 uint16_t current_socclk[MAX_CLKS]; 814 uint16_t current_vclk0[MAX_CLKS]; 815 uint16_t current_dclk0[MAX_CLKS]; 816 uint16_t current_uclk; 817 818 uint16_t padding; 819 }; 820 821 struct gpu_metrics_v1_5 { 822 struct metrics_table_header common_header; 823 824 /* Temperature (Celsius) */ 825 uint16_t temperature_hotspot; 826 uint16_t temperature_mem; 827 uint16_t temperature_vrsoc; 828 829 /* Power (Watts) */ 830 uint16_t curr_socket_power; 831 832 /* Utilization (%) */ 833 uint16_t average_gfx_activity; 834 uint16_t average_umc_activity; // memory controller 835 uint16_t vcn_activity[NUM_VCN]; 836 uint16_t jpeg_activity[NUM_JPEG_ENG]; 837 838 /* Energy (15.259uJ (2^-16) units) */ 839 uint64_t energy_accumulator; 840 841 /* Driver attached timestamp (in ns) */ 842 uint64_t system_clock_counter; 843 844 /* Throttle status */ 845 uint32_t throttle_status; 846 847 /* Clock Lock Status. Each bit corresponds to clock instance */ 848 uint32_t gfxclk_lock_status; 849 850 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 851 uint16_t pcie_link_width; 852 uint16_t pcie_link_speed; 853 854 /* XGMI bus width and bitrate (in Gbps) */ 855 uint16_t xgmi_link_width; 856 uint16_t xgmi_link_speed; 857 858 /* Utilization Accumulated (%) */ 859 uint32_t gfx_activity_acc; 860 uint32_t mem_activity_acc; 861 862 /*PCIE accumulated bandwidth (GB/sec) */ 863 uint64_t pcie_bandwidth_acc; 864 865 /*PCIE instantaneous bandwidth (GB/sec) */ 866 uint64_t pcie_bandwidth_inst; 867 868 /* PCIE L0 to recovery state transition accumulated count */ 869 uint64_t pcie_l0_to_recov_count_acc; 870 871 /* PCIE replay accumulated count */ 872 uint64_t pcie_replay_count_acc; 873 874 /* PCIE replay rollover accumulated count */ 875 uint64_t pcie_replay_rover_count_acc; 876 877 /* PCIE NAK sent accumulated count */ 878 uint32_t pcie_nak_sent_count_acc; 879 880 /* PCIE NAK received accumulated count */ 881 uint32_t pcie_nak_rcvd_count_acc; 882 883 /* XGMI accumulated data transfer size(KiloBytes) */ 884 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 885 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 886 887 /* PMFW attached timestamp (10ns resolution) */ 888 uint64_t firmware_timestamp; 889 890 /* Current clocks (Mhz) */ 891 uint16_t current_gfxclk[MAX_GFX_CLKS]; 892 uint16_t current_socclk[MAX_CLKS]; 893 uint16_t current_vclk0[MAX_CLKS]; 894 uint16_t current_dclk0[MAX_CLKS]; 895 uint16_t current_uclk; 896 897 uint16_t padding; 898 }; 899 900 struct gpu_metrics_v1_6 { 901 struct metrics_table_header common_header; 902 903 /* Temperature (Celsius) */ 904 uint16_t temperature_hotspot; 905 uint16_t temperature_mem; 906 uint16_t temperature_vrsoc; 907 908 /* Power (Watts) */ 909 uint16_t curr_socket_power; 910 911 /* Utilization (%) */ 912 uint16_t average_gfx_activity; 913 uint16_t average_umc_activity; // memory controller 914 915 /* Energy (15.259uJ (2^-16) units) */ 916 uint64_t energy_accumulator; 917 918 /* Driver attached timestamp (in ns) */ 919 uint64_t system_clock_counter; 920 921 /* Accumulation cycle counter */ 922 uint32_t accumulation_counter; 923 924 /* Accumulated throttler residencies */ 925 uint32_t prochot_residency_acc; 926 uint32_t ppt_residency_acc; 927 uint32_t socket_thm_residency_acc; 928 uint32_t vr_thm_residency_acc; 929 uint32_t hbm_thm_residency_acc; 930 931 /* Clock Lock Status. Each bit corresponds to clock instance */ 932 uint32_t gfxclk_lock_status; 933 934 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 935 uint16_t pcie_link_width; 936 uint16_t pcie_link_speed; 937 938 /* XGMI bus width and bitrate (in Gbps) */ 939 uint16_t xgmi_link_width; 940 uint16_t xgmi_link_speed; 941 942 /* Utilization Accumulated (%) */ 943 uint32_t gfx_activity_acc; 944 uint32_t mem_activity_acc; 945 946 /*PCIE accumulated bandwidth (GB/sec) */ 947 uint64_t pcie_bandwidth_acc; 948 949 /*PCIE instantaneous bandwidth (GB/sec) */ 950 uint64_t pcie_bandwidth_inst; 951 952 /* PCIE L0 to recovery state transition accumulated count */ 953 uint64_t pcie_l0_to_recov_count_acc; 954 955 /* PCIE replay accumulated count */ 956 uint64_t pcie_replay_count_acc; 957 958 /* PCIE replay rollover accumulated count */ 959 uint64_t pcie_replay_rover_count_acc; 960 961 /* PCIE NAK sent accumulated count */ 962 uint32_t pcie_nak_sent_count_acc; 963 964 /* PCIE NAK received accumulated count */ 965 uint32_t pcie_nak_rcvd_count_acc; 966 967 /* XGMI accumulated data transfer size(KiloBytes) */ 968 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 969 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 970 971 /* PMFW attached timestamp (10ns resolution) */ 972 uint64_t firmware_timestamp; 973 974 /* Current clocks (Mhz) */ 975 uint16_t current_gfxclk[MAX_GFX_CLKS]; 976 uint16_t current_socclk[MAX_CLKS]; 977 uint16_t current_vclk0[MAX_CLKS]; 978 uint16_t current_dclk0[MAX_CLKS]; 979 uint16_t current_uclk; 980 981 /* Number of current partition */ 982 uint16_t num_partition; 983 984 /* XCP metrics stats */ 985 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 986 987 /* PCIE other end recovery counter */ 988 uint32_t pcie_lc_perf_other_end_recovery; 989 }; 990 991 struct gpu_metrics_v1_7 { 992 struct metrics_table_header common_header; 993 994 /* Temperature (Celsius) */ 995 uint16_t temperature_hotspot; 996 uint16_t temperature_mem; 997 uint16_t temperature_vrsoc; 998 999 /* Power (Watts) */ 1000 uint16_t curr_socket_power; 1001 1002 /* Utilization (%) */ 1003 uint16_t average_gfx_activity; 1004 uint16_t average_umc_activity; // memory controller 1005 1006 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1007 uint64_t mem_max_bandwidth; 1008 1009 /* Energy (15.259uJ (2^-16) units) */ 1010 uint64_t energy_accumulator; 1011 1012 /* Driver attached timestamp (in ns) */ 1013 uint64_t system_clock_counter; 1014 1015 /* Accumulation cycle counter */ 1016 uint32_t accumulation_counter; 1017 1018 /* Accumulated throttler residencies */ 1019 uint32_t prochot_residency_acc; 1020 uint32_t ppt_residency_acc; 1021 uint32_t socket_thm_residency_acc; 1022 uint32_t vr_thm_residency_acc; 1023 uint32_t hbm_thm_residency_acc; 1024 1025 /* Clock Lock Status. Each bit corresponds to clock instance */ 1026 uint32_t gfxclk_lock_status; 1027 1028 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1029 uint16_t pcie_link_width; 1030 uint16_t pcie_link_speed; 1031 1032 /* XGMI bus width and bitrate (in Gbps) */ 1033 uint16_t xgmi_link_width; 1034 uint16_t xgmi_link_speed; 1035 1036 /* Utilization Accumulated (%) */ 1037 uint32_t gfx_activity_acc; 1038 uint32_t mem_activity_acc; 1039 1040 /*PCIE accumulated bandwidth (GB/sec) */ 1041 uint64_t pcie_bandwidth_acc; 1042 1043 /*PCIE instantaneous bandwidth (GB/sec) */ 1044 uint64_t pcie_bandwidth_inst; 1045 1046 /* PCIE L0 to recovery state transition accumulated count */ 1047 uint64_t pcie_l0_to_recov_count_acc; 1048 1049 /* PCIE replay accumulated count */ 1050 uint64_t pcie_replay_count_acc; 1051 1052 /* PCIE replay rollover accumulated count */ 1053 uint64_t pcie_replay_rover_count_acc; 1054 1055 /* PCIE NAK sent accumulated count */ 1056 uint32_t pcie_nak_sent_count_acc; 1057 1058 /* PCIE NAK received accumulated count */ 1059 uint32_t pcie_nak_rcvd_count_acc; 1060 1061 /* XGMI accumulated data transfer size(KiloBytes) */ 1062 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1063 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1064 1065 /* XGMI link status(active/inactive) */ 1066 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1067 1068 uint16_t padding; 1069 1070 /* PMFW attached timestamp (10ns resolution) */ 1071 uint64_t firmware_timestamp; 1072 1073 /* Current clocks (Mhz) */ 1074 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1075 uint16_t current_socclk[MAX_CLKS]; 1076 uint16_t current_vclk0[MAX_CLKS]; 1077 uint16_t current_dclk0[MAX_CLKS]; 1078 uint16_t current_uclk; 1079 1080 /* Number of current partition */ 1081 uint16_t num_partition; 1082 1083 /* XCP metrics stats */ 1084 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1085 1086 /* PCIE other end recovery counter */ 1087 uint32_t pcie_lc_perf_other_end_recovery; 1088 }; 1089 1090 /* 1091 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1092 * Use gpu_metrics_v2_1 or later instead. 1093 */ 1094 struct gpu_metrics_v2_0 { 1095 struct metrics_table_header common_header; 1096 1097 /* Driver attached timestamp (in ns) */ 1098 uint64_t system_clock_counter; 1099 1100 /* Temperature */ 1101 uint16_t temperature_gfx; // gfx temperature on APUs 1102 uint16_t temperature_soc; // soc temperature on APUs 1103 uint16_t temperature_core[8]; // CPU core temperature on APUs 1104 uint16_t temperature_l3[2]; 1105 1106 /* Utilization */ 1107 uint16_t average_gfx_activity; 1108 uint16_t average_mm_activity; // UVD or VCN 1109 1110 /* Power/Energy */ 1111 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1112 uint16_t average_cpu_power; 1113 uint16_t average_soc_power; 1114 uint16_t average_gfx_power; 1115 uint16_t average_core_power[8]; // CPU core power on APUs 1116 1117 /* Average clocks */ 1118 uint16_t average_gfxclk_frequency; 1119 uint16_t average_socclk_frequency; 1120 uint16_t average_uclk_frequency; 1121 uint16_t average_fclk_frequency; 1122 uint16_t average_vclk_frequency; 1123 uint16_t average_dclk_frequency; 1124 1125 /* Current clocks */ 1126 uint16_t current_gfxclk; 1127 uint16_t current_socclk; 1128 uint16_t current_uclk; 1129 uint16_t current_fclk; 1130 uint16_t current_vclk; 1131 uint16_t current_dclk; 1132 uint16_t current_coreclk[8]; // CPU core clocks 1133 uint16_t current_l3clk[2]; 1134 1135 /* Throttle status */ 1136 uint32_t throttle_status; 1137 1138 /* Fans */ 1139 uint16_t fan_pwm; 1140 1141 uint16_t padding; 1142 }; 1143 1144 struct gpu_metrics_v2_1 { 1145 struct metrics_table_header common_header; 1146 1147 /* Temperature */ 1148 uint16_t temperature_gfx; // gfx temperature on APUs 1149 uint16_t temperature_soc; // soc temperature on APUs 1150 uint16_t temperature_core[8]; // CPU core temperature on APUs 1151 uint16_t temperature_l3[2]; 1152 1153 /* Utilization */ 1154 uint16_t average_gfx_activity; 1155 uint16_t average_mm_activity; // UVD or VCN 1156 1157 /* Driver attached timestamp (in ns) */ 1158 uint64_t system_clock_counter; 1159 1160 /* Power/Energy */ 1161 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1162 uint16_t average_cpu_power; 1163 uint16_t average_soc_power; 1164 uint16_t average_gfx_power; 1165 uint16_t average_core_power[8]; // CPU core power on APUs 1166 1167 /* Average clocks */ 1168 uint16_t average_gfxclk_frequency; 1169 uint16_t average_socclk_frequency; 1170 uint16_t average_uclk_frequency; 1171 uint16_t average_fclk_frequency; 1172 uint16_t average_vclk_frequency; 1173 uint16_t average_dclk_frequency; 1174 1175 /* Current clocks */ 1176 uint16_t current_gfxclk; 1177 uint16_t current_socclk; 1178 uint16_t current_uclk; 1179 uint16_t current_fclk; 1180 uint16_t current_vclk; 1181 uint16_t current_dclk; 1182 uint16_t current_coreclk[8]; // CPU core clocks 1183 uint16_t current_l3clk[2]; 1184 1185 /* Throttle status */ 1186 uint32_t throttle_status; 1187 1188 /* Fans */ 1189 uint16_t fan_pwm; 1190 1191 uint16_t padding[3]; 1192 }; 1193 1194 struct gpu_metrics_v2_2 { 1195 struct metrics_table_header common_header; 1196 1197 /* Temperature */ 1198 uint16_t temperature_gfx; // gfx temperature on APUs 1199 uint16_t temperature_soc; // soc temperature on APUs 1200 uint16_t temperature_core[8]; // CPU core temperature on APUs 1201 uint16_t temperature_l3[2]; 1202 1203 /* Utilization */ 1204 uint16_t average_gfx_activity; 1205 uint16_t average_mm_activity; // UVD or VCN 1206 1207 /* Driver attached timestamp (in ns) */ 1208 uint64_t system_clock_counter; 1209 1210 /* Power/Energy */ 1211 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1212 uint16_t average_cpu_power; 1213 uint16_t average_soc_power; 1214 uint16_t average_gfx_power; 1215 uint16_t average_core_power[8]; // CPU core power on APUs 1216 1217 /* Average clocks */ 1218 uint16_t average_gfxclk_frequency; 1219 uint16_t average_socclk_frequency; 1220 uint16_t average_uclk_frequency; 1221 uint16_t average_fclk_frequency; 1222 uint16_t average_vclk_frequency; 1223 uint16_t average_dclk_frequency; 1224 1225 /* Current clocks */ 1226 uint16_t current_gfxclk; 1227 uint16_t current_socclk; 1228 uint16_t current_uclk; 1229 uint16_t current_fclk; 1230 uint16_t current_vclk; 1231 uint16_t current_dclk; 1232 uint16_t current_coreclk[8]; // CPU core clocks 1233 uint16_t current_l3clk[2]; 1234 1235 /* Throttle status (ASIC dependent) */ 1236 uint32_t throttle_status; 1237 1238 /* Fans */ 1239 uint16_t fan_pwm; 1240 1241 uint16_t padding[3]; 1242 1243 /* Throttle status (ASIC independent) */ 1244 uint64_t indep_throttle_status; 1245 }; 1246 1247 struct gpu_metrics_v2_3 { 1248 struct metrics_table_header common_header; 1249 1250 /* Temperature */ 1251 uint16_t temperature_gfx; // gfx temperature on APUs 1252 uint16_t temperature_soc; // soc temperature on APUs 1253 uint16_t temperature_core[8]; // CPU core temperature on APUs 1254 uint16_t temperature_l3[2]; 1255 1256 /* Utilization */ 1257 uint16_t average_gfx_activity; 1258 uint16_t average_mm_activity; // UVD or VCN 1259 1260 /* Driver attached timestamp (in ns) */ 1261 uint64_t system_clock_counter; 1262 1263 /* Power/Energy */ 1264 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1265 uint16_t average_cpu_power; 1266 uint16_t average_soc_power; 1267 uint16_t average_gfx_power; 1268 uint16_t average_core_power[8]; // CPU core power on APUs 1269 1270 /* Average clocks */ 1271 uint16_t average_gfxclk_frequency; 1272 uint16_t average_socclk_frequency; 1273 uint16_t average_uclk_frequency; 1274 uint16_t average_fclk_frequency; 1275 uint16_t average_vclk_frequency; 1276 uint16_t average_dclk_frequency; 1277 1278 /* Current clocks */ 1279 uint16_t current_gfxclk; 1280 uint16_t current_socclk; 1281 uint16_t current_uclk; 1282 uint16_t current_fclk; 1283 uint16_t current_vclk; 1284 uint16_t current_dclk; 1285 uint16_t current_coreclk[8]; // CPU core clocks 1286 uint16_t current_l3clk[2]; 1287 1288 /* Throttle status (ASIC dependent) */ 1289 uint32_t throttle_status; 1290 1291 /* Fans */ 1292 uint16_t fan_pwm; 1293 1294 uint16_t padding[3]; 1295 1296 /* Throttle status (ASIC independent) */ 1297 uint64_t indep_throttle_status; 1298 1299 /* Average Temperature */ 1300 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1301 uint16_t average_temperature_soc; // average soc temperature on APUs 1302 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1303 uint16_t average_temperature_l3[2]; 1304 }; 1305 1306 struct gpu_metrics_v2_4 { 1307 struct metrics_table_header common_header; 1308 1309 /* Temperature (unit: centi-Celsius) */ 1310 uint16_t temperature_gfx; 1311 uint16_t temperature_soc; 1312 uint16_t temperature_core[8]; 1313 uint16_t temperature_l3[2]; 1314 1315 /* Utilization (unit: centi) */ 1316 uint16_t average_gfx_activity; 1317 uint16_t average_mm_activity; 1318 1319 /* Driver attached timestamp (in ns) */ 1320 uint64_t system_clock_counter; 1321 1322 /* Power/Energy (unit: mW) */ 1323 uint16_t average_socket_power; 1324 uint16_t average_cpu_power; 1325 uint16_t average_soc_power; 1326 uint16_t average_gfx_power; 1327 uint16_t average_core_power[8]; 1328 1329 /* Average clocks (unit: MHz) */ 1330 uint16_t average_gfxclk_frequency; 1331 uint16_t average_socclk_frequency; 1332 uint16_t average_uclk_frequency; 1333 uint16_t average_fclk_frequency; 1334 uint16_t average_vclk_frequency; 1335 uint16_t average_dclk_frequency; 1336 1337 /* Current clocks (unit: MHz) */ 1338 uint16_t current_gfxclk; 1339 uint16_t current_socclk; 1340 uint16_t current_uclk; 1341 uint16_t current_fclk; 1342 uint16_t current_vclk; 1343 uint16_t current_dclk; 1344 uint16_t current_coreclk[8]; 1345 uint16_t current_l3clk[2]; 1346 1347 /* Throttle status (ASIC dependent) */ 1348 uint32_t throttle_status; 1349 1350 /* Fans */ 1351 uint16_t fan_pwm; 1352 1353 uint16_t padding[3]; 1354 1355 /* Throttle status (ASIC independent) */ 1356 uint64_t indep_throttle_status; 1357 1358 /* Average Temperature (unit: centi-Celsius) */ 1359 uint16_t average_temperature_gfx; 1360 uint16_t average_temperature_soc; 1361 uint16_t average_temperature_core[8]; 1362 uint16_t average_temperature_l3[2]; 1363 1364 /* Power/Voltage (unit: mV) */ 1365 uint16_t average_cpu_voltage; 1366 uint16_t average_soc_voltage; 1367 uint16_t average_gfx_voltage; 1368 1369 /* Power/Current (unit: mA) */ 1370 uint16_t average_cpu_current; 1371 uint16_t average_soc_current; 1372 uint16_t average_gfx_current; 1373 }; 1374 1375 struct gpu_metrics_v3_0 { 1376 struct metrics_table_header common_header; 1377 1378 /* Temperature */ 1379 /* gfx temperature on APUs */ 1380 uint16_t temperature_gfx; 1381 /* soc temperature on APUs */ 1382 uint16_t temperature_soc; 1383 /* CPU core temperature on APUs */ 1384 uint16_t temperature_core[16]; 1385 /* skin temperature on APUs */ 1386 uint16_t temperature_skin; 1387 1388 /* Utilization */ 1389 /* time filtered GFX busy % [0-100] */ 1390 uint16_t average_gfx_activity; 1391 /* time filtered VCN busy % [0-100] */ 1392 uint16_t average_vcn_activity; 1393 /* time filtered IPU per-column busy % [0-100] */ 1394 uint16_t average_ipu_activity[8]; 1395 /* time filtered per-core C0 residency % [0-100]*/ 1396 uint16_t average_core_c0_activity[16]; 1397 /* time filtered DRAM read bandwidth [MB/sec] */ 1398 uint16_t average_dram_reads; 1399 /* time filtered DRAM write bandwidth [MB/sec] */ 1400 uint16_t average_dram_writes; 1401 /* time filtered IPU read bandwidth [MB/sec] */ 1402 uint16_t average_ipu_reads; 1403 /* time filtered IPU write bandwidth [MB/sec] */ 1404 uint16_t average_ipu_writes; 1405 1406 /* Driver attached timestamp (in ns) */ 1407 uint64_t system_clock_counter; 1408 1409 /* Power/Energy */ 1410 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1411 uint32_t average_socket_power; 1412 /* time filtered IPU power [mW] */ 1413 uint16_t average_ipu_power; 1414 /* time filtered APU power [mW] */ 1415 uint32_t average_apu_power; 1416 /* time filtered GFX power [mW] */ 1417 uint32_t average_gfx_power; 1418 /* time filtered dGPU power [mW] */ 1419 uint32_t average_dgpu_power; 1420 /* time filtered sum of core power across all cores in the socket [mW] */ 1421 uint32_t average_all_core_power; 1422 /* calculated core power [mW] */ 1423 uint16_t average_core_power[16]; 1424 /* time filtered total system power [mW] */ 1425 uint16_t average_sys_power; 1426 /* maximum IRM defined STAPM power limit [mW] */ 1427 uint16_t stapm_power_limit; 1428 /* time filtered STAPM power limit [mW] */ 1429 uint16_t current_stapm_power_limit; 1430 1431 /* time filtered clocks [MHz] */ 1432 uint16_t average_gfxclk_frequency; 1433 uint16_t average_socclk_frequency; 1434 uint16_t average_vpeclk_frequency; 1435 uint16_t average_ipuclk_frequency; 1436 uint16_t average_fclk_frequency; 1437 uint16_t average_vclk_frequency; 1438 uint16_t average_uclk_frequency; 1439 uint16_t average_mpipu_frequency; 1440 1441 /* Current clocks */ 1442 /* target core frequency [MHz] */ 1443 uint16_t current_coreclk[16]; 1444 /* CCLK frequency limit enforced on classic cores [MHz] */ 1445 uint16_t current_core_maxfreq; 1446 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1447 uint16_t current_gfx_maxfreq; 1448 1449 /* Throttle Residency (ASIC dependent) */ 1450 uint32_t throttle_residency_prochot; 1451 uint32_t throttle_residency_spl; 1452 uint32_t throttle_residency_fppt; 1453 uint32_t throttle_residency_sppt; 1454 uint32_t throttle_residency_thm_core; 1455 uint32_t throttle_residency_thm_gfx; 1456 uint32_t throttle_residency_thm_soc; 1457 1458 /* Metrics table alpha filter time constant [us] */ 1459 uint32_t time_filter_alphavalue; 1460 }; 1461 1462 struct amdgpu_pmmetrics_header { 1463 uint16_t structure_size; 1464 uint16_t pad; 1465 uint32_t mp1_ip_discovery_version; 1466 uint32_t pmfw_version; 1467 uint32_t pmmetrics_version; 1468 }; 1469 1470 struct amdgpu_pm_metrics { 1471 struct amdgpu_pmmetrics_header common_header; 1472 1473 uint8_t data[]; 1474 }; 1475 1476 #endif 1477