1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 extern const struct amdgpu_ip_block_version smu_v15_0_ip_block; 33 34 enum smu_temp_metric_type { 35 SMU_TEMP_METRIC_BASEBOARD, 36 SMU_TEMP_METRIC_GPUBOARD, 37 SMU_TEMP_METRIC_MAX, 38 }; 39 40 enum smu_event_type { 41 SMU_EVENT_RESET_COMPLETE = 0, 42 }; 43 44 struct amd_vce_state { 45 /* vce clocks */ 46 u32 evclk; 47 u32 ecclk; 48 /* gpu clocks */ 49 u32 sclk; 50 u32 mclk; 51 u8 clk_idx; 52 u8 pstate; 53 }; 54 55 56 enum amd_dpm_forced_level { 57 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 58 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 59 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 60 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 61 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 62 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 63 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 64 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 65 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 66 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 67 }; 68 69 enum amd_pm_state_type { 70 /* not used for dpm */ 71 POWER_STATE_TYPE_DEFAULT, 72 POWER_STATE_TYPE_POWERSAVE, 73 /* user selectable states */ 74 POWER_STATE_TYPE_BATTERY, 75 POWER_STATE_TYPE_BALANCED, 76 POWER_STATE_TYPE_PERFORMANCE, 77 /* internal states */ 78 POWER_STATE_TYPE_INTERNAL_UVD, 79 POWER_STATE_TYPE_INTERNAL_UVD_SD, 80 POWER_STATE_TYPE_INTERNAL_UVD_HD, 81 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 82 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 83 POWER_STATE_TYPE_INTERNAL_BOOT, 84 POWER_STATE_TYPE_INTERNAL_THERMAL, 85 POWER_STATE_TYPE_INTERNAL_ACPI, 86 POWER_STATE_TYPE_INTERNAL_ULV, 87 POWER_STATE_TYPE_INTERNAL_3DPERF, 88 }; 89 90 #define AMD_MAX_VCE_LEVELS 6 91 92 enum amd_vce_level { 93 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 94 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 95 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 96 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 97 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 98 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 99 }; 100 101 enum amd_fan_ctrl_mode { 102 AMD_FAN_CTRL_NONE = 0, 103 AMD_FAN_CTRL_MANUAL = 1, 104 AMD_FAN_CTRL_AUTO = 2, 105 }; 106 107 enum pp_clock_type { 108 PP_SCLK, 109 PP_MCLK, 110 PP_PCIE, 111 PP_SOCCLK, 112 PP_FCLK, 113 PP_DCEFCLK, 114 PP_VCLK, 115 PP_VCLK1, 116 PP_DCLK, 117 PP_DCLK1, 118 PP_ISPICLK, 119 PP_ISPXCLK, 120 OD_SCLK, 121 OD_MCLK, 122 OD_VDDC_CURVE, 123 OD_RANGE, 124 OD_VDDGFX_OFFSET, 125 OD_CCLK, 126 OD_FAN_CURVE, 127 OD_ACOUSTIC_LIMIT, 128 OD_ACOUSTIC_TARGET, 129 OD_FAN_TARGET_TEMPERATURE, 130 OD_FAN_MINIMUM_PWM, 131 OD_FAN_ZERO_RPM_ENABLE, 132 OD_FAN_ZERO_RPM_STOP_TEMP, 133 }; 134 135 enum amd_pp_sensors { 136 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 137 AMDGPU_PP_SENSOR_CPU_CLK, 138 AMDGPU_PP_SENSOR_VDDNB, 139 AMDGPU_PP_SENSOR_VDDGFX, 140 AMDGPU_PP_SENSOR_UVD_VCLK, 141 AMDGPU_PP_SENSOR_UVD_DCLK, 142 AMDGPU_PP_SENSOR_VCE_ECCLK, 143 AMDGPU_PP_SENSOR_GPU_LOAD, 144 AMDGPU_PP_SENSOR_MEM_LOAD, 145 AMDGPU_PP_SENSOR_GFX_MCLK, 146 AMDGPU_PP_SENSOR_GPU_TEMP, 147 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 148 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 149 AMDGPU_PP_SENSOR_MEM_TEMP, 150 AMDGPU_PP_SENSOR_VCE_POWER, 151 AMDGPU_PP_SENSOR_UVD_POWER, 152 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 153 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 154 AMDGPU_PP_SENSOR_SS_APU_SHARE, 155 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 156 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 157 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 158 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 159 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 160 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 161 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 162 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 163 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 164 AMDGPU_PP_SENSOR_VCN_LOAD, 165 AMDGPU_PP_SENSOR_VDDBOARD, 166 AMDGPU_PP_SENSOR_NODEPOWERLIMIT, 167 AMDGPU_PP_SENSOR_NODEPOWER, 168 AMDGPU_PP_SENSOR_GPPTRESIDENCY, 169 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 170 AMDGPU_PP_SENSOR_UBB_POWER, 171 AMDGPU_PP_SENSOR_UBB_POWER_LIMIT, 172 }; 173 174 enum amd_pp_task { 175 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 176 AMD_PP_TASK_ENABLE_USER_STATE, 177 AMD_PP_TASK_READJUST_POWER_STATE, 178 AMD_PP_TASK_COMPLETE_INIT, 179 AMD_PP_TASK_MAX 180 }; 181 182 enum PP_SMC_POWER_PROFILE { 183 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 184 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 185 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 186 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 187 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 188 PP_SMC_POWER_PROFILE_VR = 0x4, 189 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 190 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 191 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 192 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 193 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 194 PP_SMC_POWER_PROFILE_COUNT, 195 }; 196 197 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 198 199 200 201 enum { 202 PP_GROUP_UNKNOWN = 0, 203 PP_GROUP_GFX = 1, 204 PP_GROUP_SYS, 205 PP_GROUP_MAX 206 }; 207 208 enum PP_OD_DPM_TABLE_COMMAND { 209 PP_OD_EDIT_SCLK_VDDC_TABLE, 210 PP_OD_EDIT_MCLK_VDDC_TABLE, 211 PP_OD_EDIT_CCLK_VDDC_TABLE, 212 PP_OD_EDIT_VDDC_CURVE, 213 PP_OD_RESTORE_DEFAULT_TABLE, 214 PP_OD_COMMIT_DPM_TABLE, 215 PP_OD_EDIT_VDDGFX_OFFSET, 216 PP_OD_EDIT_FAN_CURVE, 217 PP_OD_EDIT_ACOUSTIC_LIMIT, 218 PP_OD_EDIT_ACOUSTIC_TARGET, 219 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 220 PP_OD_EDIT_FAN_MINIMUM_PWM, 221 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 222 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 223 }; 224 225 struct pp_states_info { 226 uint32_t nums; 227 uint32_t states[16]; 228 }; 229 230 enum PP_HWMON_TEMP { 231 PP_TEMP_EDGE = 0, 232 PP_TEMP_JUNCTION, 233 PP_TEMP_MEM, 234 PP_TEMP_MAX 235 }; 236 237 enum pp_mp1_state { 238 PP_MP1_STATE_NONE, 239 PP_MP1_STATE_SHUTDOWN, 240 PP_MP1_STATE_UNLOAD, 241 PP_MP1_STATE_RESET, 242 PP_MP1_STATE_FLR, 243 }; 244 245 enum pp_df_cstate { 246 DF_CSTATE_DISALLOW = 0, 247 DF_CSTATE_ALLOW, 248 }; 249 250 /** 251 * DOC: amdgpu_pp_power 252 * 253 * APU power is managed to system-level requirements through the PPT 254 * (package power tracking) feature. PPT is intended to limit power to the 255 * requirements of the power source and could be dynamically updated to 256 * maximize APU performance within the system power budget. 257 * 258 * Two types of power measurement can be requested, where supported, with 259 * :c:type:`enum pp_power_type <pp_power_type>`. 260 */ 261 262 /** 263 * enum pp_power_limit_level - Used to query the power limits 264 * 265 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 266 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 267 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 268 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 269 */ 270 enum pp_power_limit_level { 271 PP_PWR_LIMIT_MIN = -1, 272 PP_PWR_LIMIT_CURRENT, 273 PP_PWR_LIMIT_DEFAULT, 274 PP_PWR_LIMIT_MAX, 275 }; 276 277 /** 278 * enum pp_power_type - Used to specify the type of the requested power 279 * 280 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 281 * moving average of APU power (default ~5000 ms). 282 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 283 * where supported. 284 */ 285 enum pp_power_type { 286 PP_PWR_TYPE_SUSTAINED, 287 PP_PWR_TYPE_FAST, 288 }; 289 290 enum pp_xgmi_plpd_mode { 291 XGMI_PLPD_NONE = -1, 292 XGMI_PLPD_DISALLOW, 293 XGMI_PLPD_DEFAULT, 294 XGMI_PLPD_OPTIMIZED, 295 XGMI_PLPD_COUNT, 296 }; 297 298 enum pp_pm_policy { 299 PP_PM_POLICY_NONE = -1, 300 PP_PM_POLICY_SOC_PSTATE = 0, 301 PP_PM_POLICY_XGMI_PLPD, 302 PP_PM_POLICY_NUM, 303 }; 304 305 enum pp_policy_soc_pstate { 306 SOC_PSTATE_DEFAULT = 0, 307 SOC_PSTATE_0, 308 SOC_PSTATE_1, 309 SOC_PSTATE_2, 310 SOC_PSTAT_COUNT, 311 }; 312 313 #define PP_POLICY_MAX_LEVELS 5 314 315 #define PP_GROUP_MASK 0xF0000000 316 #define PP_GROUP_SHIFT 28 317 318 #define PP_BLOCK_MASK 0x0FFFFF00 319 #define PP_BLOCK_SHIFT 8 320 321 #define PP_BLOCK_GFX_CG 0x01 322 #define PP_BLOCK_GFX_MG 0x02 323 #define PP_BLOCK_GFX_3D 0x04 324 #define PP_BLOCK_GFX_RLC 0x08 325 #define PP_BLOCK_GFX_CP 0x10 326 #define PP_BLOCK_SYS_BIF 0x01 327 #define PP_BLOCK_SYS_MC 0x02 328 #define PP_BLOCK_SYS_ROM 0x04 329 #define PP_BLOCK_SYS_DRM 0x08 330 #define PP_BLOCK_SYS_HDP 0x10 331 #define PP_BLOCK_SYS_SDMA 0x20 332 333 #define PP_STATE_MASK 0x0000000F 334 #define PP_STATE_SHIFT 0 335 #define PP_STATE_SUPPORT_MASK 0x000000F0 336 #define PP_STATE_SUPPORT_SHIFT 0 337 338 #define PP_STATE_CG 0x01 339 #define PP_STATE_LS 0x02 340 #define PP_STATE_DS 0x04 341 #define PP_STATE_SD 0x08 342 #define PP_STATE_SUPPORT_CG 0x10 343 #define PP_STATE_SUPPORT_LS 0x20 344 #define PP_STATE_SUPPORT_DS 0x40 345 #define PP_STATE_SUPPORT_SD 0x80 346 347 #define PP_CG_MSG_ID(group, block, support, state) \ 348 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 349 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 350 351 #define XGMI_MODE_PSTATE_D3 0 352 #define XGMI_MODE_PSTATE_D0 1 353 354 #define NUM_HBM_INSTANCES 4 355 #define NUM_XGMI_LINKS 8 356 #define MAX_GFX_CLKS 8 357 #define MAX_CLKS 4 358 #define NUM_VCN 4 359 #define NUM_JPEG_ENG 32 360 #define NUM_JPEG_ENG_V1 40 361 #define MAX_XCC 8 362 #define NUM_XCP 8 363 struct seq_file; 364 enum amd_pp_clock_type; 365 struct amd_pp_simple_clock_info; 366 struct amd_pp_display_configuration; 367 struct amd_pp_clock_info; 368 struct pp_display_clock_request; 369 struct pp_clock_levels_with_voltage; 370 struct pp_clock_levels_with_latency; 371 struct amd_pp_clocks; 372 struct pp_smu_wm_range_sets; 373 struct pp_smu_nv_clock_table; 374 struct dpm_clocks; 375 376 struct amdgpu_xcp_metrics { 377 /* Utilization Instantaneous (%) */ 378 uint32_t gfx_busy_inst[MAX_XCC]; 379 uint16_t jpeg_busy[NUM_JPEG_ENG]; 380 uint16_t vcn_busy[NUM_VCN]; 381 /* Utilization Accumulated (%) */ 382 uint64_t gfx_busy_acc[MAX_XCC]; 383 }; 384 385 struct amdgpu_xcp_metrics_v1_1 { 386 /* Utilization Instantaneous (%) */ 387 uint32_t gfx_busy_inst[MAX_XCC]; 388 uint16_t jpeg_busy[NUM_JPEG_ENG]; 389 uint16_t vcn_busy[NUM_VCN]; 390 /* Utilization Accumulated (%) */ 391 uint64_t gfx_busy_acc[MAX_XCC]; 392 /* Total App Clock Counter Accumulated */ 393 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 394 }; 395 396 struct amdgpu_xcp_metrics_v1_2 { 397 /* Utilization Instantaneous (%) */ 398 uint32_t gfx_busy_inst[MAX_XCC]; 399 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 400 uint16_t vcn_busy[NUM_VCN]; 401 /* Utilization Accumulated (%) */ 402 uint64_t gfx_busy_acc[MAX_XCC]; 403 /* Total App Clock Counter Accumulated */ 404 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 405 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 406 uint64_t gfx_low_utilization_acc[MAX_XCC]; 407 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 408 }; 409 410 struct amd_pm_funcs { 411 /* export for dpm on ci and si */ 412 int (*pre_set_power_state)(void *handle); 413 int (*set_power_state)(void *handle); 414 void (*post_set_power_state)(void *handle); 415 void (*display_configuration_changed)(void *handle); 416 void (*print_power_state)(void *handle, void *ps); 417 bool (*vblank_too_short)(void *handle); 418 void (*enable_bapm)(void *handle, bool enable); 419 int (*check_state_equal)(void *handle, 420 void *cps, 421 void *rps, 422 bool *equal); 423 /* export for sysfs */ 424 int (*set_fan_control_mode)(void *handle, u32 mode); 425 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 426 int (*set_fan_speed_pwm)(void *handle, u32 speed); 427 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 428 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 429 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 430 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 431 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 432 int (*get_sclk_od)(void *handle); 433 int (*set_sclk_od)(void *handle, uint32_t value); 434 int (*get_mclk_od)(void *handle); 435 int (*set_mclk_od)(void *handle, uint32_t value); 436 int (*read_sensor)(void *handle, int idx, void *value, int *size); 437 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 438 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 439 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 440 enum amd_pm_state_type (*get_current_power_state)(void *handle); 441 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 442 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 443 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 444 int (*get_pp_table)(void *handle, char **table); 445 int (*set_pp_table)(void *handle, const char *buf, size_t size); 446 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 447 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 448 int (*pause_power_profile)(void *handle, bool pause); 449 /* export to amdgpu */ 450 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 451 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 452 enum amd_pm_state_type *user_state); 453 int (*load_firmware)(void *handle); 454 int (*wait_for_fw_loading_complete)(void *handle); 455 int (*set_powergating_by_smu)(void *handle, 456 uint32_t block_type, 457 bool gate, 458 int inst); 459 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 460 int (*set_power_limit)(void *handle, uint32_t limit_type, uint32_t n); 461 int (*get_power_limit)(void *handle, uint32_t *limit, 462 enum pp_power_limit_level pp_limit_level, 463 enum pp_power_type power_type); 464 int (*get_power_profile_mode)(void *handle, char *buf); 465 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 466 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 467 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 468 long *input, uint32_t size); 469 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 470 int (*smu_i2c_bus_access)(void *handle, bool acquire); 471 int (*gfx_state_change_set)(void *handle, uint32_t state); 472 /* export to DC */ 473 u32 (*get_sclk)(void *handle, bool low); 474 u32 (*get_mclk)(void *handle, bool low); 475 int (*display_configuration_change)(void *handle, 476 const struct amd_pp_display_configuration *input); 477 int (*get_display_power_level)(void *handle, 478 struct amd_pp_simple_clock_info *output); 479 int (*get_current_clocks)(void *handle, 480 struct amd_pp_clock_info *clocks); 481 int (*get_clock_by_type)(void *handle, 482 enum amd_pp_clock_type type, 483 struct amd_pp_clocks *clocks); 484 int (*get_clock_by_type_with_latency)(void *handle, 485 enum amd_pp_clock_type type, 486 struct pp_clock_levels_with_latency *clocks); 487 int (*get_clock_by_type_with_voltage)(void *handle, 488 enum amd_pp_clock_type type, 489 struct pp_clock_levels_with_voltage *clocks); 490 int (*set_watermarks_for_clocks_ranges)(void *handle, 491 void *clock_ranges); 492 int (*display_clock_voltage_request)(void *handle, 493 struct pp_display_clock_request *clock); 494 int (*get_display_mode_validation_clocks)(void *handle, 495 struct amd_pp_simple_clock_info *clocks); 496 int (*notify_smu_enable_pwe)(void *handle); 497 int (*enable_mgpu_fan_boost)(void *handle); 498 int (*set_active_display_count)(void *handle, uint32_t count); 499 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 500 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 501 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 502 int (*get_asic_baco_capability)(void *handle); 503 int (*get_asic_baco_state)(void *handle, int *state); 504 int (*set_asic_baco_state)(void *handle, int state); 505 int (*get_ppfeature_status)(void *handle, char *buf); 506 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 507 int (*asic_reset_mode_2)(void *handle); 508 int (*asic_reset_enable_gfx_features)(void *handle); 509 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 510 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 511 ssize_t (*get_gpu_metrics)(void *handle, void **table); 512 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 513 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 514 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 515 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 516 int (*set_watermarks_for_clock_ranges)(void *handle, 517 struct pp_smu_wm_range_sets *ranges); 518 int (*display_disable_memory_clock_switch)(void *handle, 519 bool disable_memory_clock_switch); 520 int (*get_max_sustainable_clocks_by_dc)(void *handle, 521 struct pp_smu_nv_clock_table *max_clocks); 522 int (*get_uclk_dpm_states)(void *handle, 523 unsigned int *clock_values_in_khz, 524 unsigned int *num_states); 525 int (*get_dpm_clock_table)(void *handle, 526 struct dpm_clocks *clock_table); 527 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 528 void (*pm_compute_clocks)(void *handle); 529 int (*notify_rlc_state)(void *handle, bool en); 530 }; 531 532 struct metrics_table_header { 533 uint16_t structure_size; 534 uint8_t format_revision; 535 uint8_t content_revision; 536 }; 537 538 enum amdgpu_metrics_attr_id { 539 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_HOTSPOT, 540 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_MEM, 541 AMDGPU_METRICS_ATTR_ID_TEMPERATURE_VRSOC, 542 AMDGPU_METRICS_ATTR_ID_CURR_SOCKET_POWER, 543 AMDGPU_METRICS_ATTR_ID_AVERAGE_GFX_ACTIVITY, 544 AMDGPU_METRICS_ATTR_ID_AVERAGE_UMC_ACTIVITY, 545 AMDGPU_METRICS_ATTR_ID_MEM_MAX_BANDWIDTH, 546 AMDGPU_METRICS_ATTR_ID_ENERGY_ACCUMULATOR, 547 AMDGPU_METRICS_ATTR_ID_SYSTEM_CLOCK_COUNTER, 548 AMDGPU_METRICS_ATTR_ID_ACCUMULATION_COUNTER, 549 AMDGPU_METRICS_ATTR_ID_PROCHOT_RESIDENCY_ACC, 550 AMDGPU_METRICS_ATTR_ID_PPT_RESIDENCY_ACC, 551 AMDGPU_METRICS_ATTR_ID_SOCKET_THM_RESIDENCY_ACC, 552 AMDGPU_METRICS_ATTR_ID_VR_THM_RESIDENCY_ACC, 553 AMDGPU_METRICS_ATTR_ID_HBM_THM_RESIDENCY_ACC, 554 AMDGPU_METRICS_ATTR_ID_GFXCLK_LOCK_STATUS, 555 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_WIDTH, 556 AMDGPU_METRICS_ATTR_ID_PCIE_LINK_SPEED, 557 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_WIDTH, 558 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_SPEED, 559 AMDGPU_METRICS_ATTR_ID_GFX_ACTIVITY_ACC, 560 AMDGPU_METRICS_ATTR_ID_MEM_ACTIVITY_ACC, 561 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_ACC, 562 AMDGPU_METRICS_ATTR_ID_PCIE_BANDWIDTH_INST, 563 AMDGPU_METRICS_ATTR_ID_PCIE_L0_TO_RECOV_COUNT_ACC, 564 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_COUNT_ACC, 565 AMDGPU_METRICS_ATTR_ID_PCIE_REPLAY_ROVER_COUNT_ACC, 566 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_SENT_COUNT_ACC, 567 AMDGPU_METRICS_ATTR_ID_PCIE_NAK_RCVD_COUNT_ACC, 568 AMDGPU_METRICS_ATTR_ID_XGMI_READ_DATA_ACC, 569 AMDGPU_METRICS_ATTR_ID_XGMI_WRITE_DATA_ACC, 570 AMDGPU_METRICS_ATTR_ID_XGMI_LINK_STATUS, 571 AMDGPU_METRICS_ATTR_ID_FIRMWARE_TIMESTAMP, 572 AMDGPU_METRICS_ATTR_ID_CURRENT_GFXCLK, 573 AMDGPU_METRICS_ATTR_ID_CURRENT_SOCCLK, 574 AMDGPU_METRICS_ATTR_ID_CURRENT_VCLK0, 575 AMDGPU_METRICS_ATTR_ID_CURRENT_DCLK0, 576 AMDGPU_METRICS_ATTR_ID_CURRENT_UCLK, 577 AMDGPU_METRICS_ATTR_ID_NUM_PARTITION, 578 AMDGPU_METRICS_ATTR_ID_PCIE_LC_PERF_OTHER_END_RECOVERY, 579 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_INST, 580 AMDGPU_METRICS_ATTR_ID_JPEG_BUSY, 581 AMDGPU_METRICS_ATTR_ID_VCN_BUSY, 582 AMDGPU_METRICS_ATTR_ID_GFX_BUSY_ACC, 583 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_PPT_ACC, 584 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_THM_ACC, 585 AMDGPU_METRICS_ATTR_ID_GFX_LOW_UTILIZATION_ACC, 586 AMDGPU_METRICS_ATTR_ID_GFX_BELOW_HOST_LIMIT_TOTAL_ACC, 587 AMDGPU_METRICS_ATTR_ID_MAX, 588 }; 589 590 enum amdgpu_metrics_attr_type { 591 AMDGPU_METRICS_TYPE_U8, 592 AMDGPU_METRICS_TYPE_S8, 593 AMDGPU_METRICS_TYPE_U16, 594 AMDGPU_METRICS_TYPE_S16, 595 AMDGPU_METRICS_TYPE_U32, 596 AMDGPU_METRICS_TYPE_S32, 597 AMDGPU_METRICS_TYPE_U64, 598 AMDGPU_METRICS_TYPE_S64, 599 AMDGPU_METRICS_TYPE_MAX, 600 }; 601 602 enum amdgpu_metrics_attr_unit { 603 /* None */ 604 AMDGPU_METRICS_UNIT_NONE, 605 /* MHz*/ 606 AMDGPU_METRICS_UNIT_CLOCK_1, 607 /* Degree Celsius*/ 608 AMDGPU_METRICS_UNIT_TEMP_1, 609 /* Watts*/ 610 AMDGPU_METRICS_UNIT_POWER_1, 611 /* In nanoseconds*/ 612 AMDGPU_METRICS_UNIT_TIME_1, 613 /* In 10 nanoseconds*/ 614 AMDGPU_METRICS_UNIT_TIME_2, 615 /* Speed in GT/s */ 616 AMDGPU_METRICS_UNIT_SPEED_1, 617 /* Speed in 0.1 GT/s */ 618 AMDGPU_METRICS_UNIT_SPEED_2, 619 /* Bandwidth GB/s */ 620 AMDGPU_METRICS_UNIT_BW_1, 621 /* Data in KB */ 622 AMDGPU_METRICS_UNIT_DATA_1, 623 /* Percentage */ 624 AMDGPU_METRICS_UNIT_PERCENT, 625 AMDGPU_METRICS_UNIT_MAX, 626 }; 627 628 #define AMDGPU_METRICS_ATTR_UNIT_MASK 0xFF000000 629 #define AMDGPU_METRICS_ATTR_UNIT_SHIFT 24 630 #define AMDGPU_METRICS_ATTR_TYPE_MASK 0x00F00000 631 #define AMDGPU_METRICS_ATTR_TYPE_SHIFT 20 632 #define AMDGPU_METRICS_ATTR_ID_MASK 0x000FFC00 633 #define AMDGPU_METRICS_ATTR_ID_SHIFT 10 634 #define AMDGPU_METRICS_ATTR_INST_MASK 0x000003FF 635 #define AMDGPU_METRICS_ATTR_INST_SHIFT 0 636 637 #define AMDGPU_METRICS_ENC_ATTR(unit, type, id, inst) \ 638 (((u64)(unit) << AMDGPU_METRICS_ATTR_UNIT_SHIFT) | \ 639 ((u64)(type) << AMDGPU_METRICS_ATTR_TYPE_SHIFT) | \ 640 ((u64)(id) << AMDGPU_METRICS_ATTR_ID_SHIFT) | (inst)) 641 642 /* 643 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 644 * Use gpu_metrics_v1_1 or later instead. 645 */ 646 struct gpu_metrics_v1_0 { 647 struct metrics_table_header common_header; 648 649 /* Driver attached timestamp (in ns) */ 650 uint64_t system_clock_counter; 651 652 /* Temperature */ 653 uint16_t temperature_edge; 654 uint16_t temperature_hotspot; 655 uint16_t temperature_mem; 656 uint16_t temperature_vrgfx; 657 uint16_t temperature_vrsoc; 658 uint16_t temperature_vrmem; 659 660 /* Utilization */ 661 uint16_t average_gfx_activity; 662 uint16_t average_umc_activity; // memory controller 663 uint16_t average_mm_activity; // UVD or VCN 664 665 /* Power/Energy */ 666 uint16_t average_socket_power; 667 uint32_t energy_accumulator; 668 669 /* Average clocks */ 670 uint16_t average_gfxclk_frequency; 671 uint16_t average_socclk_frequency; 672 uint16_t average_uclk_frequency; 673 uint16_t average_vclk0_frequency; 674 uint16_t average_dclk0_frequency; 675 uint16_t average_vclk1_frequency; 676 uint16_t average_dclk1_frequency; 677 678 /* Current clocks */ 679 uint16_t current_gfxclk; 680 uint16_t current_socclk; 681 uint16_t current_uclk; 682 uint16_t current_vclk0; 683 uint16_t current_dclk0; 684 uint16_t current_vclk1; 685 uint16_t current_dclk1; 686 687 /* Throttle status */ 688 uint32_t throttle_status; 689 690 /* Fans */ 691 uint16_t current_fan_speed; 692 693 /* Link width/speed */ 694 uint8_t pcie_link_width; 695 uint8_t pcie_link_speed; // in 0.1 GT/s 696 }; 697 698 struct gpu_metrics_v1_1 { 699 struct metrics_table_header common_header; 700 701 /* Temperature */ 702 uint16_t temperature_edge; 703 uint16_t temperature_hotspot; 704 uint16_t temperature_mem; 705 uint16_t temperature_vrgfx; 706 uint16_t temperature_vrsoc; 707 uint16_t temperature_vrmem; 708 709 /* Utilization */ 710 uint16_t average_gfx_activity; 711 uint16_t average_umc_activity; // memory controller 712 uint16_t average_mm_activity; // UVD or VCN 713 714 /* Power/Energy */ 715 uint16_t average_socket_power; 716 uint64_t energy_accumulator; 717 718 /* Driver attached timestamp (in ns) */ 719 uint64_t system_clock_counter; 720 721 /* Average clocks */ 722 uint16_t average_gfxclk_frequency; 723 uint16_t average_socclk_frequency; 724 uint16_t average_uclk_frequency; 725 uint16_t average_vclk0_frequency; 726 uint16_t average_dclk0_frequency; 727 uint16_t average_vclk1_frequency; 728 uint16_t average_dclk1_frequency; 729 730 /* Current clocks */ 731 uint16_t current_gfxclk; 732 uint16_t current_socclk; 733 uint16_t current_uclk; 734 uint16_t current_vclk0; 735 uint16_t current_dclk0; 736 uint16_t current_vclk1; 737 uint16_t current_dclk1; 738 739 /* Throttle status */ 740 uint32_t throttle_status; 741 742 /* Fans */ 743 uint16_t current_fan_speed; 744 745 /* Link width/speed */ 746 uint16_t pcie_link_width; 747 uint16_t pcie_link_speed; // in 0.1 GT/s 748 749 uint16_t padding; 750 751 uint32_t gfx_activity_acc; 752 uint32_t mem_activity_acc; 753 754 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 755 }; 756 757 struct gpu_metrics_v1_2 { 758 struct metrics_table_header common_header; 759 760 /* Temperature */ 761 uint16_t temperature_edge; 762 uint16_t temperature_hotspot; 763 uint16_t temperature_mem; 764 uint16_t temperature_vrgfx; 765 uint16_t temperature_vrsoc; 766 uint16_t temperature_vrmem; 767 768 /* Utilization */ 769 uint16_t average_gfx_activity; 770 uint16_t average_umc_activity; // memory controller 771 uint16_t average_mm_activity; // UVD or VCN 772 773 /* Power/Energy */ 774 uint16_t average_socket_power; 775 uint64_t energy_accumulator; 776 777 /* Driver attached timestamp (in ns) */ 778 uint64_t system_clock_counter; 779 780 /* Average clocks */ 781 uint16_t average_gfxclk_frequency; 782 uint16_t average_socclk_frequency; 783 uint16_t average_uclk_frequency; 784 uint16_t average_vclk0_frequency; 785 uint16_t average_dclk0_frequency; 786 uint16_t average_vclk1_frequency; 787 uint16_t average_dclk1_frequency; 788 789 /* Current clocks */ 790 uint16_t current_gfxclk; 791 uint16_t current_socclk; 792 uint16_t current_uclk; 793 uint16_t current_vclk0; 794 uint16_t current_dclk0; 795 uint16_t current_vclk1; 796 uint16_t current_dclk1; 797 798 /* Throttle status (ASIC dependent) */ 799 uint32_t throttle_status; 800 801 /* Fans */ 802 uint16_t current_fan_speed; 803 804 /* Link width/speed */ 805 uint16_t pcie_link_width; 806 uint16_t pcie_link_speed; // in 0.1 GT/s 807 808 uint16_t padding; 809 810 uint32_t gfx_activity_acc; 811 uint32_t mem_activity_acc; 812 813 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 814 815 /* PMFW attached timestamp (10ns resolution) */ 816 uint64_t firmware_timestamp; 817 }; 818 819 struct gpu_metrics_v1_3 { 820 struct metrics_table_header common_header; 821 822 /* Temperature */ 823 uint16_t temperature_edge; 824 uint16_t temperature_hotspot; 825 uint16_t temperature_mem; 826 uint16_t temperature_vrgfx; 827 uint16_t temperature_vrsoc; 828 uint16_t temperature_vrmem; 829 830 /* Utilization */ 831 uint16_t average_gfx_activity; 832 uint16_t average_umc_activity; // memory controller 833 uint16_t average_mm_activity; // UVD or VCN 834 835 /* Power/Energy */ 836 uint16_t average_socket_power; 837 uint64_t energy_accumulator; 838 839 /* Driver attached timestamp (in ns) */ 840 uint64_t system_clock_counter; 841 842 /* Average clocks */ 843 uint16_t average_gfxclk_frequency; 844 uint16_t average_socclk_frequency; 845 uint16_t average_uclk_frequency; 846 uint16_t average_vclk0_frequency; 847 uint16_t average_dclk0_frequency; 848 uint16_t average_vclk1_frequency; 849 uint16_t average_dclk1_frequency; 850 851 /* Current clocks */ 852 uint16_t current_gfxclk; 853 uint16_t current_socclk; 854 uint16_t current_uclk; 855 uint16_t current_vclk0; 856 uint16_t current_dclk0; 857 uint16_t current_vclk1; 858 uint16_t current_dclk1; 859 860 /* Throttle status */ 861 uint32_t throttle_status; 862 863 /* Fans */ 864 uint16_t current_fan_speed; 865 866 /* Link width/speed */ 867 uint16_t pcie_link_width; 868 uint16_t pcie_link_speed; // in 0.1 GT/s 869 870 uint16_t padding; 871 872 uint32_t gfx_activity_acc; 873 uint32_t mem_activity_acc; 874 875 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 876 877 /* PMFW attached timestamp (10ns resolution) */ 878 uint64_t firmware_timestamp; 879 880 /* Voltage (mV) */ 881 uint16_t voltage_soc; 882 uint16_t voltage_gfx; 883 uint16_t voltage_mem; 884 885 uint16_t padding1; 886 887 /* Throttle status (ASIC independent) */ 888 uint64_t indep_throttle_status; 889 }; 890 891 struct gpu_metrics_v1_4 { 892 struct metrics_table_header common_header; 893 894 /* Temperature (Celsius) */ 895 uint16_t temperature_hotspot; 896 uint16_t temperature_mem; 897 uint16_t temperature_vrsoc; 898 899 /* Power (Watts) */ 900 uint16_t curr_socket_power; 901 902 /* Utilization (%) */ 903 uint16_t average_gfx_activity; 904 uint16_t average_umc_activity; // memory controller 905 uint16_t vcn_activity[NUM_VCN]; 906 907 /* Energy (15.259uJ (2^-16) units) */ 908 uint64_t energy_accumulator; 909 910 /* Driver attached timestamp (in ns) */ 911 uint64_t system_clock_counter; 912 913 /* Throttle status */ 914 uint32_t throttle_status; 915 916 /* Clock Lock Status. Each bit corresponds to clock instance */ 917 uint32_t gfxclk_lock_status; 918 919 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 920 uint16_t pcie_link_width; 921 uint16_t pcie_link_speed; 922 923 /* XGMI bus width and bitrate (in Gbps) */ 924 uint16_t xgmi_link_width; 925 uint16_t xgmi_link_speed; 926 927 /* Utilization Accumulated (%) */ 928 uint32_t gfx_activity_acc; 929 uint32_t mem_activity_acc; 930 931 /*PCIE accumulated bandwidth (GB/sec) */ 932 uint64_t pcie_bandwidth_acc; 933 934 /*PCIE instantaneous bandwidth (GB/sec) */ 935 uint64_t pcie_bandwidth_inst; 936 937 /* PCIE L0 to recovery state transition accumulated count */ 938 uint64_t pcie_l0_to_recov_count_acc; 939 940 /* PCIE replay accumulated count */ 941 uint64_t pcie_replay_count_acc; 942 943 /* PCIE replay rollover accumulated count */ 944 uint64_t pcie_replay_rover_count_acc; 945 946 /* XGMI accumulated data transfer size(KiloBytes) */ 947 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 948 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 949 950 /* PMFW attached timestamp (10ns resolution) */ 951 uint64_t firmware_timestamp; 952 953 /* Current clocks (Mhz) */ 954 uint16_t current_gfxclk[MAX_GFX_CLKS]; 955 uint16_t current_socclk[MAX_CLKS]; 956 uint16_t current_vclk0[MAX_CLKS]; 957 uint16_t current_dclk0[MAX_CLKS]; 958 uint16_t current_uclk; 959 960 uint16_t padding; 961 }; 962 963 struct gpu_metrics_v1_5 { 964 struct metrics_table_header common_header; 965 966 /* Temperature (Celsius) */ 967 uint16_t temperature_hotspot; 968 uint16_t temperature_mem; 969 uint16_t temperature_vrsoc; 970 971 /* Power (Watts) */ 972 uint16_t curr_socket_power; 973 974 /* Utilization (%) */ 975 uint16_t average_gfx_activity; 976 uint16_t average_umc_activity; // memory controller 977 uint16_t vcn_activity[NUM_VCN]; 978 uint16_t jpeg_activity[NUM_JPEG_ENG]; 979 980 /* Energy (15.259uJ (2^-16) units) */ 981 uint64_t energy_accumulator; 982 983 /* Driver attached timestamp (in ns) */ 984 uint64_t system_clock_counter; 985 986 /* Throttle status */ 987 uint32_t throttle_status; 988 989 /* Clock Lock Status. Each bit corresponds to clock instance */ 990 uint32_t gfxclk_lock_status; 991 992 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 993 uint16_t pcie_link_width; 994 uint16_t pcie_link_speed; 995 996 /* XGMI bus width and bitrate (in Gbps) */ 997 uint16_t xgmi_link_width; 998 uint16_t xgmi_link_speed; 999 1000 /* Utilization Accumulated (%) */ 1001 uint32_t gfx_activity_acc; 1002 uint32_t mem_activity_acc; 1003 1004 /*PCIE accumulated bandwidth (GB/sec) */ 1005 uint64_t pcie_bandwidth_acc; 1006 1007 /*PCIE instantaneous bandwidth (GB/sec) */ 1008 uint64_t pcie_bandwidth_inst; 1009 1010 /* PCIE L0 to recovery state transition accumulated count */ 1011 uint64_t pcie_l0_to_recov_count_acc; 1012 1013 /* PCIE replay accumulated count */ 1014 uint64_t pcie_replay_count_acc; 1015 1016 /* PCIE replay rollover accumulated count */ 1017 uint64_t pcie_replay_rover_count_acc; 1018 1019 /* PCIE NAK sent accumulated count */ 1020 uint32_t pcie_nak_sent_count_acc; 1021 1022 /* PCIE NAK received accumulated count */ 1023 uint32_t pcie_nak_rcvd_count_acc; 1024 1025 /* XGMI accumulated data transfer size(KiloBytes) */ 1026 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1027 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1028 1029 /* PMFW attached timestamp (10ns resolution) */ 1030 uint64_t firmware_timestamp; 1031 1032 /* Current clocks (Mhz) */ 1033 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1034 uint16_t current_socclk[MAX_CLKS]; 1035 uint16_t current_vclk0[MAX_CLKS]; 1036 uint16_t current_dclk0[MAX_CLKS]; 1037 uint16_t current_uclk; 1038 1039 uint16_t padding; 1040 }; 1041 1042 struct gpu_metrics_v1_6 { 1043 struct metrics_table_header common_header; 1044 1045 /* Temperature (Celsius) */ 1046 uint16_t temperature_hotspot; 1047 uint16_t temperature_mem; 1048 uint16_t temperature_vrsoc; 1049 1050 /* Power (Watts) */ 1051 uint16_t curr_socket_power; 1052 1053 /* Utilization (%) */ 1054 uint16_t average_gfx_activity; 1055 uint16_t average_umc_activity; // memory controller 1056 1057 /* Energy (15.259uJ (2^-16) units) */ 1058 uint64_t energy_accumulator; 1059 1060 /* Driver attached timestamp (in ns) */ 1061 uint64_t system_clock_counter; 1062 1063 /* Accumulation cycle counter */ 1064 uint32_t accumulation_counter; 1065 1066 /* Accumulated throttler residencies */ 1067 uint32_t prochot_residency_acc; 1068 uint32_t ppt_residency_acc; 1069 uint32_t socket_thm_residency_acc; 1070 uint32_t vr_thm_residency_acc; 1071 uint32_t hbm_thm_residency_acc; 1072 1073 /* Clock Lock Status. Each bit corresponds to clock instance */ 1074 uint32_t gfxclk_lock_status; 1075 1076 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1077 uint16_t pcie_link_width; 1078 uint16_t pcie_link_speed; 1079 1080 /* XGMI bus width and bitrate (in Gbps) */ 1081 uint16_t xgmi_link_width; 1082 uint16_t xgmi_link_speed; 1083 1084 /* Utilization Accumulated (%) */ 1085 uint32_t gfx_activity_acc; 1086 uint32_t mem_activity_acc; 1087 1088 /*PCIE accumulated bandwidth (GB/sec) */ 1089 uint64_t pcie_bandwidth_acc; 1090 1091 /*PCIE instantaneous bandwidth (GB/sec) */ 1092 uint64_t pcie_bandwidth_inst; 1093 1094 /* PCIE L0 to recovery state transition accumulated count */ 1095 uint64_t pcie_l0_to_recov_count_acc; 1096 1097 /* PCIE replay accumulated count */ 1098 uint64_t pcie_replay_count_acc; 1099 1100 /* PCIE replay rollover accumulated count */ 1101 uint64_t pcie_replay_rover_count_acc; 1102 1103 /* PCIE NAK sent accumulated count */ 1104 uint32_t pcie_nak_sent_count_acc; 1105 1106 /* PCIE NAK received accumulated count */ 1107 uint32_t pcie_nak_rcvd_count_acc; 1108 1109 /* XGMI accumulated data transfer size(KiloBytes) */ 1110 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1111 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1112 1113 /* PMFW attached timestamp (10ns resolution) */ 1114 uint64_t firmware_timestamp; 1115 1116 /* Current clocks (Mhz) */ 1117 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1118 uint16_t current_socclk[MAX_CLKS]; 1119 uint16_t current_vclk0[MAX_CLKS]; 1120 uint16_t current_dclk0[MAX_CLKS]; 1121 uint16_t current_uclk; 1122 1123 /* Number of current partition */ 1124 uint16_t num_partition; 1125 1126 /* XCP metrics stats */ 1127 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1128 1129 /* PCIE other end recovery counter */ 1130 uint32_t pcie_lc_perf_other_end_recovery; 1131 }; 1132 1133 struct gpu_metrics_v1_7 { 1134 struct metrics_table_header common_header; 1135 1136 /* Temperature (Celsius) */ 1137 uint16_t temperature_hotspot; 1138 uint16_t temperature_mem; 1139 uint16_t temperature_vrsoc; 1140 1141 /* Power (Watts) */ 1142 uint16_t curr_socket_power; 1143 1144 /* Utilization (%) */ 1145 uint16_t average_gfx_activity; 1146 uint16_t average_umc_activity; // memory controller 1147 1148 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1149 uint64_t mem_max_bandwidth; 1150 1151 /* Energy (15.259uJ (2^-16) units) */ 1152 uint64_t energy_accumulator; 1153 1154 /* Driver attached timestamp (in ns) */ 1155 uint64_t system_clock_counter; 1156 1157 /* Accumulation cycle counter */ 1158 uint32_t accumulation_counter; 1159 1160 /* Accumulated throttler residencies */ 1161 uint32_t prochot_residency_acc; 1162 uint32_t ppt_residency_acc; 1163 uint32_t socket_thm_residency_acc; 1164 uint32_t vr_thm_residency_acc; 1165 uint32_t hbm_thm_residency_acc; 1166 1167 /* Clock Lock Status. Each bit corresponds to clock instance */ 1168 uint32_t gfxclk_lock_status; 1169 1170 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1171 uint16_t pcie_link_width; 1172 uint16_t pcie_link_speed; 1173 1174 /* XGMI bus width and bitrate (in Gbps) */ 1175 uint16_t xgmi_link_width; 1176 uint16_t xgmi_link_speed; 1177 1178 /* Utilization Accumulated (%) */ 1179 uint32_t gfx_activity_acc; 1180 uint32_t mem_activity_acc; 1181 1182 /*PCIE accumulated bandwidth (GB/sec) */ 1183 uint64_t pcie_bandwidth_acc; 1184 1185 /*PCIE instantaneous bandwidth (GB/sec) */ 1186 uint64_t pcie_bandwidth_inst; 1187 1188 /* PCIE L0 to recovery state transition accumulated count */ 1189 uint64_t pcie_l0_to_recov_count_acc; 1190 1191 /* PCIE replay accumulated count */ 1192 uint64_t pcie_replay_count_acc; 1193 1194 /* PCIE replay rollover accumulated count */ 1195 uint64_t pcie_replay_rover_count_acc; 1196 1197 /* PCIE NAK sent accumulated count */ 1198 uint32_t pcie_nak_sent_count_acc; 1199 1200 /* PCIE NAK received accumulated count */ 1201 uint32_t pcie_nak_rcvd_count_acc; 1202 1203 /* XGMI accumulated data transfer size(KiloBytes) */ 1204 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1205 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1206 1207 /* XGMI link status(active/inactive) */ 1208 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1209 1210 uint16_t padding; 1211 1212 /* PMFW attached timestamp (10ns resolution) */ 1213 uint64_t firmware_timestamp; 1214 1215 /* Current clocks (Mhz) */ 1216 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1217 uint16_t current_socclk[MAX_CLKS]; 1218 uint16_t current_vclk0[MAX_CLKS]; 1219 uint16_t current_dclk0[MAX_CLKS]; 1220 uint16_t current_uclk; 1221 1222 /* Number of current partition */ 1223 uint16_t num_partition; 1224 1225 /* XCP metrics stats */ 1226 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1227 1228 /* PCIE other end recovery counter */ 1229 uint32_t pcie_lc_perf_other_end_recovery; 1230 }; 1231 1232 struct gpu_metrics_v1_8 { 1233 struct metrics_table_header common_header; 1234 1235 /* Temperature (Celsius) */ 1236 uint16_t temperature_hotspot; 1237 uint16_t temperature_mem; 1238 uint16_t temperature_vrsoc; 1239 1240 /* Power (Watts) */ 1241 uint16_t curr_socket_power; 1242 1243 /* Utilization (%) */ 1244 uint16_t average_gfx_activity; 1245 uint16_t average_umc_activity; // memory controller 1246 1247 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1248 uint64_t mem_max_bandwidth; 1249 1250 /* Energy (15.259uJ (2^-16) units) */ 1251 uint64_t energy_accumulator; 1252 1253 /* Driver attached timestamp (in ns) */ 1254 uint64_t system_clock_counter; 1255 1256 /* Accumulation cycle counter */ 1257 uint32_t accumulation_counter; 1258 1259 /* Accumulated throttler residencies */ 1260 uint32_t prochot_residency_acc; 1261 uint32_t ppt_residency_acc; 1262 uint32_t socket_thm_residency_acc; 1263 uint32_t vr_thm_residency_acc; 1264 uint32_t hbm_thm_residency_acc; 1265 1266 /* Clock Lock Status. Each bit corresponds to clock instance */ 1267 uint32_t gfxclk_lock_status; 1268 1269 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1270 uint16_t pcie_link_width; 1271 uint16_t pcie_link_speed; 1272 1273 /* XGMI bus width and bitrate (in Gbps) */ 1274 uint16_t xgmi_link_width; 1275 uint16_t xgmi_link_speed; 1276 1277 /* Utilization Accumulated (%) */ 1278 uint32_t gfx_activity_acc; 1279 uint32_t mem_activity_acc; 1280 1281 /*PCIE accumulated bandwidth (GB/sec) */ 1282 uint64_t pcie_bandwidth_acc; 1283 1284 /*PCIE instantaneous bandwidth (GB/sec) */ 1285 uint64_t pcie_bandwidth_inst; 1286 1287 /* PCIE L0 to recovery state transition accumulated count */ 1288 uint64_t pcie_l0_to_recov_count_acc; 1289 1290 /* PCIE replay accumulated count */ 1291 uint64_t pcie_replay_count_acc; 1292 1293 /* PCIE replay rollover accumulated count */ 1294 uint64_t pcie_replay_rover_count_acc; 1295 1296 /* PCIE NAK sent accumulated count */ 1297 uint32_t pcie_nak_sent_count_acc; 1298 1299 /* PCIE NAK received accumulated count */ 1300 uint32_t pcie_nak_rcvd_count_acc; 1301 1302 /* XGMI accumulated data transfer size(KiloBytes) */ 1303 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1304 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1305 1306 /* XGMI link status(active/inactive) */ 1307 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1308 1309 uint16_t padding; 1310 1311 /* PMFW attached timestamp (10ns resolution) */ 1312 uint64_t firmware_timestamp; 1313 1314 /* Current clocks (Mhz) */ 1315 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1316 uint16_t current_socclk[MAX_CLKS]; 1317 uint16_t current_vclk0[MAX_CLKS]; 1318 uint16_t current_dclk0[MAX_CLKS]; 1319 uint16_t current_uclk; 1320 1321 /* Number of current partition */ 1322 uint16_t num_partition; 1323 1324 /* XCP metrics stats */ 1325 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1326 1327 /* PCIE other end recovery counter */ 1328 uint32_t pcie_lc_perf_other_end_recovery; 1329 }; 1330 1331 struct gpu_metrics_attr { 1332 /* Field type encoded with AMDGPU_METRICS_ENC_ATTR */ 1333 uint64_t attr_encoding; 1334 /* Attribute value, depends on attr_encoding */ 1335 void *attr_value; 1336 }; 1337 1338 struct gpu_metrics_v1_9 { 1339 struct metrics_table_header common_header; 1340 int attr_count; 1341 struct gpu_metrics_attr metrics_attrs[]; 1342 }; 1343 1344 /* 1345 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1346 * Use gpu_metrics_v2_1 or later instead. 1347 */ 1348 struct gpu_metrics_v2_0 { 1349 struct metrics_table_header common_header; 1350 1351 /* Driver attached timestamp (in ns) */ 1352 uint64_t system_clock_counter; 1353 1354 /* Temperature */ 1355 uint16_t temperature_gfx; // gfx temperature on APUs 1356 uint16_t temperature_soc; // soc temperature on APUs 1357 uint16_t temperature_core[8]; // CPU core temperature on APUs 1358 uint16_t temperature_l3[2]; 1359 1360 /* Utilization */ 1361 uint16_t average_gfx_activity; 1362 uint16_t average_mm_activity; // UVD or VCN 1363 1364 /* Power/Energy */ 1365 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1366 uint16_t average_cpu_power; 1367 uint16_t average_soc_power; 1368 uint16_t average_gfx_power; 1369 uint16_t average_core_power[8]; // CPU core power on APUs 1370 1371 /* Average clocks */ 1372 uint16_t average_gfxclk_frequency; 1373 uint16_t average_socclk_frequency; 1374 uint16_t average_uclk_frequency; 1375 uint16_t average_fclk_frequency; 1376 uint16_t average_vclk_frequency; 1377 uint16_t average_dclk_frequency; 1378 1379 /* Current clocks */ 1380 uint16_t current_gfxclk; 1381 uint16_t current_socclk; 1382 uint16_t current_uclk; 1383 uint16_t current_fclk; 1384 uint16_t current_vclk; 1385 uint16_t current_dclk; 1386 uint16_t current_coreclk[8]; // CPU core clocks 1387 uint16_t current_l3clk[2]; 1388 1389 /* Throttle status */ 1390 uint32_t throttle_status; 1391 1392 /* Fans */ 1393 uint16_t fan_pwm; 1394 1395 uint16_t padding; 1396 }; 1397 1398 struct gpu_metrics_v2_1 { 1399 struct metrics_table_header common_header; 1400 1401 /* Temperature */ 1402 uint16_t temperature_gfx; // gfx temperature on APUs 1403 uint16_t temperature_soc; // soc temperature on APUs 1404 uint16_t temperature_core[8]; // CPU core temperature on APUs 1405 uint16_t temperature_l3[2]; 1406 1407 /* Utilization */ 1408 uint16_t average_gfx_activity; 1409 uint16_t average_mm_activity; // UVD or VCN 1410 1411 /* Driver attached timestamp (in ns) */ 1412 uint64_t system_clock_counter; 1413 1414 /* Power/Energy */ 1415 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1416 uint16_t average_cpu_power; 1417 uint16_t average_soc_power; 1418 uint16_t average_gfx_power; 1419 uint16_t average_core_power[8]; // CPU core power on APUs 1420 1421 /* Average clocks */ 1422 uint16_t average_gfxclk_frequency; 1423 uint16_t average_socclk_frequency; 1424 uint16_t average_uclk_frequency; 1425 uint16_t average_fclk_frequency; 1426 uint16_t average_vclk_frequency; 1427 uint16_t average_dclk_frequency; 1428 1429 /* Current clocks */ 1430 uint16_t current_gfxclk; 1431 uint16_t current_socclk; 1432 uint16_t current_uclk; 1433 uint16_t current_fclk; 1434 uint16_t current_vclk; 1435 uint16_t current_dclk; 1436 uint16_t current_coreclk[8]; // CPU core clocks 1437 uint16_t current_l3clk[2]; 1438 1439 /* Throttle status */ 1440 uint32_t throttle_status; 1441 1442 /* Fans */ 1443 uint16_t fan_pwm; 1444 1445 uint16_t padding[3]; 1446 }; 1447 1448 struct gpu_metrics_v2_2 { 1449 struct metrics_table_header common_header; 1450 1451 /* Temperature */ 1452 uint16_t temperature_gfx; // gfx temperature on APUs 1453 uint16_t temperature_soc; // soc temperature on APUs 1454 uint16_t temperature_core[8]; // CPU core temperature on APUs 1455 uint16_t temperature_l3[2]; 1456 1457 /* Utilization */ 1458 uint16_t average_gfx_activity; 1459 uint16_t average_mm_activity; // UVD or VCN 1460 1461 /* Driver attached timestamp (in ns) */ 1462 uint64_t system_clock_counter; 1463 1464 /* Power/Energy */ 1465 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1466 uint16_t average_cpu_power; 1467 uint16_t average_soc_power; 1468 uint16_t average_gfx_power; 1469 uint16_t average_core_power[8]; // CPU core power on APUs 1470 1471 /* Average clocks */ 1472 uint16_t average_gfxclk_frequency; 1473 uint16_t average_socclk_frequency; 1474 uint16_t average_uclk_frequency; 1475 uint16_t average_fclk_frequency; 1476 uint16_t average_vclk_frequency; 1477 uint16_t average_dclk_frequency; 1478 1479 /* Current clocks */ 1480 uint16_t current_gfxclk; 1481 uint16_t current_socclk; 1482 uint16_t current_uclk; 1483 uint16_t current_fclk; 1484 uint16_t current_vclk; 1485 uint16_t current_dclk; 1486 uint16_t current_coreclk[8]; // CPU core clocks 1487 uint16_t current_l3clk[2]; 1488 1489 /* Throttle status (ASIC dependent) */ 1490 uint32_t throttle_status; 1491 1492 /* Fans */ 1493 uint16_t fan_pwm; 1494 1495 uint16_t padding[3]; 1496 1497 /* Throttle status (ASIC independent) */ 1498 uint64_t indep_throttle_status; 1499 }; 1500 1501 struct gpu_metrics_v2_3 { 1502 struct metrics_table_header common_header; 1503 1504 /* Temperature */ 1505 uint16_t temperature_gfx; // gfx temperature on APUs 1506 uint16_t temperature_soc; // soc temperature on APUs 1507 uint16_t temperature_core[8]; // CPU core temperature on APUs 1508 uint16_t temperature_l3[2]; 1509 1510 /* Utilization */ 1511 uint16_t average_gfx_activity; 1512 uint16_t average_mm_activity; // UVD or VCN 1513 1514 /* Driver attached timestamp (in ns) */ 1515 uint64_t system_clock_counter; 1516 1517 /* Power/Energy */ 1518 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1519 uint16_t average_cpu_power; 1520 uint16_t average_soc_power; 1521 uint16_t average_gfx_power; 1522 uint16_t average_core_power[8]; // CPU core power on APUs 1523 1524 /* Average clocks */ 1525 uint16_t average_gfxclk_frequency; 1526 uint16_t average_socclk_frequency; 1527 uint16_t average_uclk_frequency; 1528 uint16_t average_fclk_frequency; 1529 uint16_t average_vclk_frequency; 1530 uint16_t average_dclk_frequency; 1531 1532 /* Current clocks */ 1533 uint16_t current_gfxclk; 1534 uint16_t current_socclk; 1535 uint16_t current_uclk; 1536 uint16_t current_fclk; 1537 uint16_t current_vclk; 1538 uint16_t current_dclk; 1539 uint16_t current_coreclk[8]; // CPU core clocks 1540 uint16_t current_l3clk[2]; 1541 1542 /* Throttle status (ASIC dependent) */ 1543 uint32_t throttle_status; 1544 1545 /* Fans */ 1546 uint16_t fan_pwm; 1547 1548 uint16_t padding[3]; 1549 1550 /* Throttle status (ASIC independent) */ 1551 uint64_t indep_throttle_status; 1552 1553 /* Average Temperature */ 1554 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1555 uint16_t average_temperature_soc; // average soc temperature on APUs 1556 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1557 uint16_t average_temperature_l3[2]; 1558 }; 1559 1560 struct gpu_metrics_v2_4 { 1561 struct metrics_table_header common_header; 1562 1563 /* Temperature (unit: centi-Celsius) */ 1564 uint16_t temperature_gfx; 1565 uint16_t temperature_soc; 1566 uint16_t temperature_core[8]; 1567 uint16_t temperature_l3[2]; 1568 1569 /* Utilization (unit: centi) */ 1570 uint16_t average_gfx_activity; 1571 uint16_t average_mm_activity; 1572 1573 /* Driver attached timestamp (in ns) */ 1574 uint64_t system_clock_counter; 1575 1576 /* Power/Energy (unit: mW) */ 1577 uint16_t average_socket_power; 1578 uint16_t average_cpu_power; 1579 uint16_t average_soc_power; 1580 uint16_t average_gfx_power; 1581 uint16_t average_core_power[8]; 1582 1583 /* Average clocks (unit: MHz) */ 1584 uint16_t average_gfxclk_frequency; 1585 uint16_t average_socclk_frequency; 1586 uint16_t average_uclk_frequency; 1587 uint16_t average_fclk_frequency; 1588 uint16_t average_vclk_frequency; 1589 uint16_t average_dclk_frequency; 1590 1591 /* Current clocks (unit: MHz) */ 1592 uint16_t current_gfxclk; 1593 uint16_t current_socclk; 1594 uint16_t current_uclk; 1595 uint16_t current_fclk; 1596 uint16_t current_vclk; 1597 uint16_t current_dclk; 1598 uint16_t current_coreclk[8]; 1599 uint16_t current_l3clk[2]; 1600 1601 /* Throttle status (ASIC dependent) */ 1602 uint32_t throttle_status; 1603 1604 /* Fans */ 1605 uint16_t fan_pwm; 1606 1607 uint16_t padding[3]; 1608 1609 /* Throttle status (ASIC independent) */ 1610 uint64_t indep_throttle_status; 1611 1612 /* Average Temperature (unit: centi-Celsius) */ 1613 uint16_t average_temperature_gfx; 1614 uint16_t average_temperature_soc; 1615 uint16_t average_temperature_core[8]; 1616 uint16_t average_temperature_l3[2]; 1617 1618 /* Power/Voltage (unit: mV) */ 1619 uint16_t average_cpu_voltage; 1620 uint16_t average_soc_voltage; 1621 uint16_t average_gfx_voltage; 1622 1623 /* Power/Current (unit: mA) */ 1624 uint16_t average_cpu_current; 1625 uint16_t average_soc_current; 1626 uint16_t average_gfx_current; 1627 }; 1628 1629 struct gpu_metrics_v3_0 { 1630 struct metrics_table_header common_header; 1631 1632 /* Temperature */ 1633 /* gfx temperature on APUs */ 1634 uint16_t temperature_gfx; 1635 /* soc temperature on APUs */ 1636 uint16_t temperature_soc; 1637 /* CPU core temperature on APUs */ 1638 uint16_t temperature_core[16]; 1639 /* skin temperature on APUs */ 1640 uint16_t temperature_skin; 1641 1642 /* Utilization */ 1643 /* time filtered GFX busy % [0-100] */ 1644 uint16_t average_gfx_activity; 1645 /* time filtered VCN busy % [0-100] */ 1646 uint16_t average_vcn_activity; 1647 /* time filtered IPU per-column busy % [0-100] */ 1648 uint16_t average_ipu_activity[8]; 1649 /* time filtered per-core C0 residency % [0-100]*/ 1650 uint16_t average_core_c0_activity[16]; 1651 /* time filtered DRAM read bandwidth [MB/sec] */ 1652 uint16_t average_dram_reads; 1653 /* time filtered DRAM write bandwidth [MB/sec] */ 1654 uint16_t average_dram_writes; 1655 /* time filtered IPU read bandwidth [MB/sec] */ 1656 uint16_t average_ipu_reads; 1657 /* time filtered IPU write bandwidth [MB/sec] */ 1658 uint16_t average_ipu_writes; 1659 1660 /* Driver attached timestamp (in ns) */ 1661 uint64_t system_clock_counter; 1662 1663 /* Power/Energy */ 1664 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1665 uint32_t average_socket_power; 1666 /* time filtered IPU power [mW] */ 1667 uint16_t average_ipu_power; 1668 /* time filtered APU power [mW] */ 1669 uint32_t average_apu_power; 1670 /* time filtered GFX power [mW] */ 1671 uint32_t average_gfx_power; 1672 /* time filtered dGPU power [mW] */ 1673 uint32_t average_dgpu_power; 1674 /* time filtered sum of core power across all cores in the socket [mW] */ 1675 uint32_t average_all_core_power; 1676 /* calculated core power [mW] */ 1677 uint16_t average_core_power[16]; 1678 /* time filtered total system power [mW] */ 1679 uint16_t average_sys_power; 1680 /* maximum IRM defined STAPM power limit [mW] */ 1681 uint16_t stapm_power_limit; 1682 /* time filtered STAPM power limit [mW] */ 1683 uint16_t current_stapm_power_limit; 1684 1685 /* time filtered clocks [MHz] */ 1686 uint16_t average_gfxclk_frequency; 1687 uint16_t average_socclk_frequency; 1688 uint16_t average_vpeclk_frequency; 1689 uint16_t average_ipuclk_frequency; 1690 uint16_t average_fclk_frequency; 1691 uint16_t average_vclk_frequency; 1692 uint16_t average_uclk_frequency; 1693 uint16_t average_mpipu_frequency; 1694 1695 /* Current clocks */ 1696 /* target core frequency [MHz] */ 1697 uint16_t current_coreclk[16]; 1698 /* CCLK frequency limit enforced on classic cores [MHz] */ 1699 uint16_t current_core_maxfreq; 1700 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1701 uint16_t current_gfx_maxfreq; 1702 1703 /* Throttle Residency (ASIC dependent) */ 1704 uint32_t throttle_residency_prochot; 1705 uint32_t throttle_residency_spl; 1706 uint32_t throttle_residency_fppt; 1707 uint32_t throttle_residency_sppt; 1708 uint32_t throttle_residency_thm_core; 1709 uint32_t throttle_residency_thm_gfx; 1710 uint32_t throttle_residency_thm_soc; 1711 1712 /* Metrics table alpha filter time constant [us] */ 1713 uint32_t time_filter_alphavalue; 1714 }; 1715 1716 struct amdgpu_pmmetrics_header { 1717 uint16_t structure_size; 1718 uint16_t pad; 1719 uint32_t mp1_ip_discovery_version; 1720 uint32_t pmfw_version; 1721 uint32_t pmmetrics_version; 1722 }; 1723 1724 struct amdgpu_pm_metrics { 1725 struct amdgpu_pmmetrics_header common_header; 1726 1727 uint8_t data[]; 1728 }; 1729 1730 enum amdgpu_vr_temp { 1731 AMDGPU_VDDCR_VDD0_TEMP, 1732 AMDGPU_VDDCR_VDD1_TEMP, 1733 AMDGPU_VDDCR_VDD2_TEMP, 1734 AMDGPU_VDDCR_VDD3_TEMP, 1735 AMDGPU_VDDCR_SOC_A_TEMP, 1736 AMDGPU_VDDCR_SOC_C_TEMP, 1737 AMDGPU_VDDCR_SOCIO_A_TEMP, 1738 AMDGPU_VDDCR_SOCIO_C_TEMP, 1739 AMDGPU_VDD_085_HBM_TEMP, 1740 AMDGPU_VDDCR_11_HBM_B_TEMP, 1741 AMDGPU_VDDCR_11_HBM_D_TEMP, 1742 AMDGPU_VDD_USR_TEMP, 1743 AMDGPU_VDDIO_11_E32_TEMP, 1744 AMDGPU_VR_MAX_TEMP_ENTRIES, 1745 }; 1746 1747 enum amdgpu_system_temp { 1748 AMDGPU_UBB_FPGA_TEMP, 1749 AMDGPU_UBB_FRONT_TEMP, 1750 AMDGPU_UBB_BACK_TEMP, 1751 AMDGPU_UBB_OAM7_TEMP, 1752 AMDGPU_UBB_IBC_TEMP, 1753 AMDGPU_UBB_UFPGA_TEMP, 1754 AMDGPU_UBB_OAM1_TEMP, 1755 AMDGPU_OAM_0_1_HSC_TEMP, 1756 AMDGPU_OAM_2_3_HSC_TEMP, 1757 AMDGPU_OAM_4_5_HSC_TEMP, 1758 AMDGPU_OAM_6_7_HSC_TEMP, 1759 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1760 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1761 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1762 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1763 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1764 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1765 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1766 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1767 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1768 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1769 AMDGPU_IBC_HSC_TEMP, 1770 AMDGPU_IBC_TEMP, 1771 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1772 }; 1773 1774 enum amdgpu_node_temp { 1775 AMDGPU_RETIMER_X_TEMP, 1776 AMDGPU_OAM_X_IBC_TEMP, 1777 AMDGPU_OAM_X_IBC_2_TEMP, 1778 AMDGPU_OAM_X_VDD18_VR_TEMP, 1779 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1780 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1781 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1782 }; 1783 1784 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1785 struct metrics_table_header common_header; 1786 uint16_t label_version; 1787 uint16_t node_id; 1788 uint64_t accumulation_counter; 1789 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1790 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1791 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1792 }; 1793 1794 struct amdgpu_baseboard_temp_metrics_v1_0 { 1795 struct metrics_table_header common_header; 1796 uint16_t label_version; 1797 uint16_t node_id; 1798 uint64_t accumulation_counter; 1799 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1800 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1801 }; 1802 1803 struct amdgpu_partition_metrics_v1_0 { 1804 struct metrics_table_header common_header; 1805 /* Current clocks (Mhz) */ 1806 uint16_t current_gfxclk[MAX_XCC]; 1807 uint16_t current_socclk[MAX_CLKS]; 1808 uint16_t current_vclk0[MAX_CLKS]; 1809 uint16_t current_dclk0[MAX_CLKS]; 1810 uint16_t current_uclk; 1811 uint16_t padding; 1812 1813 /* Utilization Instantaneous (%) */ 1814 uint32_t gfx_busy_inst[MAX_XCC]; 1815 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1816 uint16_t vcn_busy[NUM_VCN]; 1817 /* Utilization Accumulated (%) */ 1818 uint64_t gfx_busy_acc[MAX_XCC]; 1819 /* Total App Clock Counter Accumulated */ 1820 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1821 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1822 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1823 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1824 }; 1825 1826 struct amdgpu_partition_metrics_v1_1 { 1827 struct metrics_table_header common_header; 1828 int attr_count; 1829 struct gpu_metrics_attr metrics_attrs[]; 1830 }; 1831 1832 #endif 1833