1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_temp_metric_type { 34 SMU_TEMP_METRIC_BASEBOARD, 35 SMU_TEMP_METRIC_GPUBOARD, 36 SMU_TEMP_METRIC_MAX, 37 }; 38 39 enum smu_event_type { 40 SMU_EVENT_RESET_COMPLETE = 0, 41 }; 42 43 struct amd_vce_state { 44 /* vce clocks */ 45 u32 evclk; 46 u32 ecclk; 47 /* gpu clocks */ 48 u32 sclk; 49 u32 mclk; 50 u8 clk_idx; 51 u8 pstate; 52 }; 53 54 55 enum amd_dpm_forced_level { 56 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 57 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 58 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 59 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 60 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 61 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 62 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 63 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 64 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 65 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 66 }; 67 68 enum amd_pm_state_type { 69 /* not used for dpm */ 70 POWER_STATE_TYPE_DEFAULT, 71 POWER_STATE_TYPE_POWERSAVE, 72 /* user selectable states */ 73 POWER_STATE_TYPE_BATTERY, 74 POWER_STATE_TYPE_BALANCED, 75 POWER_STATE_TYPE_PERFORMANCE, 76 /* internal states */ 77 POWER_STATE_TYPE_INTERNAL_UVD, 78 POWER_STATE_TYPE_INTERNAL_UVD_SD, 79 POWER_STATE_TYPE_INTERNAL_UVD_HD, 80 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 81 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 82 POWER_STATE_TYPE_INTERNAL_BOOT, 83 POWER_STATE_TYPE_INTERNAL_THERMAL, 84 POWER_STATE_TYPE_INTERNAL_ACPI, 85 POWER_STATE_TYPE_INTERNAL_ULV, 86 POWER_STATE_TYPE_INTERNAL_3DPERF, 87 }; 88 89 #define AMD_MAX_VCE_LEVELS 6 90 91 enum amd_vce_level { 92 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 93 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 94 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 95 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 96 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 97 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 98 }; 99 100 enum amd_fan_ctrl_mode { 101 AMD_FAN_CTRL_NONE = 0, 102 AMD_FAN_CTRL_MANUAL = 1, 103 AMD_FAN_CTRL_AUTO = 2, 104 }; 105 106 enum pp_clock_type { 107 PP_SCLK, 108 PP_MCLK, 109 PP_PCIE, 110 PP_SOCCLK, 111 PP_FCLK, 112 PP_DCEFCLK, 113 PP_VCLK, 114 PP_VCLK1, 115 PP_DCLK, 116 PP_DCLK1, 117 PP_ISPICLK, 118 PP_ISPXCLK, 119 OD_SCLK, 120 OD_MCLK, 121 OD_VDDC_CURVE, 122 OD_RANGE, 123 OD_VDDGFX_OFFSET, 124 OD_CCLK, 125 OD_FAN_CURVE, 126 OD_ACOUSTIC_LIMIT, 127 OD_ACOUSTIC_TARGET, 128 OD_FAN_TARGET_TEMPERATURE, 129 OD_FAN_MINIMUM_PWM, 130 OD_FAN_ZERO_RPM_ENABLE, 131 OD_FAN_ZERO_RPM_STOP_TEMP, 132 }; 133 134 enum amd_pp_sensors { 135 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 136 AMDGPU_PP_SENSOR_CPU_CLK, 137 AMDGPU_PP_SENSOR_VDDNB, 138 AMDGPU_PP_SENSOR_VDDGFX, 139 AMDGPU_PP_SENSOR_VDDBOARD, 140 AMDGPU_PP_SENSOR_UVD_VCLK, 141 AMDGPU_PP_SENSOR_UVD_DCLK, 142 AMDGPU_PP_SENSOR_VCE_ECCLK, 143 AMDGPU_PP_SENSOR_GPU_LOAD, 144 AMDGPU_PP_SENSOR_MEM_LOAD, 145 AMDGPU_PP_SENSOR_GFX_MCLK, 146 AMDGPU_PP_SENSOR_GPU_TEMP, 147 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 148 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 149 AMDGPU_PP_SENSOR_MEM_TEMP, 150 AMDGPU_PP_SENSOR_VCE_POWER, 151 AMDGPU_PP_SENSOR_UVD_POWER, 152 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 153 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 154 AMDGPU_PP_SENSOR_SS_APU_SHARE, 155 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 156 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 157 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 158 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 159 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 160 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 161 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 162 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 163 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 164 AMDGPU_PP_SENSOR_VCN_LOAD, 165 }; 166 167 enum amd_pp_task { 168 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 169 AMD_PP_TASK_ENABLE_USER_STATE, 170 AMD_PP_TASK_READJUST_POWER_STATE, 171 AMD_PP_TASK_COMPLETE_INIT, 172 AMD_PP_TASK_MAX 173 }; 174 175 enum PP_SMC_POWER_PROFILE { 176 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 177 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 178 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 179 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 180 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 181 PP_SMC_POWER_PROFILE_VR = 0x4, 182 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 183 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 184 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 185 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 186 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 187 PP_SMC_POWER_PROFILE_COUNT, 188 }; 189 190 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 191 192 193 194 enum { 195 PP_GROUP_UNKNOWN = 0, 196 PP_GROUP_GFX = 1, 197 PP_GROUP_SYS, 198 PP_GROUP_MAX 199 }; 200 201 enum PP_OD_DPM_TABLE_COMMAND { 202 PP_OD_EDIT_SCLK_VDDC_TABLE, 203 PP_OD_EDIT_MCLK_VDDC_TABLE, 204 PP_OD_EDIT_CCLK_VDDC_TABLE, 205 PP_OD_EDIT_VDDC_CURVE, 206 PP_OD_RESTORE_DEFAULT_TABLE, 207 PP_OD_COMMIT_DPM_TABLE, 208 PP_OD_EDIT_VDDGFX_OFFSET, 209 PP_OD_EDIT_FAN_CURVE, 210 PP_OD_EDIT_ACOUSTIC_LIMIT, 211 PP_OD_EDIT_ACOUSTIC_TARGET, 212 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 213 PP_OD_EDIT_FAN_MINIMUM_PWM, 214 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 215 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 216 }; 217 218 struct pp_states_info { 219 uint32_t nums; 220 uint32_t states[16]; 221 }; 222 223 enum PP_HWMON_TEMP { 224 PP_TEMP_EDGE = 0, 225 PP_TEMP_JUNCTION, 226 PP_TEMP_MEM, 227 PP_TEMP_MAX 228 }; 229 230 enum pp_mp1_state { 231 PP_MP1_STATE_NONE, 232 PP_MP1_STATE_SHUTDOWN, 233 PP_MP1_STATE_UNLOAD, 234 PP_MP1_STATE_RESET, 235 PP_MP1_STATE_FLR, 236 }; 237 238 enum pp_df_cstate { 239 DF_CSTATE_DISALLOW = 0, 240 DF_CSTATE_ALLOW, 241 }; 242 243 /** 244 * DOC: amdgpu_pp_power 245 * 246 * APU power is managed to system-level requirements through the PPT 247 * (package power tracking) feature. PPT is intended to limit power to the 248 * requirements of the power source and could be dynamically updated to 249 * maximize APU performance within the system power budget. 250 * 251 * Two types of power measurement can be requested, where supported, with 252 * :c:type:`enum pp_power_type <pp_power_type>`. 253 */ 254 255 /** 256 * enum pp_power_limit_level - Used to query the power limits 257 * 258 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 259 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 260 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 261 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 262 */ 263 enum pp_power_limit_level { 264 PP_PWR_LIMIT_MIN = -1, 265 PP_PWR_LIMIT_CURRENT, 266 PP_PWR_LIMIT_DEFAULT, 267 PP_PWR_LIMIT_MAX, 268 }; 269 270 /** 271 * enum pp_power_type - Used to specify the type of the requested power 272 * 273 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 274 * moving average of APU power (default ~5000 ms). 275 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 276 * where supported. 277 */ 278 enum pp_power_type { 279 PP_PWR_TYPE_SUSTAINED, 280 PP_PWR_TYPE_FAST, 281 }; 282 283 enum pp_xgmi_plpd_mode { 284 XGMI_PLPD_NONE = -1, 285 XGMI_PLPD_DISALLOW, 286 XGMI_PLPD_DEFAULT, 287 XGMI_PLPD_OPTIMIZED, 288 XGMI_PLPD_COUNT, 289 }; 290 291 enum pp_pm_policy { 292 PP_PM_POLICY_NONE = -1, 293 PP_PM_POLICY_SOC_PSTATE = 0, 294 PP_PM_POLICY_XGMI_PLPD, 295 PP_PM_POLICY_NUM, 296 }; 297 298 enum pp_policy_soc_pstate { 299 SOC_PSTATE_DEFAULT = 0, 300 SOC_PSTATE_0, 301 SOC_PSTATE_1, 302 SOC_PSTATE_2, 303 SOC_PSTAT_COUNT, 304 }; 305 306 #define PP_POLICY_MAX_LEVELS 5 307 308 #define PP_GROUP_MASK 0xF0000000 309 #define PP_GROUP_SHIFT 28 310 311 #define PP_BLOCK_MASK 0x0FFFFF00 312 #define PP_BLOCK_SHIFT 8 313 314 #define PP_BLOCK_GFX_CG 0x01 315 #define PP_BLOCK_GFX_MG 0x02 316 #define PP_BLOCK_GFX_3D 0x04 317 #define PP_BLOCK_GFX_RLC 0x08 318 #define PP_BLOCK_GFX_CP 0x10 319 #define PP_BLOCK_SYS_BIF 0x01 320 #define PP_BLOCK_SYS_MC 0x02 321 #define PP_BLOCK_SYS_ROM 0x04 322 #define PP_BLOCK_SYS_DRM 0x08 323 #define PP_BLOCK_SYS_HDP 0x10 324 #define PP_BLOCK_SYS_SDMA 0x20 325 326 #define PP_STATE_MASK 0x0000000F 327 #define PP_STATE_SHIFT 0 328 #define PP_STATE_SUPPORT_MASK 0x000000F0 329 #define PP_STATE_SUPPORT_SHIFT 0 330 331 #define PP_STATE_CG 0x01 332 #define PP_STATE_LS 0x02 333 #define PP_STATE_DS 0x04 334 #define PP_STATE_SD 0x08 335 #define PP_STATE_SUPPORT_CG 0x10 336 #define PP_STATE_SUPPORT_LS 0x20 337 #define PP_STATE_SUPPORT_DS 0x40 338 #define PP_STATE_SUPPORT_SD 0x80 339 340 #define PP_CG_MSG_ID(group, block, support, state) \ 341 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 342 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 343 344 #define XGMI_MODE_PSTATE_D3 0 345 #define XGMI_MODE_PSTATE_D0 1 346 347 #define NUM_HBM_INSTANCES 4 348 #define NUM_XGMI_LINKS 8 349 #define MAX_GFX_CLKS 8 350 #define MAX_CLKS 4 351 #define NUM_VCN 4 352 #define NUM_JPEG_ENG 32 353 #define NUM_JPEG_ENG_V1 40 354 #define MAX_XCC 8 355 #define NUM_XCP 8 356 struct seq_file; 357 enum amd_pp_clock_type; 358 struct amd_pp_simple_clock_info; 359 struct amd_pp_display_configuration; 360 struct amd_pp_clock_info; 361 struct pp_display_clock_request; 362 struct pp_clock_levels_with_voltage; 363 struct pp_clock_levels_with_latency; 364 struct amd_pp_clocks; 365 struct pp_smu_wm_range_sets; 366 struct pp_smu_nv_clock_table; 367 struct dpm_clocks; 368 369 struct amdgpu_xcp_metrics { 370 /* Utilization Instantaneous (%) */ 371 uint32_t gfx_busy_inst[MAX_XCC]; 372 uint16_t jpeg_busy[NUM_JPEG_ENG]; 373 uint16_t vcn_busy[NUM_VCN]; 374 /* Utilization Accumulated (%) */ 375 uint64_t gfx_busy_acc[MAX_XCC]; 376 }; 377 378 struct amdgpu_xcp_metrics_v1_1 { 379 /* Utilization Instantaneous (%) */ 380 uint32_t gfx_busy_inst[MAX_XCC]; 381 uint16_t jpeg_busy[NUM_JPEG_ENG]; 382 uint16_t vcn_busy[NUM_VCN]; 383 /* Utilization Accumulated (%) */ 384 uint64_t gfx_busy_acc[MAX_XCC]; 385 /* Total App Clock Counter Accumulated */ 386 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 387 }; 388 389 struct amdgpu_xcp_metrics_v1_2 { 390 /* Utilization Instantaneous (%) */ 391 uint32_t gfx_busy_inst[MAX_XCC]; 392 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 393 uint16_t vcn_busy[NUM_VCN]; 394 /* Utilization Accumulated (%) */ 395 uint64_t gfx_busy_acc[MAX_XCC]; 396 /* Total App Clock Counter Accumulated */ 397 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 398 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 399 uint64_t gfx_low_utilization_acc[MAX_XCC]; 400 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 401 }; 402 403 struct amd_pm_funcs { 404 /* export for dpm on ci and si */ 405 int (*pre_set_power_state)(void *handle); 406 int (*set_power_state)(void *handle); 407 void (*post_set_power_state)(void *handle); 408 void (*display_configuration_changed)(void *handle); 409 void (*print_power_state)(void *handle, void *ps); 410 bool (*vblank_too_short)(void *handle); 411 void (*enable_bapm)(void *handle, bool enable); 412 int (*check_state_equal)(void *handle, 413 void *cps, 414 void *rps, 415 bool *equal); 416 /* export for sysfs */ 417 int (*set_fan_control_mode)(void *handle, u32 mode); 418 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 419 int (*set_fan_speed_pwm)(void *handle, u32 speed); 420 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 421 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 422 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 423 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 424 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 425 int (*get_sclk_od)(void *handle); 426 int (*set_sclk_od)(void *handle, uint32_t value); 427 int (*get_mclk_od)(void *handle); 428 int (*set_mclk_od)(void *handle, uint32_t value); 429 int (*read_sensor)(void *handle, int idx, void *value, int *size); 430 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 431 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 432 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 433 enum amd_pm_state_type (*get_current_power_state)(void *handle); 434 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 435 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 436 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 437 int (*get_pp_table)(void *handle, char **table); 438 int (*set_pp_table)(void *handle, const char *buf, size_t size); 439 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 440 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 441 int (*pause_power_profile)(void *handle, bool pause); 442 /* export to amdgpu */ 443 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 444 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 445 enum amd_pm_state_type *user_state); 446 int (*load_firmware)(void *handle); 447 int (*wait_for_fw_loading_complete)(void *handle); 448 int (*set_powergating_by_smu)(void *handle, 449 uint32_t block_type, 450 bool gate, 451 int inst); 452 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 453 int (*set_power_limit)(void *handle, uint32_t n); 454 int (*get_power_limit)(void *handle, uint32_t *limit, 455 enum pp_power_limit_level pp_limit_level, 456 enum pp_power_type power_type); 457 int (*get_power_profile_mode)(void *handle, char *buf); 458 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 459 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 460 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 461 long *input, uint32_t size); 462 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 463 int (*smu_i2c_bus_access)(void *handle, bool acquire); 464 int (*gfx_state_change_set)(void *handle, uint32_t state); 465 /* export to DC */ 466 u32 (*get_sclk)(void *handle, bool low); 467 u32 (*get_mclk)(void *handle, bool low); 468 int (*display_configuration_change)(void *handle, 469 const struct amd_pp_display_configuration *input); 470 int (*get_display_power_level)(void *handle, 471 struct amd_pp_simple_clock_info *output); 472 int (*get_current_clocks)(void *handle, 473 struct amd_pp_clock_info *clocks); 474 int (*get_clock_by_type)(void *handle, 475 enum amd_pp_clock_type type, 476 struct amd_pp_clocks *clocks); 477 int (*get_clock_by_type_with_latency)(void *handle, 478 enum amd_pp_clock_type type, 479 struct pp_clock_levels_with_latency *clocks); 480 int (*get_clock_by_type_with_voltage)(void *handle, 481 enum amd_pp_clock_type type, 482 struct pp_clock_levels_with_voltage *clocks); 483 int (*set_watermarks_for_clocks_ranges)(void *handle, 484 void *clock_ranges); 485 int (*display_clock_voltage_request)(void *handle, 486 struct pp_display_clock_request *clock); 487 int (*get_display_mode_validation_clocks)(void *handle, 488 struct amd_pp_simple_clock_info *clocks); 489 int (*notify_smu_enable_pwe)(void *handle); 490 int (*enable_mgpu_fan_boost)(void *handle); 491 int (*set_active_display_count)(void *handle, uint32_t count); 492 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 493 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 494 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 495 int (*get_asic_baco_capability)(void *handle); 496 int (*get_asic_baco_state)(void *handle, int *state); 497 int (*set_asic_baco_state)(void *handle, int state); 498 int (*get_ppfeature_status)(void *handle, char *buf); 499 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 500 int (*asic_reset_mode_2)(void *handle); 501 int (*asic_reset_enable_gfx_features)(void *handle); 502 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 503 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 504 ssize_t (*get_gpu_metrics)(void *handle, void **table); 505 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 506 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 507 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 508 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 509 int (*set_watermarks_for_clock_ranges)(void *handle, 510 struct pp_smu_wm_range_sets *ranges); 511 int (*display_disable_memory_clock_switch)(void *handle, 512 bool disable_memory_clock_switch); 513 int (*get_max_sustainable_clocks_by_dc)(void *handle, 514 struct pp_smu_nv_clock_table *max_clocks); 515 int (*get_uclk_dpm_states)(void *handle, 516 unsigned int *clock_values_in_khz, 517 unsigned int *num_states); 518 int (*get_dpm_clock_table)(void *handle, 519 struct dpm_clocks *clock_table); 520 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 521 void (*pm_compute_clocks)(void *handle); 522 int (*notify_rlc_state)(void *handle, bool en); 523 }; 524 525 struct metrics_table_header { 526 uint16_t structure_size; 527 uint8_t format_revision; 528 uint8_t content_revision; 529 }; 530 531 /* 532 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 533 * Use gpu_metrics_v1_1 or later instead. 534 */ 535 struct gpu_metrics_v1_0 { 536 struct metrics_table_header common_header; 537 538 /* Driver attached timestamp (in ns) */ 539 uint64_t system_clock_counter; 540 541 /* Temperature */ 542 uint16_t temperature_edge; 543 uint16_t temperature_hotspot; 544 uint16_t temperature_mem; 545 uint16_t temperature_vrgfx; 546 uint16_t temperature_vrsoc; 547 uint16_t temperature_vrmem; 548 549 /* Utilization */ 550 uint16_t average_gfx_activity; 551 uint16_t average_umc_activity; // memory controller 552 uint16_t average_mm_activity; // UVD or VCN 553 554 /* Power/Energy */ 555 uint16_t average_socket_power; 556 uint32_t energy_accumulator; 557 558 /* Average clocks */ 559 uint16_t average_gfxclk_frequency; 560 uint16_t average_socclk_frequency; 561 uint16_t average_uclk_frequency; 562 uint16_t average_vclk0_frequency; 563 uint16_t average_dclk0_frequency; 564 uint16_t average_vclk1_frequency; 565 uint16_t average_dclk1_frequency; 566 567 /* Current clocks */ 568 uint16_t current_gfxclk; 569 uint16_t current_socclk; 570 uint16_t current_uclk; 571 uint16_t current_vclk0; 572 uint16_t current_dclk0; 573 uint16_t current_vclk1; 574 uint16_t current_dclk1; 575 576 /* Throttle status */ 577 uint32_t throttle_status; 578 579 /* Fans */ 580 uint16_t current_fan_speed; 581 582 /* Link width/speed */ 583 uint8_t pcie_link_width; 584 uint8_t pcie_link_speed; // in 0.1 GT/s 585 }; 586 587 struct gpu_metrics_v1_1 { 588 struct metrics_table_header common_header; 589 590 /* Temperature */ 591 uint16_t temperature_edge; 592 uint16_t temperature_hotspot; 593 uint16_t temperature_mem; 594 uint16_t temperature_vrgfx; 595 uint16_t temperature_vrsoc; 596 uint16_t temperature_vrmem; 597 598 /* Utilization */ 599 uint16_t average_gfx_activity; 600 uint16_t average_umc_activity; // memory controller 601 uint16_t average_mm_activity; // UVD or VCN 602 603 /* Power/Energy */ 604 uint16_t average_socket_power; 605 uint64_t energy_accumulator; 606 607 /* Driver attached timestamp (in ns) */ 608 uint64_t system_clock_counter; 609 610 /* Average clocks */ 611 uint16_t average_gfxclk_frequency; 612 uint16_t average_socclk_frequency; 613 uint16_t average_uclk_frequency; 614 uint16_t average_vclk0_frequency; 615 uint16_t average_dclk0_frequency; 616 uint16_t average_vclk1_frequency; 617 uint16_t average_dclk1_frequency; 618 619 /* Current clocks */ 620 uint16_t current_gfxclk; 621 uint16_t current_socclk; 622 uint16_t current_uclk; 623 uint16_t current_vclk0; 624 uint16_t current_dclk0; 625 uint16_t current_vclk1; 626 uint16_t current_dclk1; 627 628 /* Throttle status */ 629 uint32_t throttle_status; 630 631 /* Fans */ 632 uint16_t current_fan_speed; 633 634 /* Link width/speed */ 635 uint16_t pcie_link_width; 636 uint16_t pcie_link_speed; // in 0.1 GT/s 637 638 uint16_t padding; 639 640 uint32_t gfx_activity_acc; 641 uint32_t mem_activity_acc; 642 643 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 644 }; 645 646 struct gpu_metrics_v1_2 { 647 struct metrics_table_header common_header; 648 649 /* Temperature */ 650 uint16_t temperature_edge; 651 uint16_t temperature_hotspot; 652 uint16_t temperature_mem; 653 uint16_t temperature_vrgfx; 654 uint16_t temperature_vrsoc; 655 uint16_t temperature_vrmem; 656 657 /* Utilization */ 658 uint16_t average_gfx_activity; 659 uint16_t average_umc_activity; // memory controller 660 uint16_t average_mm_activity; // UVD or VCN 661 662 /* Power/Energy */ 663 uint16_t average_socket_power; 664 uint64_t energy_accumulator; 665 666 /* Driver attached timestamp (in ns) */ 667 uint64_t system_clock_counter; 668 669 /* Average clocks */ 670 uint16_t average_gfxclk_frequency; 671 uint16_t average_socclk_frequency; 672 uint16_t average_uclk_frequency; 673 uint16_t average_vclk0_frequency; 674 uint16_t average_dclk0_frequency; 675 uint16_t average_vclk1_frequency; 676 uint16_t average_dclk1_frequency; 677 678 /* Current clocks */ 679 uint16_t current_gfxclk; 680 uint16_t current_socclk; 681 uint16_t current_uclk; 682 uint16_t current_vclk0; 683 uint16_t current_dclk0; 684 uint16_t current_vclk1; 685 uint16_t current_dclk1; 686 687 /* Throttle status (ASIC dependent) */ 688 uint32_t throttle_status; 689 690 /* Fans */ 691 uint16_t current_fan_speed; 692 693 /* Link width/speed */ 694 uint16_t pcie_link_width; 695 uint16_t pcie_link_speed; // in 0.1 GT/s 696 697 uint16_t padding; 698 699 uint32_t gfx_activity_acc; 700 uint32_t mem_activity_acc; 701 702 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 703 704 /* PMFW attached timestamp (10ns resolution) */ 705 uint64_t firmware_timestamp; 706 }; 707 708 struct gpu_metrics_v1_3 { 709 struct metrics_table_header common_header; 710 711 /* Temperature */ 712 uint16_t temperature_edge; 713 uint16_t temperature_hotspot; 714 uint16_t temperature_mem; 715 uint16_t temperature_vrgfx; 716 uint16_t temperature_vrsoc; 717 uint16_t temperature_vrmem; 718 719 /* Utilization */ 720 uint16_t average_gfx_activity; 721 uint16_t average_umc_activity; // memory controller 722 uint16_t average_mm_activity; // UVD or VCN 723 724 /* Power/Energy */ 725 uint16_t average_socket_power; 726 uint64_t energy_accumulator; 727 728 /* Driver attached timestamp (in ns) */ 729 uint64_t system_clock_counter; 730 731 /* Average clocks */ 732 uint16_t average_gfxclk_frequency; 733 uint16_t average_socclk_frequency; 734 uint16_t average_uclk_frequency; 735 uint16_t average_vclk0_frequency; 736 uint16_t average_dclk0_frequency; 737 uint16_t average_vclk1_frequency; 738 uint16_t average_dclk1_frequency; 739 740 /* Current clocks */ 741 uint16_t current_gfxclk; 742 uint16_t current_socclk; 743 uint16_t current_uclk; 744 uint16_t current_vclk0; 745 uint16_t current_dclk0; 746 uint16_t current_vclk1; 747 uint16_t current_dclk1; 748 749 /* Throttle status */ 750 uint32_t throttle_status; 751 752 /* Fans */ 753 uint16_t current_fan_speed; 754 755 /* Link width/speed */ 756 uint16_t pcie_link_width; 757 uint16_t pcie_link_speed; // in 0.1 GT/s 758 759 uint16_t padding; 760 761 uint32_t gfx_activity_acc; 762 uint32_t mem_activity_acc; 763 764 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 765 766 /* PMFW attached timestamp (10ns resolution) */ 767 uint64_t firmware_timestamp; 768 769 /* Voltage (mV) */ 770 uint16_t voltage_soc; 771 uint16_t voltage_gfx; 772 uint16_t voltage_mem; 773 774 uint16_t padding1; 775 776 /* Throttle status (ASIC independent) */ 777 uint64_t indep_throttle_status; 778 }; 779 780 struct gpu_metrics_v1_4 { 781 struct metrics_table_header common_header; 782 783 /* Temperature (Celsius) */ 784 uint16_t temperature_hotspot; 785 uint16_t temperature_mem; 786 uint16_t temperature_vrsoc; 787 788 /* Power (Watts) */ 789 uint16_t curr_socket_power; 790 791 /* Utilization (%) */ 792 uint16_t average_gfx_activity; 793 uint16_t average_umc_activity; // memory controller 794 uint16_t vcn_activity[NUM_VCN]; 795 796 /* Energy (15.259uJ (2^-16) units) */ 797 uint64_t energy_accumulator; 798 799 /* Driver attached timestamp (in ns) */ 800 uint64_t system_clock_counter; 801 802 /* Throttle status */ 803 uint32_t throttle_status; 804 805 /* Clock Lock Status. Each bit corresponds to clock instance */ 806 uint32_t gfxclk_lock_status; 807 808 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 809 uint16_t pcie_link_width; 810 uint16_t pcie_link_speed; 811 812 /* XGMI bus width and bitrate (in Gbps) */ 813 uint16_t xgmi_link_width; 814 uint16_t xgmi_link_speed; 815 816 /* Utilization Accumulated (%) */ 817 uint32_t gfx_activity_acc; 818 uint32_t mem_activity_acc; 819 820 /*PCIE accumulated bandwidth (GB/sec) */ 821 uint64_t pcie_bandwidth_acc; 822 823 /*PCIE instantaneous bandwidth (GB/sec) */ 824 uint64_t pcie_bandwidth_inst; 825 826 /* PCIE L0 to recovery state transition accumulated count */ 827 uint64_t pcie_l0_to_recov_count_acc; 828 829 /* PCIE replay accumulated count */ 830 uint64_t pcie_replay_count_acc; 831 832 /* PCIE replay rollover accumulated count */ 833 uint64_t pcie_replay_rover_count_acc; 834 835 /* XGMI accumulated data transfer size(KiloBytes) */ 836 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 837 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 838 839 /* PMFW attached timestamp (10ns resolution) */ 840 uint64_t firmware_timestamp; 841 842 /* Current clocks (Mhz) */ 843 uint16_t current_gfxclk[MAX_GFX_CLKS]; 844 uint16_t current_socclk[MAX_CLKS]; 845 uint16_t current_vclk0[MAX_CLKS]; 846 uint16_t current_dclk0[MAX_CLKS]; 847 uint16_t current_uclk; 848 849 uint16_t padding; 850 }; 851 852 struct gpu_metrics_v1_5 { 853 struct metrics_table_header common_header; 854 855 /* Temperature (Celsius) */ 856 uint16_t temperature_hotspot; 857 uint16_t temperature_mem; 858 uint16_t temperature_vrsoc; 859 860 /* Power (Watts) */ 861 uint16_t curr_socket_power; 862 863 /* Utilization (%) */ 864 uint16_t average_gfx_activity; 865 uint16_t average_umc_activity; // memory controller 866 uint16_t vcn_activity[NUM_VCN]; 867 uint16_t jpeg_activity[NUM_JPEG_ENG]; 868 869 /* Energy (15.259uJ (2^-16) units) */ 870 uint64_t energy_accumulator; 871 872 /* Driver attached timestamp (in ns) */ 873 uint64_t system_clock_counter; 874 875 /* Throttle status */ 876 uint32_t throttle_status; 877 878 /* Clock Lock Status. Each bit corresponds to clock instance */ 879 uint32_t gfxclk_lock_status; 880 881 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 882 uint16_t pcie_link_width; 883 uint16_t pcie_link_speed; 884 885 /* XGMI bus width and bitrate (in Gbps) */ 886 uint16_t xgmi_link_width; 887 uint16_t xgmi_link_speed; 888 889 /* Utilization Accumulated (%) */ 890 uint32_t gfx_activity_acc; 891 uint32_t mem_activity_acc; 892 893 /*PCIE accumulated bandwidth (GB/sec) */ 894 uint64_t pcie_bandwidth_acc; 895 896 /*PCIE instantaneous bandwidth (GB/sec) */ 897 uint64_t pcie_bandwidth_inst; 898 899 /* PCIE L0 to recovery state transition accumulated count */ 900 uint64_t pcie_l0_to_recov_count_acc; 901 902 /* PCIE replay accumulated count */ 903 uint64_t pcie_replay_count_acc; 904 905 /* PCIE replay rollover accumulated count */ 906 uint64_t pcie_replay_rover_count_acc; 907 908 /* PCIE NAK sent accumulated count */ 909 uint32_t pcie_nak_sent_count_acc; 910 911 /* PCIE NAK received accumulated count */ 912 uint32_t pcie_nak_rcvd_count_acc; 913 914 /* XGMI accumulated data transfer size(KiloBytes) */ 915 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 916 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 917 918 /* PMFW attached timestamp (10ns resolution) */ 919 uint64_t firmware_timestamp; 920 921 /* Current clocks (Mhz) */ 922 uint16_t current_gfxclk[MAX_GFX_CLKS]; 923 uint16_t current_socclk[MAX_CLKS]; 924 uint16_t current_vclk0[MAX_CLKS]; 925 uint16_t current_dclk0[MAX_CLKS]; 926 uint16_t current_uclk; 927 928 uint16_t padding; 929 }; 930 931 struct gpu_metrics_v1_6 { 932 struct metrics_table_header common_header; 933 934 /* Temperature (Celsius) */ 935 uint16_t temperature_hotspot; 936 uint16_t temperature_mem; 937 uint16_t temperature_vrsoc; 938 939 /* Power (Watts) */ 940 uint16_t curr_socket_power; 941 942 /* Utilization (%) */ 943 uint16_t average_gfx_activity; 944 uint16_t average_umc_activity; // memory controller 945 946 /* Energy (15.259uJ (2^-16) units) */ 947 uint64_t energy_accumulator; 948 949 /* Driver attached timestamp (in ns) */ 950 uint64_t system_clock_counter; 951 952 /* Accumulation cycle counter */ 953 uint32_t accumulation_counter; 954 955 /* Accumulated throttler residencies */ 956 uint32_t prochot_residency_acc; 957 uint32_t ppt_residency_acc; 958 uint32_t socket_thm_residency_acc; 959 uint32_t vr_thm_residency_acc; 960 uint32_t hbm_thm_residency_acc; 961 962 /* Clock Lock Status. Each bit corresponds to clock instance */ 963 uint32_t gfxclk_lock_status; 964 965 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 966 uint16_t pcie_link_width; 967 uint16_t pcie_link_speed; 968 969 /* XGMI bus width and bitrate (in Gbps) */ 970 uint16_t xgmi_link_width; 971 uint16_t xgmi_link_speed; 972 973 /* Utilization Accumulated (%) */ 974 uint32_t gfx_activity_acc; 975 uint32_t mem_activity_acc; 976 977 /*PCIE accumulated bandwidth (GB/sec) */ 978 uint64_t pcie_bandwidth_acc; 979 980 /*PCIE instantaneous bandwidth (GB/sec) */ 981 uint64_t pcie_bandwidth_inst; 982 983 /* PCIE L0 to recovery state transition accumulated count */ 984 uint64_t pcie_l0_to_recov_count_acc; 985 986 /* PCIE replay accumulated count */ 987 uint64_t pcie_replay_count_acc; 988 989 /* PCIE replay rollover accumulated count */ 990 uint64_t pcie_replay_rover_count_acc; 991 992 /* PCIE NAK sent accumulated count */ 993 uint32_t pcie_nak_sent_count_acc; 994 995 /* PCIE NAK received accumulated count */ 996 uint32_t pcie_nak_rcvd_count_acc; 997 998 /* XGMI accumulated data transfer size(KiloBytes) */ 999 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1000 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1001 1002 /* PMFW attached timestamp (10ns resolution) */ 1003 uint64_t firmware_timestamp; 1004 1005 /* Current clocks (Mhz) */ 1006 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1007 uint16_t current_socclk[MAX_CLKS]; 1008 uint16_t current_vclk0[MAX_CLKS]; 1009 uint16_t current_dclk0[MAX_CLKS]; 1010 uint16_t current_uclk; 1011 1012 /* Number of current partition */ 1013 uint16_t num_partition; 1014 1015 /* XCP metrics stats */ 1016 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1017 1018 /* PCIE other end recovery counter */ 1019 uint32_t pcie_lc_perf_other_end_recovery; 1020 }; 1021 1022 struct gpu_metrics_v1_7 { 1023 struct metrics_table_header common_header; 1024 1025 /* Temperature (Celsius) */ 1026 uint16_t temperature_hotspot; 1027 uint16_t temperature_mem; 1028 uint16_t temperature_vrsoc; 1029 1030 /* Power (Watts) */ 1031 uint16_t curr_socket_power; 1032 1033 /* Utilization (%) */ 1034 uint16_t average_gfx_activity; 1035 uint16_t average_umc_activity; // memory controller 1036 1037 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1038 uint64_t mem_max_bandwidth; 1039 1040 /* Energy (15.259uJ (2^-16) units) */ 1041 uint64_t energy_accumulator; 1042 1043 /* Driver attached timestamp (in ns) */ 1044 uint64_t system_clock_counter; 1045 1046 /* Accumulation cycle counter */ 1047 uint32_t accumulation_counter; 1048 1049 /* Accumulated throttler residencies */ 1050 uint32_t prochot_residency_acc; 1051 uint32_t ppt_residency_acc; 1052 uint32_t socket_thm_residency_acc; 1053 uint32_t vr_thm_residency_acc; 1054 uint32_t hbm_thm_residency_acc; 1055 1056 /* Clock Lock Status. Each bit corresponds to clock instance */ 1057 uint32_t gfxclk_lock_status; 1058 1059 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1060 uint16_t pcie_link_width; 1061 uint16_t pcie_link_speed; 1062 1063 /* XGMI bus width and bitrate (in Gbps) */ 1064 uint16_t xgmi_link_width; 1065 uint16_t xgmi_link_speed; 1066 1067 /* Utilization Accumulated (%) */ 1068 uint32_t gfx_activity_acc; 1069 uint32_t mem_activity_acc; 1070 1071 /*PCIE accumulated bandwidth (GB/sec) */ 1072 uint64_t pcie_bandwidth_acc; 1073 1074 /*PCIE instantaneous bandwidth (GB/sec) */ 1075 uint64_t pcie_bandwidth_inst; 1076 1077 /* PCIE L0 to recovery state transition accumulated count */ 1078 uint64_t pcie_l0_to_recov_count_acc; 1079 1080 /* PCIE replay accumulated count */ 1081 uint64_t pcie_replay_count_acc; 1082 1083 /* PCIE replay rollover accumulated count */ 1084 uint64_t pcie_replay_rover_count_acc; 1085 1086 /* PCIE NAK sent accumulated count */ 1087 uint32_t pcie_nak_sent_count_acc; 1088 1089 /* PCIE NAK received accumulated count */ 1090 uint32_t pcie_nak_rcvd_count_acc; 1091 1092 /* XGMI accumulated data transfer size(KiloBytes) */ 1093 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1094 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1095 1096 /* XGMI link status(active/inactive) */ 1097 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1098 1099 uint16_t padding; 1100 1101 /* PMFW attached timestamp (10ns resolution) */ 1102 uint64_t firmware_timestamp; 1103 1104 /* Current clocks (Mhz) */ 1105 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1106 uint16_t current_socclk[MAX_CLKS]; 1107 uint16_t current_vclk0[MAX_CLKS]; 1108 uint16_t current_dclk0[MAX_CLKS]; 1109 uint16_t current_uclk; 1110 1111 /* Number of current partition */ 1112 uint16_t num_partition; 1113 1114 /* XCP metrics stats */ 1115 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1116 1117 /* PCIE other end recovery counter */ 1118 uint32_t pcie_lc_perf_other_end_recovery; 1119 }; 1120 1121 struct gpu_metrics_v1_8 { 1122 struct metrics_table_header common_header; 1123 1124 /* Temperature (Celsius) */ 1125 uint16_t temperature_hotspot; 1126 uint16_t temperature_mem; 1127 uint16_t temperature_vrsoc; 1128 1129 /* Power (Watts) */ 1130 uint16_t curr_socket_power; 1131 1132 /* Utilization (%) */ 1133 uint16_t average_gfx_activity; 1134 uint16_t average_umc_activity; // memory controller 1135 1136 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1137 uint64_t mem_max_bandwidth; 1138 1139 /* Energy (15.259uJ (2^-16) units) */ 1140 uint64_t energy_accumulator; 1141 1142 /* Driver attached timestamp (in ns) */ 1143 uint64_t system_clock_counter; 1144 1145 /* Accumulation cycle counter */ 1146 uint32_t accumulation_counter; 1147 1148 /* Accumulated throttler residencies */ 1149 uint32_t prochot_residency_acc; 1150 uint32_t ppt_residency_acc; 1151 uint32_t socket_thm_residency_acc; 1152 uint32_t vr_thm_residency_acc; 1153 uint32_t hbm_thm_residency_acc; 1154 1155 /* Clock Lock Status. Each bit corresponds to clock instance */ 1156 uint32_t gfxclk_lock_status; 1157 1158 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1159 uint16_t pcie_link_width; 1160 uint16_t pcie_link_speed; 1161 1162 /* XGMI bus width and bitrate (in Gbps) */ 1163 uint16_t xgmi_link_width; 1164 uint16_t xgmi_link_speed; 1165 1166 /* Utilization Accumulated (%) */ 1167 uint32_t gfx_activity_acc; 1168 uint32_t mem_activity_acc; 1169 1170 /*PCIE accumulated bandwidth (GB/sec) */ 1171 uint64_t pcie_bandwidth_acc; 1172 1173 /*PCIE instantaneous bandwidth (GB/sec) */ 1174 uint64_t pcie_bandwidth_inst; 1175 1176 /* PCIE L0 to recovery state transition accumulated count */ 1177 uint64_t pcie_l0_to_recov_count_acc; 1178 1179 /* PCIE replay accumulated count */ 1180 uint64_t pcie_replay_count_acc; 1181 1182 /* PCIE replay rollover accumulated count */ 1183 uint64_t pcie_replay_rover_count_acc; 1184 1185 /* PCIE NAK sent accumulated count */ 1186 uint32_t pcie_nak_sent_count_acc; 1187 1188 /* PCIE NAK received accumulated count */ 1189 uint32_t pcie_nak_rcvd_count_acc; 1190 1191 /* XGMI accumulated data transfer size(KiloBytes) */ 1192 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1193 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1194 1195 /* XGMI link status(active/inactive) */ 1196 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1197 1198 uint16_t padding; 1199 1200 /* PMFW attached timestamp (10ns resolution) */ 1201 uint64_t firmware_timestamp; 1202 1203 /* Current clocks (Mhz) */ 1204 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1205 uint16_t current_socclk[MAX_CLKS]; 1206 uint16_t current_vclk0[MAX_CLKS]; 1207 uint16_t current_dclk0[MAX_CLKS]; 1208 uint16_t current_uclk; 1209 1210 /* Number of current partition */ 1211 uint16_t num_partition; 1212 1213 /* XCP metrics stats */ 1214 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1215 1216 /* PCIE other end recovery counter */ 1217 uint32_t pcie_lc_perf_other_end_recovery; 1218 }; 1219 1220 /* 1221 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1222 * Use gpu_metrics_v2_1 or later instead. 1223 */ 1224 struct gpu_metrics_v2_0 { 1225 struct metrics_table_header common_header; 1226 1227 /* Driver attached timestamp (in ns) */ 1228 uint64_t system_clock_counter; 1229 1230 /* Temperature */ 1231 uint16_t temperature_gfx; // gfx temperature on APUs 1232 uint16_t temperature_soc; // soc temperature on APUs 1233 uint16_t temperature_core[8]; // CPU core temperature on APUs 1234 uint16_t temperature_l3[2]; 1235 1236 /* Utilization */ 1237 uint16_t average_gfx_activity; 1238 uint16_t average_mm_activity; // UVD or VCN 1239 1240 /* Power/Energy */ 1241 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1242 uint16_t average_cpu_power; 1243 uint16_t average_soc_power; 1244 uint16_t average_gfx_power; 1245 uint16_t average_core_power[8]; // CPU core power on APUs 1246 1247 /* Average clocks */ 1248 uint16_t average_gfxclk_frequency; 1249 uint16_t average_socclk_frequency; 1250 uint16_t average_uclk_frequency; 1251 uint16_t average_fclk_frequency; 1252 uint16_t average_vclk_frequency; 1253 uint16_t average_dclk_frequency; 1254 1255 /* Current clocks */ 1256 uint16_t current_gfxclk; 1257 uint16_t current_socclk; 1258 uint16_t current_uclk; 1259 uint16_t current_fclk; 1260 uint16_t current_vclk; 1261 uint16_t current_dclk; 1262 uint16_t current_coreclk[8]; // CPU core clocks 1263 uint16_t current_l3clk[2]; 1264 1265 /* Throttle status */ 1266 uint32_t throttle_status; 1267 1268 /* Fans */ 1269 uint16_t fan_pwm; 1270 1271 uint16_t padding; 1272 }; 1273 1274 struct gpu_metrics_v2_1 { 1275 struct metrics_table_header common_header; 1276 1277 /* Temperature */ 1278 uint16_t temperature_gfx; // gfx temperature on APUs 1279 uint16_t temperature_soc; // soc temperature on APUs 1280 uint16_t temperature_core[8]; // CPU core temperature on APUs 1281 uint16_t temperature_l3[2]; 1282 1283 /* Utilization */ 1284 uint16_t average_gfx_activity; 1285 uint16_t average_mm_activity; // UVD or VCN 1286 1287 /* Driver attached timestamp (in ns) */ 1288 uint64_t system_clock_counter; 1289 1290 /* Power/Energy */ 1291 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1292 uint16_t average_cpu_power; 1293 uint16_t average_soc_power; 1294 uint16_t average_gfx_power; 1295 uint16_t average_core_power[8]; // CPU core power on APUs 1296 1297 /* Average clocks */ 1298 uint16_t average_gfxclk_frequency; 1299 uint16_t average_socclk_frequency; 1300 uint16_t average_uclk_frequency; 1301 uint16_t average_fclk_frequency; 1302 uint16_t average_vclk_frequency; 1303 uint16_t average_dclk_frequency; 1304 1305 /* Current clocks */ 1306 uint16_t current_gfxclk; 1307 uint16_t current_socclk; 1308 uint16_t current_uclk; 1309 uint16_t current_fclk; 1310 uint16_t current_vclk; 1311 uint16_t current_dclk; 1312 uint16_t current_coreclk[8]; // CPU core clocks 1313 uint16_t current_l3clk[2]; 1314 1315 /* Throttle status */ 1316 uint32_t throttle_status; 1317 1318 /* Fans */ 1319 uint16_t fan_pwm; 1320 1321 uint16_t padding[3]; 1322 }; 1323 1324 struct gpu_metrics_v2_2 { 1325 struct metrics_table_header common_header; 1326 1327 /* Temperature */ 1328 uint16_t temperature_gfx; // gfx temperature on APUs 1329 uint16_t temperature_soc; // soc temperature on APUs 1330 uint16_t temperature_core[8]; // CPU core temperature on APUs 1331 uint16_t temperature_l3[2]; 1332 1333 /* Utilization */ 1334 uint16_t average_gfx_activity; 1335 uint16_t average_mm_activity; // UVD or VCN 1336 1337 /* Driver attached timestamp (in ns) */ 1338 uint64_t system_clock_counter; 1339 1340 /* Power/Energy */ 1341 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1342 uint16_t average_cpu_power; 1343 uint16_t average_soc_power; 1344 uint16_t average_gfx_power; 1345 uint16_t average_core_power[8]; // CPU core power on APUs 1346 1347 /* Average clocks */ 1348 uint16_t average_gfxclk_frequency; 1349 uint16_t average_socclk_frequency; 1350 uint16_t average_uclk_frequency; 1351 uint16_t average_fclk_frequency; 1352 uint16_t average_vclk_frequency; 1353 uint16_t average_dclk_frequency; 1354 1355 /* Current clocks */ 1356 uint16_t current_gfxclk; 1357 uint16_t current_socclk; 1358 uint16_t current_uclk; 1359 uint16_t current_fclk; 1360 uint16_t current_vclk; 1361 uint16_t current_dclk; 1362 uint16_t current_coreclk[8]; // CPU core clocks 1363 uint16_t current_l3clk[2]; 1364 1365 /* Throttle status (ASIC dependent) */ 1366 uint32_t throttle_status; 1367 1368 /* Fans */ 1369 uint16_t fan_pwm; 1370 1371 uint16_t padding[3]; 1372 1373 /* Throttle status (ASIC independent) */ 1374 uint64_t indep_throttle_status; 1375 }; 1376 1377 struct gpu_metrics_v2_3 { 1378 struct metrics_table_header common_header; 1379 1380 /* Temperature */ 1381 uint16_t temperature_gfx; // gfx temperature on APUs 1382 uint16_t temperature_soc; // soc temperature on APUs 1383 uint16_t temperature_core[8]; // CPU core temperature on APUs 1384 uint16_t temperature_l3[2]; 1385 1386 /* Utilization */ 1387 uint16_t average_gfx_activity; 1388 uint16_t average_mm_activity; // UVD or VCN 1389 1390 /* Driver attached timestamp (in ns) */ 1391 uint64_t system_clock_counter; 1392 1393 /* Power/Energy */ 1394 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1395 uint16_t average_cpu_power; 1396 uint16_t average_soc_power; 1397 uint16_t average_gfx_power; 1398 uint16_t average_core_power[8]; // CPU core power on APUs 1399 1400 /* Average clocks */ 1401 uint16_t average_gfxclk_frequency; 1402 uint16_t average_socclk_frequency; 1403 uint16_t average_uclk_frequency; 1404 uint16_t average_fclk_frequency; 1405 uint16_t average_vclk_frequency; 1406 uint16_t average_dclk_frequency; 1407 1408 /* Current clocks */ 1409 uint16_t current_gfxclk; 1410 uint16_t current_socclk; 1411 uint16_t current_uclk; 1412 uint16_t current_fclk; 1413 uint16_t current_vclk; 1414 uint16_t current_dclk; 1415 uint16_t current_coreclk[8]; // CPU core clocks 1416 uint16_t current_l3clk[2]; 1417 1418 /* Throttle status (ASIC dependent) */ 1419 uint32_t throttle_status; 1420 1421 /* Fans */ 1422 uint16_t fan_pwm; 1423 1424 uint16_t padding[3]; 1425 1426 /* Throttle status (ASIC independent) */ 1427 uint64_t indep_throttle_status; 1428 1429 /* Average Temperature */ 1430 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1431 uint16_t average_temperature_soc; // average soc temperature on APUs 1432 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1433 uint16_t average_temperature_l3[2]; 1434 }; 1435 1436 struct gpu_metrics_v2_4 { 1437 struct metrics_table_header common_header; 1438 1439 /* Temperature (unit: centi-Celsius) */ 1440 uint16_t temperature_gfx; 1441 uint16_t temperature_soc; 1442 uint16_t temperature_core[8]; 1443 uint16_t temperature_l3[2]; 1444 1445 /* Utilization (unit: centi) */ 1446 uint16_t average_gfx_activity; 1447 uint16_t average_mm_activity; 1448 1449 /* Driver attached timestamp (in ns) */ 1450 uint64_t system_clock_counter; 1451 1452 /* Power/Energy (unit: mW) */ 1453 uint16_t average_socket_power; 1454 uint16_t average_cpu_power; 1455 uint16_t average_soc_power; 1456 uint16_t average_gfx_power; 1457 uint16_t average_core_power[8]; 1458 1459 /* Average clocks (unit: MHz) */ 1460 uint16_t average_gfxclk_frequency; 1461 uint16_t average_socclk_frequency; 1462 uint16_t average_uclk_frequency; 1463 uint16_t average_fclk_frequency; 1464 uint16_t average_vclk_frequency; 1465 uint16_t average_dclk_frequency; 1466 1467 /* Current clocks (unit: MHz) */ 1468 uint16_t current_gfxclk; 1469 uint16_t current_socclk; 1470 uint16_t current_uclk; 1471 uint16_t current_fclk; 1472 uint16_t current_vclk; 1473 uint16_t current_dclk; 1474 uint16_t current_coreclk[8]; 1475 uint16_t current_l3clk[2]; 1476 1477 /* Throttle status (ASIC dependent) */ 1478 uint32_t throttle_status; 1479 1480 /* Fans */ 1481 uint16_t fan_pwm; 1482 1483 uint16_t padding[3]; 1484 1485 /* Throttle status (ASIC independent) */ 1486 uint64_t indep_throttle_status; 1487 1488 /* Average Temperature (unit: centi-Celsius) */ 1489 uint16_t average_temperature_gfx; 1490 uint16_t average_temperature_soc; 1491 uint16_t average_temperature_core[8]; 1492 uint16_t average_temperature_l3[2]; 1493 1494 /* Power/Voltage (unit: mV) */ 1495 uint16_t average_cpu_voltage; 1496 uint16_t average_soc_voltage; 1497 uint16_t average_gfx_voltage; 1498 1499 /* Power/Current (unit: mA) */ 1500 uint16_t average_cpu_current; 1501 uint16_t average_soc_current; 1502 uint16_t average_gfx_current; 1503 }; 1504 1505 struct gpu_metrics_v3_0 { 1506 struct metrics_table_header common_header; 1507 1508 /* Temperature */ 1509 /* gfx temperature on APUs */ 1510 uint16_t temperature_gfx; 1511 /* soc temperature on APUs */ 1512 uint16_t temperature_soc; 1513 /* CPU core temperature on APUs */ 1514 uint16_t temperature_core[16]; 1515 /* skin temperature on APUs */ 1516 uint16_t temperature_skin; 1517 1518 /* Utilization */ 1519 /* time filtered GFX busy % [0-100] */ 1520 uint16_t average_gfx_activity; 1521 /* time filtered VCN busy % [0-100] */ 1522 uint16_t average_vcn_activity; 1523 /* time filtered IPU per-column busy % [0-100] */ 1524 uint16_t average_ipu_activity[8]; 1525 /* time filtered per-core C0 residency % [0-100]*/ 1526 uint16_t average_core_c0_activity[16]; 1527 /* time filtered DRAM read bandwidth [MB/sec] */ 1528 uint16_t average_dram_reads; 1529 /* time filtered DRAM write bandwidth [MB/sec] */ 1530 uint16_t average_dram_writes; 1531 /* time filtered IPU read bandwidth [MB/sec] */ 1532 uint16_t average_ipu_reads; 1533 /* time filtered IPU write bandwidth [MB/sec] */ 1534 uint16_t average_ipu_writes; 1535 1536 /* Driver attached timestamp (in ns) */ 1537 uint64_t system_clock_counter; 1538 1539 /* Power/Energy */ 1540 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1541 uint32_t average_socket_power; 1542 /* time filtered IPU power [mW] */ 1543 uint16_t average_ipu_power; 1544 /* time filtered APU power [mW] */ 1545 uint32_t average_apu_power; 1546 /* time filtered GFX power [mW] */ 1547 uint32_t average_gfx_power; 1548 /* time filtered dGPU power [mW] */ 1549 uint32_t average_dgpu_power; 1550 /* time filtered sum of core power across all cores in the socket [mW] */ 1551 uint32_t average_all_core_power; 1552 /* calculated core power [mW] */ 1553 uint16_t average_core_power[16]; 1554 /* time filtered total system power [mW] */ 1555 uint16_t average_sys_power; 1556 /* maximum IRM defined STAPM power limit [mW] */ 1557 uint16_t stapm_power_limit; 1558 /* time filtered STAPM power limit [mW] */ 1559 uint16_t current_stapm_power_limit; 1560 1561 /* time filtered clocks [MHz] */ 1562 uint16_t average_gfxclk_frequency; 1563 uint16_t average_socclk_frequency; 1564 uint16_t average_vpeclk_frequency; 1565 uint16_t average_ipuclk_frequency; 1566 uint16_t average_fclk_frequency; 1567 uint16_t average_vclk_frequency; 1568 uint16_t average_uclk_frequency; 1569 uint16_t average_mpipu_frequency; 1570 1571 /* Current clocks */ 1572 /* target core frequency [MHz] */ 1573 uint16_t current_coreclk[16]; 1574 /* CCLK frequency limit enforced on classic cores [MHz] */ 1575 uint16_t current_core_maxfreq; 1576 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1577 uint16_t current_gfx_maxfreq; 1578 1579 /* Throttle Residency (ASIC dependent) */ 1580 uint32_t throttle_residency_prochot; 1581 uint32_t throttle_residency_spl; 1582 uint32_t throttle_residency_fppt; 1583 uint32_t throttle_residency_sppt; 1584 uint32_t throttle_residency_thm_core; 1585 uint32_t throttle_residency_thm_gfx; 1586 uint32_t throttle_residency_thm_soc; 1587 1588 /* Metrics table alpha filter time constant [us] */ 1589 uint32_t time_filter_alphavalue; 1590 }; 1591 1592 struct amdgpu_pmmetrics_header { 1593 uint16_t structure_size; 1594 uint16_t pad; 1595 uint32_t mp1_ip_discovery_version; 1596 uint32_t pmfw_version; 1597 uint32_t pmmetrics_version; 1598 }; 1599 1600 struct amdgpu_pm_metrics { 1601 struct amdgpu_pmmetrics_header common_header; 1602 1603 uint8_t data[]; 1604 }; 1605 1606 enum amdgpu_vr_temp { 1607 AMDGPU_VDDCR_VDD0_TEMP, 1608 AMDGPU_VDDCR_VDD1_TEMP, 1609 AMDGPU_VDDCR_VDD2_TEMP, 1610 AMDGPU_VDDCR_VDD3_TEMP, 1611 AMDGPU_VDDCR_SOC_A_TEMP, 1612 AMDGPU_VDDCR_SOC_C_TEMP, 1613 AMDGPU_VDDCR_SOCIO_A_TEMP, 1614 AMDGPU_VDDCR_SOCIO_C_TEMP, 1615 AMDGPU_VDD_085_HBM_TEMP, 1616 AMDGPU_VDDCR_11_HBM_B_TEMP, 1617 AMDGPU_VDDCR_11_HBM_D_TEMP, 1618 AMDGPU_VDD_USR_TEMP, 1619 AMDGPU_VDDIO_11_E32_TEMP, 1620 AMDGPU_VR_MAX_TEMP_ENTRIES, 1621 }; 1622 1623 enum amdgpu_system_temp { 1624 AMDGPU_UBB_FPGA_TEMP, 1625 AMDGPU_UBB_FRONT_TEMP, 1626 AMDGPU_UBB_BACK_TEMP, 1627 AMDGPU_UBB_OAM7_TEMP, 1628 AMDGPU_UBB_IBC_TEMP, 1629 AMDGPU_UBB_UFPGA_TEMP, 1630 AMDGPU_UBB_OAM1_TEMP, 1631 AMDGPU_OAM_0_1_HSC_TEMP, 1632 AMDGPU_OAM_2_3_HSC_TEMP, 1633 AMDGPU_OAM_4_5_HSC_TEMP, 1634 AMDGPU_OAM_6_7_HSC_TEMP, 1635 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1636 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1637 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1638 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1639 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1640 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1641 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1642 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1643 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1644 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1645 AMDGPU_IBC_HSC_TEMP, 1646 AMDGPU_IBC_TEMP, 1647 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1648 }; 1649 1650 enum amdgpu_node_temp { 1651 AMDGPU_RETIMER_X_TEMP, 1652 AMDGPU_OAM_X_IBC_TEMP, 1653 AMDGPU_OAM_X_IBC_2_TEMP, 1654 AMDGPU_OAM_X_VDD18_VR_TEMP, 1655 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1656 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1657 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1658 }; 1659 1660 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1661 struct metrics_table_header common_header; 1662 uint16_t label_version; 1663 uint16_t node_id; 1664 uint64_t accumulation_counter; 1665 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1666 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1667 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1668 }; 1669 1670 struct amdgpu_baseboard_temp_metrics_v1_0 { 1671 struct metrics_table_header common_header; 1672 uint16_t label_version; 1673 uint16_t node_id; 1674 uint64_t accumulation_counter; 1675 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1676 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1677 }; 1678 1679 struct amdgpu_partition_metrics_v1_0 { 1680 struct metrics_table_header common_header; 1681 /* Current clocks (Mhz) */ 1682 uint16_t current_gfxclk[MAX_XCC]; 1683 uint16_t current_socclk[MAX_CLKS]; 1684 uint16_t current_vclk0[MAX_CLKS]; 1685 uint16_t current_dclk0[MAX_CLKS]; 1686 uint16_t current_uclk; 1687 uint16_t padding; 1688 1689 /* Utilization Instantaneous (%) */ 1690 uint32_t gfx_busy_inst[MAX_XCC]; 1691 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1692 uint16_t vcn_busy[NUM_VCN]; 1693 /* Utilization Accumulated (%) */ 1694 uint64_t gfx_busy_acc[MAX_XCC]; 1695 /* Total App Clock Counter Accumulated */ 1696 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1697 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1698 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1699 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1700 }; 1701 1702 #endif 1703