1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_event_type { 34 SMU_EVENT_RESET_COMPLETE = 0, 35 }; 36 37 struct amd_vce_state { 38 /* vce clocks */ 39 u32 evclk; 40 u32 ecclk; 41 /* gpu clocks */ 42 u32 sclk; 43 u32 mclk; 44 u8 clk_idx; 45 u8 pstate; 46 }; 47 48 49 enum amd_dpm_forced_level { 50 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 51 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 52 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 53 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 54 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 56 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 57 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 58 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 59 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 60 }; 61 62 enum amd_pm_state_type { 63 /* not used for dpm */ 64 POWER_STATE_TYPE_DEFAULT, 65 POWER_STATE_TYPE_POWERSAVE, 66 /* user selectable states */ 67 POWER_STATE_TYPE_BATTERY, 68 POWER_STATE_TYPE_BALANCED, 69 POWER_STATE_TYPE_PERFORMANCE, 70 /* internal states */ 71 POWER_STATE_TYPE_INTERNAL_UVD, 72 POWER_STATE_TYPE_INTERNAL_UVD_SD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD, 74 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 75 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 76 POWER_STATE_TYPE_INTERNAL_BOOT, 77 POWER_STATE_TYPE_INTERNAL_THERMAL, 78 POWER_STATE_TYPE_INTERNAL_ACPI, 79 POWER_STATE_TYPE_INTERNAL_ULV, 80 POWER_STATE_TYPE_INTERNAL_3DPERF, 81 }; 82 83 #define AMD_MAX_VCE_LEVELS 6 84 85 enum amd_vce_level { 86 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 87 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 88 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 89 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 90 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 91 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 92 }; 93 94 enum amd_fan_ctrl_mode { 95 AMD_FAN_CTRL_NONE = 0, 96 AMD_FAN_CTRL_MANUAL = 1, 97 AMD_FAN_CTRL_AUTO = 2, 98 }; 99 100 enum pp_clock_type { 101 PP_SCLK, 102 PP_MCLK, 103 PP_PCIE, 104 PP_SOCCLK, 105 PP_FCLK, 106 PP_DCEFCLK, 107 PP_VCLK, 108 PP_VCLK1, 109 PP_DCLK, 110 PP_DCLK1, 111 OD_SCLK, 112 OD_MCLK, 113 OD_VDDC_CURVE, 114 OD_RANGE, 115 OD_VDDGFX_OFFSET, 116 OD_CCLK, 117 OD_FAN_CURVE, 118 OD_ACOUSTIC_LIMIT, 119 OD_ACOUSTIC_TARGET, 120 OD_FAN_TARGET_TEMPERATURE, 121 OD_FAN_MINIMUM_PWM, 122 }; 123 124 enum amd_pp_sensors { 125 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 126 AMDGPU_PP_SENSOR_CPU_CLK, 127 AMDGPU_PP_SENSOR_VDDNB, 128 AMDGPU_PP_SENSOR_VDDGFX, 129 AMDGPU_PP_SENSOR_UVD_VCLK, 130 AMDGPU_PP_SENSOR_UVD_DCLK, 131 AMDGPU_PP_SENSOR_VCE_ECCLK, 132 AMDGPU_PP_SENSOR_GPU_LOAD, 133 AMDGPU_PP_SENSOR_MEM_LOAD, 134 AMDGPU_PP_SENSOR_GFX_MCLK, 135 AMDGPU_PP_SENSOR_GPU_TEMP, 136 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 137 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 138 AMDGPU_PP_SENSOR_MEM_TEMP, 139 AMDGPU_PP_SENSOR_VCE_POWER, 140 AMDGPU_PP_SENSOR_UVD_POWER, 141 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 142 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 143 AMDGPU_PP_SENSOR_SS_APU_SHARE, 144 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 145 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 146 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 147 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 148 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 149 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 150 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 151 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 152 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 153 AMDGPU_PP_SENSOR_VCN_LOAD, 154 }; 155 156 enum amd_pp_task { 157 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 158 AMD_PP_TASK_ENABLE_USER_STATE, 159 AMD_PP_TASK_READJUST_POWER_STATE, 160 AMD_PP_TASK_COMPLETE_INIT, 161 AMD_PP_TASK_MAX 162 }; 163 164 enum PP_SMC_POWER_PROFILE { 165 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 166 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 167 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 168 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 169 PP_SMC_POWER_PROFILE_VR = 0x4, 170 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 171 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 172 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 173 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 174 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 175 PP_SMC_POWER_PROFILE_COUNT, 176 }; 177 178 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 179 180 181 182 enum { 183 PP_GROUP_UNKNOWN = 0, 184 PP_GROUP_GFX = 1, 185 PP_GROUP_SYS, 186 PP_GROUP_MAX 187 }; 188 189 enum PP_OD_DPM_TABLE_COMMAND { 190 PP_OD_EDIT_SCLK_VDDC_TABLE, 191 PP_OD_EDIT_MCLK_VDDC_TABLE, 192 PP_OD_EDIT_CCLK_VDDC_TABLE, 193 PP_OD_EDIT_VDDC_CURVE, 194 PP_OD_RESTORE_DEFAULT_TABLE, 195 PP_OD_COMMIT_DPM_TABLE, 196 PP_OD_EDIT_VDDGFX_OFFSET, 197 PP_OD_EDIT_FAN_CURVE, 198 PP_OD_EDIT_ACOUSTIC_LIMIT, 199 PP_OD_EDIT_ACOUSTIC_TARGET, 200 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 201 PP_OD_EDIT_FAN_MINIMUM_PWM, 202 }; 203 204 struct pp_states_info { 205 uint32_t nums; 206 uint32_t states[16]; 207 }; 208 209 enum PP_HWMON_TEMP { 210 PP_TEMP_EDGE = 0, 211 PP_TEMP_JUNCTION, 212 PP_TEMP_MEM, 213 PP_TEMP_MAX 214 }; 215 216 enum pp_mp1_state { 217 PP_MP1_STATE_NONE, 218 PP_MP1_STATE_SHUTDOWN, 219 PP_MP1_STATE_UNLOAD, 220 PP_MP1_STATE_RESET, 221 }; 222 223 enum pp_df_cstate { 224 DF_CSTATE_DISALLOW = 0, 225 DF_CSTATE_ALLOW, 226 }; 227 228 /** 229 * DOC: amdgpu_pp_power 230 * 231 * APU power is managed to system-level requirements through the PPT 232 * (package power tracking) feature. PPT is intended to limit power to the 233 * requirements of the power source and could be dynamically updated to 234 * maximize APU performance within the system power budget. 235 * 236 * Two types of power measurement can be requested, where supported, with 237 * :c:type:`enum pp_power_type <pp_power_type>`. 238 */ 239 240 /** 241 * enum pp_power_limit_level - Used to query the power limits 242 * 243 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 244 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 245 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 246 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 247 */ 248 enum pp_power_limit_level { 249 PP_PWR_LIMIT_MIN = -1, 250 PP_PWR_LIMIT_CURRENT, 251 PP_PWR_LIMIT_DEFAULT, 252 PP_PWR_LIMIT_MAX, 253 }; 254 255 /** 256 * enum pp_power_type - Used to specify the type of the requested power 257 * 258 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 259 * moving average of APU power (default ~5000 ms). 260 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 261 * where supported. 262 */ 263 enum pp_power_type { 264 PP_PWR_TYPE_SUSTAINED, 265 PP_PWR_TYPE_FAST, 266 }; 267 268 enum pp_xgmi_plpd_mode { 269 XGMI_PLPD_NONE = -1, 270 XGMI_PLPD_DISALLOW, 271 XGMI_PLPD_DEFAULT, 272 XGMI_PLPD_OPTIMIZED, 273 XGMI_PLPD_COUNT, 274 }; 275 276 #define PP_GROUP_MASK 0xF0000000 277 #define PP_GROUP_SHIFT 28 278 279 #define PP_BLOCK_MASK 0x0FFFFF00 280 #define PP_BLOCK_SHIFT 8 281 282 #define PP_BLOCK_GFX_CG 0x01 283 #define PP_BLOCK_GFX_MG 0x02 284 #define PP_BLOCK_GFX_3D 0x04 285 #define PP_BLOCK_GFX_RLC 0x08 286 #define PP_BLOCK_GFX_CP 0x10 287 #define PP_BLOCK_SYS_BIF 0x01 288 #define PP_BLOCK_SYS_MC 0x02 289 #define PP_BLOCK_SYS_ROM 0x04 290 #define PP_BLOCK_SYS_DRM 0x08 291 #define PP_BLOCK_SYS_HDP 0x10 292 #define PP_BLOCK_SYS_SDMA 0x20 293 294 #define PP_STATE_MASK 0x0000000F 295 #define PP_STATE_SHIFT 0 296 #define PP_STATE_SUPPORT_MASK 0x000000F0 297 #define PP_STATE_SUPPORT_SHIFT 0 298 299 #define PP_STATE_CG 0x01 300 #define PP_STATE_LS 0x02 301 #define PP_STATE_DS 0x04 302 #define PP_STATE_SD 0x08 303 #define PP_STATE_SUPPORT_CG 0x10 304 #define PP_STATE_SUPPORT_LS 0x20 305 #define PP_STATE_SUPPORT_DS 0x40 306 #define PP_STATE_SUPPORT_SD 0x80 307 308 #define PP_CG_MSG_ID(group, block, support, state) \ 309 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 310 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 311 312 #define XGMI_MODE_PSTATE_D3 0 313 #define XGMI_MODE_PSTATE_D0 1 314 315 #define NUM_HBM_INSTANCES 4 316 #define NUM_XGMI_LINKS 8 317 #define MAX_GFX_CLKS 8 318 #define MAX_CLKS 4 319 #define NUM_VCN 4 320 #define NUM_JPEG_ENG 32 321 322 struct seq_file; 323 enum amd_pp_clock_type; 324 struct amd_pp_simple_clock_info; 325 struct amd_pp_display_configuration; 326 struct amd_pp_clock_info; 327 struct pp_display_clock_request; 328 struct pp_clock_levels_with_voltage; 329 struct pp_clock_levels_with_latency; 330 struct amd_pp_clocks; 331 struct pp_smu_wm_range_sets; 332 struct pp_smu_nv_clock_table; 333 struct dpm_clocks; 334 335 struct amd_pm_funcs { 336 /* export for dpm on ci and si */ 337 int (*pre_set_power_state)(void *handle); 338 int (*set_power_state)(void *handle); 339 void (*post_set_power_state)(void *handle); 340 void (*display_configuration_changed)(void *handle); 341 void (*print_power_state)(void *handle, void *ps); 342 bool (*vblank_too_short)(void *handle); 343 void (*enable_bapm)(void *handle, bool enable); 344 int (*check_state_equal)(void *handle, 345 void *cps, 346 void *rps, 347 bool *equal); 348 /* export for sysfs */ 349 int (*set_fan_control_mode)(void *handle, u32 mode); 350 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 351 int (*set_fan_speed_pwm)(void *handle, u32 speed); 352 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 353 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 354 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 355 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 356 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 357 int (*get_sclk_od)(void *handle); 358 int (*set_sclk_od)(void *handle, uint32_t value); 359 int (*get_mclk_od)(void *handle); 360 int (*set_mclk_od)(void *handle, uint32_t value); 361 int (*read_sensor)(void *handle, int idx, void *value, int *size); 362 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 363 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 364 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 365 enum amd_pm_state_type (*get_current_power_state)(void *handle); 366 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 367 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 368 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 369 int (*get_pp_table)(void *handle, char **table); 370 int (*set_pp_table)(void *handle, const char *buf, size_t size); 371 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 372 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 373 /* export to amdgpu */ 374 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 375 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 376 enum amd_pm_state_type *user_state); 377 int (*load_firmware)(void *handle); 378 int (*wait_for_fw_loading_complete)(void *handle); 379 int (*set_powergating_by_smu)(void *handle, 380 uint32_t block_type, bool gate); 381 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 382 int (*set_power_limit)(void *handle, uint32_t n); 383 int (*get_power_limit)(void *handle, uint32_t *limit, 384 enum pp_power_limit_level pp_limit_level, 385 enum pp_power_type power_type); 386 int (*get_power_profile_mode)(void *handle, char *buf); 387 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 388 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 389 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 390 long *input, uint32_t size); 391 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 392 int (*smu_i2c_bus_access)(void *handle, bool acquire); 393 int (*gfx_state_change_set)(void *handle, uint32_t state); 394 /* export to DC */ 395 u32 (*get_sclk)(void *handle, bool low); 396 u32 (*get_mclk)(void *handle, bool low); 397 int (*display_configuration_change)(void *handle, 398 const struct amd_pp_display_configuration *input); 399 int (*get_display_power_level)(void *handle, 400 struct amd_pp_simple_clock_info *output); 401 int (*get_current_clocks)(void *handle, 402 struct amd_pp_clock_info *clocks); 403 int (*get_clock_by_type)(void *handle, 404 enum amd_pp_clock_type type, 405 struct amd_pp_clocks *clocks); 406 int (*get_clock_by_type_with_latency)(void *handle, 407 enum amd_pp_clock_type type, 408 struct pp_clock_levels_with_latency *clocks); 409 int (*get_clock_by_type_with_voltage)(void *handle, 410 enum amd_pp_clock_type type, 411 struct pp_clock_levels_with_voltage *clocks); 412 int (*set_watermarks_for_clocks_ranges)(void *handle, 413 void *clock_ranges); 414 int (*display_clock_voltage_request)(void *handle, 415 struct pp_display_clock_request *clock); 416 int (*get_display_mode_validation_clocks)(void *handle, 417 struct amd_pp_simple_clock_info *clocks); 418 int (*notify_smu_enable_pwe)(void *handle); 419 int (*enable_mgpu_fan_boost)(void *handle); 420 int (*set_active_display_count)(void *handle, uint32_t count); 421 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 422 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 423 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 424 int (*get_asic_baco_capability)(void *handle); 425 int (*get_asic_baco_state)(void *handle, int *state); 426 int (*set_asic_baco_state)(void *handle, int state); 427 int (*get_ppfeature_status)(void *handle, char *buf); 428 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 429 int (*asic_reset_mode_2)(void *handle); 430 int (*asic_reset_enable_gfx_features)(void *handle); 431 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 432 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 433 ssize_t (*get_gpu_metrics)(void *handle, void **table); 434 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 435 int (*set_watermarks_for_clock_ranges)(void *handle, 436 struct pp_smu_wm_range_sets *ranges); 437 int (*display_disable_memory_clock_switch)(void *handle, 438 bool disable_memory_clock_switch); 439 int (*get_max_sustainable_clocks_by_dc)(void *handle, 440 struct pp_smu_nv_clock_table *max_clocks); 441 int (*get_uclk_dpm_states)(void *handle, 442 unsigned int *clock_values_in_khz, 443 unsigned int *num_states); 444 int (*get_dpm_clock_table)(void *handle, 445 struct dpm_clocks *clock_table); 446 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 447 void (*pm_compute_clocks)(void *handle); 448 int (*notify_rlc_state)(void *handle, bool en); 449 }; 450 451 struct metrics_table_header { 452 uint16_t structure_size; 453 uint8_t format_revision; 454 uint8_t content_revision; 455 }; 456 457 /* 458 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 459 * Use gpu_metrics_v1_1 or later instead. 460 */ 461 struct gpu_metrics_v1_0 { 462 struct metrics_table_header common_header; 463 464 /* Driver attached timestamp (in ns) */ 465 uint64_t system_clock_counter; 466 467 /* Temperature */ 468 uint16_t temperature_edge; 469 uint16_t temperature_hotspot; 470 uint16_t temperature_mem; 471 uint16_t temperature_vrgfx; 472 uint16_t temperature_vrsoc; 473 uint16_t temperature_vrmem; 474 475 /* Utilization */ 476 uint16_t average_gfx_activity; 477 uint16_t average_umc_activity; // memory controller 478 uint16_t average_mm_activity; // UVD or VCN 479 480 /* Power/Energy */ 481 uint16_t average_socket_power; 482 uint32_t energy_accumulator; 483 484 /* Average clocks */ 485 uint16_t average_gfxclk_frequency; 486 uint16_t average_socclk_frequency; 487 uint16_t average_uclk_frequency; 488 uint16_t average_vclk0_frequency; 489 uint16_t average_dclk0_frequency; 490 uint16_t average_vclk1_frequency; 491 uint16_t average_dclk1_frequency; 492 493 /* Current clocks */ 494 uint16_t current_gfxclk; 495 uint16_t current_socclk; 496 uint16_t current_uclk; 497 uint16_t current_vclk0; 498 uint16_t current_dclk0; 499 uint16_t current_vclk1; 500 uint16_t current_dclk1; 501 502 /* Throttle status */ 503 uint32_t throttle_status; 504 505 /* Fans */ 506 uint16_t current_fan_speed; 507 508 /* Link width/speed */ 509 uint8_t pcie_link_width; 510 uint8_t pcie_link_speed; // in 0.1 GT/s 511 }; 512 513 struct gpu_metrics_v1_1 { 514 struct metrics_table_header common_header; 515 516 /* Temperature */ 517 uint16_t temperature_edge; 518 uint16_t temperature_hotspot; 519 uint16_t temperature_mem; 520 uint16_t temperature_vrgfx; 521 uint16_t temperature_vrsoc; 522 uint16_t temperature_vrmem; 523 524 /* Utilization */ 525 uint16_t average_gfx_activity; 526 uint16_t average_umc_activity; // memory controller 527 uint16_t average_mm_activity; // UVD or VCN 528 529 /* Power/Energy */ 530 uint16_t average_socket_power; 531 uint64_t energy_accumulator; 532 533 /* Driver attached timestamp (in ns) */ 534 uint64_t system_clock_counter; 535 536 /* Average clocks */ 537 uint16_t average_gfxclk_frequency; 538 uint16_t average_socclk_frequency; 539 uint16_t average_uclk_frequency; 540 uint16_t average_vclk0_frequency; 541 uint16_t average_dclk0_frequency; 542 uint16_t average_vclk1_frequency; 543 uint16_t average_dclk1_frequency; 544 545 /* Current clocks */ 546 uint16_t current_gfxclk; 547 uint16_t current_socclk; 548 uint16_t current_uclk; 549 uint16_t current_vclk0; 550 uint16_t current_dclk0; 551 uint16_t current_vclk1; 552 uint16_t current_dclk1; 553 554 /* Throttle status */ 555 uint32_t throttle_status; 556 557 /* Fans */ 558 uint16_t current_fan_speed; 559 560 /* Link width/speed */ 561 uint16_t pcie_link_width; 562 uint16_t pcie_link_speed; // in 0.1 GT/s 563 564 uint16_t padding; 565 566 uint32_t gfx_activity_acc; 567 uint32_t mem_activity_acc; 568 569 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 570 }; 571 572 struct gpu_metrics_v1_2 { 573 struct metrics_table_header common_header; 574 575 /* Temperature */ 576 uint16_t temperature_edge; 577 uint16_t temperature_hotspot; 578 uint16_t temperature_mem; 579 uint16_t temperature_vrgfx; 580 uint16_t temperature_vrsoc; 581 uint16_t temperature_vrmem; 582 583 /* Utilization */ 584 uint16_t average_gfx_activity; 585 uint16_t average_umc_activity; // memory controller 586 uint16_t average_mm_activity; // UVD or VCN 587 588 /* Power/Energy */ 589 uint16_t average_socket_power; 590 uint64_t energy_accumulator; 591 592 /* Driver attached timestamp (in ns) */ 593 uint64_t system_clock_counter; 594 595 /* Average clocks */ 596 uint16_t average_gfxclk_frequency; 597 uint16_t average_socclk_frequency; 598 uint16_t average_uclk_frequency; 599 uint16_t average_vclk0_frequency; 600 uint16_t average_dclk0_frequency; 601 uint16_t average_vclk1_frequency; 602 uint16_t average_dclk1_frequency; 603 604 /* Current clocks */ 605 uint16_t current_gfxclk; 606 uint16_t current_socclk; 607 uint16_t current_uclk; 608 uint16_t current_vclk0; 609 uint16_t current_dclk0; 610 uint16_t current_vclk1; 611 uint16_t current_dclk1; 612 613 /* Throttle status (ASIC dependent) */ 614 uint32_t throttle_status; 615 616 /* Fans */ 617 uint16_t current_fan_speed; 618 619 /* Link width/speed */ 620 uint16_t pcie_link_width; 621 uint16_t pcie_link_speed; // in 0.1 GT/s 622 623 uint16_t padding; 624 625 uint32_t gfx_activity_acc; 626 uint32_t mem_activity_acc; 627 628 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 629 630 /* PMFW attached timestamp (10ns resolution) */ 631 uint64_t firmware_timestamp; 632 }; 633 634 struct gpu_metrics_v1_3 { 635 struct metrics_table_header common_header; 636 637 /* Temperature */ 638 uint16_t temperature_edge; 639 uint16_t temperature_hotspot; 640 uint16_t temperature_mem; 641 uint16_t temperature_vrgfx; 642 uint16_t temperature_vrsoc; 643 uint16_t temperature_vrmem; 644 645 /* Utilization */ 646 uint16_t average_gfx_activity; 647 uint16_t average_umc_activity; // memory controller 648 uint16_t average_mm_activity; // UVD or VCN 649 650 /* Power/Energy */ 651 uint16_t average_socket_power; 652 uint64_t energy_accumulator; 653 654 /* Driver attached timestamp (in ns) */ 655 uint64_t system_clock_counter; 656 657 /* Average clocks */ 658 uint16_t average_gfxclk_frequency; 659 uint16_t average_socclk_frequency; 660 uint16_t average_uclk_frequency; 661 uint16_t average_vclk0_frequency; 662 uint16_t average_dclk0_frequency; 663 uint16_t average_vclk1_frequency; 664 uint16_t average_dclk1_frequency; 665 666 /* Current clocks */ 667 uint16_t current_gfxclk; 668 uint16_t current_socclk; 669 uint16_t current_uclk; 670 uint16_t current_vclk0; 671 uint16_t current_dclk0; 672 uint16_t current_vclk1; 673 uint16_t current_dclk1; 674 675 /* Throttle status */ 676 uint32_t throttle_status; 677 678 /* Fans */ 679 uint16_t current_fan_speed; 680 681 /* Link width/speed */ 682 uint16_t pcie_link_width; 683 uint16_t pcie_link_speed; // in 0.1 GT/s 684 685 uint16_t padding; 686 687 uint32_t gfx_activity_acc; 688 uint32_t mem_activity_acc; 689 690 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 691 692 /* PMFW attached timestamp (10ns resolution) */ 693 uint64_t firmware_timestamp; 694 695 /* Voltage (mV) */ 696 uint16_t voltage_soc; 697 uint16_t voltage_gfx; 698 uint16_t voltage_mem; 699 700 uint16_t padding1; 701 702 /* Throttle status (ASIC independent) */ 703 uint64_t indep_throttle_status; 704 }; 705 706 struct gpu_metrics_v1_4 { 707 struct metrics_table_header common_header; 708 709 /* Temperature (Celsius) */ 710 uint16_t temperature_hotspot; 711 uint16_t temperature_mem; 712 uint16_t temperature_vrsoc; 713 714 /* Power (Watts) */ 715 uint16_t curr_socket_power; 716 717 /* Utilization (%) */ 718 uint16_t average_gfx_activity; 719 uint16_t average_umc_activity; // memory controller 720 uint16_t vcn_activity[NUM_VCN]; 721 722 /* Energy (15.259uJ (2^-16) units) */ 723 uint64_t energy_accumulator; 724 725 /* Driver attached timestamp (in ns) */ 726 uint64_t system_clock_counter; 727 728 /* Throttle status */ 729 uint32_t throttle_status; 730 731 /* Clock Lock Status. Each bit corresponds to clock instance */ 732 uint32_t gfxclk_lock_status; 733 734 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 735 uint16_t pcie_link_width; 736 uint16_t pcie_link_speed; 737 738 /* XGMI bus width and bitrate (in Gbps) */ 739 uint16_t xgmi_link_width; 740 uint16_t xgmi_link_speed; 741 742 /* Utilization Accumulated (%) */ 743 uint32_t gfx_activity_acc; 744 uint32_t mem_activity_acc; 745 746 /*PCIE accumulated bandwidth (GB/sec) */ 747 uint64_t pcie_bandwidth_acc; 748 749 /*PCIE instantaneous bandwidth (GB/sec) */ 750 uint64_t pcie_bandwidth_inst; 751 752 /* PCIE L0 to recovery state transition accumulated count */ 753 uint64_t pcie_l0_to_recov_count_acc; 754 755 /* PCIE replay accumulated count */ 756 uint64_t pcie_replay_count_acc; 757 758 /* PCIE replay rollover accumulated count */ 759 uint64_t pcie_replay_rover_count_acc; 760 761 /* XGMI accumulated data transfer size(KiloBytes) */ 762 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 763 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 764 765 /* PMFW attached timestamp (10ns resolution) */ 766 uint64_t firmware_timestamp; 767 768 /* Current clocks (Mhz) */ 769 uint16_t current_gfxclk[MAX_GFX_CLKS]; 770 uint16_t current_socclk[MAX_CLKS]; 771 uint16_t current_vclk0[MAX_CLKS]; 772 uint16_t current_dclk0[MAX_CLKS]; 773 uint16_t current_uclk; 774 775 uint16_t padding; 776 }; 777 778 struct gpu_metrics_v1_5 { 779 struct metrics_table_header common_header; 780 781 /* Temperature (Celsius) */ 782 uint16_t temperature_hotspot; 783 uint16_t temperature_mem; 784 uint16_t temperature_vrsoc; 785 786 /* Power (Watts) */ 787 uint16_t curr_socket_power; 788 789 /* Utilization (%) */ 790 uint16_t average_gfx_activity; 791 uint16_t average_umc_activity; // memory controller 792 uint16_t vcn_activity[NUM_VCN]; 793 uint16_t jpeg_activity[NUM_JPEG_ENG]; 794 795 /* Energy (15.259uJ (2^-16) units) */ 796 uint64_t energy_accumulator; 797 798 /* Driver attached timestamp (in ns) */ 799 uint64_t system_clock_counter; 800 801 /* Throttle status */ 802 uint32_t throttle_status; 803 804 /* Clock Lock Status. Each bit corresponds to clock instance */ 805 uint32_t gfxclk_lock_status; 806 807 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 808 uint16_t pcie_link_width; 809 uint16_t pcie_link_speed; 810 811 /* XGMI bus width and bitrate (in Gbps) */ 812 uint16_t xgmi_link_width; 813 uint16_t xgmi_link_speed; 814 815 /* Utilization Accumulated (%) */ 816 uint32_t gfx_activity_acc; 817 uint32_t mem_activity_acc; 818 819 /*PCIE accumulated bandwidth (GB/sec) */ 820 uint64_t pcie_bandwidth_acc; 821 822 /*PCIE instantaneous bandwidth (GB/sec) */ 823 uint64_t pcie_bandwidth_inst; 824 825 /* PCIE L0 to recovery state transition accumulated count */ 826 uint64_t pcie_l0_to_recov_count_acc; 827 828 /* PCIE replay accumulated count */ 829 uint64_t pcie_replay_count_acc; 830 831 /* PCIE replay rollover accumulated count */ 832 uint64_t pcie_replay_rover_count_acc; 833 834 /* PCIE NAK sent accumulated count */ 835 uint32_t pcie_nak_sent_count_acc; 836 837 /* PCIE NAK received accumulated count */ 838 uint32_t pcie_nak_rcvd_count_acc; 839 840 /* XGMI accumulated data transfer size(KiloBytes) */ 841 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 842 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 843 844 /* PMFW attached timestamp (10ns resolution) */ 845 uint64_t firmware_timestamp; 846 847 /* Current clocks (Mhz) */ 848 uint16_t current_gfxclk[MAX_GFX_CLKS]; 849 uint16_t current_socclk[MAX_CLKS]; 850 uint16_t current_vclk0[MAX_CLKS]; 851 uint16_t current_dclk0[MAX_CLKS]; 852 uint16_t current_uclk; 853 854 uint16_t padding; 855 }; 856 857 /* 858 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 859 * Use gpu_metrics_v2_1 or later instead. 860 */ 861 struct gpu_metrics_v2_0 { 862 struct metrics_table_header common_header; 863 864 /* Driver attached timestamp (in ns) */ 865 uint64_t system_clock_counter; 866 867 /* Temperature */ 868 uint16_t temperature_gfx; // gfx temperature on APUs 869 uint16_t temperature_soc; // soc temperature on APUs 870 uint16_t temperature_core[8]; // CPU core temperature on APUs 871 uint16_t temperature_l3[2]; 872 873 /* Utilization */ 874 uint16_t average_gfx_activity; 875 uint16_t average_mm_activity; // UVD or VCN 876 877 /* Power/Energy */ 878 uint16_t average_socket_power; // dGPU + APU power on A + A platform 879 uint16_t average_cpu_power; 880 uint16_t average_soc_power; 881 uint16_t average_gfx_power; 882 uint16_t average_core_power[8]; // CPU core power on APUs 883 884 /* Average clocks */ 885 uint16_t average_gfxclk_frequency; 886 uint16_t average_socclk_frequency; 887 uint16_t average_uclk_frequency; 888 uint16_t average_fclk_frequency; 889 uint16_t average_vclk_frequency; 890 uint16_t average_dclk_frequency; 891 892 /* Current clocks */ 893 uint16_t current_gfxclk; 894 uint16_t current_socclk; 895 uint16_t current_uclk; 896 uint16_t current_fclk; 897 uint16_t current_vclk; 898 uint16_t current_dclk; 899 uint16_t current_coreclk[8]; // CPU core clocks 900 uint16_t current_l3clk[2]; 901 902 /* Throttle status */ 903 uint32_t throttle_status; 904 905 /* Fans */ 906 uint16_t fan_pwm; 907 908 uint16_t padding; 909 }; 910 911 struct gpu_metrics_v2_1 { 912 struct metrics_table_header common_header; 913 914 /* Temperature */ 915 uint16_t temperature_gfx; // gfx temperature on APUs 916 uint16_t temperature_soc; // soc temperature on APUs 917 uint16_t temperature_core[8]; // CPU core temperature on APUs 918 uint16_t temperature_l3[2]; 919 920 /* Utilization */ 921 uint16_t average_gfx_activity; 922 uint16_t average_mm_activity; // UVD or VCN 923 924 /* Driver attached timestamp (in ns) */ 925 uint64_t system_clock_counter; 926 927 /* Power/Energy */ 928 uint16_t average_socket_power; // dGPU + APU power on A + A platform 929 uint16_t average_cpu_power; 930 uint16_t average_soc_power; 931 uint16_t average_gfx_power; 932 uint16_t average_core_power[8]; // CPU core power on APUs 933 934 /* Average clocks */ 935 uint16_t average_gfxclk_frequency; 936 uint16_t average_socclk_frequency; 937 uint16_t average_uclk_frequency; 938 uint16_t average_fclk_frequency; 939 uint16_t average_vclk_frequency; 940 uint16_t average_dclk_frequency; 941 942 /* Current clocks */ 943 uint16_t current_gfxclk; 944 uint16_t current_socclk; 945 uint16_t current_uclk; 946 uint16_t current_fclk; 947 uint16_t current_vclk; 948 uint16_t current_dclk; 949 uint16_t current_coreclk[8]; // CPU core clocks 950 uint16_t current_l3clk[2]; 951 952 /* Throttle status */ 953 uint32_t throttle_status; 954 955 /* Fans */ 956 uint16_t fan_pwm; 957 958 uint16_t padding[3]; 959 }; 960 961 struct gpu_metrics_v2_2 { 962 struct metrics_table_header common_header; 963 964 /* Temperature */ 965 uint16_t temperature_gfx; // gfx temperature on APUs 966 uint16_t temperature_soc; // soc temperature on APUs 967 uint16_t temperature_core[8]; // CPU core temperature on APUs 968 uint16_t temperature_l3[2]; 969 970 /* Utilization */ 971 uint16_t average_gfx_activity; 972 uint16_t average_mm_activity; // UVD or VCN 973 974 /* Driver attached timestamp (in ns) */ 975 uint64_t system_clock_counter; 976 977 /* Power/Energy */ 978 uint16_t average_socket_power; // dGPU + APU power on A + A platform 979 uint16_t average_cpu_power; 980 uint16_t average_soc_power; 981 uint16_t average_gfx_power; 982 uint16_t average_core_power[8]; // CPU core power on APUs 983 984 /* Average clocks */ 985 uint16_t average_gfxclk_frequency; 986 uint16_t average_socclk_frequency; 987 uint16_t average_uclk_frequency; 988 uint16_t average_fclk_frequency; 989 uint16_t average_vclk_frequency; 990 uint16_t average_dclk_frequency; 991 992 /* Current clocks */ 993 uint16_t current_gfxclk; 994 uint16_t current_socclk; 995 uint16_t current_uclk; 996 uint16_t current_fclk; 997 uint16_t current_vclk; 998 uint16_t current_dclk; 999 uint16_t current_coreclk[8]; // CPU core clocks 1000 uint16_t current_l3clk[2]; 1001 1002 /* Throttle status (ASIC dependent) */ 1003 uint32_t throttle_status; 1004 1005 /* Fans */ 1006 uint16_t fan_pwm; 1007 1008 uint16_t padding[3]; 1009 1010 /* Throttle status (ASIC independent) */ 1011 uint64_t indep_throttle_status; 1012 }; 1013 1014 struct gpu_metrics_v2_3 { 1015 struct metrics_table_header common_header; 1016 1017 /* Temperature */ 1018 uint16_t temperature_gfx; // gfx temperature on APUs 1019 uint16_t temperature_soc; // soc temperature on APUs 1020 uint16_t temperature_core[8]; // CPU core temperature on APUs 1021 uint16_t temperature_l3[2]; 1022 1023 /* Utilization */ 1024 uint16_t average_gfx_activity; 1025 uint16_t average_mm_activity; // UVD or VCN 1026 1027 /* Driver attached timestamp (in ns) */ 1028 uint64_t system_clock_counter; 1029 1030 /* Power/Energy */ 1031 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1032 uint16_t average_cpu_power; 1033 uint16_t average_soc_power; 1034 uint16_t average_gfx_power; 1035 uint16_t average_core_power[8]; // CPU core power on APUs 1036 1037 /* Average clocks */ 1038 uint16_t average_gfxclk_frequency; 1039 uint16_t average_socclk_frequency; 1040 uint16_t average_uclk_frequency; 1041 uint16_t average_fclk_frequency; 1042 uint16_t average_vclk_frequency; 1043 uint16_t average_dclk_frequency; 1044 1045 /* Current clocks */ 1046 uint16_t current_gfxclk; 1047 uint16_t current_socclk; 1048 uint16_t current_uclk; 1049 uint16_t current_fclk; 1050 uint16_t current_vclk; 1051 uint16_t current_dclk; 1052 uint16_t current_coreclk[8]; // CPU core clocks 1053 uint16_t current_l3clk[2]; 1054 1055 /* Throttle status (ASIC dependent) */ 1056 uint32_t throttle_status; 1057 1058 /* Fans */ 1059 uint16_t fan_pwm; 1060 1061 uint16_t padding[3]; 1062 1063 /* Throttle status (ASIC independent) */ 1064 uint64_t indep_throttle_status; 1065 1066 /* Average Temperature */ 1067 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1068 uint16_t average_temperature_soc; // average soc temperature on APUs 1069 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1070 uint16_t average_temperature_l3[2]; 1071 }; 1072 1073 struct gpu_metrics_v2_4 { 1074 struct metrics_table_header common_header; 1075 1076 /* Temperature (unit: centi-Celsius) */ 1077 uint16_t temperature_gfx; 1078 uint16_t temperature_soc; 1079 uint16_t temperature_core[8]; 1080 uint16_t temperature_l3[2]; 1081 1082 /* Utilization (unit: centi) */ 1083 uint16_t average_gfx_activity; 1084 uint16_t average_mm_activity; 1085 1086 /* Driver attached timestamp (in ns) */ 1087 uint64_t system_clock_counter; 1088 1089 /* Power/Energy (unit: mW) */ 1090 uint16_t average_socket_power; 1091 uint16_t average_cpu_power; 1092 uint16_t average_soc_power; 1093 uint16_t average_gfx_power; 1094 uint16_t average_core_power[8]; 1095 1096 /* Average clocks (unit: MHz) */ 1097 uint16_t average_gfxclk_frequency; 1098 uint16_t average_socclk_frequency; 1099 uint16_t average_uclk_frequency; 1100 uint16_t average_fclk_frequency; 1101 uint16_t average_vclk_frequency; 1102 uint16_t average_dclk_frequency; 1103 1104 /* Current clocks (unit: MHz) */ 1105 uint16_t current_gfxclk; 1106 uint16_t current_socclk; 1107 uint16_t current_uclk; 1108 uint16_t current_fclk; 1109 uint16_t current_vclk; 1110 uint16_t current_dclk; 1111 uint16_t current_coreclk[8]; 1112 uint16_t current_l3clk[2]; 1113 1114 /* Throttle status (ASIC dependent) */ 1115 uint32_t throttle_status; 1116 1117 /* Fans */ 1118 uint16_t fan_pwm; 1119 1120 uint16_t padding[3]; 1121 1122 /* Throttle status (ASIC independent) */ 1123 uint64_t indep_throttle_status; 1124 1125 /* Average Temperature (unit: centi-Celsius) */ 1126 uint16_t average_temperature_gfx; 1127 uint16_t average_temperature_soc; 1128 uint16_t average_temperature_core[8]; 1129 uint16_t average_temperature_l3[2]; 1130 1131 /* Power/Voltage (unit: mV) */ 1132 uint16_t average_cpu_voltage; 1133 uint16_t average_soc_voltage; 1134 uint16_t average_gfx_voltage; 1135 1136 /* Power/Current (unit: mA) */ 1137 uint16_t average_cpu_current; 1138 uint16_t average_soc_current; 1139 uint16_t average_gfx_current; 1140 }; 1141 1142 struct gpu_metrics_v3_0 { 1143 struct metrics_table_header common_header; 1144 1145 /* Temperature */ 1146 /* gfx temperature on APUs */ 1147 uint16_t temperature_gfx; 1148 /* soc temperature on APUs */ 1149 uint16_t temperature_soc; 1150 /* CPU core temperature on APUs */ 1151 uint16_t temperature_core[16]; 1152 /* skin temperature on APUs */ 1153 uint16_t temperature_skin; 1154 1155 /* Utilization */ 1156 /* time filtered GFX busy % [0-100] */ 1157 uint16_t average_gfx_activity; 1158 /* time filtered VCN busy % [0-100] */ 1159 uint16_t average_vcn_activity; 1160 /* time filtered IPU per-column busy % [0-100] */ 1161 uint16_t average_ipu_activity[8]; 1162 /* time filtered per-core C0 residency % [0-100]*/ 1163 uint16_t average_core_c0_activity[16]; 1164 /* time filtered DRAM read bandwidth [MB/sec] */ 1165 uint16_t average_dram_reads; 1166 /* time filtered DRAM write bandwidth [MB/sec] */ 1167 uint16_t average_dram_writes; 1168 /* time filtered IPU read bandwidth [MB/sec] */ 1169 uint16_t average_ipu_reads; 1170 /* time filtered IPU write bandwidth [MB/sec] */ 1171 uint16_t average_ipu_writes; 1172 1173 /* Driver attached timestamp (in ns) */ 1174 uint64_t system_clock_counter; 1175 1176 /* Power/Energy */ 1177 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1178 uint32_t average_socket_power; 1179 /* time filtered IPU power [mW] */ 1180 uint16_t average_ipu_power; 1181 /* time filtered APU power [mW] */ 1182 uint32_t average_apu_power; 1183 /* time filtered GFX power [mW] */ 1184 uint32_t average_gfx_power; 1185 /* time filtered dGPU power [mW] */ 1186 uint32_t average_dgpu_power; 1187 /* time filtered sum of core power across all cores in the socket [mW] */ 1188 uint32_t average_all_core_power; 1189 /* calculated core power [mW] */ 1190 uint16_t average_core_power[16]; 1191 /* time filtered total system power [mW] */ 1192 uint16_t average_sys_power; 1193 /* maximum IRM defined STAPM power limit [mW] */ 1194 uint16_t stapm_power_limit; 1195 /* time filtered STAPM power limit [mW] */ 1196 uint16_t current_stapm_power_limit; 1197 1198 /* time filtered clocks [MHz] */ 1199 uint16_t average_gfxclk_frequency; 1200 uint16_t average_socclk_frequency; 1201 uint16_t average_vpeclk_frequency; 1202 uint16_t average_ipuclk_frequency; 1203 uint16_t average_fclk_frequency; 1204 uint16_t average_vclk_frequency; 1205 uint16_t average_uclk_frequency; 1206 uint16_t average_mpipu_frequency; 1207 1208 /* Current clocks */ 1209 /* target core frequency [MHz] */ 1210 uint16_t current_coreclk[16]; 1211 /* CCLK frequency limit enforced on classic cores [MHz] */ 1212 uint16_t current_core_maxfreq; 1213 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1214 uint16_t current_gfx_maxfreq; 1215 1216 /* Throttle Residency (ASIC dependent) */ 1217 uint32_t throttle_residency_prochot; 1218 uint32_t throttle_residency_spl; 1219 uint32_t throttle_residency_fppt; 1220 uint32_t throttle_residency_sppt; 1221 uint32_t throttle_residency_thm_core; 1222 uint32_t throttle_residency_thm_gfx; 1223 uint32_t throttle_residency_thm_soc; 1224 1225 /* Metrics table alpha filter time constant [us] */ 1226 uint32_t time_filter_alphavalue; 1227 }; 1228 1229 struct amdgpu_pmmetrics_header { 1230 uint16_t structure_size; 1231 uint16_t pad; 1232 uint32_t mp1_ip_discovery_version; 1233 uint32_t pmfw_version; 1234 uint32_t pmmetrics_version; 1235 }; 1236 1237 struct amdgpu_pm_metrics { 1238 struct amdgpu_pmmetrics_header common_header; 1239 1240 uint8_t data[]; 1241 }; 1242 1243 #endif 1244