1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 32 enum smu_event_type { 33 SMU_EVENT_RESET_COMPLETE = 0, 34 }; 35 36 struct amd_vce_state { 37 /* vce clocks */ 38 u32 evclk; 39 u32 ecclk; 40 /* gpu clocks */ 41 u32 sclk; 42 u32 mclk; 43 u8 clk_idx; 44 u8 pstate; 45 }; 46 47 48 enum amd_dpm_forced_level { 49 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 50 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 51 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 52 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 53 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 54 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 55 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 56 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 57 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 58 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 59 }; 60 61 enum amd_pm_state_type { 62 /* not used for dpm */ 63 POWER_STATE_TYPE_DEFAULT, 64 POWER_STATE_TYPE_POWERSAVE, 65 /* user selectable states */ 66 POWER_STATE_TYPE_BATTERY, 67 POWER_STATE_TYPE_BALANCED, 68 POWER_STATE_TYPE_PERFORMANCE, 69 /* internal states */ 70 POWER_STATE_TYPE_INTERNAL_UVD, 71 POWER_STATE_TYPE_INTERNAL_UVD_SD, 72 POWER_STATE_TYPE_INTERNAL_UVD_HD, 73 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 74 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 75 POWER_STATE_TYPE_INTERNAL_BOOT, 76 POWER_STATE_TYPE_INTERNAL_THERMAL, 77 POWER_STATE_TYPE_INTERNAL_ACPI, 78 POWER_STATE_TYPE_INTERNAL_ULV, 79 POWER_STATE_TYPE_INTERNAL_3DPERF, 80 }; 81 82 #define AMD_MAX_VCE_LEVELS 6 83 84 enum amd_vce_level { 85 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 86 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 87 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 88 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 89 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 90 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 91 }; 92 93 enum amd_fan_ctrl_mode { 94 AMD_FAN_CTRL_NONE = 0, 95 AMD_FAN_CTRL_MANUAL = 1, 96 AMD_FAN_CTRL_AUTO = 2, 97 }; 98 99 enum pp_clock_type { 100 PP_SCLK, 101 PP_MCLK, 102 PP_PCIE, 103 PP_SOCCLK, 104 PP_FCLK, 105 PP_DCEFCLK, 106 PP_VCLK, 107 PP_DCLK, 108 OD_SCLK, 109 OD_MCLK, 110 OD_VDDC_CURVE, 111 OD_RANGE, 112 OD_VDDGFX_OFFSET, 113 OD_CCLK, 114 }; 115 116 enum amd_pp_sensors { 117 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 118 AMDGPU_PP_SENSOR_CPU_CLK, 119 AMDGPU_PP_SENSOR_VDDNB, 120 AMDGPU_PP_SENSOR_VDDGFX, 121 AMDGPU_PP_SENSOR_UVD_VCLK, 122 AMDGPU_PP_SENSOR_UVD_DCLK, 123 AMDGPU_PP_SENSOR_VCE_ECCLK, 124 AMDGPU_PP_SENSOR_GPU_LOAD, 125 AMDGPU_PP_SENSOR_MEM_LOAD, 126 AMDGPU_PP_SENSOR_GFX_MCLK, 127 AMDGPU_PP_SENSOR_GPU_TEMP, 128 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 129 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 130 AMDGPU_PP_SENSOR_MEM_TEMP, 131 AMDGPU_PP_SENSOR_VCE_POWER, 132 AMDGPU_PP_SENSOR_UVD_POWER, 133 AMDGPU_PP_SENSOR_GPU_POWER, 134 AMDGPU_PP_SENSOR_SS_APU_SHARE, 135 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 136 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 137 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 138 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 139 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 140 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 141 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 142 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 143 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 144 }; 145 146 enum amd_pp_task { 147 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 148 AMD_PP_TASK_ENABLE_USER_STATE, 149 AMD_PP_TASK_READJUST_POWER_STATE, 150 AMD_PP_TASK_COMPLETE_INIT, 151 AMD_PP_TASK_MAX 152 }; 153 154 enum PP_SMC_POWER_PROFILE { 155 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 156 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 157 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 158 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 159 PP_SMC_POWER_PROFILE_VR = 0x4, 160 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 161 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 162 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 163 PP_SMC_POWER_PROFILE_COUNT, 164 }; 165 166 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 167 168 169 170 enum { 171 PP_GROUP_UNKNOWN = 0, 172 PP_GROUP_GFX = 1, 173 PP_GROUP_SYS, 174 PP_GROUP_MAX 175 }; 176 177 enum PP_OD_DPM_TABLE_COMMAND { 178 PP_OD_EDIT_SCLK_VDDC_TABLE, 179 PP_OD_EDIT_MCLK_VDDC_TABLE, 180 PP_OD_EDIT_CCLK_VDDC_TABLE, 181 PP_OD_EDIT_VDDC_CURVE, 182 PP_OD_RESTORE_DEFAULT_TABLE, 183 PP_OD_COMMIT_DPM_TABLE, 184 PP_OD_EDIT_VDDGFX_OFFSET 185 }; 186 187 struct pp_states_info { 188 uint32_t nums; 189 uint32_t states[16]; 190 }; 191 192 enum PP_HWMON_TEMP { 193 PP_TEMP_EDGE = 0, 194 PP_TEMP_JUNCTION, 195 PP_TEMP_MEM, 196 PP_TEMP_MAX 197 }; 198 199 enum pp_mp1_state { 200 PP_MP1_STATE_NONE, 201 PP_MP1_STATE_SHUTDOWN, 202 PP_MP1_STATE_UNLOAD, 203 PP_MP1_STATE_RESET, 204 }; 205 206 enum pp_df_cstate { 207 DF_CSTATE_DISALLOW = 0, 208 DF_CSTATE_ALLOW, 209 }; 210 211 /** 212 * DOC: amdgpu_pp_power 213 * 214 * APU power is managed to system-level requirements through the PPT 215 * (package power tracking) feature. PPT is intended to limit power to the 216 * requirements of the power source and could be dynamically updated to 217 * maximize APU performance within the system power budget. 218 * 219 * Two types of power measurement can be requested, where supported, with 220 * :c:type:`enum pp_power_type <pp_power_type>`. 221 */ 222 223 /** 224 * enum pp_power_limit_level - Used to query the power limits 225 * 226 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 227 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 228 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 229 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 230 */ 231 enum pp_power_limit_level 232 { 233 PP_PWR_LIMIT_MIN = -1, 234 PP_PWR_LIMIT_CURRENT, 235 PP_PWR_LIMIT_DEFAULT, 236 PP_PWR_LIMIT_MAX, 237 }; 238 239 /** 240 * enum pp_power_type - Used to specify the type of the requested power 241 * 242 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 243 * moving average of APU power (default ~5000 ms). 244 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 245 * where supported. 246 */ 247 enum pp_power_type 248 { 249 PP_PWR_TYPE_SUSTAINED, 250 PP_PWR_TYPE_FAST, 251 }; 252 253 #define PP_GROUP_MASK 0xF0000000 254 #define PP_GROUP_SHIFT 28 255 256 #define PP_BLOCK_MASK 0x0FFFFF00 257 #define PP_BLOCK_SHIFT 8 258 259 #define PP_BLOCK_GFX_CG 0x01 260 #define PP_BLOCK_GFX_MG 0x02 261 #define PP_BLOCK_GFX_3D 0x04 262 #define PP_BLOCK_GFX_RLC 0x08 263 #define PP_BLOCK_GFX_CP 0x10 264 #define PP_BLOCK_SYS_BIF 0x01 265 #define PP_BLOCK_SYS_MC 0x02 266 #define PP_BLOCK_SYS_ROM 0x04 267 #define PP_BLOCK_SYS_DRM 0x08 268 #define PP_BLOCK_SYS_HDP 0x10 269 #define PP_BLOCK_SYS_SDMA 0x20 270 271 #define PP_STATE_MASK 0x0000000F 272 #define PP_STATE_SHIFT 0 273 #define PP_STATE_SUPPORT_MASK 0x000000F0 274 #define PP_STATE_SUPPORT_SHIFT 0 275 276 #define PP_STATE_CG 0x01 277 #define PP_STATE_LS 0x02 278 #define PP_STATE_DS 0x04 279 #define PP_STATE_SD 0x08 280 #define PP_STATE_SUPPORT_CG 0x10 281 #define PP_STATE_SUPPORT_LS 0x20 282 #define PP_STATE_SUPPORT_DS 0x40 283 #define PP_STATE_SUPPORT_SD 0x80 284 285 #define PP_CG_MSG_ID(group, block, support, state) \ 286 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 287 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 288 289 #define XGMI_MODE_PSTATE_D3 0 290 #define XGMI_MODE_PSTATE_D0 1 291 292 #define NUM_HBM_INSTANCES 4 293 294 struct seq_file; 295 enum amd_pp_clock_type; 296 struct amd_pp_simple_clock_info; 297 struct amd_pp_display_configuration; 298 struct amd_pp_clock_info; 299 struct pp_display_clock_request; 300 struct pp_clock_levels_with_voltage; 301 struct pp_clock_levels_with_latency; 302 struct amd_pp_clocks; 303 struct pp_smu_wm_range_sets; 304 struct pp_smu_nv_clock_table; 305 struct dpm_clocks; 306 307 struct amd_pm_funcs { 308 /* export for dpm on ci and si */ 309 int (*pre_set_power_state)(void *handle); 310 int (*set_power_state)(void *handle); 311 void (*post_set_power_state)(void *handle); 312 void (*display_configuration_changed)(void *handle); 313 void (*print_power_state)(void *handle, void *ps); 314 bool (*vblank_too_short)(void *handle); 315 void (*enable_bapm)(void *handle, bool enable); 316 int (*check_state_equal)(void *handle, 317 void *cps, 318 void *rps, 319 bool *equal); 320 /* export for sysfs */ 321 int (*set_fan_control_mode)(void *handle, u32 mode); 322 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 323 int (*set_fan_speed_pwm)(void *handle, u32 speed); 324 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 325 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 326 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 327 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 328 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 329 int (*get_sclk_od)(void *handle); 330 int (*set_sclk_od)(void *handle, uint32_t value); 331 int (*get_mclk_od)(void *handle); 332 int (*set_mclk_od)(void *handle, uint32_t value); 333 int (*read_sensor)(void *handle, int idx, void *value, int *size); 334 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 335 enum amd_pm_state_type (*get_current_power_state)(void *handle); 336 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 337 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 338 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 339 int (*get_pp_table)(void *handle, char **table); 340 int (*set_pp_table)(void *handle, const char *buf, size_t size); 341 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 342 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 343 /* export to amdgpu */ 344 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 345 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 346 enum amd_pm_state_type *user_state); 347 int (*load_firmware)(void *handle); 348 int (*wait_for_fw_loading_complete)(void *handle); 349 int (*set_powergating_by_smu)(void *handle, 350 uint32_t block_type, bool gate); 351 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 352 int (*set_power_limit)(void *handle, uint32_t n); 353 int (*get_power_limit)(void *handle, uint32_t *limit, 354 enum pp_power_limit_level pp_limit_level, 355 enum pp_power_type power_type); 356 int (*get_power_profile_mode)(void *handle, char *buf); 357 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 358 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 359 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 360 long *input, uint32_t size); 361 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 362 int (*smu_i2c_bus_access)(void *handle, bool acquire); 363 int (*gfx_state_change_set)(void *handle, uint32_t state); 364 /* export to DC */ 365 u32 (*get_sclk)(void *handle, bool low); 366 u32 (*get_mclk)(void *handle, bool low); 367 int (*display_configuration_change)(void *handle, 368 const struct amd_pp_display_configuration *input); 369 int (*get_display_power_level)(void *handle, 370 struct amd_pp_simple_clock_info *output); 371 int (*get_current_clocks)(void *handle, 372 struct amd_pp_clock_info *clocks); 373 int (*get_clock_by_type)(void *handle, 374 enum amd_pp_clock_type type, 375 struct amd_pp_clocks *clocks); 376 int (*get_clock_by_type_with_latency)(void *handle, 377 enum amd_pp_clock_type type, 378 struct pp_clock_levels_with_latency *clocks); 379 int (*get_clock_by_type_with_voltage)(void *handle, 380 enum amd_pp_clock_type type, 381 struct pp_clock_levels_with_voltage *clocks); 382 int (*set_watermarks_for_clocks_ranges)(void *handle, 383 void *clock_ranges); 384 int (*display_clock_voltage_request)(void *handle, 385 struct pp_display_clock_request *clock); 386 int (*get_display_mode_validation_clocks)(void *handle, 387 struct amd_pp_simple_clock_info *clocks); 388 int (*notify_smu_enable_pwe)(void *handle); 389 int (*enable_mgpu_fan_boost)(void *handle); 390 int (*set_active_display_count)(void *handle, uint32_t count); 391 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 392 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 393 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 394 int (*get_asic_baco_capability)(void *handle, bool *cap); 395 int (*get_asic_baco_state)(void *handle, int *state); 396 int (*set_asic_baco_state)(void *handle, int state); 397 int (*get_ppfeature_status)(void *handle, char *buf); 398 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 399 int (*asic_reset_mode_2)(void *handle); 400 int (*asic_reset_enable_gfx_features)(void *handle); 401 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 402 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 403 ssize_t (*get_gpu_metrics)(void *handle, void **table); 404 int (*set_watermarks_for_clock_ranges)(void *handle, 405 struct pp_smu_wm_range_sets *ranges); 406 int (*display_disable_memory_clock_switch)(void *handle, 407 bool disable_memory_clock_switch); 408 int (*get_max_sustainable_clocks_by_dc)(void *handle, 409 struct pp_smu_nv_clock_table *max_clocks); 410 int (*get_uclk_dpm_states)(void *handle, 411 unsigned int *clock_values_in_khz, 412 unsigned int *num_states); 413 int (*get_dpm_clock_table)(void *handle, 414 struct dpm_clocks *clock_table); 415 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 416 void (*pm_compute_clocks)(void *handle); 417 }; 418 419 struct metrics_table_header { 420 uint16_t structure_size; 421 uint8_t format_revision; 422 uint8_t content_revision; 423 }; 424 425 /* 426 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 427 * Use gpu_metrics_v1_1 or later instead. 428 */ 429 struct gpu_metrics_v1_0 { 430 struct metrics_table_header common_header; 431 432 /* Driver attached timestamp (in ns) */ 433 uint64_t system_clock_counter; 434 435 /* Temperature */ 436 uint16_t temperature_edge; 437 uint16_t temperature_hotspot; 438 uint16_t temperature_mem; 439 uint16_t temperature_vrgfx; 440 uint16_t temperature_vrsoc; 441 uint16_t temperature_vrmem; 442 443 /* Utilization */ 444 uint16_t average_gfx_activity; 445 uint16_t average_umc_activity; // memory controller 446 uint16_t average_mm_activity; // UVD or VCN 447 448 /* Power/Energy */ 449 uint16_t average_socket_power; 450 uint32_t energy_accumulator; 451 452 /* Average clocks */ 453 uint16_t average_gfxclk_frequency; 454 uint16_t average_socclk_frequency; 455 uint16_t average_uclk_frequency; 456 uint16_t average_vclk0_frequency; 457 uint16_t average_dclk0_frequency; 458 uint16_t average_vclk1_frequency; 459 uint16_t average_dclk1_frequency; 460 461 /* Current clocks */ 462 uint16_t current_gfxclk; 463 uint16_t current_socclk; 464 uint16_t current_uclk; 465 uint16_t current_vclk0; 466 uint16_t current_dclk0; 467 uint16_t current_vclk1; 468 uint16_t current_dclk1; 469 470 /* Throttle status */ 471 uint32_t throttle_status; 472 473 /* Fans */ 474 uint16_t current_fan_speed; 475 476 /* Link width/speed */ 477 uint8_t pcie_link_width; 478 uint8_t pcie_link_speed; // in 0.1 GT/s 479 }; 480 481 struct gpu_metrics_v1_1 { 482 struct metrics_table_header common_header; 483 484 /* Temperature */ 485 uint16_t temperature_edge; 486 uint16_t temperature_hotspot; 487 uint16_t temperature_mem; 488 uint16_t temperature_vrgfx; 489 uint16_t temperature_vrsoc; 490 uint16_t temperature_vrmem; 491 492 /* Utilization */ 493 uint16_t average_gfx_activity; 494 uint16_t average_umc_activity; // memory controller 495 uint16_t average_mm_activity; // UVD or VCN 496 497 /* Power/Energy */ 498 uint16_t average_socket_power; 499 uint64_t energy_accumulator; 500 501 /* Driver attached timestamp (in ns) */ 502 uint64_t system_clock_counter; 503 504 /* Average clocks */ 505 uint16_t average_gfxclk_frequency; 506 uint16_t average_socclk_frequency; 507 uint16_t average_uclk_frequency; 508 uint16_t average_vclk0_frequency; 509 uint16_t average_dclk0_frequency; 510 uint16_t average_vclk1_frequency; 511 uint16_t average_dclk1_frequency; 512 513 /* Current clocks */ 514 uint16_t current_gfxclk; 515 uint16_t current_socclk; 516 uint16_t current_uclk; 517 uint16_t current_vclk0; 518 uint16_t current_dclk0; 519 uint16_t current_vclk1; 520 uint16_t current_dclk1; 521 522 /* Throttle status */ 523 uint32_t throttle_status; 524 525 /* Fans */ 526 uint16_t current_fan_speed; 527 528 /* Link width/speed */ 529 uint16_t pcie_link_width; 530 uint16_t pcie_link_speed; // in 0.1 GT/s 531 532 uint16_t padding; 533 534 uint32_t gfx_activity_acc; 535 uint32_t mem_activity_acc; 536 537 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 538 }; 539 540 struct gpu_metrics_v1_2 { 541 struct metrics_table_header common_header; 542 543 /* Temperature */ 544 uint16_t temperature_edge; 545 uint16_t temperature_hotspot; 546 uint16_t temperature_mem; 547 uint16_t temperature_vrgfx; 548 uint16_t temperature_vrsoc; 549 uint16_t temperature_vrmem; 550 551 /* Utilization */ 552 uint16_t average_gfx_activity; 553 uint16_t average_umc_activity; // memory controller 554 uint16_t average_mm_activity; // UVD or VCN 555 556 /* Power/Energy */ 557 uint16_t average_socket_power; 558 uint64_t energy_accumulator; 559 560 /* Driver attached timestamp (in ns) */ 561 uint64_t system_clock_counter; 562 563 /* Average clocks */ 564 uint16_t average_gfxclk_frequency; 565 uint16_t average_socclk_frequency; 566 uint16_t average_uclk_frequency; 567 uint16_t average_vclk0_frequency; 568 uint16_t average_dclk0_frequency; 569 uint16_t average_vclk1_frequency; 570 uint16_t average_dclk1_frequency; 571 572 /* Current clocks */ 573 uint16_t current_gfxclk; 574 uint16_t current_socclk; 575 uint16_t current_uclk; 576 uint16_t current_vclk0; 577 uint16_t current_dclk0; 578 uint16_t current_vclk1; 579 uint16_t current_dclk1; 580 581 /* Throttle status (ASIC dependent) */ 582 uint32_t throttle_status; 583 584 /* Fans */ 585 uint16_t current_fan_speed; 586 587 /* Link width/speed */ 588 uint16_t pcie_link_width; 589 uint16_t pcie_link_speed; // in 0.1 GT/s 590 591 uint16_t padding; 592 593 uint32_t gfx_activity_acc; 594 uint32_t mem_activity_acc; 595 596 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 597 598 /* PMFW attached timestamp (10ns resolution) */ 599 uint64_t firmware_timestamp; 600 }; 601 602 struct gpu_metrics_v1_3 { 603 struct metrics_table_header common_header; 604 605 /* Temperature */ 606 uint16_t temperature_edge; 607 uint16_t temperature_hotspot; 608 uint16_t temperature_mem; 609 uint16_t temperature_vrgfx; 610 uint16_t temperature_vrsoc; 611 uint16_t temperature_vrmem; 612 613 /* Utilization */ 614 uint16_t average_gfx_activity; 615 uint16_t average_umc_activity; // memory controller 616 uint16_t average_mm_activity; // UVD or VCN 617 618 /* Power/Energy */ 619 uint16_t average_socket_power; 620 uint64_t energy_accumulator; 621 622 /* Driver attached timestamp (in ns) */ 623 uint64_t system_clock_counter; 624 625 /* Average clocks */ 626 uint16_t average_gfxclk_frequency; 627 uint16_t average_socclk_frequency; 628 uint16_t average_uclk_frequency; 629 uint16_t average_vclk0_frequency; 630 uint16_t average_dclk0_frequency; 631 uint16_t average_vclk1_frequency; 632 uint16_t average_dclk1_frequency; 633 634 /* Current clocks */ 635 uint16_t current_gfxclk; 636 uint16_t current_socclk; 637 uint16_t current_uclk; 638 uint16_t current_vclk0; 639 uint16_t current_dclk0; 640 uint16_t current_vclk1; 641 uint16_t current_dclk1; 642 643 /* Throttle status */ 644 uint32_t throttle_status; 645 646 /* Fans */ 647 uint16_t current_fan_speed; 648 649 /* Link width/speed */ 650 uint16_t pcie_link_width; 651 uint16_t pcie_link_speed; // in 0.1 GT/s 652 653 uint16_t padding; 654 655 uint32_t gfx_activity_acc; 656 uint32_t mem_activity_acc; 657 658 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 659 660 /* PMFW attached timestamp (10ns resolution) */ 661 uint64_t firmware_timestamp; 662 663 /* Voltage (mV) */ 664 uint16_t voltage_soc; 665 uint16_t voltage_gfx; 666 uint16_t voltage_mem; 667 668 uint16_t padding1; 669 670 /* Throttle status (ASIC independent) */ 671 uint64_t indep_throttle_status; 672 }; 673 674 /* 675 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 676 * Use gpu_metrics_v2_1 or later instead. 677 */ 678 struct gpu_metrics_v2_0 { 679 struct metrics_table_header common_header; 680 681 /* Driver attached timestamp (in ns) */ 682 uint64_t system_clock_counter; 683 684 /* Temperature */ 685 uint16_t temperature_gfx; // gfx temperature on APUs 686 uint16_t temperature_soc; // soc temperature on APUs 687 uint16_t temperature_core[8]; // CPU core temperature on APUs 688 uint16_t temperature_l3[2]; 689 690 /* Utilization */ 691 uint16_t average_gfx_activity; 692 uint16_t average_mm_activity; // UVD or VCN 693 694 /* Power/Energy */ 695 uint16_t average_socket_power; // dGPU + APU power on A + A platform 696 uint16_t average_cpu_power; 697 uint16_t average_soc_power; 698 uint16_t average_gfx_power; 699 uint16_t average_core_power[8]; // CPU core power on APUs 700 701 /* Average clocks */ 702 uint16_t average_gfxclk_frequency; 703 uint16_t average_socclk_frequency; 704 uint16_t average_uclk_frequency; 705 uint16_t average_fclk_frequency; 706 uint16_t average_vclk_frequency; 707 uint16_t average_dclk_frequency; 708 709 /* Current clocks */ 710 uint16_t current_gfxclk; 711 uint16_t current_socclk; 712 uint16_t current_uclk; 713 uint16_t current_fclk; 714 uint16_t current_vclk; 715 uint16_t current_dclk; 716 uint16_t current_coreclk[8]; // CPU core clocks 717 uint16_t current_l3clk[2]; 718 719 /* Throttle status */ 720 uint32_t throttle_status; 721 722 /* Fans */ 723 uint16_t fan_pwm; 724 725 uint16_t padding; 726 }; 727 728 struct gpu_metrics_v2_1 { 729 struct metrics_table_header common_header; 730 731 /* Temperature */ 732 uint16_t temperature_gfx; // gfx temperature on APUs 733 uint16_t temperature_soc; // soc temperature on APUs 734 uint16_t temperature_core[8]; // CPU core temperature on APUs 735 uint16_t temperature_l3[2]; 736 737 /* Utilization */ 738 uint16_t average_gfx_activity; 739 uint16_t average_mm_activity; // UVD or VCN 740 741 /* Driver attached timestamp (in ns) */ 742 uint64_t system_clock_counter; 743 744 /* Power/Energy */ 745 uint16_t average_socket_power; // dGPU + APU power on A + A platform 746 uint16_t average_cpu_power; 747 uint16_t average_soc_power; 748 uint16_t average_gfx_power; 749 uint16_t average_core_power[8]; // CPU core power on APUs 750 751 /* Average clocks */ 752 uint16_t average_gfxclk_frequency; 753 uint16_t average_socclk_frequency; 754 uint16_t average_uclk_frequency; 755 uint16_t average_fclk_frequency; 756 uint16_t average_vclk_frequency; 757 uint16_t average_dclk_frequency; 758 759 /* Current clocks */ 760 uint16_t current_gfxclk; 761 uint16_t current_socclk; 762 uint16_t current_uclk; 763 uint16_t current_fclk; 764 uint16_t current_vclk; 765 uint16_t current_dclk; 766 uint16_t current_coreclk[8]; // CPU core clocks 767 uint16_t current_l3clk[2]; 768 769 /* Throttle status */ 770 uint32_t throttle_status; 771 772 /* Fans */ 773 uint16_t fan_pwm; 774 775 uint16_t padding[3]; 776 }; 777 778 struct gpu_metrics_v2_2 { 779 struct metrics_table_header common_header; 780 781 /* Temperature */ 782 uint16_t temperature_gfx; // gfx temperature on APUs 783 uint16_t temperature_soc; // soc temperature on APUs 784 uint16_t temperature_core[8]; // CPU core temperature on APUs 785 uint16_t temperature_l3[2]; 786 787 /* Utilization */ 788 uint16_t average_gfx_activity; 789 uint16_t average_mm_activity; // UVD or VCN 790 791 /* Driver attached timestamp (in ns) */ 792 uint64_t system_clock_counter; 793 794 /* Power/Energy */ 795 uint16_t average_socket_power; // dGPU + APU power on A + A platform 796 uint16_t average_cpu_power; 797 uint16_t average_soc_power; 798 uint16_t average_gfx_power; 799 uint16_t average_core_power[8]; // CPU core power on APUs 800 801 /* Average clocks */ 802 uint16_t average_gfxclk_frequency; 803 uint16_t average_socclk_frequency; 804 uint16_t average_uclk_frequency; 805 uint16_t average_fclk_frequency; 806 uint16_t average_vclk_frequency; 807 uint16_t average_dclk_frequency; 808 809 /* Current clocks */ 810 uint16_t current_gfxclk; 811 uint16_t current_socclk; 812 uint16_t current_uclk; 813 uint16_t current_fclk; 814 uint16_t current_vclk; 815 uint16_t current_dclk; 816 uint16_t current_coreclk[8]; // CPU core clocks 817 uint16_t current_l3clk[2]; 818 819 /* Throttle status (ASIC dependent) */ 820 uint32_t throttle_status; 821 822 /* Fans */ 823 uint16_t fan_pwm; 824 825 uint16_t padding[3]; 826 827 /* Throttle status (ASIC independent) */ 828 uint64_t indep_throttle_status; 829 }; 830 831 struct gpu_metrics_v2_3 { 832 struct metrics_table_header common_header; 833 834 /* Temperature */ 835 uint16_t temperature_gfx; // gfx temperature on APUs 836 uint16_t temperature_soc; // soc temperature on APUs 837 uint16_t temperature_core[8]; // CPU core temperature on APUs 838 uint16_t temperature_l3[2]; 839 840 /* Utilization */ 841 uint16_t average_gfx_activity; 842 uint16_t average_mm_activity; // UVD or VCN 843 844 /* Driver attached timestamp (in ns) */ 845 uint64_t system_clock_counter; 846 847 /* Power/Energy */ 848 uint16_t average_socket_power; // dGPU + APU power on A + A platform 849 uint16_t average_cpu_power; 850 uint16_t average_soc_power; 851 uint16_t average_gfx_power; 852 uint16_t average_core_power[8]; // CPU core power on APUs 853 854 /* Average clocks */ 855 uint16_t average_gfxclk_frequency; 856 uint16_t average_socclk_frequency; 857 uint16_t average_uclk_frequency; 858 uint16_t average_fclk_frequency; 859 uint16_t average_vclk_frequency; 860 uint16_t average_dclk_frequency; 861 862 /* Current clocks */ 863 uint16_t current_gfxclk; 864 uint16_t current_socclk; 865 uint16_t current_uclk; 866 uint16_t current_fclk; 867 uint16_t current_vclk; 868 uint16_t current_dclk; 869 uint16_t current_coreclk[8]; // CPU core clocks 870 uint16_t current_l3clk[2]; 871 872 /* Throttle status (ASIC dependent) */ 873 uint32_t throttle_status; 874 875 /* Fans */ 876 uint16_t fan_pwm; 877 878 uint16_t padding[3]; 879 880 /* Throttle status (ASIC independent) */ 881 uint64_t indep_throttle_status; 882 883 /* Average Temperature */ 884 uint16_t average_temperature_gfx; // average gfx temperature on APUs 885 uint16_t average_temperature_soc; // average soc temperature on APUs 886 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 887 uint16_t average_temperature_l3[2]; 888 }; 889 #endif 890