1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 29 struct amd_vce_state { 30 /* vce clocks */ 31 u32 evclk; 32 u32 ecclk; 33 /* gpu clocks */ 34 u32 sclk; 35 u32 mclk; 36 u8 clk_idx; 37 u8 pstate; 38 }; 39 40 41 enum amd_dpm_forced_level { 42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 44 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 51 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 52 }; 53 54 enum amd_pm_state_type { 55 /* not used for dpm */ 56 POWER_STATE_TYPE_DEFAULT, 57 POWER_STATE_TYPE_POWERSAVE, 58 /* user selectable states */ 59 POWER_STATE_TYPE_BATTERY, 60 POWER_STATE_TYPE_BALANCED, 61 POWER_STATE_TYPE_PERFORMANCE, 62 /* internal states */ 63 POWER_STATE_TYPE_INTERNAL_UVD, 64 POWER_STATE_TYPE_INTERNAL_UVD_SD, 65 POWER_STATE_TYPE_INTERNAL_UVD_HD, 66 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 67 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 68 POWER_STATE_TYPE_INTERNAL_BOOT, 69 POWER_STATE_TYPE_INTERNAL_THERMAL, 70 POWER_STATE_TYPE_INTERNAL_ACPI, 71 POWER_STATE_TYPE_INTERNAL_ULV, 72 POWER_STATE_TYPE_INTERNAL_3DPERF, 73 }; 74 75 #define AMD_MAX_VCE_LEVELS 6 76 77 enum amd_vce_level { 78 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 79 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 80 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 81 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 82 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 83 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 84 }; 85 86 enum amd_fan_ctrl_mode { 87 AMD_FAN_CTRL_NONE = 0, 88 AMD_FAN_CTRL_MANUAL = 1, 89 AMD_FAN_CTRL_AUTO = 2, 90 }; 91 92 enum pp_clock_type { 93 PP_SCLK, 94 PP_MCLK, 95 PP_PCIE, 96 PP_SOCCLK, 97 PP_FCLK, 98 PP_DCEFCLK, 99 PP_VCLK, 100 PP_DCLK, 101 OD_SCLK, 102 OD_MCLK, 103 OD_VDDC_CURVE, 104 OD_RANGE, 105 OD_VDDGFX_OFFSET, 106 OD_CCLK, 107 }; 108 109 enum amd_pp_sensors { 110 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 111 AMDGPU_PP_SENSOR_CPU_CLK, 112 AMDGPU_PP_SENSOR_VDDNB, 113 AMDGPU_PP_SENSOR_VDDGFX, 114 AMDGPU_PP_SENSOR_UVD_VCLK, 115 AMDGPU_PP_SENSOR_UVD_DCLK, 116 AMDGPU_PP_SENSOR_VCE_ECCLK, 117 AMDGPU_PP_SENSOR_GPU_LOAD, 118 AMDGPU_PP_SENSOR_MEM_LOAD, 119 AMDGPU_PP_SENSOR_GFX_MCLK, 120 AMDGPU_PP_SENSOR_GPU_TEMP, 121 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 122 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 123 AMDGPU_PP_SENSOR_MEM_TEMP, 124 AMDGPU_PP_SENSOR_VCE_POWER, 125 AMDGPU_PP_SENSOR_UVD_POWER, 126 AMDGPU_PP_SENSOR_GPU_POWER, 127 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 128 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 129 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 130 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 131 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 132 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 133 }; 134 135 enum amd_pp_task { 136 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 137 AMD_PP_TASK_ENABLE_USER_STATE, 138 AMD_PP_TASK_READJUST_POWER_STATE, 139 AMD_PP_TASK_COMPLETE_INIT, 140 AMD_PP_TASK_MAX 141 }; 142 143 enum PP_SMC_POWER_PROFILE { 144 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 145 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 146 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 147 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 148 PP_SMC_POWER_PROFILE_VR = 0x4, 149 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 150 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 151 PP_SMC_POWER_PROFILE_COUNT, 152 }; 153 154 enum { 155 PP_GROUP_UNKNOWN = 0, 156 PP_GROUP_GFX = 1, 157 PP_GROUP_SYS, 158 PP_GROUP_MAX 159 }; 160 161 enum PP_OD_DPM_TABLE_COMMAND { 162 PP_OD_EDIT_SCLK_VDDC_TABLE, 163 PP_OD_EDIT_MCLK_VDDC_TABLE, 164 PP_OD_EDIT_CCLK_VDDC_TABLE, 165 PP_OD_EDIT_VDDC_CURVE, 166 PP_OD_RESTORE_DEFAULT_TABLE, 167 PP_OD_COMMIT_DPM_TABLE, 168 PP_OD_EDIT_VDDGFX_OFFSET 169 }; 170 171 struct pp_states_info { 172 uint32_t nums; 173 uint32_t states[16]; 174 }; 175 176 enum PP_HWMON_TEMP { 177 PP_TEMP_EDGE = 0, 178 PP_TEMP_JUNCTION, 179 PP_TEMP_MEM, 180 PP_TEMP_MAX 181 }; 182 183 enum pp_mp1_state { 184 PP_MP1_STATE_NONE, 185 PP_MP1_STATE_SHUTDOWN, 186 PP_MP1_STATE_UNLOAD, 187 PP_MP1_STATE_RESET, 188 }; 189 190 enum pp_df_cstate { 191 DF_CSTATE_DISALLOW = 0, 192 DF_CSTATE_ALLOW, 193 }; 194 195 #define PP_GROUP_MASK 0xF0000000 196 #define PP_GROUP_SHIFT 28 197 198 #define PP_BLOCK_MASK 0x0FFFFF00 199 #define PP_BLOCK_SHIFT 8 200 201 #define PP_BLOCK_GFX_CG 0x01 202 #define PP_BLOCK_GFX_MG 0x02 203 #define PP_BLOCK_GFX_3D 0x04 204 #define PP_BLOCK_GFX_RLC 0x08 205 #define PP_BLOCK_GFX_CP 0x10 206 #define PP_BLOCK_SYS_BIF 0x01 207 #define PP_BLOCK_SYS_MC 0x02 208 #define PP_BLOCK_SYS_ROM 0x04 209 #define PP_BLOCK_SYS_DRM 0x08 210 #define PP_BLOCK_SYS_HDP 0x10 211 #define PP_BLOCK_SYS_SDMA 0x20 212 213 #define PP_STATE_MASK 0x0000000F 214 #define PP_STATE_SHIFT 0 215 #define PP_STATE_SUPPORT_MASK 0x000000F0 216 #define PP_STATE_SUPPORT_SHIFT 0 217 218 #define PP_STATE_CG 0x01 219 #define PP_STATE_LS 0x02 220 #define PP_STATE_DS 0x04 221 #define PP_STATE_SD 0x08 222 #define PP_STATE_SUPPORT_CG 0x10 223 #define PP_STATE_SUPPORT_LS 0x20 224 #define PP_STATE_SUPPORT_DS 0x40 225 #define PP_STATE_SUPPORT_SD 0x80 226 227 #define PP_CG_MSG_ID(group, block, support, state) \ 228 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 229 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 230 231 #define XGMI_MODE_PSTATE_D3 0 232 #define XGMI_MODE_PSTATE_D0 1 233 234 #define NUM_HBM_INSTANCES 4 235 236 struct seq_file; 237 enum amd_pp_clock_type; 238 struct amd_pp_simple_clock_info; 239 struct amd_pp_display_configuration; 240 struct amd_pp_clock_info; 241 struct pp_display_clock_request; 242 struct pp_clock_levels_with_voltage; 243 struct pp_clock_levels_with_latency; 244 struct amd_pp_clocks; 245 struct pp_smu_wm_range_sets; 246 struct pp_smu_nv_clock_table; 247 struct dpm_clocks; 248 249 struct amd_pm_funcs { 250 /* export for dpm on ci and si */ 251 int (*pre_set_power_state)(void *handle); 252 int (*set_power_state)(void *handle); 253 void (*post_set_power_state)(void *handle); 254 void (*display_configuration_changed)(void *handle); 255 void (*print_power_state)(void *handle, void *ps); 256 bool (*vblank_too_short)(void *handle); 257 void (*enable_bapm)(void *handle, bool enable); 258 int (*check_state_equal)(void *handle, 259 void *cps, 260 void *rps, 261 bool *equal); 262 /* export for sysfs */ 263 void (*set_fan_control_mode)(void *handle, u32 mode); 264 u32 (*get_fan_control_mode)(void *handle); 265 int (*set_fan_speed_percent)(void *handle, u32 speed); 266 int (*get_fan_speed_percent)(void *handle, u32 *speed); 267 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 268 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 269 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 270 int (*get_sclk_od)(void *handle); 271 int (*set_sclk_od)(void *handle, uint32_t value); 272 int (*get_mclk_od)(void *handle); 273 int (*set_mclk_od)(void *handle, uint32_t value); 274 int (*read_sensor)(void *handle, int idx, void *value, int *size); 275 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 276 enum amd_pm_state_type (*get_current_power_state)(void *handle); 277 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 278 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 279 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 280 int (*get_pp_table)(void *handle, char **table); 281 int (*set_pp_table)(void *handle, const char *buf, size_t size); 282 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 283 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 284 /* export to amdgpu */ 285 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 286 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 287 enum amd_pm_state_type *user_state); 288 int (*load_firmware)(void *handle); 289 int (*wait_for_fw_loading_complete)(void *handle); 290 int (*set_powergating_by_smu)(void *handle, 291 uint32_t block_type, bool gate); 292 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 293 int (*set_power_limit)(void *handle, uint32_t n); 294 int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit, 295 bool default_limit); 296 int (*get_power_profile_mode)(void *handle, char *buf); 297 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 298 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 299 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 300 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 301 int (*smu_i2c_bus_access)(void *handle, bool acquire); 302 int (*gfx_state_change_set)(void *handle, uint32_t state); 303 /* export to DC */ 304 u32 (*get_sclk)(void *handle, bool low); 305 u32 (*get_mclk)(void *handle, bool low); 306 int (*display_configuration_change)(void *handle, 307 const struct amd_pp_display_configuration *input); 308 int (*get_display_power_level)(void *handle, 309 struct amd_pp_simple_clock_info *output); 310 int (*get_current_clocks)(void *handle, 311 struct amd_pp_clock_info *clocks); 312 int (*get_clock_by_type)(void *handle, 313 enum amd_pp_clock_type type, 314 struct amd_pp_clocks *clocks); 315 int (*get_clock_by_type_with_latency)(void *handle, 316 enum amd_pp_clock_type type, 317 struct pp_clock_levels_with_latency *clocks); 318 int (*get_clock_by_type_with_voltage)(void *handle, 319 enum amd_pp_clock_type type, 320 struct pp_clock_levels_with_voltage *clocks); 321 int (*set_watermarks_for_clocks_ranges)(void *handle, 322 void *clock_ranges); 323 int (*display_clock_voltage_request)(void *handle, 324 struct pp_display_clock_request *clock); 325 int (*get_display_mode_validation_clocks)(void *handle, 326 struct amd_pp_simple_clock_info *clocks); 327 int (*notify_smu_enable_pwe)(void *handle); 328 int (*enable_mgpu_fan_boost)(void *handle); 329 int (*set_active_display_count)(void *handle, uint32_t count); 330 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 331 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 332 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 333 int (*get_asic_baco_capability)(void *handle, bool *cap); 334 int (*get_asic_baco_state)(void *handle, int *state); 335 int (*set_asic_baco_state)(void *handle, int state); 336 int (*get_ppfeature_status)(void *handle, char *buf); 337 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 338 int (*asic_reset_mode_2)(void *handle); 339 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 340 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 341 ssize_t (*get_gpu_metrics)(void *handle, void **table); 342 int (*set_watermarks_for_clock_ranges)(void *handle, 343 struct pp_smu_wm_range_sets *ranges); 344 int (*display_disable_memory_clock_switch)(void *handle, 345 bool disable_memory_clock_switch); 346 int (*get_max_sustainable_clocks_by_dc)(void *handle, 347 struct pp_smu_nv_clock_table *max_clocks); 348 int (*get_uclk_dpm_states)(void *handle, 349 unsigned int *clock_values_in_khz, 350 unsigned int *num_states); 351 int (*get_dpm_clock_table)(void *handle, 352 struct dpm_clocks *clock_table); 353 }; 354 355 struct metrics_table_header { 356 uint16_t structure_size; 357 uint8_t format_revision; 358 uint8_t content_revision; 359 }; 360 361 /* 362 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 363 * Use gpu_metrics_v1_1 or later instead. 364 */ 365 struct gpu_metrics_v1_0 { 366 struct metrics_table_header common_header; 367 368 /* Driver attached timestamp (in ns) */ 369 uint64_t system_clock_counter; 370 371 /* Temperature */ 372 uint16_t temperature_edge; 373 uint16_t temperature_hotspot; 374 uint16_t temperature_mem; 375 uint16_t temperature_vrgfx; 376 uint16_t temperature_vrsoc; 377 uint16_t temperature_vrmem; 378 379 /* Utilization */ 380 uint16_t average_gfx_activity; 381 uint16_t average_umc_activity; // memory controller 382 uint16_t average_mm_activity; // UVD or VCN 383 384 /* Power/Energy */ 385 uint16_t average_socket_power; 386 uint32_t energy_accumulator; 387 388 /* Average clocks */ 389 uint16_t average_gfxclk_frequency; 390 uint16_t average_socclk_frequency; 391 uint16_t average_uclk_frequency; 392 uint16_t average_vclk0_frequency; 393 uint16_t average_dclk0_frequency; 394 uint16_t average_vclk1_frequency; 395 uint16_t average_dclk1_frequency; 396 397 /* Current clocks */ 398 uint16_t current_gfxclk; 399 uint16_t current_socclk; 400 uint16_t current_uclk; 401 uint16_t current_vclk0; 402 uint16_t current_dclk0; 403 uint16_t current_vclk1; 404 uint16_t current_dclk1; 405 406 /* Throttle status */ 407 uint32_t throttle_status; 408 409 /* Fans */ 410 uint16_t current_fan_speed; 411 412 /* Link width/speed */ 413 uint8_t pcie_link_width; 414 uint8_t pcie_link_speed; // in 0.1 GT/s 415 }; 416 417 struct gpu_metrics_v1_1 { 418 struct metrics_table_header common_header; 419 420 /* Temperature */ 421 uint16_t temperature_edge; 422 uint16_t temperature_hotspot; 423 uint16_t temperature_mem; 424 uint16_t temperature_vrgfx; 425 uint16_t temperature_vrsoc; 426 uint16_t temperature_vrmem; 427 428 /* Utilization */ 429 uint16_t average_gfx_activity; 430 uint16_t average_umc_activity; // memory controller 431 uint16_t average_mm_activity; // UVD or VCN 432 433 /* Power/Energy */ 434 uint16_t average_socket_power; 435 uint64_t energy_accumulator; 436 437 /* Driver attached timestamp (in ns) */ 438 uint64_t system_clock_counter; 439 440 /* Average clocks */ 441 uint16_t average_gfxclk_frequency; 442 uint16_t average_socclk_frequency; 443 uint16_t average_uclk_frequency; 444 uint16_t average_vclk0_frequency; 445 uint16_t average_dclk0_frequency; 446 uint16_t average_vclk1_frequency; 447 uint16_t average_dclk1_frequency; 448 449 /* Current clocks */ 450 uint16_t current_gfxclk; 451 uint16_t current_socclk; 452 uint16_t current_uclk; 453 uint16_t current_vclk0; 454 uint16_t current_dclk0; 455 uint16_t current_vclk1; 456 uint16_t current_dclk1; 457 458 /* Throttle status */ 459 uint32_t throttle_status; 460 461 /* Fans */ 462 uint16_t current_fan_speed; 463 464 /* Link width/speed */ 465 uint16_t pcie_link_width; 466 uint16_t pcie_link_speed; // in 0.1 GT/s 467 468 uint16_t padding; 469 470 uint32_t gfx_activity_acc; 471 uint32_t mem_activity_acc; 472 473 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 474 }; 475 476 /* 477 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 478 * Use gpu_metrics_v2_1 or later instead. 479 */ 480 struct gpu_metrics_v2_0 { 481 struct metrics_table_header common_header; 482 483 /* Driver attached timestamp (in ns) */ 484 uint64_t system_clock_counter; 485 486 /* Temperature */ 487 uint16_t temperature_gfx; // gfx temperature on APUs 488 uint16_t temperature_soc; // soc temperature on APUs 489 uint16_t temperature_core[8]; // CPU core temperature on APUs 490 uint16_t temperature_l3[2]; 491 492 /* Utilization */ 493 uint16_t average_gfx_activity; 494 uint16_t average_mm_activity; // UVD or VCN 495 496 /* Power/Energy */ 497 uint16_t average_socket_power; // dGPU + APU power on A + A platform 498 uint16_t average_cpu_power; 499 uint16_t average_soc_power; 500 uint16_t average_gfx_power; 501 uint16_t average_core_power[8]; // CPU core power on APUs 502 503 /* Average clocks */ 504 uint16_t average_gfxclk_frequency; 505 uint16_t average_socclk_frequency; 506 uint16_t average_uclk_frequency; 507 uint16_t average_fclk_frequency; 508 uint16_t average_vclk_frequency; 509 uint16_t average_dclk_frequency; 510 511 /* Current clocks */ 512 uint16_t current_gfxclk; 513 uint16_t current_socclk; 514 uint16_t current_uclk; 515 uint16_t current_fclk; 516 uint16_t current_vclk; 517 uint16_t current_dclk; 518 uint16_t current_coreclk[8]; // CPU core clocks 519 uint16_t current_l3clk[2]; 520 521 /* Throttle status */ 522 uint32_t throttle_status; 523 524 /* Fans */ 525 uint16_t fan_pwm; 526 527 uint16_t padding; 528 }; 529 530 struct gpu_metrics_v2_1 { 531 struct metrics_table_header common_header; 532 533 /* Temperature */ 534 uint16_t temperature_gfx; // gfx temperature on APUs 535 uint16_t temperature_soc; // soc temperature on APUs 536 uint16_t temperature_core[8]; // CPU core temperature on APUs 537 uint16_t temperature_l3[2]; 538 539 /* Utilization */ 540 uint16_t average_gfx_activity; 541 uint16_t average_mm_activity; // UVD or VCN 542 543 /* Driver attached timestamp (in ns) */ 544 uint64_t system_clock_counter; 545 546 /* Power/Energy */ 547 uint16_t average_socket_power; // dGPU + APU power on A + A platform 548 uint16_t average_cpu_power; 549 uint16_t average_soc_power; 550 uint16_t average_gfx_power; 551 uint16_t average_core_power[8]; // CPU core power on APUs 552 553 /* Average clocks */ 554 uint16_t average_gfxclk_frequency; 555 uint16_t average_socclk_frequency; 556 uint16_t average_uclk_frequency; 557 uint16_t average_fclk_frequency; 558 uint16_t average_vclk_frequency; 559 uint16_t average_dclk_frequency; 560 561 /* Current clocks */ 562 uint16_t current_gfxclk; 563 uint16_t current_socclk; 564 uint16_t current_uclk; 565 uint16_t current_fclk; 566 uint16_t current_vclk; 567 uint16_t current_dclk; 568 uint16_t current_coreclk[8]; // CPU core clocks 569 uint16_t current_l3clk[2]; 570 571 /* Throttle status */ 572 uint32_t throttle_status; 573 574 /* Fans */ 575 uint16_t fan_pwm; 576 577 uint16_t padding[3]; 578 }; 579 580 #endif 581