1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __KGD_PP_INTERFACE_H__ 25 #define __KGD_PP_INTERFACE_H__ 26 27 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block; 29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block; 30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block; 31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block; 32 33 enum smu_temp_metric_type { 34 SMU_TEMP_METRIC_BASEBOARD, 35 SMU_TEMP_METRIC_GPUBOARD, 36 SMU_TEMP_METRIC_MAX, 37 }; 38 39 enum smu_event_type { 40 SMU_EVENT_RESET_COMPLETE = 0, 41 }; 42 43 struct amd_vce_state { 44 /* vce clocks */ 45 u32 evclk; 46 u32 ecclk; 47 /* gpu clocks */ 48 u32 sclk; 49 u32 mclk; 50 u8 clk_idx; 51 u8 pstate; 52 }; 53 54 55 enum amd_dpm_forced_level { 56 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 57 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 58 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 59 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 60 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 61 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 62 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 63 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 64 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 65 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200, 66 }; 67 68 enum amd_pm_state_type { 69 /* not used for dpm */ 70 POWER_STATE_TYPE_DEFAULT, 71 POWER_STATE_TYPE_POWERSAVE, 72 /* user selectable states */ 73 POWER_STATE_TYPE_BATTERY, 74 POWER_STATE_TYPE_BALANCED, 75 POWER_STATE_TYPE_PERFORMANCE, 76 /* internal states */ 77 POWER_STATE_TYPE_INTERNAL_UVD, 78 POWER_STATE_TYPE_INTERNAL_UVD_SD, 79 POWER_STATE_TYPE_INTERNAL_UVD_HD, 80 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 81 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 82 POWER_STATE_TYPE_INTERNAL_BOOT, 83 POWER_STATE_TYPE_INTERNAL_THERMAL, 84 POWER_STATE_TYPE_INTERNAL_ACPI, 85 POWER_STATE_TYPE_INTERNAL_ULV, 86 POWER_STATE_TYPE_INTERNAL_3DPERF, 87 }; 88 89 #define AMD_MAX_VCE_LEVELS 6 90 91 enum amd_vce_level { 92 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 93 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 94 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 95 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 96 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 97 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 98 }; 99 100 enum amd_fan_ctrl_mode { 101 AMD_FAN_CTRL_NONE = 0, 102 AMD_FAN_CTRL_MANUAL = 1, 103 AMD_FAN_CTRL_AUTO = 2, 104 }; 105 106 enum pp_clock_type { 107 PP_SCLK, 108 PP_MCLK, 109 PP_PCIE, 110 PP_SOCCLK, 111 PP_FCLK, 112 PP_DCEFCLK, 113 PP_VCLK, 114 PP_VCLK1, 115 PP_DCLK, 116 PP_DCLK1, 117 PP_ISPICLK, 118 PP_ISPXCLK, 119 OD_SCLK, 120 OD_MCLK, 121 OD_VDDC_CURVE, 122 OD_RANGE, 123 OD_VDDGFX_OFFSET, 124 OD_CCLK, 125 OD_FAN_CURVE, 126 OD_ACOUSTIC_LIMIT, 127 OD_ACOUSTIC_TARGET, 128 OD_FAN_TARGET_TEMPERATURE, 129 OD_FAN_MINIMUM_PWM, 130 OD_FAN_ZERO_RPM_ENABLE, 131 OD_FAN_ZERO_RPM_STOP_TEMP, 132 }; 133 134 enum amd_pp_sensors { 135 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 136 AMDGPU_PP_SENSOR_CPU_CLK, 137 AMDGPU_PP_SENSOR_VDDNB, 138 AMDGPU_PP_SENSOR_VDDGFX, 139 AMDGPU_PP_SENSOR_VDDBOARD, 140 AMDGPU_PP_SENSOR_UVD_VCLK, 141 AMDGPU_PP_SENSOR_UVD_DCLK, 142 AMDGPU_PP_SENSOR_VCE_ECCLK, 143 AMDGPU_PP_SENSOR_GPU_LOAD, 144 AMDGPU_PP_SENSOR_MEM_LOAD, 145 AMDGPU_PP_SENSOR_GFX_MCLK, 146 AMDGPU_PP_SENSOR_GPU_TEMP, 147 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 148 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 149 AMDGPU_PP_SENSOR_MEM_TEMP, 150 AMDGPU_PP_SENSOR_VCE_POWER, 151 AMDGPU_PP_SENSOR_UVD_POWER, 152 AMDGPU_PP_SENSOR_GPU_AVG_POWER, 153 AMDGPU_PP_SENSOR_GPU_INPUT_POWER, 154 AMDGPU_PP_SENSOR_SS_APU_SHARE, 155 AMDGPU_PP_SENSOR_SS_DGPU_SHARE, 156 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 157 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 158 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 159 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 160 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 161 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 162 AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK, 163 AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK, 164 AMDGPU_PP_SENSOR_VCN_LOAD, 165 AMDGPU_PP_SENSOR_NODEPOWERLIMIT, 166 AMDGPU_PP_SENSOR_NODEPOWER, 167 AMDGPU_PP_SENSOR_GPPTRESIDENCY, 168 AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT, 169 }; 170 171 enum amd_pp_task { 172 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 173 AMD_PP_TASK_ENABLE_USER_STATE, 174 AMD_PP_TASK_READJUST_POWER_STATE, 175 AMD_PP_TASK_COMPLETE_INIT, 176 AMD_PP_TASK_MAX 177 }; 178 179 enum PP_SMC_POWER_PROFILE { 180 PP_SMC_POWER_PROFILE_UNKNOWN = -1, 181 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 182 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 183 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 184 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 185 PP_SMC_POWER_PROFILE_VR = 0x4, 186 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 187 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 188 PP_SMC_POWER_PROFILE_WINDOW3D = 0x7, 189 PP_SMC_POWER_PROFILE_CAPPED = 0x8, 190 PP_SMC_POWER_PROFILE_UNCAPPED = 0x9, 191 PP_SMC_POWER_PROFILE_COUNT, 192 }; 193 194 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT]; 195 196 197 198 enum { 199 PP_GROUP_UNKNOWN = 0, 200 PP_GROUP_GFX = 1, 201 PP_GROUP_SYS, 202 PP_GROUP_MAX 203 }; 204 205 enum PP_OD_DPM_TABLE_COMMAND { 206 PP_OD_EDIT_SCLK_VDDC_TABLE, 207 PP_OD_EDIT_MCLK_VDDC_TABLE, 208 PP_OD_EDIT_CCLK_VDDC_TABLE, 209 PP_OD_EDIT_VDDC_CURVE, 210 PP_OD_RESTORE_DEFAULT_TABLE, 211 PP_OD_COMMIT_DPM_TABLE, 212 PP_OD_EDIT_VDDGFX_OFFSET, 213 PP_OD_EDIT_FAN_CURVE, 214 PP_OD_EDIT_ACOUSTIC_LIMIT, 215 PP_OD_EDIT_ACOUSTIC_TARGET, 216 PP_OD_EDIT_FAN_TARGET_TEMPERATURE, 217 PP_OD_EDIT_FAN_MINIMUM_PWM, 218 PP_OD_EDIT_FAN_ZERO_RPM_ENABLE, 219 PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP, 220 }; 221 222 struct pp_states_info { 223 uint32_t nums; 224 uint32_t states[16]; 225 }; 226 227 enum PP_HWMON_TEMP { 228 PP_TEMP_EDGE = 0, 229 PP_TEMP_JUNCTION, 230 PP_TEMP_MEM, 231 PP_TEMP_MAX 232 }; 233 234 enum pp_mp1_state { 235 PP_MP1_STATE_NONE, 236 PP_MP1_STATE_SHUTDOWN, 237 PP_MP1_STATE_UNLOAD, 238 PP_MP1_STATE_RESET, 239 PP_MP1_STATE_FLR, 240 }; 241 242 enum pp_df_cstate { 243 DF_CSTATE_DISALLOW = 0, 244 DF_CSTATE_ALLOW, 245 }; 246 247 /** 248 * DOC: amdgpu_pp_power 249 * 250 * APU power is managed to system-level requirements through the PPT 251 * (package power tracking) feature. PPT is intended to limit power to the 252 * requirements of the power source and could be dynamically updated to 253 * maximize APU performance within the system power budget. 254 * 255 * Two types of power measurement can be requested, where supported, with 256 * :c:type:`enum pp_power_type <pp_power_type>`. 257 */ 258 259 /** 260 * enum pp_power_limit_level - Used to query the power limits 261 * 262 * @PP_PWR_LIMIT_MIN: Minimum Power Limit 263 * @PP_PWR_LIMIT_CURRENT: Current Power Limit 264 * @PP_PWR_LIMIT_DEFAULT: Default Power Limit 265 * @PP_PWR_LIMIT_MAX: Maximum Power Limit 266 */ 267 enum pp_power_limit_level { 268 PP_PWR_LIMIT_MIN = -1, 269 PP_PWR_LIMIT_CURRENT, 270 PP_PWR_LIMIT_DEFAULT, 271 PP_PWR_LIMIT_MAX, 272 }; 273 274 /** 275 * enum pp_power_type - Used to specify the type of the requested power 276 * 277 * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant 278 * moving average of APU power (default ~5000 ms). 279 * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power, 280 * where supported. 281 */ 282 enum pp_power_type { 283 PP_PWR_TYPE_SUSTAINED, 284 PP_PWR_TYPE_FAST, 285 }; 286 287 enum pp_xgmi_plpd_mode { 288 XGMI_PLPD_NONE = -1, 289 XGMI_PLPD_DISALLOW, 290 XGMI_PLPD_DEFAULT, 291 XGMI_PLPD_OPTIMIZED, 292 XGMI_PLPD_COUNT, 293 }; 294 295 enum pp_pm_policy { 296 PP_PM_POLICY_NONE = -1, 297 PP_PM_POLICY_SOC_PSTATE = 0, 298 PP_PM_POLICY_XGMI_PLPD, 299 PP_PM_POLICY_NUM, 300 }; 301 302 enum pp_policy_soc_pstate { 303 SOC_PSTATE_DEFAULT = 0, 304 SOC_PSTATE_0, 305 SOC_PSTATE_1, 306 SOC_PSTATE_2, 307 SOC_PSTAT_COUNT, 308 }; 309 310 #define PP_POLICY_MAX_LEVELS 5 311 312 #define PP_GROUP_MASK 0xF0000000 313 #define PP_GROUP_SHIFT 28 314 315 #define PP_BLOCK_MASK 0x0FFFFF00 316 #define PP_BLOCK_SHIFT 8 317 318 #define PP_BLOCK_GFX_CG 0x01 319 #define PP_BLOCK_GFX_MG 0x02 320 #define PP_BLOCK_GFX_3D 0x04 321 #define PP_BLOCK_GFX_RLC 0x08 322 #define PP_BLOCK_GFX_CP 0x10 323 #define PP_BLOCK_SYS_BIF 0x01 324 #define PP_BLOCK_SYS_MC 0x02 325 #define PP_BLOCK_SYS_ROM 0x04 326 #define PP_BLOCK_SYS_DRM 0x08 327 #define PP_BLOCK_SYS_HDP 0x10 328 #define PP_BLOCK_SYS_SDMA 0x20 329 330 #define PP_STATE_MASK 0x0000000F 331 #define PP_STATE_SHIFT 0 332 #define PP_STATE_SUPPORT_MASK 0x000000F0 333 #define PP_STATE_SUPPORT_SHIFT 0 334 335 #define PP_STATE_CG 0x01 336 #define PP_STATE_LS 0x02 337 #define PP_STATE_DS 0x04 338 #define PP_STATE_SD 0x08 339 #define PP_STATE_SUPPORT_CG 0x10 340 #define PP_STATE_SUPPORT_LS 0x20 341 #define PP_STATE_SUPPORT_DS 0x40 342 #define PP_STATE_SUPPORT_SD 0x80 343 344 #define PP_CG_MSG_ID(group, block, support, state) \ 345 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 346 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 347 348 #define XGMI_MODE_PSTATE_D3 0 349 #define XGMI_MODE_PSTATE_D0 1 350 351 #define NUM_HBM_INSTANCES 4 352 #define NUM_XGMI_LINKS 8 353 #define MAX_GFX_CLKS 8 354 #define MAX_CLKS 4 355 #define NUM_VCN 4 356 #define NUM_JPEG_ENG 32 357 #define NUM_JPEG_ENG_V1 40 358 #define MAX_XCC 8 359 #define NUM_XCP 8 360 struct seq_file; 361 enum amd_pp_clock_type; 362 struct amd_pp_simple_clock_info; 363 struct amd_pp_display_configuration; 364 struct amd_pp_clock_info; 365 struct pp_display_clock_request; 366 struct pp_clock_levels_with_voltage; 367 struct pp_clock_levels_with_latency; 368 struct amd_pp_clocks; 369 struct pp_smu_wm_range_sets; 370 struct pp_smu_nv_clock_table; 371 struct dpm_clocks; 372 373 struct amdgpu_xcp_metrics { 374 /* Utilization Instantaneous (%) */ 375 uint32_t gfx_busy_inst[MAX_XCC]; 376 uint16_t jpeg_busy[NUM_JPEG_ENG]; 377 uint16_t vcn_busy[NUM_VCN]; 378 /* Utilization Accumulated (%) */ 379 uint64_t gfx_busy_acc[MAX_XCC]; 380 }; 381 382 struct amdgpu_xcp_metrics_v1_1 { 383 /* Utilization Instantaneous (%) */ 384 uint32_t gfx_busy_inst[MAX_XCC]; 385 uint16_t jpeg_busy[NUM_JPEG_ENG]; 386 uint16_t vcn_busy[NUM_VCN]; 387 /* Utilization Accumulated (%) */ 388 uint64_t gfx_busy_acc[MAX_XCC]; 389 /* Total App Clock Counter Accumulated */ 390 uint64_t gfx_below_host_limit_acc[MAX_XCC]; 391 }; 392 393 struct amdgpu_xcp_metrics_v1_2 { 394 /* Utilization Instantaneous (%) */ 395 uint32_t gfx_busy_inst[MAX_XCC]; 396 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 397 uint16_t vcn_busy[NUM_VCN]; 398 /* Utilization Accumulated (%) */ 399 uint64_t gfx_busy_acc[MAX_XCC]; 400 /* Total App Clock Counter Accumulated */ 401 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 402 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 403 uint64_t gfx_low_utilization_acc[MAX_XCC]; 404 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 405 }; 406 407 struct amd_pm_funcs { 408 /* export for dpm on ci and si */ 409 int (*pre_set_power_state)(void *handle); 410 int (*set_power_state)(void *handle); 411 void (*post_set_power_state)(void *handle); 412 void (*display_configuration_changed)(void *handle); 413 void (*print_power_state)(void *handle, void *ps); 414 bool (*vblank_too_short)(void *handle); 415 void (*enable_bapm)(void *handle, bool enable); 416 int (*check_state_equal)(void *handle, 417 void *cps, 418 void *rps, 419 bool *equal); 420 /* export for sysfs */ 421 int (*set_fan_control_mode)(void *handle, u32 mode); 422 int (*get_fan_control_mode)(void *handle, u32 *fan_mode); 423 int (*set_fan_speed_pwm)(void *handle, u32 speed); 424 int (*get_fan_speed_pwm)(void *handle, u32 *speed); 425 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 426 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 427 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset); 428 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 429 int (*get_sclk_od)(void *handle); 430 int (*set_sclk_od)(void *handle, uint32_t value); 431 int (*get_mclk_od)(void *handle); 432 int (*set_mclk_od)(void *handle, uint32_t value); 433 int (*read_sensor)(void *handle, int idx, void *value, int *size); 434 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit); 435 int (*set_apu_thermal_limit)(void *handle, uint32_t limit); 436 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 437 enum amd_pm_state_type (*get_current_power_state)(void *handle); 438 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 439 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 440 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 441 int (*get_pp_table)(void *handle, char **table); 442 int (*set_pp_table)(void *handle, const char *buf, size_t size); 443 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 444 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 445 int (*pause_power_profile)(void *handle, bool pause); 446 /* export to amdgpu */ 447 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 448 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 449 enum amd_pm_state_type *user_state); 450 int (*load_firmware)(void *handle); 451 int (*wait_for_fw_loading_complete)(void *handle); 452 int (*set_powergating_by_smu)(void *handle, 453 uint32_t block_type, 454 bool gate, 455 int inst); 456 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 457 int (*set_power_limit)(void *handle, uint32_t n); 458 int (*get_power_limit)(void *handle, uint32_t *limit, 459 enum pp_power_limit_level pp_limit_level, 460 enum pp_power_type power_type); 461 int (*get_power_profile_mode)(void *handle, char *buf); 462 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 463 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size); 464 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type, 465 long *input, uint32_t size); 466 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 467 int (*smu_i2c_bus_access)(void *handle, bool acquire); 468 int (*gfx_state_change_set)(void *handle, uint32_t state); 469 /* export to DC */ 470 u32 (*get_sclk)(void *handle, bool low); 471 u32 (*get_mclk)(void *handle, bool low); 472 int (*display_configuration_change)(void *handle, 473 const struct amd_pp_display_configuration *input); 474 int (*get_display_power_level)(void *handle, 475 struct amd_pp_simple_clock_info *output); 476 int (*get_current_clocks)(void *handle, 477 struct amd_pp_clock_info *clocks); 478 int (*get_clock_by_type)(void *handle, 479 enum amd_pp_clock_type type, 480 struct amd_pp_clocks *clocks); 481 int (*get_clock_by_type_with_latency)(void *handle, 482 enum amd_pp_clock_type type, 483 struct pp_clock_levels_with_latency *clocks); 484 int (*get_clock_by_type_with_voltage)(void *handle, 485 enum amd_pp_clock_type type, 486 struct pp_clock_levels_with_voltage *clocks); 487 int (*set_watermarks_for_clocks_ranges)(void *handle, 488 void *clock_ranges); 489 int (*display_clock_voltage_request)(void *handle, 490 struct pp_display_clock_request *clock); 491 int (*get_display_mode_validation_clocks)(void *handle, 492 struct amd_pp_simple_clock_info *clocks); 493 int (*notify_smu_enable_pwe)(void *handle); 494 int (*enable_mgpu_fan_boost)(void *handle); 495 int (*set_active_display_count)(void *handle, uint32_t count); 496 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 497 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 498 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 499 int (*get_asic_baco_capability)(void *handle); 500 int (*get_asic_baco_state)(void *handle, int *state); 501 int (*set_asic_baco_state)(void *handle, int state); 502 int (*get_ppfeature_status)(void *handle, char *buf); 503 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 504 int (*asic_reset_mode_2)(void *handle); 505 int (*asic_reset_enable_gfx_features)(void *handle); 506 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 507 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 508 ssize_t (*get_gpu_metrics)(void *handle, void **table); 509 ssize_t (*get_temp_metrics)(void *handle, enum smu_temp_metric_type type, void *table); 510 bool (*temp_metrics_is_supported)(void *handle, enum smu_temp_metric_type type); 511 ssize_t (*get_xcp_metrics)(void *handle, int xcp_id, void *table); 512 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size); 513 int (*set_watermarks_for_clock_ranges)(void *handle, 514 struct pp_smu_wm_range_sets *ranges); 515 int (*display_disable_memory_clock_switch)(void *handle, 516 bool disable_memory_clock_switch); 517 int (*get_max_sustainable_clocks_by_dc)(void *handle, 518 struct pp_smu_nv_clock_table *max_clocks); 519 int (*get_uclk_dpm_states)(void *handle, 520 unsigned int *clock_values_in_khz, 521 unsigned int *num_states); 522 int (*get_dpm_clock_table)(void *handle, 523 struct dpm_clocks *clock_table); 524 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size); 525 void (*pm_compute_clocks)(void *handle); 526 int (*notify_rlc_state)(void *handle, bool en); 527 }; 528 529 struct metrics_table_header { 530 uint16_t structure_size; 531 uint8_t format_revision; 532 uint8_t content_revision; 533 }; 534 535 /* 536 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned. 537 * Use gpu_metrics_v1_1 or later instead. 538 */ 539 struct gpu_metrics_v1_0 { 540 struct metrics_table_header common_header; 541 542 /* Driver attached timestamp (in ns) */ 543 uint64_t system_clock_counter; 544 545 /* Temperature */ 546 uint16_t temperature_edge; 547 uint16_t temperature_hotspot; 548 uint16_t temperature_mem; 549 uint16_t temperature_vrgfx; 550 uint16_t temperature_vrsoc; 551 uint16_t temperature_vrmem; 552 553 /* Utilization */ 554 uint16_t average_gfx_activity; 555 uint16_t average_umc_activity; // memory controller 556 uint16_t average_mm_activity; // UVD or VCN 557 558 /* Power/Energy */ 559 uint16_t average_socket_power; 560 uint32_t energy_accumulator; 561 562 /* Average clocks */ 563 uint16_t average_gfxclk_frequency; 564 uint16_t average_socclk_frequency; 565 uint16_t average_uclk_frequency; 566 uint16_t average_vclk0_frequency; 567 uint16_t average_dclk0_frequency; 568 uint16_t average_vclk1_frequency; 569 uint16_t average_dclk1_frequency; 570 571 /* Current clocks */ 572 uint16_t current_gfxclk; 573 uint16_t current_socclk; 574 uint16_t current_uclk; 575 uint16_t current_vclk0; 576 uint16_t current_dclk0; 577 uint16_t current_vclk1; 578 uint16_t current_dclk1; 579 580 /* Throttle status */ 581 uint32_t throttle_status; 582 583 /* Fans */ 584 uint16_t current_fan_speed; 585 586 /* Link width/speed */ 587 uint8_t pcie_link_width; 588 uint8_t pcie_link_speed; // in 0.1 GT/s 589 }; 590 591 struct gpu_metrics_v1_1 { 592 struct metrics_table_header common_header; 593 594 /* Temperature */ 595 uint16_t temperature_edge; 596 uint16_t temperature_hotspot; 597 uint16_t temperature_mem; 598 uint16_t temperature_vrgfx; 599 uint16_t temperature_vrsoc; 600 uint16_t temperature_vrmem; 601 602 /* Utilization */ 603 uint16_t average_gfx_activity; 604 uint16_t average_umc_activity; // memory controller 605 uint16_t average_mm_activity; // UVD or VCN 606 607 /* Power/Energy */ 608 uint16_t average_socket_power; 609 uint64_t energy_accumulator; 610 611 /* Driver attached timestamp (in ns) */ 612 uint64_t system_clock_counter; 613 614 /* Average clocks */ 615 uint16_t average_gfxclk_frequency; 616 uint16_t average_socclk_frequency; 617 uint16_t average_uclk_frequency; 618 uint16_t average_vclk0_frequency; 619 uint16_t average_dclk0_frequency; 620 uint16_t average_vclk1_frequency; 621 uint16_t average_dclk1_frequency; 622 623 /* Current clocks */ 624 uint16_t current_gfxclk; 625 uint16_t current_socclk; 626 uint16_t current_uclk; 627 uint16_t current_vclk0; 628 uint16_t current_dclk0; 629 uint16_t current_vclk1; 630 uint16_t current_dclk1; 631 632 /* Throttle status */ 633 uint32_t throttle_status; 634 635 /* Fans */ 636 uint16_t current_fan_speed; 637 638 /* Link width/speed */ 639 uint16_t pcie_link_width; 640 uint16_t pcie_link_speed; // in 0.1 GT/s 641 642 uint16_t padding; 643 644 uint32_t gfx_activity_acc; 645 uint32_t mem_activity_acc; 646 647 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 648 }; 649 650 struct gpu_metrics_v1_2 { 651 struct metrics_table_header common_header; 652 653 /* Temperature */ 654 uint16_t temperature_edge; 655 uint16_t temperature_hotspot; 656 uint16_t temperature_mem; 657 uint16_t temperature_vrgfx; 658 uint16_t temperature_vrsoc; 659 uint16_t temperature_vrmem; 660 661 /* Utilization */ 662 uint16_t average_gfx_activity; 663 uint16_t average_umc_activity; // memory controller 664 uint16_t average_mm_activity; // UVD or VCN 665 666 /* Power/Energy */ 667 uint16_t average_socket_power; 668 uint64_t energy_accumulator; 669 670 /* Driver attached timestamp (in ns) */ 671 uint64_t system_clock_counter; 672 673 /* Average clocks */ 674 uint16_t average_gfxclk_frequency; 675 uint16_t average_socclk_frequency; 676 uint16_t average_uclk_frequency; 677 uint16_t average_vclk0_frequency; 678 uint16_t average_dclk0_frequency; 679 uint16_t average_vclk1_frequency; 680 uint16_t average_dclk1_frequency; 681 682 /* Current clocks */ 683 uint16_t current_gfxclk; 684 uint16_t current_socclk; 685 uint16_t current_uclk; 686 uint16_t current_vclk0; 687 uint16_t current_dclk0; 688 uint16_t current_vclk1; 689 uint16_t current_dclk1; 690 691 /* Throttle status (ASIC dependent) */ 692 uint32_t throttle_status; 693 694 /* Fans */ 695 uint16_t current_fan_speed; 696 697 /* Link width/speed */ 698 uint16_t pcie_link_width; 699 uint16_t pcie_link_speed; // in 0.1 GT/s 700 701 uint16_t padding; 702 703 uint32_t gfx_activity_acc; 704 uint32_t mem_activity_acc; 705 706 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 707 708 /* PMFW attached timestamp (10ns resolution) */ 709 uint64_t firmware_timestamp; 710 }; 711 712 struct gpu_metrics_v1_3 { 713 struct metrics_table_header common_header; 714 715 /* Temperature */ 716 uint16_t temperature_edge; 717 uint16_t temperature_hotspot; 718 uint16_t temperature_mem; 719 uint16_t temperature_vrgfx; 720 uint16_t temperature_vrsoc; 721 uint16_t temperature_vrmem; 722 723 /* Utilization */ 724 uint16_t average_gfx_activity; 725 uint16_t average_umc_activity; // memory controller 726 uint16_t average_mm_activity; // UVD or VCN 727 728 /* Power/Energy */ 729 uint16_t average_socket_power; 730 uint64_t energy_accumulator; 731 732 /* Driver attached timestamp (in ns) */ 733 uint64_t system_clock_counter; 734 735 /* Average clocks */ 736 uint16_t average_gfxclk_frequency; 737 uint16_t average_socclk_frequency; 738 uint16_t average_uclk_frequency; 739 uint16_t average_vclk0_frequency; 740 uint16_t average_dclk0_frequency; 741 uint16_t average_vclk1_frequency; 742 uint16_t average_dclk1_frequency; 743 744 /* Current clocks */ 745 uint16_t current_gfxclk; 746 uint16_t current_socclk; 747 uint16_t current_uclk; 748 uint16_t current_vclk0; 749 uint16_t current_dclk0; 750 uint16_t current_vclk1; 751 uint16_t current_dclk1; 752 753 /* Throttle status */ 754 uint32_t throttle_status; 755 756 /* Fans */ 757 uint16_t current_fan_speed; 758 759 /* Link width/speed */ 760 uint16_t pcie_link_width; 761 uint16_t pcie_link_speed; // in 0.1 GT/s 762 763 uint16_t padding; 764 765 uint32_t gfx_activity_acc; 766 uint32_t mem_activity_acc; 767 768 uint16_t temperature_hbm[NUM_HBM_INSTANCES]; 769 770 /* PMFW attached timestamp (10ns resolution) */ 771 uint64_t firmware_timestamp; 772 773 /* Voltage (mV) */ 774 uint16_t voltage_soc; 775 uint16_t voltage_gfx; 776 uint16_t voltage_mem; 777 778 uint16_t padding1; 779 780 /* Throttle status (ASIC independent) */ 781 uint64_t indep_throttle_status; 782 }; 783 784 struct gpu_metrics_v1_4 { 785 struct metrics_table_header common_header; 786 787 /* Temperature (Celsius) */ 788 uint16_t temperature_hotspot; 789 uint16_t temperature_mem; 790 uint16_t temperature_vrsoc; 791 792 /* Power (Watts) */ 793 uint16_t curr_socket_power; 794 795 /* Utilization (%) */ 796 uint16_t average_gfx_activity; 797 uint16_t average_umc_activity; // memory controller 798 uint16_t vcn_activity[NUM_VCN]; 799 800 /* Energy (15.259uJ (2^-16) units) */ 801 uint64_t energy_accumulator; 802 803 /* Driver attached timestamp (in ns) */ 804 uint64_t system_clock_counter; 805 806 /* Throttle status */ 807 uint32_t throttle_status; 808 809 /* Clock Lock Status. Each bit corresponds to clock instance */ 810 uint32_t gfxclk_lock_status; 811 812 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 813 uint16_t pcie_link_width; 814 uint16_t pcie_link_speed; 815 816 /* XGMI bus width and bitrate (in Gbps) */ 817 uint16_t xgmi_link_width; 818 uint16_t xgmi_link_speed; 819 820 /* Utilization Accumulated (%) */ 821 uint32_t gfx_activity_acc; 822 uint32_t mem_activity_acc; 823 824 /*PCIE accumulated bandwidth (GB/sec) */ 825 uint64_t pcie_bandwidth_acc; 826 827 /*PCIE instantaneous bandwidth (GB/sec) */ 828 uint64_t pcie_bandwidth_inst; 829 830 /* PCIE L0 to recovery state transition accumulated count */ 831 uint64_t pcie_l0_to_recov_count_acc; 832 833 /* PCIE replay accumulated count */ 834 uint64_t pcie_replay_count_acc; 835 836 /* PCIE replay rollover accumulated count */ 837 uint64_t pcie_replay_rover_count_acc; 838 839 /* XGMI accumulated data transfer size(KiloBytes) */ 840 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 841 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 842 843 /* PMFW attached timestamp (10ns resolution) */ 844 uint64_t firmware_timestamp; 845 846 /* Current clocks (Mhz) */ 847 uint16_t current_gfxclk[MAX_GFX_CLKS]; 848 uint16_t current_socclk[MAX_CLKS]; 849 uint16_t current_vclk0[MAX_CLKS]; 850 uint16_t current_dclk0[MAX_CLKS]; 851 uint16_t current_uclk; 852 853 uint16_t padding; 854 }; 855 856 struct gpu_metrics_v1_5 { 857 struct metrics_table_header common_header; 858 859 /* Temperature (Celsius) */ 860 uint16_t temperature_hotspot; 861 uint16_t temperature_mem; 862 uint16_t temperature_vrsoc; 863 864 /* Power (Watts) */ 865 uint16_t curr_socket_power; 866 867 /* Utilization (%) */ 868 uint16_t average_gfx_activity; 869 uint16_t average_umc_activity; // memory controller 870 uint16_t vcn_activity[NUM_VCN]; 871 uint16_t jpeg_activity[NUM_JPEG_ENG]; 872 873 /* Energy (15.259uJ (2^-16) units) */ 874 uint64_t energy_accumulator; 875 876 /* Driver attached timestamp (in ns) */ 877 uint64_t system_clock_counter; 878 879 /* Throttle status */ 880 uint32_t throttle_status; 881 882 /* Clock Lock Status. Each bit corresponds to clock instance */ 883 uint32_t gfxclk_lock_status; 884 885 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 886 uint16_t pcie_link_width; 887 uint16_t pcie_link_speed; 888 889 /* XGMI bus width and bitrate (in Gbps) */ 890 uint16_t xgmi_link_width; 891 uint16_t xgmi_link_speed; 892 893 /* Utilization Accumulated (%) */ 894 uint32_t gfx_activity_acc; 895 uint32_t mem_activity_acc; 896 897 /*PCIE accumulated bandwidth (GB/sec) */ 898 uint64_t pcie_bandwidth_acc; 899 900 /*PCIE instantaneous bandwidth (GB/sec) */ 901 uint64_t pcie_bandwidth_inst; 902 903 /* PCIE L0 to recovery state transition accumulated count */ 904 uint64_t pcie_l0_to_recov_count_acc; 905 906 /* PCIE replay accumulated count */ 907 uint64_t pcie_replay_count_acc; 908 909 /* PCIE replay rollover accumulated count */ 910 uint64_t pcie_replay_rover_count_acc; 911 912 /* PCIE NAK sent accumulated count */ 913 uint32_t pcie_nak_sent_count_acc; 914 915 /* PCIE NAK received accumulated count */ 916 uint32_t pcie_nak_rcvd_count_acc; 917 918 /* XGMI accumulated data transfer size(KiloBytes) */ 919 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 920 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 921 922 /* PMFW attached timestamp (10ns resolution) */ 923 uint64_t firmware_timestamp; 924 925 /* Current clocks (Mhz) */ 926 uint16_t current_gfxclk[MAX_GFX_CLKS]; 927 uint16_t current_socclk[MAX_CLKS]; 928 uint16_t current_vclk0[MAX_CLKS]; 929 uint16_t current_dclk0[MAX_CLKS]; 930 uint16_t current_uclk; 931 932 uint16_t padding; 933 }; 934 935 struct gpu_metrics_v1_6 { 936 struct metrics_table_header common_header; 937 938 /* Temperature (Celsius) */ 939 uint16_t temperature_hotspot; 940 uint16_t temperature_mem; 941 uint16_t temperature_vrsoc; 942 943 /* Power (Watts) */ 944 uint16_t curr_socket_power; 945 946 /* Utilization (%) */ 947 uint16_t average_gfx_activity; 948 uint16_t average_umc_activity; // memory controller 949 950 /* Energy (15.259uJ (2^-16) units) */ 951 uint64_t energy_accumulator; 952 953 /* Driver attached timestamp (in ns) */ 954 uint64_t system_clock_counter; 955 956 /* Accumulation cycle counter */ 957 uint32_t accumulation_counter; 958 959 /* Accumulated throttler residencies */ 960 uint32_t prochot_residency_acc; 961 uint32_t ppt_residency_acc; 962 uint32_t socket_thm_residency_acc; 963 uint32_t vr_thm_residency_acc; 964 uint32_t hbm_thm_residency_acc; 965 966 /* Clock Lock Status. Each bit corresponds to clock instance */ 967 uint32_t gfxclk_lock_status; 968 969 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 970 uint16_t pcie_link_width; 971 uint16_t pcie_link_speed; 972 973 /* XGMI bus width and bitrate (in Gbps) */ 974 uint16_t xgmi_link_width; 975 uint16_t xgmi_link_speed; 976 977 /* Utilization Accumulated (%) */ 978 uint32_t gfx_activity_acc; 979 uint32_t mem_activity_acc; 980 981 /*PCIE accumulated bandwidth (GB/sec) */ 982 uint64_t pcie_bandwidth_acc; 983 984 /*PCIE instantaneous bandwidth (GB/sec) */ 985 uint64_t pcie_bandwidth_inst; 986 987 /* PCIE L0 to recovery state transition accumulated count */ 988 uint64_t pcie_l0_to_recov_count_acc; 989 990 /* PCIE replay accumulated count */ 991 uint64_t pcie_replay_count_acc; 992 993 /* PCIE replay rollover accumulated count */ 994 uint64_t pcie_replay_rover_count_acc; 995 996 /* PCIE NAK sent accumulated count */ 997 uint32_t pcie_nak_sent_count_acc; 998 999 /* PCIE NAK received accumulated count */ 1000 uint32_t pcie_nak_rcvd_count_acc; 1001 1002 /* XGMI accumulated data transfer size(KiloBytes) */ 1003 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1004 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1005 1006 /* PMFW attached timestamp (10ns resolution) */ 1007 uint64_t firmware_timestamp; 1008 1009 /* Current clocks (Mhz) */ 1010 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1011 uint16_t current_socclk[MAX_CLKS]; 1012 uint16_t current_vclk0[MAX_CLKS]; 1013 uint16_t current_dclk0[MAX_CLKS]; 1014 uint16_t current_uclk; 1015 1016 /* Number of current partition */ 1017 uint16_t num_partition; 1018 1019 /* XCP metrics stats */ 1020 struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; 1021 1022 /* PCIE other end recovery counter */ 1023 uint32_t pcie_lc_perf_other_end_recovery; 1024 }; 1025 1026 struct gpu_metrics_v1_7 { 1027 struct metrics_table_header common_header; 1028 1029 /* Temperature (Celsius) */ 1030 uint16_t temperature_hotspot; 1031 uint16_t temperature_mem; 1032 uint16_t temperature_vrsoc; 1033 1034 /* Power (Watts) */ 1035 uint16_t curr_socket_power; 1036 1037 /* Utilization (%) */ 1038 uint16_t average_gfx_activity; 1039 uint16_t average_umc_activity; // memory controller 1040 1041 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1042 uint64_t mem_max_bandwidth; 1043 1044 /* Energy (15.259uJ (2^-16) units) */ 1045 uint64_t energy_accumulator; 1046 1047 /* Driver attached timestamp (in ns) */ 1048 uint64_t system_clock_counter; 1049 1050 /* Accumulation cycle counter */ 1051 uint32_t accumulation_counter; 1052 1053 /* Accumulated throttler residencies */ 1054 uint32_t prochot_residency_acc; 1055 uint32_t ppt_residency_acc; 1056 uint32_t socket_thm_residency_acc; 1057 uint32_t vr_thm_residency_acc; 1058 uint32_t hbm_thm_residency_acc; 1059 1060 /* Clock Lock Status. Each bit corresponds to clock instance */ 1061 uint32_t gfxclk_lock_status; 1062 1063 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1064 uint16_t pcie_link_width; 1065 uint16_t pcie_link_speed; 1066 1067 /* XGMI bus width and bitrate (in Gbps) */ 1068 uint16_t xgmi_link_width; 1069 uint16_t xgmi_link_speed; 1070 1071 /* Utilization Accumulated (%) */ 1072 uint32_t gfx_activity_acc; 1073 uint32_t mem_activity_acc; 1074 1075 /*PCIE accumulated bandwidth (GB/sec) */ 1076 uint64_t pcie_bandwidth_acc; 1077 1078 /*PCIE instantaneous bandwidth (GB/sec) */ 1079 uint64_t pcie_bandwidth_inst; 1080 1081 /* PCIE L0 to recovery state transition accumulated count */ 1082 uint64_t pcie_l0_to_recov_count_acc; 1083 1084 /* PCIE replay accumulated count */ 1085 uint64_t pcie_replay_count_acc; 1086 1087 /* PCIE replay rollover accumulated count */ 1088 uint64_t pcie_replay_rover_count_acc; 1089 1090 /* PCIE NAK sent accumulated count */ 1091 uint32_t pcie_nak_sent_count_acc; 1092 1093 /* PCIE NAK received accumulated count */ 1094 uint32_t pcie_nak_rcvd_count_acc; 1095 1096 /* XGMI accumulated data transfer size(KiloBytes) */ 1097 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1098 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1099 1100 /* XGMI link status(active/inactive) */ 1101 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1102 1103 uint16_t padding; 1104 1105 /* PMFW attached timestamp (10ns resolution) */ 1106 uint64_t firmware_timestamp; 1107 1108 /* Current clocks (Mhz) */ 1109 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1110 uint16_t current_socclk[MAX_CLKS]; 1111 uint16_t current_vclk0[MAX_CLKS]; 1112 uint16_t current_dclk0[MAX_CLKS]; 1113 uint16_t current_uclk; 1114 1115 /* Number of current partition */ 1116 uint16_t num_partition; 1117 1118 /* XCP metrics stats */ 1119 struct amdgpu_xcp_metrics_v1_1 xcp_stats[NUM_XCP]; 1120 1121 /* PCIE other end recovery counter */ 1122 uint32_t pcie_lc_perf_other_end_recovery; 1123 }; 1124 1125 struct gpu_metrics_v1_8 { 1126 struct metrics_table_header common_header; 1127 1128 /* Temperature (Celsius) */ 1129 uint16_t temperature_hotspot; 1130 uint16_t temperature_mem; 1131 uint16_t temperature_vrsoc; 1132 1133 /* Power (Watts) */ 1134 uint16_t curr_socket_power; 1135 1136 /* Utilization (%) */ 1137 uint16_t average_gfx_activity; 1138 uint16_t average_umc_activity; // memory controller 1139 1140 /* VRAM max bandwidthi (in GB/sec) at max memory clock */ 1141 uint64_t mem_max_bandwidth; 1142 1143 /* Energy (15.259uJ (2^-16) units) */ 1144 uint64_t energy_accumulator; 1145 1146 /* Driver attached timestamp (in ns) */ 1147 uint64_t system_clock_counter; 1148 1149 /* Accumulation cycle counter */ 1150 uint32_t accumulation_counter; 1151 1152 /* Accumulated throttler residencies */ 1153 uint32_t prochot_residency_acc; 1154 uint32_t ppt_residency_acc; 1155 uint32_t socket_thm_residency_acc; 1156 uint32_t vr_thm_residency_acc; 1157 uint32_t hbm_thm_residency_acc; 1158 1159 /* Clock Lock Status. Each bit corresponds to clock instance */ 1160 uint32_t gfxclk_lock_status; 1161 1162 /* Link width (number of lanes) and speed (in 0.1 GT/s) */ 1163 uint16_t pcie_link_width; 1164 uint16_t pcie_link_speed; 1165 1166 /* XGMI bus width and bitrate (in Gbps) */ 1167 uint16_t xgmi_link_width; 1168 uint16_t xgmi_link_speed; 1169 1170 /* Utilization Accumulated (%) */ 1171 uint32_t gfx_activity_acc; 1172 uint32_t mem_activity_acc; 1173 1174 /*PCIE accumulated bandwidth (GB/sec) */ 1175 uint64_t pcie_bandwidth_acc; 1176 1177 /*PCIE instantaneous bandwidth (GB/sec) */ 1178 uint64_t pcie_bandwidth_inst; 1179 1180 /* PCIE L0 to recovery state transition accumulated count */ 1181 uint64_t pcie_l0_to_recov_count_acc; 1182 1183 /* PCIE replay accumulated count */ 1184 uint64_t pcie_replay_count_acc; 1185 1186 /* PCIE replay rollover accumulated count */ 1187 uint64_t pcie_replay_rover_count_acc; 1188 1189 /* PCIE NAK sent accumulated count */ 1190 uint32_t pcie_nak_sent_count_acc; 1191 1192 /* PCIE NAK received accumulated count */ 1193 uint32_t pcie_nak_rcvd_count_acc; 1194 1195 /* XGMI accumulated data transfer size(KiloBytes) */ 1196 uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; 1197 uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; 1198 1199 /* XGMI link status(active/inactive) */ 1200 uint16_t xgmi_link_status[NUM_XGMI_LINKS]; 1201 1202 uint16_t padding; 1203 1204 /* PMFW attached timestamp (10ns resolution) */ 1205 uint64_t firmware_timestamp; 1206 1207 /* Current clocks (Mhz) */ 1208 uint16_t current_gfxclk[MAX_GFX_CLKS]; 1209 uint16_t current_socclk[MAX_CLKS]; 1210 uint16_t current_vclk0[MAX_CLKS]; 1211 uint16_t current_dclk0[MAX_CLKS]; 1212 uint16_t current_uclk; 1213 1214 /* Number of current partition */ 1215 uint16_t num_partition; 1216 1217 /* XCP metrics stats */ 1218 struct amdgpu_xcp_metrics_v1_2 xcp_stats[NUM_XCP]; 1219 1220 /* PCIE other end recovery counter */ 1221 uint32_t pcie_lc_perf_other_end_recovery; 1222 }; 1223 1224 /* 1225 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. 1226 * Use gpu_metrics_v2_1 or later instead. 1227 */ 1228 struct gpu_metrics_v2_0 { 1229 struct metrics_table_header common_header; 1230 1231 /* Driver attached timestamp (in ns) */ 1232 uint64_t system_clock_counter; 1233 1234 /* Temperature */ 1235 uint16_t temperature_gfx; // gfx temperature on APUs 1236 uint16_t temperature_soc; // soc temperature on APUs 1237 uint16_t temperature_core[8]; // CPU core temperature on APUs 1238 uint16_t temperature_l3[2]; 1239 1240 /* Utilization */ 1241 uint16_t average_gfx_activity; 1242 uint16_t average_mm_activity; // UVD or VCN 1243 1244 /* Power/Energy */ 1245 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1246 uint16_t average_cpu_power; 1247 uint16_t average_soc_power; 1248 uint16_t average_gfx_power; 1249 uint16_t average_core_power[8]; // CPU core power on APUs 1250 1251 /* Average clocks */ 1252 uint16_t average_gfxclk_frequency; 1253 uint16_t average_socclk_frequency; 1254 uint16_t average_uclk_frequency; 1255 uint16_t average_fclk_frequency; 1256 uint16_t average_vclk_frequency; 1257 uint16_t average_dclk_frequency; 1258 1259 /* Current clocks */ 1260 uint16_t current_gfxclk; 1261 uint16_t current_socclk; 1262 uint16_t current_uclk; 1263 uint16_t current_fclk; 1264 uint16_t current_vclk; 1265 uint16_t current_dclk; 1266 uint16_t current_coreclk[8]; // CPU core clocks 1267 uint16_t current_l3clk[2]; 1268 1269 /* Throttle status */ 1270 uint32_t throttle_status; 1271 1272 /* Fans */ 1273 uint16_t fan_pwm; 1274 1275 uint16_t padding; 1276 }; 1277 1278 struct gpu_metrics_v2_1 { 1279 struct metrics_table_header common_header; 1280 1281 /* Temperature */ 1282 uint16_t temperature_gfx; // gfx temperature on APUs 1283 uint16_t temperature_soc; // soc temperature on APUs 1284 uint16_t temperature_core[8]; // CPU core temperature on APUs 1285 uint16_t temperature_l3[2]; 1286 1287 /* Utilization */ 1288 uint16_t average_gfx_activity; 1289 uint16_t average_mm_activity; // UVD or VCN 1290 1291 /* Driver attached timestamp (in ns) */ 1292 uint64_t system_clock_counter; 1293 1294 /* Power/Energy */ 1295 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1296 uint16_t average_cpu_power; 1297 uint16_t average_soc_power; 1298 uint16_t average_gfx_power; 1299 uint16_t average_core_power[8]; // CPU core power on APUs 1300 1301 /* Average clocks */ 1302 uint16_t average_gfxclk_frequency; 1303 uint16_t average_socclk_frequency; 1304 uint16_t average_uclk_frequency; 1305 uint16_t average_fclk_frequency; 1306 uint16_t average_vclk_frequency; 1307 uint16_t average_dclk_frequency; 1308 1309 /* Current clocks */ 1310 uint16_t current_gfxclk; 1311 uint16_t current_socclk; 1312 uint16_t current_uclk; 1313 uint16_t current_fclk; 1314 uint16_t current_vclk; 1315 uint16_t current_dclk; 1316 uint16_t current_coreclk[8]; // CPU core clocks 1317 uint16_t current_l3clk[2]; 1318 1319 /* Throttle status */ 1320 uint32_t throttle_status; 1321 1322 /* Fans */ 1323 uint16_t fan_pwm; 1324 1325 uint16_t padding[3]; 1326 }; 1327 1328 struct gpu_metrics_v2_2 { 1329 struct metrics_table_header common_header; 1330 1331 /* Temperature */ 1332 uint16_t temperature_gfx; // gfx temperature on APUs 1333 uint16_t temperature_soc; // soc temperature on APUs 1334 uint16_t temperature_core[8]; // CPU core temperature on APUs 1335 uint16_t temperature_l3[2]; 1336 1337 /* Utilization */ 1338 uint16_t average_gfx_activity; 1339 uint16_t average_mm_activity; // UVD or VCN 1340 1341 /* Driver attached timestamp (in ns) */ 1342 uint64_t system_clock_counter; 1343 1344 /* Power/Energy */ 1345 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1346 uint16_t average_cpu_power; 1347 uint16_t average_soc_power; 1348 uint16_t average_gfx_power; 1349 uint16_t average_core_power[8]; // CPU core power on APUs 1350 1351 /* Average clocks */ 1352 uint16_t average_gfxclk_frequency; 1353 uint16_t average_socclk_frequency; 1354 uint16_t average_uclk_frequency; 1355 uint16_t average_fclk_frequency; 1356 uint16_t average_vclk_frequency; 1357 uint16_t average_dclk_frequency; 1358 1359 /* Current clocks */ 1360 uint16_t current_gfxclk; 1361 uint16_t current_socclk; 1362 uint16_t current_uclk; 1363 uint16_t current_fclk; 1364 uint16_t current_vclk; 1365 uint16_t current_dclk; 1366 uint16_t current_coreclk[8]; // CPU core clocks 1367 uint16_t current_l3clk[2]; 1368 1369 /* Throttle status (ASIC dependent) */ 1370 uint32_t throttle_status; 1371 1372 /* Fans */ 1373 uint16_t fan_pwm; 1374 1375 uint16_t padding[3]; 1376 1377 /* Throttle status (ASIC independent) */ 1378 uint64_t indep_throttle_status; 1379 }; 1380 1381 struct gpu_metrics_v2_3 { 1382 struct metrics_table_header common_header; 1383 1384 /* Temperature */ 1385 uint16_t temperature_gfx; // gfx temperature on APUs 1386 uint16_t temperature_soc; // soc temperature on APUs 1387 uint16_t temperature_core[8]; // CPU core temperature on APUs 1388 uint16_t temperature_l3[2]; 1389 1390 /* Utilization */ 1391 uint16_t average_gfx_activity; 1392 uint16_t average_mm_activity; // UVD or VCN 1393 1394 /* Driver attached timestamp (in ns) */ 1395 uint64_t system_clock_counter; 1396 1397 /* Power/Energy */ 1398 uint16_t average_socket_power; // dGPU + APU power on A + A platform 1399 uint16_t average_cpu_power; 1400 uint16_t average_soc_power; 1401 uint16_t average_gfx_power; 1402 uint16_t average_core_power[8]; // CPU core power on APUs 1403 1404 /* Average clocks */ 1405 uint16_t average_gfxclk_frequency; 1406 uint16_t average_socclk_frequency; 1407 uint16_t average_uclk_frequency; 1408 uint16_t average_fclk_frequency; 1409 uint16_t average_vclk_frequency; 1410 uint16_t average_dclk_frequency; 1411 1412 /* Current clocks */ 1413 uint16_t current_gfxclk; 1414 uint16_t current_socclk; 1415 uint16_t current_uclk; 1416 uint16_t current_fclk; 1417 uint16_t current_vclk; 1418 uint16_t current_dclk; 1419 uint16_t current_coreclk[8]; // CPU core clocks 1420 uint16_t current_l3clk[2]; 1421 1422 /* Throttle status (ASIC dependent) */ 1423 uint32_t throttle_status; 1424 1425 /* Fans */ 1426 uint16_t fan_pwm; 1427 1428 uint16_t padding[3]; 1429 1430 /* Throttle status (ASIC independent) */ 1431 uint64_t indep_throttle_status; 1432 1433 /* Average Temperature */ 1434 uint16_t average_temperature_gfx; // average gfx temperature on APUs 1435 uint16_t average_temperature_soc; // average soc temperature on APUs 1436 uint16_t average_temperature_core[8]; // average CPU core temperature on APUs 1437 uint16_t average_temperature_l3[2]; 1438 }; 1439 1440 struct gpu_metrics_v2_4 { 1441 struct metrics_table_header common_header; 1442 1443 /* Temperature (unit: centi-Celsius) */ 1444 uint16_t temperature_gfx; 1445 uint16_t temperature_soc; 1446 uint16_t temperature_core[8]; 1447 uint16_t temperature_l3[2]; 1448 1449 /* Utilization (unit: centi) */ 1450 uint16_t average_gfx_activity; 1451 uint16_t average_mm_activity; 1452 1453 /* Driver attached timestamp (in ns) */ 1454 uint64_t system_clock_counter; 1455 1456 /* Power/Energy (unit: mW) */ 1457 uint16_t average_socket_power; 1458 uint16_t average_cpu_power; 1459 uint16_t average_soc_power; 1460 uint16_t average_gfx_power; 1461 uint16_t average_core_power[8]; 1462 1463 /* Average clocks (unit: MHz) */ 1464 uint16_t average_gfxclk_frequency; 1465 uint16_t average_socclk_frequency; 1466 uint16_t average_uclk_frequency; 1467 uint16_t average_fclk_frequency; 1468 uint16_t average_vclk_frequency; 1469 uint16_t average_dclk_frequency; 1470 1471 /* Current clocks (unit: MHz) */ 1472 uint16_t current_gfxclk; 1473 uint16_t current_socclk; 1474 uint16_t current_uclk; 1475 uint16_t current_fclk; 1476 uint16_t current_vclk; 1477 uint16_t current_dclk; 1478 uint16_t current_coreclk[8]; 1479 uint16_t current_l3clk[2]; 1480 1481 /* Throttle status (ASIC dependent) */ 1482 uint32_t throttle_status; 1483 1484 /* Fans */ 1485 uint16_t fan_pwm; 1486 1487 uint16_t padding[3]; 1488 1489 /* Throttle status (ASIC independent) */ 1490 uint64_t indep_throttle_status; 1491 1492 /* Average Temperature (unit: centi-Celsius) */ 1493 uint16_t average_temperature_gfx; 1494 uint16_t average_temperature_soc; 1495 uint16_t average_temperature_core[8]; 1496 uint16_t average_temperature_l3[2]; 1497 1498 /* Power/Voltage (unit: mV) */ 1499 uint16_t average_cpu_voltage; 1500 uint16_t average_soc_voltage; 1501 uint16_t average_gfx_voltage; 1502 1503 /* Power/Current (unit: mA) */ 1504 uint16_t average_cpu_current; 1505 uint16_t average_soc_current; 1506 uint16_t average_gfx_current; 1507 }; 1508 1509 struct gpu_metrics_v3_0 { 1510 struct metrics_table_header common_header; 1511 1512 /* Temperature */ 1513 /* gfx temperature on APUs */ 1514 uint16_t temperature_gfx; 1515 /* soc temperature on APUs */ 1516 uint16_t temperature_soc; 1517 /* CPU core temperature on APUs */ 1518 uint16_t temperature_core[16]; 1519 /* skin temperature on APUs */ 1520 uint16_t temperature_skin; 1521 1522 /* Utilization */ 1523 /* time filtered GFX busy % [0-100] */ 1524 uint16_t average_gfx_activity; 1525 /* time filtered VCN busy % [0-100] */ 1526 uint16_t average_vcn_activity; 1527 /* time filtered IPU per-column busy % [0-100] */ 1528 uint16_t average_ipu_activity[8]; 1529 /* time filtered per-core C0 residency % [0-100]*/ 1530 uint16_t average_core_c0_activity[16]; 1531 /* time filtered DRAM read bandwidth [MB/sec] */ 1532 uint16_t average_dram_reads; 1533 /* time filtered DRAM write bandwidth [MB/sec] */ 1534 uint16_t average_dram_writes; 1535 /* time filtered IPU read bandwidth [MB/sec] */ 1536 uint16_t average_ipu_reads; 1537 /* time filtered IPU write bandwidth [MB/sec] */ 1538 uint16_t average_ipu_writes; 1539 1540 /* Driver attached timestamp (in ns) */ 1541 uint64_t system_clock_counter; 1542 1543 /* Power/Energy */ 1544 /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */ 1545 uint32_t average_socket_power; 1546 /* time filtered IPU power [mW] */ 1547 uint16_t average_ipu_power; 1548 /* time filtered APU power [mW] */ 1549 uint32_t average_apu_power; 1550 /* time filtered GFX power [mW] */ 1551 uint32_t average_gfx_power; 1552 /* time filtered dGPU power [mW] */ 1553 uint32_t average_dgpu_power; 1554 /* time filtered sum of core power across all cores in the socket [mW] */ 1555 uint32_t average_all_core_power; 1556 /* calculated core power [mW] */ 1557 uint16_t average_core_power[16]; 1558 /* time filtered total system power [mW] */ 1559 uint16_t average_sys_power; 1560 /* maximum IRM defined STAPM power limit [mW] */ 1561 uint16_t stapm_power_limit; 1562 /* time filtered STAPM power limit [mW] */ 1563 uint16_t current_stapm_power_limit; 1564 1565 /* time filtered clocks [MHz] */ 1566 uint16_t average_gfxclk_frequency; 1567 uint16_t average_socclk_frequency; 1568 uint16_t average_vpeclk_frequency; 1569 uint16_t average_ipuclk_frequency; 1570 uint16_t average_fclk_frequency; 1571 uint16_t average_vclk_frequency; 1572 uint16_t average_uclk_frequency; 1573 uint16_t average_mpipu_frequency; 1574 1575 /* Current clocks */ 1576 /* target core frequency [MHz] */ 1577 uint16_t current_coreclk[16]; 1578 /* CCLK frequency limit enforced on classic cores [MHz] */ 1579 uint16_t current_core_maxfreq; 1580 /* GFXCLK frequency limit enforced on GFX [MHz] */ 1581 uint16_t current_gfx_maxfreq; 1582 1583 /* Throttle Residency (ASIC dependent) */ 1584 uint32_t throttle_residency_prochot; 1585 uint32_t throttle_residency_spl; 1586 uint32_t throttle_residency_fppt; 1587 uint32_t throttle_residency_sppt; 1588 uint32_t throttle_residency_thm_core; 1589 uint32_t throttle_residency_thm_gfx; 1590 uint32_t throttle_residency_thm_soc; 1591 1592 /* Metrics table alpha filter time constant [us] */ 1593 uint32_t time_filter_alphavalue; 1594 }; 1595 1596 struct amdgpu_pmmetrics_header { 1597 uint16_t structure_size; 1598 uint16_t pad; 1599 uint32_t mp1_ip_discovery_version; 1600 uint32_t pmfw_version; 1601 uint32_t pmmetrics_version; 1602 }; 1603 1604 struct amdgpu_pm_metrics { 1605 struct amdgpu_pmmetrics_header common_header; 1606 1607 uint8_t data[]; 1608 }; 1609 1610 enum amdgpu_vr_temp { 1611 AMDGPU_VDDCR_VDD0_TEMP, 1612 AMDGPU_VDDCR_VDD1_TEMP, 1613 AMDGPU_VDDCR_VDD2_TEMP, 1614 AMDGPU_VDDCR_VDD3_TEMP, 1615 AMDGPU_VDDCR_SOC_A_TEMP, 1616 AMDGPU_VDDCR_SOC_C_TEMP, 1617 AMDGPU_VDDCR_SOCIO_A_TEMP, 1618 AMDGPU_VDDCR_SOCIO_C_TEMP, 1619 AMDGPU_VDD_085_HBM_TEMP, 1620 AMDGPU_VDDCR_11_HBM_B_TEMP, 1621 AMDGPU_VDDCR_11_HBM_D_TEMP, 1622 AMDGPU_VDD_USR_TEMP, 1623 AMDGPU_VDDIO_11_E32_TEMP, 1624 AMDGPU_VR_MAX_TEMP_ENTRIES, 1625 }; 1626 1627 enum amdgpu_system_temp { 1628 AMDGPU_UBB_FPGA_TEMP, 1629 AMDGPU_UBB_FRONT_TEMP, 1630 AMDGPU_UBB_BACK_TEMP, 1631 AMDGPU_UBB_OAM7_TEMP, 1632 AMDGPU_UBB_IBC_TEMP, 1633 AMDGPU_UBB_UFPGA_TEMP, 1634 AMDGPU_UBB_OAM1_TEMP, 1635 AMDGPU_OAM_0_1_HSC_TEMP, 1636 AMDGPU_OAM_2_3_HSC_TEMP, 1637 AMDGPU_OAM_4_5_HSC_TEMP, 1638 AMDGPU_OAM_6_7_HSC_TEMP, 1639 AMDGPU_UBB_FPGA_0V72_VR_TEMP, 1640 AMDGPU_UBB_FPGA_3V3_VR_TEMP, 1641 AMDGPU_RETIMER_0_1_2_3_1V2_VR_TEMP, 1642 AMDGPU_RETIMER_4_5_6_7_1V2_VR_TEMP, 1643 AMDGPU_RETIMER_0_1_0V9_VR_TEMP, 1644 AMDGPU_RETIMER_4_5_0V9_VR_TEMP, 1645 AMDGPU_RETIMER_2_3_0V9_VR_TEMP, 1646 AMDGPU_RETIMER_6_7_0V9_VR_TEMP, 1647 AMDGPU_OAM_0_1_2_3_3V3_VR_TEMP, 1648 AMDGPU_OAM_4_5_6_7_3V3_VR_TEMP, 1649 AMDGPU_IBC_HSC_TEMP, 1650 AMDGPU_IBC_TEMP, 1651 AMDGPU_SYSTEM_MAX_TEMP_ENTRIES = 32, 1652 }; 1653 1654 enum amdgpu_node_temp { 1655 AMDGPU_RETIMER_X_TEMP, 1656 AMDGPU_OAM_X_IBC_TEMP, 1657 AMDGPU_OAM_X_IBC_2_TEMP, 1658 AMDGPU_OAM_X_VDD18_VR_TEMP, 1659 AMDGPU_OAM_X_04_HBM_B_VR_TEMP, 1660 AMDGPU_OAM_X_04_HBM_D_VR_TEMP, 1661 AMDGPU_NODE_MAX_TEMP_ENTRIES = 12, 1662 }; 1663 1664 struct amdgpu_gpuboard_temp_metrics_v1_0 { 1665 struct metrics_table_header common_header; 1666 uint16_t label_version; 1667 uint16_t node_id; 1668 uint64_t accumulation_counter; 1669 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1670 uint32_t node_temp[AMDGPU_NODE_MAX_TEMP_ENTRIES]; 1671 uint32_t vr_temp[AMDGPU_VR_MAX_TEMP_ENTRIES]; 1672 }; 1673 1674 struct amdgpu_baseboard_temp_metrics_v1_0 { 1675 struct metrics_table_header common_header; 1676 uint16_t label_version; 1677 uint16_t node_id; 1678 uint64_t accumulation_counter; 1679 /* Encoded temperature in Celcius, 24:31 is sensor id 0:23 is temp value */ 1680 uint32_t system_temp[AMDGPU_SYSTEM_MAX_TEMP_ENTRIES]; 1681 }; 1682 1683 struct amdgpu_partition_metrics_v1_0 { 1684 struct metrics_table_header common_header; 1685 /* Current clocks (Mhz) */ 1686 uint16_t current_gfxclk[MAX_XCC]; 1687 uint16_t current_socclk[MAX_CLKS]; 1688 uint16_t current_vclk0[MAX_CLKS]; 1689 uint16_t current_dclk0[MAX_CLKS]; 1690 uint16_t current_uclk; 1691 uint16_t padding; 1692 1693 /* Utilization Instantaneous (%) */ 1694 uint32_t gfx_busy_inst[MAX_XCC]; 1695 uint16_t jpeg_busy[NUM_JPEG_ENG_V1]; 1696 uint16_t vcn_busy[NUM_VCN]; 1697 /* Utilization Accumulated (%) */ 1698 uint64_t gfx_busy_acc[MAX_XCC]; 1699 /* Total App Clock Counter Accumulated */ 1700 uint64_t gfx_below_host_limit_ppt_acc[MAX_XCC]; 1701 uint64_t gfx_below_host_limit_thm_acc[MAX_XCC]; 1702 uint64_t gfx_low_utilization_acc[MAX_XCC]; 1703 uint64_t gfx_below_host_limit_total_acc[MAX_XCC]; 1704 }; 1705 1706 #endif 1707