1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _DM_PP_INTERFACE_ 24 #define _DM_PP_INTERFACE_ 25 26 #include "dm_services_types.h" 27 28 #define PP_MAX_CLOCK_LEVELS 16 29 30 enum amd_pp_display_config_type { 31 AMD_PP_DisplayConfigType_None = 0, 32 AMD_PP_DisplayConfigType_DP54 , 33 AMD_PP_DisplayConfigType_DP432 , 34 AMD_PP_DisplayConfigType_DP324 , 35 AMD_PP_DisplayConfigType_DP27, 36 AMD_PP_DisplayConfigType_DP243, 37 AMD_PP_DisplayConfigType_DP216, 38 AMD_PP_DisplayConfigType_DP162, 39 AMD_PP_DisplayConfigType_HDMI6G, 40 AMD_PP_DisplayConfigType_HDMI297, 41 AMD_PP_DisplayConfigType_HDMI162, 42 AMD_PP_DisplayConfigType_LVDS, 43 AMD_PP_DisplayConfigType_DVI, 44 AMD_PP_DisplayConfigType_WIRELESS, 45 AMD_PP_DisplayConfigType_VGA 46 }; 47 48 struct single_display_configuration { 49 uint32_t controller_index; 50 uint32_t controller_id; 51 uint32_t signal_type; 52 uint32_t display_state; 53 /* phy id for the primary internal transmitter */ 54 uint8_t primary_transmitter_phyi_d; 55 /* bitmap with the active lanes */ 56 uint8_t primary_transmitter_active_lanemap; 57 /* phy id for the secondary internal transmitter (for dual-link dvi) */ 58 uint8_t secondary_transmitter_phy_id; 59 /* bitmap with the active lanes */ 60 uint8_t secondary_transmitter_active_lanemap; 61 /* misc phy settings for SMU. */ 62 uint32_t config_flags; 63 uint32_t display_type; 64 uint32_t view_resolution_cx; 65 uint32_t view_resolution_cy; 66 enum amd_pp_display_config_type displayconfigtype; 67 uint32_t vertical_refresh; /* for active display */ 68 }; 69 70 #define MAX_NUM_DISPLAY 32 71 72 struct amd_pp_display_configuration { 73 bool nb_pstate_switch_disable;/* controls NB PState switch */ 74 bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 75 bool cpu_pstate_disable; 76 uint32_t cpu_pstate_separation_time; 77 78 uint32_t num_display; /* total number of display*/ 79 uint32_t num_path_including_non_display; 80 uint32_t crossfire_display_index; 81 uint32_t min_mem_set_clock; 82 uint32_t min_core_set_clock; 83 /* unit 10KHz x bit*/ 84 uint32_t min_bus_bandwidth; 85 /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/ 86 uint32_t min_core_set_clock_in_sr; 87 88 struct single_display_configuration displays[MAX_NUM_DISPLAY]; 89 90 uint32_t vrefresh; /* for active display*/ 91 92 uint32_t min_vblank_time; /* for active display*/ 93 bool multi_monitor_in_sync; 94 /* Controller Index of primary display - used in MCLK SMC switching hang 95 * SW Workaround*/ 96 uint32_t crtc_index; 97 /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/ 98 uint32_t line_time_in_us; 99 bool invalid_vblank_time; 100 101 uint32_t display_clk; 102 /* 103 * for given display configuration if multimonitormnsync == false then 104 * Memory clock DPMS with this latency or below is allowed, DPMS with 105 * higher latency not allowed. 106 */ 107 uint32_t dce_tolerable_mclk_in_active_latency; 108 uint32_t min_dcef_set_clk; 109 uint32_t min_dcef_deep_sleep_set_clk; 110 }; 111 112 struct amd_pp_simple_clock_info { 113 uint32_t engine_max_clock; 114 uint32_t memory_max_clock; 115 uint32_t level; 116 }; 117 118 enum PP_DAL_POWERLEVEL { 119 PP_DAL_POWERLEVEL_INVALID = 0, 120 PP_DAL_POWERLEVEL_ULTRALOW, 121 PP_DAL_POWERLEVEL_LOW, 122 PP_DAL_POWERLEVEL_NOMINAL, 123 PP_DAL_POWERLEVEL_PERFORMANCE, 124 125 PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW, 126 PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW, 127 PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL, 128 PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE, 129 PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1, 130 PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1, 131 PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1, 132 PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1, 133 }; 134 135 struct amd_pp_clock_info { 136 uint32_t min_engine_clock; 137 uint32_t max_engine_clock; 138 uint32_t min_memory_clock; 139 uint32_t max_memory_clock; 140 uint32_t min_bus_bandwidth; 141 uint32_t max_bus_bandwidth; 142 uint32_t max_engine_clock_in_sr; 143 uint32_t min_engine_clock_in_sr; 144 enum PP_DAL_POWERLEVEL max_clocks_state; 145 }; 146 147 enum amd_pp_clock_type { 148 amd_pp_disp_clock = 1, 149 amd_pp_sys_clock, 150 amd_pp_mem_clock, 151 amd_pp_dcef_clock, 152 amd_pp_soc_clock, 153 amd_pp_pixel_clock, 154 amd_pp_phy_clock, 155 amd_pp_dcf_clock, 156 amd_pp_dpp_clock, 157 amd_pp_f_clock = amd_pp_dcef_clock, 158 }; 159 160 #define MAX_NUM_CLOCKS 16 161 162 struct amd_pp_clocks { 163 uint32_t count; 164 uint32_t clock[MAX_NUM_CLOCKS]; 165 uint32_t latency[MAX_NUM_CLOCKS]; 166 }; 167 168 struct pp_clock_with_latency { 169 uint32_t clocks_in_khz; 170 uint32_t latency_in_us; 171 }; 172 173 struct pp_clock_levels_with_latency { 174 uint32_t num_levels; 175 struct pp_clock_with_latency data[PP_MAX_CLOCK_LEVELS]; 176 }; 177 178 struct pp_clock_with_voltage { 179 uint32_t clocks_in_khz; 180 uint32_t voltage_in_mv; 181 }; 182 183 struct pp_clock_levels_with_voltage { 184 uint32_t num_levels; 185 struct pp_clock_with_voltage data[PP_MAX_CLOCK_LEVELS]; 186 }; 187 188 struct pp_display_clock_request { 189 enum amd_pp_clock_type clock_type; 190 uint32_t clock_freq_in_khz; 191 }; 192 193 #endif /* _DM_PP_INTERFACE_ */ 194