1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _DISCOVERY_H_ 25 #define _DISCOVERY_H_ 26 27 #define PSP_HEADER_SIZE 256 28 #define BINARY_SIGNATURE 0x28211407 29 #define DISCOVERY_TABLE_SIGNATURE 0x53445049 30 #define GC_TABLE_ID 0x4347 31 #define HARVEST_TABLE_SIGNATURE 0x56524148 32 #define VCN_INFO_TABLE_ID 0x004E4356 33 #define MALL_INFO_TABLE_ID 0x4C4C414D 34 #define NPS_INFO_TABLE_ID 0x0053504E 35 36 typedef enum { 37 IP_DISCOVERY = 0, 38 GC, 39 HARVEST_INFO, 40 VCN_INFO, 41 MALL_INFO, 42 NPS_INFO, 43 TOTAL_TABLES = 6 44 } table; 45 46 #pragma pack(1) 47 48 typedef struct table_info 49 { 50 uint16_t offset; /* Byte offset */ 51 uint16_t checksum; /* Byte sum of the table */ 52 uint16_t size; /* Table size */ 53 uint16_t padding; 54 } table_info; 55 56 typedef struct binary_header 57 { 58 /* psp structure should go at the top of this structure */ 59 uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */ 60 uint16_t version_major; 61 uint16_t version_minor; 62 uint16_t binary_checksum; /* Byte sum of the binary after this field */ 63 uint16_t binary_size; /* Binary Size*/ 64 table_info table_list[TOTAL_TABLES]; 65 } binary_header; 66 67 typedef struct die_info 68 { 69 uint16_t die_id; 70 uint16_t die_offset; /* Points to the corresponding die_header structure */ 71 } die_info; 72 73 74 typedef struct ip_discovery_header 75 { 76 uint32_t signature; /* Table Signature */ 77 uint16_t version; /* Table Version */ 78 uint16_t size; /* Table Size */ 79 uint32_t id; /* Table ID */ 80 uint16_t num_dies; /* Number of Dies */ 81 die_info die_info[16]; /* list die information for up to 16 dies */ 82 union { 83 uint16_t padding[1]; /* version <= 3 */ 84 struct { /* version == 4 */ 85 uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */ 86 uint8_t reserved : 7; 87 uint8_t reserved2; 88 }; 89 }; 90 } ip_discovery_header; 91 92 typedef struct ip 93 { 94 uint16_t hw_id; /* Hardware ID */ 95 uint8_t number_instance; /* instance of the IP */ 96 uint8_t num_base_address; /* Number of Base Addresses */ 97 uint8_t major; /* HCID Major */ 98 uint8_t minor; /* HCID Minor */ 99 uint8_t revision; /* HCID Revision */ 100 #if defined(__BIG_ENDIAN) 101 uint8_t reserved : 4; /* Placeholder field */ 102 uint8_t harvest : 4; /* Harvest */ 103 #else 104 uint8_t harvest : 4; /* Harvest */ 105 uint8_t reserved : 4; /* Placeholder field */ 106 #endif 107 uint32_t base_address[]; /* variable number of Addresses */ 108 } ip; 109 110 typedef struct ip_v3 111 { 112 uint16_t hw_id; /* Hardware ID */ 113 uint8_t instance_number; /* Instance number for the IP */ 114 uint8_t num_base_address; /* Number of base addresses*/ 115 uint8_t major; /* Hardware ID.major version */ 116 uint8_t minor; /* Hardware ID.minor version */ 117 uint8_t revision; /* Hardware ID.revision version */ 118 #if defined(__BIG_ENDIAN) 119 uint8_t variant : 4; /* HW variant */ 120 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 121 #else 122 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 123 uint8_t variant : 4; /* HW variant */ 124 #endif 125 uint32_t base_address[]; /* Base Address list. Corresponds to the num_base_address field*/ 126 } ip_v3; 127 128 typedef struct ip_v4 { 129 uint16_t hw_id; /* Hardware ID */ 130 uint8_t instance_number; /* Instance number for the IP */ 131 uint8_t num_base_address; /* Number of base addresses*/ 132 uint8_t major; /* Hardware ID.major version */ 133 uint8_t minor; /* Hardware ID.minor version */ 134 uint8_t revision; /* Hardware ID.revision version */ 135 #if defined(LITTLEENDIAN_CPU) 136 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 137 uint8_t variant : 4; /* HW variant */ 138 #elif defined(BIGENDIAN_CPU) 139 uint8_t variant : 4; /* HW variant */ 140 uint8_t sub_revision : 4; /* HCID Sub-Revision */ 141 #endif 142 union { 143 DECLARE_FLEX_ARRAY(uint32_t, base_address); /* 32-bit Base Address list. Corresponds to the num_base_address field*/ 144 DECLARE_FLEX_ARRAY(uint64_t, base_address_64); /* 64-bit Base Address list. Corresponds to the num_base_address field*/ 145 } __packed; 146 } ip_v4; 147 148 typedef struct die_header 149 { 150 uint16_t die_id; 151 uint16_t num_ips; 152 } die_header; 153 154 typedef struct ip_structure 155 { 156 ip_discovery_header* header; 157 struct die 158 { 159 die_header *die_header; 160 union 161 { 162 ip *ip_list; 163 ip_v3 *ip_v3_list; 164 ip_v4 *ip_v4_list; 165 }; /* IP list. Variable size*/ 166 } die; 167 } ip_structure; 168 169 struct gpu_info_header { 170 uint32_t table_id; /* table ID */ 171 uint16_t version_major; /* table version */ 172 uint16_t version_minor; /* table version */ 173 uint32_t size; /* size of the entire header+data in bytes */ 174 }; 175 176 struct gc_info_v1_0 { 177 struct gpu_info_header header; 178 179 uint32_t gc_num_se; 180 uint32_t gc_num_wgp0_per_sa; 181 uint32_t gc_num_wgp1_per_sa; 182 uint32_t gc_num_rb_per_se; 183 uint32_t gc_num_gl2c; 184 uint32_t gc_num_gprs; 185 uint32_t gc_num_max_gs_thds; 186 uint32_t gc_gs_table_depth; 187 uint32_t gc_gsprim_buff_depth; 188 uint32_t gc_parameter_cache_depth; 189 uint32_t gc_double_offchip_lds_buffer; 190 uint32_t gc_wave_size; 191 uint32_t gc_max_waves_per_simd; 192 uint32_t gc_max_scratch_slots_per_cu; 193 uint32_t gc_lds_size; 194 uint32_t gc_num_sc_per_se; 195 uint32_t gc_num_sa_per_se; 196 uint32_t gc_num_packer_per_sc; 197 uint32_t gc_num_gl2a; 198 }; 199 200 struct gc_info_v1_1 { 201 struct gpu_info_header header; 202 203 uint32_t gc_num_se; 204 uint32_t gc_num_wgp0_per_sa; 205 uint32_t gc_num_wgp1_per_sa; 206 uint32_t gc_num_rb_per_se; 207 uint32_t gc_num_gl2c; 208 uint32_t gc_num_gprs; 209 uint32_t gc_num_max_gs_thds; 210 uint32_t gc_gs_table_depth; 211 uint32_t gc_gsprim_buff_depth; 212 uint32_t gc_parameter_cache_depth; 213 uint32_t gc_double_offchip_lds_buffer; 214 uint32_t gc_wave_size; 215 uint32_t gc_max_waves_per_simd; 216 uint32_t gc_max_scratch_slots_per_cu; 217 uint32_t gc_lds_size; 218 uint32_t gc_num_sc_per_se; 219 uint32_t gc_num_sa_per_se; 220 uint32_t gc_num_packer_per_sc; 221 uint32_t gc_num_gl2a; 222 uint32_t gc_num_tcp_per_sa; 223 uint32_t gc_num_sdp_interface; 224 uint32_t gc_num_tcps; 225 }; 226 227 struct gc_info_v1_2 { 228 struct gpu_info_header header; 229 uint32_t gc_num_se; 230 uint32_t gc_num_wgp0_per_sa; 231 uint32_t gc_num_wgp1_per_sa; 232 uint32_t gc_num_rb_per_se; 233 uint32_t gc_num_gl2c; 234 uint32_t gc_num_gprs; 235 uint32_t gc_num_max_gs_thds; 236 uint32_t gc_gs_table_depth; 237 uint32_t gc_gsprim_buff_depth; 238 uint32_t gc_parameter_cache_depth; 239 uint32_t gc_double_offchip_lds_buffer; 240 uint32_t gc_wave_size; 241 uint32_t gc_max_waves_per_simd; 242 uint32_t gc_max_scratch_slots_per_cu; 243 uint32_t gc_lds_size; 244 uint32_t gc_num_sc_per_se; 245 uint32_t gc_num_sa_per_se; 246 uint32_t gc_num_packer_per_sc; 247 uint32_t gc_num_gl2a; 248 uint32_t gc_num_tcp_per_sa; 249 uint32_t gc_num_sdp_interface; 250 uint32_t gc_num_tcps; 251 uint32_t gc_num_tcp_per_wpg; 252 uint32_t gc_tcp_l1_size; 253 uint32_t gc_num_sqc_per_wgp; 254 uint32_t gc_l1_instruction_cache_size_per_sqc; 255 uint32_t gc_l1_data_cache_size_per_sqc; 256 uint32_t gc_gl1c_per_sa; 257 uint32_t gc_gl1c_size_per_instance; 258 uint32_t gc_gl2c_per_gpu; 259 }; 260 261 struct gc_info_v1_3 { 262 struct gpu_info_header header; 263 uint32_t gc_num_se; 264 uint32_t gc_num_wgp0_per_sa; 265 uint32_t gc_num_wgp1_per_sa; 266 uint32_t gc_num_rb_per_se; 267 uint32_t gc_num_gl2c; 268 uint32_t gc_num_gprs; 269 uint32_t gc_num_max_gs_thds; 270 uint32_t gc_gs_table_depth; 271 uint32_t gc_gsprim_buff_depth; 272 uint32_t gc_parameter_cache_depth; 273 uint32_t gc_double_offchip_lds_buffer; 274 uint32_t gc_wave_size; 275 uint32_t gc_max_waves_per_simd; 276 uint32_t gc_max_scratch_slots_per_cu; 277 uint32_t gc_lds_size; 278 uint32_t gc_num_sc_per_se; 279 uint32_t gc_num_sa_per_se; 280 uint32_t gc_num_packer_per_sc; 281 uint32_t gc_num_gl2a; 282 uint32_t gc_num_tcp_per_sa; 283 uint32_t gc_num_sdp_interface; 284 uint32_t gc_num_tcps; 285 uint32_t gc_num_tcp_per_wpg; 286 uint32_t gc_tcp_l1_size; 287 uint32_t gc_num_sqc_per_wgp; 288 uint32_t gc_l1_instruction_cache_size_per_sqc; 289 uint32_t gc_l1_data_cache_size_per_sqc; 290 uint32_t gc_gl1c_per_sa; 291 uint32_t gc_gl1c_size_per_instance; 292 uint32_t gc_gl2c_per_gpu; 293 uint32_t gc_tcp_size_per_cu; 294 uint32_t gc_tcp_cache_line_size; 295 uint32_t gc_instruction_cache_size_per_sqc; 296 uint32_t gc_instruction_cache_line_size; 297 uint32_t gc_scalar_data_cache_size_per_sqc; 298 uint32_t gc_scalar_data_cache_line_size; 299 uint32_t gc_tcc_size; 300 uint32_t gc_tcc_cache_line_size; 301 }; 302 303 struct gc_info_v2_0 { 304 struct gpu_info_header header; 305 306 uint32_t gc_num_se; 307 uint32_t gc_num_cu_per_sh; 308 uint32_t gc_num_sh_per_se; 309 uint32_t gc_num_rb_per_se; 310 uint32_t gc_num_tccs; 311 uint32_t gc_num_gprs; 312 uint32_t gc_num_max_gs_thds; 313 uint32_t gc_gs_table_depth; 314 uint32_t gc_gsprim_buff_depth; 315 uint32_t gc_parameter_cache_depth; 316 uint32_t gc_double_offchip_lds_buffer; 317 uint32_t gc_wave_size; 318 uint32_t gc_max_waves_per_simd; 319 uint32_t gc_max_scratch_slots_per_cu; 320 uint32_t gc_lds_size; 321 uint32_t gc_num_sc_per_se; 322 uint32_t gc_num_packer_per_sc; 323 }; 324 325 struct gc_info_v2_1 { 326 struct gpu_info_header header; 327 328 uint32_t gc_num_se; 329 uint32_t gc_num_cu_per_sh; 330 uint32_t gc_num_sh_per_se; 331 uint32_t gc_num_rb_per_se; 332 uint32_t gc_num_tccs; 333 uint32_t gc_num_gprs; 334 uint32_t gc_num_max_gs_thds; 335 uint32_t gc_gs_table_depth; 336 uint32_t gc_gsprim_buff_depth; 337 uint32_t gc_parameter_cache_depth; 338 uint32_t gc_double_offchip_lds_buffer; 339 uint32_t gc_wave_size; 340 uint32_t gc_max_waves_per_simd; 341 uint32_t gc_max_scratch_slots_per_cu; 342 uint32_t gc_lds_size; 343 uint32_t gc_num_sc_per_se; 344 uint32_t gc_num_packer_per_sc; 345 /* new for v2_1 */ 346 uint32_t gc_num_tcp_per_sh; 347 uint32_t gc_tcp_size_per_cu; 348 uint32_t gc_num_sdp_interface; 349 uint32_t gc_num_cu_per_sqc; 350 uint32_t gc_instruction_cache_size_per_sqc; 351 uint32_t gc_scalar_data_cache_size_per_sqc; 352 uint32_t gc_tcc_size; 353 }; 354 355 typedef struct harvest_info_header { 356 uint32_t signature; /* Table Signature */ 357 uint32_t version; /* Table Version */ 358 } harvest_info_header; 359 360 typedef struct harvest_info { 361 uint16_t hw_id; /* Hardware ID */ 362 uint8_t number_instance; /* Instance of the IP */ 363 uint8_t reserved; /* Reserved for alignment */ 364 } harvest_info; 365 366 typedef struct harvest_table { 367 harvest_info_header header; 368 harvest_info list[32]; 369 } harvest_table; 370 371 struct mall_info_header { 372 uint32_t table_id; /* table ID */ 373 uint16_t version_major; /* table version */ 374 uint16_t version_minor; /* table version */ 375 uint32_t size_bytes; /* size of the entire header+data in bytes */ 376 }; 377 378 struct mall_info_v1_0 { 379 struct mall_info_header header; 380 uint32_t mall_size_per_m; 381 uint32_t m_s_present; 382 uint32_t m_half_use; 383 uint32_t m_mall_config; 384 uint32_t reserved[5]; 385 }; 386 387 struct mall_info_v2_0 { 388 struct mall_info_header header; 389 uint32_t mall_size_per_umc; 390 uint32_t reserved[8]; 391 }; 392 393 #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4 394 395 struct vcn_info_header { 396 uint32_t table_id; /* table ID */ 397 uint16_t version_major; /* table version */ 398 uint16_t version_minor; /* table version */ 399 uint32_t size_bytes; /* size of the entire header+data in bytes */ 400 }; 401 402 struct vcn_instance_info_v1_0 403 { 404 uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/ 405 union _fuse_data { 406 struct { 407 uint32_t av1_disabled : 1; 408 uint32_t vp9_disabled : 1; 409 uint32_t hevc_disabled : 1; 410 uint32_t h264_disabled : 1; 411 uint32_t reserved : 28; 412 } bits; 413 uint32_t all_bits; 414 } fuse_data; 415 uint32_t reserved[2]; 416 }; 417 418 struct vcn_info_v1_0 { 419 struct vcn_info_header header; 420 uint32_t num_of_instances; /* number of entries used in instance_info below*/ 421 struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES]; 422 uint32_t reserved[4]; 423 }; 424 425 #define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12 426 427 struct nps_info_header { 428 uint32_t table_id; /* table ID */ 429 uint16_t version_major; /* table version */ 430 uint16_t version_minor; /* table version */ 431 uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */ 432 }; 433 434 struct nps_instance_info_v1_0 { 435 uint64_t base_address; 436 uint64_t limit_address; 437 }; 438 439 struct nps_info_v1_0 { 440 struct nps_info_header header; 441 uint32_t nps_type; 442 uint32_t count; 443 struct nps_instance_info_v1_0 444 instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES]; 445 }; 446 447 #pragma pack() 448 449 #endif 450