1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _dimgrey_cavefish_ip_offset_HEADER 22 #define _dimgrey_cavefish_ip_offset_HEADER 23 24 #define MAX_INSTANCE 7 25 #define MAX_SEGMENT 6 26 27 28 struct IP_BASE_INSTANCE { 29 unsigned int segment[MAX_SEGMENT]; 30 }; 31 32 struct IP_BASE { 33 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 34 } __maybe_unused; 35 36 37 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } }, 38 { { 0, 0, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } } } }; 44 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 45 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 46 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 47 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 48 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 49 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 50 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } }; 51 static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } }, 52 { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } } } }; 58 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } } } }; 65 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } } } }; 72 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 73 { { 0, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } } } }; 79 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } } } }; 86 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } } } }; 93 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } } } }; 100 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } } } }; 107 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } } } }; 114 static const struct IP_BASE MP1_BASE = { { { { 0x00016200, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } } } }; 121 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } } } }; 128 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } } } }; 135 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } } } }; 142 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0, 0 } } } }; 149 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, 150 { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } }, 151 { { 0x00094000, 0x02426000, 0, 0, 0, 0 } }, 152 { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } } } }; 156 static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } } } }; 163 164 165 #define ATHUB_BASE__INST0_SEG0 0x00000C00 166 #define ATHUB_BASE__INST0_SEG1 0x02408C00 167 #define ATHUB_BASE__INST0_SEG2 0 168 #define ATHUB_BASE__INST0_SEG3 0 169 #define ATHUB_BASE__INST0_SEG4 0 170 #define ATHUB_BASE__INST0_SEG5 0 171 172 #define ATHUB_BASE__INST1_SEG0 0 173 #define ATHUB_BASE__INST1_SEG1 0 174 #define ATHUB_BASE__INST1_SEG2 0 175 #define ATHUB_BASE__INST1_SEG3 0 176 #define ATHUB_BASE__INST1_SEG4 0 177 #define ATHUB_BASE__INST1_SEG5 0 178 179 #define ATHUB_BASE__INST2_SEG0 0 180 #define ATHUB_BASE__INST2_SEG1 0 181 #define ATHUB_BASE__INST2_SEG2 0 182 #define ATHUB_BASE__INST2_SEG3 0 183 #define ATHUB_BASE__INST2_SEG4 0 184 #define ATHUB_BASE__INST2_SEG5 0 185 186 #define ATHUB_BASE__INST3_SEG0 0 187 #define ATHUB_BASE__INST3_SEG1 0 188 #define ATHUB_BASE__INST3_SEG2 0 189 #define ATHUB_BASE__INST3_SEG3 0 190 #define ATHUB_BASE__INST3_SEG4 0 191 #define ATHUB_BASE__INST3_SEG5 0 192 193 #define ATHUB_BASE__INST4_SEG0 0 194 #define ATHUB_BASE__INST4_SEG1 0 195 #define ATHUB_BASE__INST4_SEG2 0 196 #define ATHUB_BASE__INST4_SEG3 0 197 #define ATHUB_BASE__INST4_SEG4 0 198 #define ATHUB_BASE__INST4_SEG5 0 199 200 #define ATHUB_BASE__INST5_SEG0 0 201 #define ATHUB_BASE__INST5_SEG1 0 202 #define ATHUB_BASE__INST5_SEG2 0 203 #define ATHUB_BASE__INST5_SEG3 0 204 #define ATHUB_BASE__INST5_SEG4 0 205 #define ATHUB_BASE__INST5_SEG5 0 206 207 #define ATHUB_BASE__INST6_SEG0 0 208 #define ATHUB_BASE__INST6_SEG1 0 209 #define ATHUB_BASE__INST6_SEG2 0 210 #define ATHUB_BASE__INST6_SEG3 0 211 #define ATHUB_BASE__INST6_SEG4 0 212 #define ATHUB_BASE__INST6_SEG5 0 213 214 #define CLK_BASE__INST0_SEG0 0x00016C00 215 #define CLK_BASE__INST0_SEG1 0x02401800 216 #define CLK_BASE__INST0_SEG2 0 217 #define CLK_BASE__INST0_SEG3 0 218 #define CLK_BASE__INST0_SEG4 0 219 #define CLK_BASE__INST0_SEG5 0 220 221 #define CLK_BASE__INST1_SEG0 0x00016E00 222 #define CLK_BASE__INST1_SEG1 0x02401C00 223 #define CLK_BASE__INST1_SEG2 0 224 #define CLK_BASE__INST1_SEG3 0 225 #define CLK_BASE__INST1_SEG4 0 226 #define CLK_BASE__INST1_SEG5 0 227 228 #define CLK_BASE__INST2_SEG0 0x00017000 229 #define CLK_BASE__INST2_SEG1 0x02402000 230 #define CLK_BASE__INST2_SEG2 0 231 #define CLK_BASE__INST2_SEG3 0 232 #define CLK_BASE__INST2_SEG4 0 233 #define CLK_BASE__INST2_SEG5 0 234 235 #define CLK_BASE__INST3_SEG0 0x00017200 236 #define CLK_BASE__INST3_SEG1 0x02402400 237 #define CLK_BASE__INST3_SEG2 0 238 #define CLK_BASE__INST3_SEG3 0 239 #define CLK_BASE__INST3_SEG4 0 240 #define CLK_BASE__INST3_SEG5 0 241 242 #define CLK_BASE__INST4_SEG0 0x0001B000 243 #define CLK_BASE__INST4_SEG1 0x0242D800 244 #define CLK_BASE__INST4_SEG2 0 245 #define CLK_BASE__INST4_SEG3 0 246 #define CLK_BASE__INST4_SEG4 0 247 #define CLK_BASE__INST4_SEG5 0 248 249 #define CLK_BASE__INST5_SEG0 0x0001B200 250 #define CLK_BASE__INST5_SEG1 0x0242DC00 251 #define CLK_BASE__INST5_SEG2 0 252 #define CLK_BASE__INST5_SEG3 0 253 #define CLK_BASE__INST5_SEG4 0 254 #define CLK_BASE__INST5_SEG5 0 255 256 #define CLK_BASE__INST6_SEG0 0x0001B400 257 #define CLK_BASE__INST6_SEG1 0x0242E000 258 #define CLK_BASE__INST6_SEG2 0 259 #define CLK_BASE__INST6_SEG3 0 260 #define CLK_BASE__INST6_SEG4 0 261 #define CLK_BASE__INST6_SEG5 0 262 263 #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 264 #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 265 #define DBGU_IO0_BASE__INST0_SEG2 0 266 #define DBGU_IO0_BASE__INST0_SEG3 0 267 #define DBGU_IO0_BASE__INST0_SEG4 0 268 #define DBGU_IO0_BASE__INST0_SEG5 0 269 270 #define DBGU_IO0_BASE__INST1_SEG0 0x00000260 271 #define DBGU_IO0_BASE__INST1_SEG1 0x02413C00 272 #define DBGU_IO0_BASE__INST1_SEG2 0 273 #define DBGU_IO0_BASE__INST1_SEG3 0 274 #define DBGU_IO0_BASE__INST1_SEG4 0 275 #define DBGU_IO0_BASE__INST1_SEG5 0 276 277 #define DBGU_IO0_BASE__INST2_SEG0 0 278 #define DBGU_IO0_BASE__INST2_SEG1 0 279 #define DBGU_IO0_BASE__INST2_SEG2 0 280 #define DBGU_IO0_BASE__INST2_SEG3 0 281 #define DBGU_IO0_BASE__INST2_SEG4 0 282 #define DBGU_IO0_BASE__INST2_SEG5 0 283 284 #define DBGU_IO0_BASE__INST3_SEG0 0 285 #define DBGU_IO0_BASE__INST3_SEG1 0 286 #define DBGU_IO0_BASE__INST3_SEG2 0 287 #define DBGU_IO0_BASE__INST3_SEG3 0 288 #define DBGU_IO0_BASE__INST3_SEG4 0 289 #define DBGU_IO0_BASE__INST3_SEG5 0 290 291 #define DBGU_IO0_BASE__INST4_SEG0 0 292 #define DBGU_IO0_BASE__INST4_SEG1 0 293 #define DBGU_IO0_BASE__INST4_SEG2 0 294 #define DBGU_IO0_BASE__INST4_SEG3 0 295 #define DBGU_IO0_BASE__INST4_SEG4 0 296 #define DBGU_IO0_BASE__INST4_SEG5 0 297 298 #define DBGU_IO0_BASE__INST5_SEG0 0 299 #define DBGU_IO0_BASE__INST5_SEG1 0 300 #define DBGU_IO0_BASE__INST5_SEG2 0 301 #define DBGU_IO0_BASE__INST5_SEG3 0 302 #define DBGU_IO0_BASE__INST5_SEG4 0 303 #define DBGU_IO0_BASE__INST5_SEG5 0 304 305 #define DBGU_IO0_BASE__INST6_SEG0 0 306 #define DBGU_IO0_BASE__INST6_SEG1 0 307 #define DBGU_IO0_BASE__INST6_SEG2 0 308 #define DBGU_IO0_BASE__INST6_SEG3 0 309 #define DBGU_IO0_BASE__INST6_SEG4 0 310 #define DBGU_IO0_BASE__INST6_SEG5 0 311 312 #define DF_BASE__INST0_SEG0 0x00007000 313 #define DF_BASE__INST0_SEG1 0x0240B800 314 #define DF_BASE__INST0_SEG2 0 315 #define DF_BASE__INST0_SEG3 0 316 #define DF_BASE__INST0_SEG4 0 317 #define DF_BASE__INST0_SEG5 0 318 319 #define DF_BASE__INST1_SEG0 0 320 #define DF_BASE__INST1_SEG1 0 321 #define DF_BASE__INST1_SEG2 0 322 #define DF_BASE__INST1_SEG3 0 323 #define DF_BASE__INST1_SEG4 0 324 #define DF_BASE__INST1_SEG5 0 325 326 #define DF_BASE__INST2_SEG0 0 327 #define DF_BASE__INST2_SEG1 0 328 #define DF_BASE__INST2_SEG2 0 329 #define DF_BASE__INST2_SEG3 0 330 #define DF_BASE__INST2_SEG4 0 331 #define DF_BASE__INST2_SEG5 0 332 333 #define DF_BASE__INST3_SEG0 0 334 #define DF_BASE__INST3_SEG1 0 335 #define DF_BASE__INST3_SEG2 0 336 #define DF_BASE__INST3_SEG3 0 337 #define DF_BASE__INST3_SEG4 0 338 #define DF_BASE__INST3_SEG5 0 339 340 #define DF_BASE__INST4_SEG0 0 341 #define DF_BASE__INST4_SEG1 0 342 #define DF_BASE__INST4_SEG2 0 343 #define DF_BASE__INST4_SEG3 0 344 #define DF_BASE__INST4_SEG4 0 345 #define DF_BASE__INST4_SEG5 0 346 347 #define DF_BASE__INST5_SEG0 0 348 #define DF_BASE__INST5_SEG1 0 349 #define DF_BASE__INST5_SEG2 0 350 #define DF_BASE__INST5_SEG3 0 351 #define DF_BASE__INST5_SEG4 0 352 #define DF_BASE__INST5_SEG5 0 353 354 #define DF_BASE__INST6_SEG0 0 355 #define DF_BASE__INST6_SEG1 0 356 #define DF_BASE__INST6_SEG2 0 357 #define DF_BASE__INST6_SEG3 0 358 #define DF_BASE__INST6_SEG4 0 359 #define DF_BASE__INST6_SEG5 0 360 361 #define DCN_BASE__INST0_SEG0 0x00000012 362 #define DCN_BASE__INST0_SEG1 0x000000C0 363 #define DCN_BASE__INST0_SEG2 0x000034C0 364 #define DCN_BASE__INST0_SEG3 0x00009000 365 #define DCN_BASE__INST0_SEG4 0x02403C00 366 #define DCN_BASE__INST0_SEG5 0 367 368 #define DCN_BASE__INST1_SEG0 0 369 #define DCN_BASE__INST1_SEG1 0 370 #define DCN_BASE__INST1_SEG2 0 371 #define DCN_BASE__INST1_SEG3 0 372 #define DCN_BASE__INST1_SEG4 0 373 #define DCN_BASE__INST1_SEG5 0 374 375 #define DCN_BASE__INST2_SEG0 0 376 #define DCN_BASE__INST2_SEG1 0 377 #define DCN_BASE__INST2_SEG2 0 378 #define DCN_BASE__INST2_SEG3 0 379 #define DCN_BASE__INST2_SEG4 0 380 #define DCN_BASE__INST2_SEG5 0 381 382 #define DCN_BASE__INST3_SEG0 0 383 #define DCN_BASE__INST3_SEG1 0 384 #define DCN_BASE__INST3_SEG2 0 385 #define DCN_BASE__INST3_SEG3 0 386 #define DCN_BASE__INST3_SEG4 0 387 #define DCN_BASE__INST3_SEG5 0 388 389 #define DCN_BASE__INST4_SEG0 0 390 #define DCN_BASE__INST4_SEG1 0 391 #define DCN_BASE__INST4_SEG2 0 392 #define DCN_BASE__INST4_SEG3 0 393 #define DCN_BASE__INST4_SEG4 0 394 #define DCN_BASE__INST4_SEG5 0 395 396 #define DCN_BASE__INST5_SEG0 0 397 #define DCN_BASE__INST5_SEG1 0 398 #define DCN_BASE__INST5_SEG2 0 399 #define DCN_BASE__INST5_SEG3 0 400 #define DCN_BASE__INST5_SEG4 0 401 #define DCN_BASE__INST5_SEG5 0 402 403 #define DCN_BASE__INST6_SEG0 0 404 #define DCN_BASE__INST6_SEG1 0 405 #define DCN_BASE__INST6_SEG2 0 406 #define DCN_BASE__INST6_SEG3 0 407 #define DCN_BASE__INST6_SEG4 0 408 #define DCN_BASE__INST6_SEG5 0 409 410 #define DPCS_BASE__INST0_SEG0 0x00000012 411 #define DPCS_BASE__INST0_SEG1 0x000000C0 412 #define DPCS_BASE__INST0_SEG2 0x000034C0 413 #define DPCS_BASE__INST0_SEG3 0x00009000 414 #define DPCS_BASE__INST0_SEG4 0x02403C00 415 #define DPCS_BASE__INST0_SEG5 0 416 417 #define DPCS_BASE__INST1_SEG0 0 418 #define DPCS_BASE__INST1_SEG1 0 419 #define DPCS_BASE__INST1_SEG2 0 420 #define DPCS_BASE__INST1_SEG3 0 421 #define DPCS_BASE__INST1_SEG4 0 422 #define DPCS_BASE__INST1_SEG5 0 423 424 #define DPCS_BASE__INST2_SEG0 0 425 #define DPCS_BASE__INST2_SEG1 0 426 #define DPCS_BASE__INST2_SEG2 0 427 #define DPCS_BASE__INST2_SEG3 0 428 #define DPCS_BASE__INST2_SEG4 0 429 #define DPCS_BASE__INST2_SEG5 0 430 431 #define DPCS_BASE__INST3_SEG0 0 432 #define DPCS_BASE__INST3_SEG1 0 433 #define DPCS_BASE__INST3_SEG2 0 434 #define DPCS_BASE__INST3_SEG3 0 435 #define DPCS_BASE__INST3_SEG4 0 436 #define DPCS_BASE__INST3_SEG5 0 437 438 #define DPCS_BASE__INST4_SEG0 0 439 #define DPCS_BASE__INST4_SEG1 0 440 #define DPCS_BASE__INST4_SEG2 0 441 #define DPCS_BASE__INST4_SEG3 0 442 #define DPCS_BASE__INST4_SEG4 0 443 #define DPCS_BASE__INST4_SEG5 0 444 445 #define DPCS_BASE__INST5_SEG0 0 446 #define DPCS_BASE__INST5_SEG1 0 447 #define DPCS_BASE__INST5_SEG2 0 448 #define DPCS_BASE__INST5_SEG3 0 449 #define DPCS_BASE__INST5_SEG4 0 450 #define DPCS_BASE__INST5_SEG5 0 451 452 #define DPCS_BASE__INST6_SEG0 0 453 #define DPCS_BASE__INST6_SEG1 0 454 #define DPCS_BASE__INST6_SEG2 0 455 #define DPCS_BASE__INST6_SEG3 0 456 #define DPCS_BASE__INST6_SEG4 0 457 #define DPCS_BASE__INST6_SEG5 0 458 459 #define FUSE_BASE__INST0_SEG0 0x00017400 460 #define FUSE_BASE__INST0_SEG1 0x02401400 461 #define FUSE_BASE__INST0_SEG2 0 462 #define FUSE_BASE__INST0_SEG3 0 463 #define FUSE_BASE__INST0_SEG4 0 464 #define FUSE_BASE__INST0_SEG5 0 465 466 #define FUSE_BASE__INST1_SEG0 0 467 #define FUSE_BASE__INST1_SEG1 0 468 #define FUSE_BASE__INST1_SEG2 0 469 #define FUSE_BASE__INST1_SEG3 0 470 #define FUSE_BASE__INST1_SEG4 0 471 #define FUSE_BASE__INST1_SEG5 0 472 473 #define FUSE_BASE__INST2_SEG0 0 474 #define FUSE_BASE__INST2_SEG1 0 475 #define FUSE_BASE__INST2_SEG2 0 476 #define FUSE_BASE__INST2_SEG3 0 477 #define FUSE_BASE__INST2_SEG4 0 478 #define FUSE_BASE__INST2_SEG5 0 479 480 #define FUSE_BASE__INST3_SEG0 0 481 #define FUSE_BASE__INST3_SEG1 0 482 #define FUSE_BASE__INST3_SEG2 0 483 #define FUSE_BASE__INST3_SEG3 0 484 #define FUSE_BASE__INST3_SEG4 0 485 #define FUSE_BASE__INST3_SEG5 0 486 487 #define FUSE_BASE__INST4_SEG0 0 488 #define FUSE_BASE__INST4_SEG1 0 489 #define FUSE_BASE__INST4_SEG2 0 490 #define FUSE_BASE__INST4_SEG3 0 491 #define FUSE_BASE__INST4_SEG4 0 492 #define FUSE_BASE__INST4_SEG5 0 493 494 #define FUSE_BASE__INST5_SEG0 0 495 #define FUSE_BASE__INST5_SEG1 0 496 #define FUSE_BASE__INST5_SEG2 0 497 #define FUSE_BASE__INST5_SEG3 0 498 #define FUSE_BASE__INST5_SEG4 0 499 #define FUSE_BASE__INST5_SEG5 0 500 501 #define FUSE_BASE__INST6_SEG0 0 502 #define FUSE_BASE__INST6_SEG1 0 503 #define FUSE_BASE__INST6_SEG2 0 504 #define FUSE_BASE__INST6_SEG3 0 505 #define FUSE_BASE__INST6_SEG4 0 506 #define FUSE_BASE__INST6_SEG5 0 507 508 #define GC_BASE__INST0_SEG0 0x00001260 509 #define GC_BASE__INST0_SEG1 0x0000A000 510 #define GC_BASE__INST0_SEG2 0x0001C000 511 #define GC_BASE__INST0_SEG3 0x02402C00 512 #define GC_BASE__INST0_SEG4 0 513 #define GC_BASE__INST0_SEG5 0 514 515 #define GC_BASE__INST1_SEG0 0 516 #define GC_BASE__INST1_SEG1 0 517 #define GC_BASE__INST1_SEG2 0 518 #define GC_BASE__INST1_SEG3 0 519 #define GC_BASE__INST1_SEG4 0 520 #define GC_BASE__INST1_SEG5 0 521 522 #define GC_BASE__INST2_SEG0 0 523 #define GC_BASE__INST2_SEG1 0 524 #define GC_BASE__INST2_SEG2 0 525 #define GC_BASE__INST2_SEG3 0 526 #define GC_BASE__INST2_SEG4 0 527 #define GC_BASE__INST2_SEG5 0 528 529 #define GC_BASE__INST3_SEG0 0 530 #define GC_BASE__INST3_SEG1 0 531 #define GC_BASE__INST3_SEG2 0 532 #define GC_BASE__INST3_SEG3 0 533 #define GC_BASE__INST3_SEG4 0 534 #define GC_BASE__INST3_SEG5 0 535 536 #define GC_BASE__INST4_SEG0 0 537 #define GC_BASE__INST4_SEG1 0 538 #define GC_BASE__INST4_SEG2 0 539 #define GC_BASE__INST4_SEG3 0 540 #define GC_BASE__INST4_SEG4 0 541 #define GC_BASE__INST4_SEG5 0 542 543 #define GC_BASE__INST5_SEG0 0 544 #define GC_BASE__INST5_SEG1 0 545 #define GC_BASE__INST5_SEG2 0 546 #define GC_BASE__INST5_SEG3 0 547 #define GC_BASE__INST5_SEG4 0 548 #define GC_BASE__INST5_SEG5 0 549 550 #define GC_BASE__INST6_SEG0 0 551 #define GC_BASE__INST6_SEG1 0 552 #define GC_BASE__INST6_SEG2 0 553 #define GC_BASE__INST6_SEG3 0 554 #define GC_BASE__INST6_SEG4 0 555 #define GC_BASE__INST6_SEG5 0 556 557 #define HDP_BASE__INST0_SEG0 0x00000F20 558 #define HDP_BASE__INST0_SEG1 0x0240A400 559 #define HDP_BASE__INST0_SEG2 0 560 #define HDP_BASE__INST0_SEG3 0 561 #define HDP_BASE__INST0_SEG4 0 562 #define HDP_BASE__INST0_SEG5 0 563 564 #define HDP_BASE__INST1_SEG0 0 565 #define HDP_BASE__INST1_SEG1 0 566 #define HDP_BASE__INST1_SEG2 0 567 #define HDP_BASE__INST1_SEG3 0 568 #define HDP_BASE__INST1_SEG4 0 569 #define HDP_BASE__INST1_SEG5 0 570 571 #define HDP_BASE__INST2_SEG0 0 572 #define HDP_BASE__INST2_SEG1 0 573 #define HDP_BASE__INST2_SEG2 0 574 #define HDP_BASE__INST2_SEG3 0 575 #define HDP_BASE__INST2_SEG4 0 576 #define HDP_BASE__INST2_SEG5 0 577 578 #define HDP_BASE__INST3_SEG0 0 579 #define HDP_BASE__INST3_SEG1 0 580 #define HDP_BASE__INST3_SEG2 0 581 #define HDP_BASE__INST3_SEG3 0 582 #define HDP_BASE__INST3_SEG4 0 583 #define HDP_BASE__INST3_SEG5 0 584 585 #define HDP_BASE__INST4_SEG0 0 586 #define HDP_BASE__INST4_SEG1 0 587 #define HDP_BASE__INST4_SEG2 0 588 #define HDP_BASE__INST4_SEG3 0 589 #define HDP_BASE__INST4_SEG4 0 590 #define HDP_BASE__INST4_SEG5 0 591 592 #define HDP_BASE__INST5_SEG0 0 593 #define HDP_BASE__INST5_SEG1 0 594 #define HDP_BASE__INST5_SEG2 0 595 #define HDP_BASE__INST5_SEG3 0 596 #define HDP_BASE__INST5_SEG4 0 597 #define HDP_BASE__INST5_SEG5 0 598 599 #define HDP_BASE__INST6_SEG0 0 600 #define HDP_BASE__INST6_SEG1 0 601 #define HDP_BASE__INST6_SEG2 0 602 #define HDP_BASE__INST6_SEG3 0 603 #define HDP_BASE__INST6_SEG4 0 604 #define HDP_BASE__INST6_SEG5 0 605 606 #define MMHUB_BASE__INST0_SEG0 0x0001A000 607 #define MMHUB_BASE__INST0_SEG1 0x02408800 608 #define MMHUB_BASE__INST0_SEG2 0 609 #define MMHUB_BASE__INST0_SEG3 0 610 #define MMHUB_BASE__INST0_SEG4 0 611 #define MMHUB_BASE__INST0_SEG5 0 612 613 #define MMHUB_BASE__INST1_SEG0 0 614 #define MMHUB_BASE__INST1_SEG1 0 615 #define MMHUB_BASE__INST1_SEG2 0 616 #define MMHUB_BASE__INST1_SEG3 0 617 #define MMHUB_BASE__INST1_SEG4 0 618 #define MMHUB_BASE__INST1_SEG5 0 619 620 #define MMHUB_BASE__INST2_SEG0 0 621 #define MMHUB_BASE__INST2_SEG1 0 622 #define MMHUB_BASE__INST2_SEG2 0 623 #define MMHUB_BASE__INST2_SEG3 0 624 #define MMHUB_BASE__INST2_SEG4 0 625 #define MMHUB_BASE__INST2_SEG5 0 626 627 #define MMHUB_BASE__INST3_SEG0 0 628 #define MMHUB_BASE__INST3_SEG1 0 629 #define MMHUB_BASE__INST3_SEG2 0 630 #define MMHUB_BASE__INST3_SEG3 0 631 #define MMHUB_BASE__INST3_SEG4 0 632 #define MMHUB_BASE__INST3_SEG5 0 633 634 #define MMHUB_BASE__INST4_SEG0 0 635 #define MMHUB_BASE__INST4_SEG1 0 636 #define MMHUB_BASE__INST4_SEG2 0 637 #define MMHUB_BASE__INST4_SEG3 0 638 #define MMHUB_BASE__INST4_SEG4 0 639 #define MMHUB_BASE__INST4_SEG5 0 640 641 #define MMHUB_BASE__INST5_SEG0 0 642 #define MMHUB_BASE__INST5_SEG1 0 643 #define MMHUB_BASE__INST5_SEG2 0 644 #define MMHUB_BASE__INST5_SEG3 0 645 #define MMHUB_BASE__INST5_SEG4 0 646 #define MMHUB_BASE__INST5_SEG5 0 647 648 #define MMHUB_BASE__INST6_SEG0 0 649 #define MMHUB_BASE__INST6_SEG1 0 650 #define MMHUB_BASE__INST6_SEG2 0 651 #define MMHUB_BASE__INST6_SEG3 0 652 #define MMHUB_BASE__INST6_SEG4 0 653 #define MMHUB_BASE__INST6_SEG5 0 654 655 #define MP0_BASE__INST0_SEG0 0x00016000 656 #define MP0_BASE__INST0_SEG1 0x00DC0000 657 #define MP0_BASE__INST0_SEG2 0x00E00000 658 #define MP0_BASE__INST0_SEG3 0x00E40000 659 #define MP0_BASE__INST0_SEG4 0x0243FC00 660 #define MP0_BASE__INST0_SEG5 0 661 662 #define MP0_BASE__INST1_SEG0 0 663 #define MP0_BASE__INST1_SEG1 0 664 #define MP0_BASE__INST1_SEG2 0 665 #define MP0_BASE__INST1_SEG3 0 666 #define MP0_BASE__INST1_SEG4 0 667 #define MP0_BASE__INST1_SEG5 0 668 669 #define MP0_BASE__INST2_SEG0 0 670 #define MP0_BASE__INST2_SEG1 0 671 #define MP0_BASE__INST2_SEG2 0 672 #define MP0_BASE__INST2_SEG3 0 673 #define MP0_BASE__INST2_SEG4 0 674 #define MP0_BASE__INST2_SEG5 0 675 676 #define MP0_BASE__INST3_SEG0 0 677 #define MP0_BASE__INST3_SEG1 0 678 #define MP0_BASE__INST3_SEG2 0 679 #define MP0_BASE__INST3_SEG3 0 680 #define MP0_BASE__INST3_SEG4 0 681 #define MP0_BASE__INST3_SEG5 0 682 683 #define MP0_BASE__INST4_SEG0 0 684 #define MP0_BASE__INST4_SEG1 0 685 #define MP0_BASE__INST4_SEG2 0 686 #define MP0_BASE__INST4_SEG3 0 687 #define MP0_BASE__INST4_SEG4 0 688 #define MP0_BASE__INST4_SEG5 0 689 690 #define MP0_BASE__INST5_SEG0 0 691 #define MP0_BASE__INST5_SEG1 0 692 #define MP0_BASE__INST5_SEG2 0 693 #define MP0_BASE__INST5_SEG3 0 694 #define MP0_BASE__INST5_SEG4 0 695 #define MP0_BASE__INST5_SEG5 0 696 697 #define MP0_BASE__INST6_SEG0 0 698 #define MP0_BASE__INST6_SEG1 0 699 #define MP0_BASE__INST6_SEG2 0 700 #define MP0_BASE__INST6_SEG3 0 701 #define MP0_BASE__INST6_SEG4 0 702 #define MP0_BASE__INST6_SEG5 0 703 704 #define MP1_BASE__INST0_SEG0 0x00016200 705 #define MP1_BASE__INST0_SEG1 0x00E80000 706 #define MP1_BASE__INST0_SEG2 0x00EC0000 707 #define MP1_BASE__INST0_SEG3 0x00F00000 708 #define MP1_BASE__INST0_SEG4 0x02400400 709 #define MP1_BASE__INST0_SEG5 0 710 711 #define MP1_BASE__INST1_SEG0 0 712 #define MP1_BASE__INST1_SEG1 0 713 #define MP1_BASE__INST1_SEG2 0 714 #define MP1_BASE__INST1_SEG3 0 715 #define MP1_BASE__INST1_SEG4 0 716 #define MP1_BASE__INST1_SEG5 0 717 718 #define MP1_BASE__INST2_SEG0 0 719 #define MP1_BASE__INST2_SEG1 0 720 #define MP1_BASE__INST2_SEG2 0 721 #define MP1_BASE__INST2_SEG3 0 722 #define MP1_BASE__INST2_SEG4 0 723 #define MP1_BASE__INST2_SEG5 0 724 725 #define MP1_BASE__INST3_SEG0 0 726 #define MP1_BASE__INST3_SEG1 0 727 #define MP1_BASE__INST3_SEG2 0 728 #define MP1_BASE__INST3_SEG3 0 729 #define MP1_BASE__INST3_SEG4 0 730 #define MP1_BASE__INST3_SEG5 0 731 732 #define MP1_BASE__INST4_SEG0 0 733 #define MP1_BASE__INST4_SEG1 0 734 #define MP1_BASE__INST4_SEG2 0 735 #define MP1_BASE__INST4_SEG3 0 736 #define MP1_BASE__INST4_SEG4 0 737 #define MP1_BASE__INST4_SEG5 0 738 739 #define MP1_BASE__INST5_SEG0 0 740 #define MP1_BASE__INST5_SEG1 0 741 #define MP1_BASE__INST5_SEG2 0 742 #define MP1_BASE__INST5_SEG3 0 743 #define MP1_BASE__INST5_SEG4 0 744 #define MP1_BASE__INST5_SEG5 0 745 746 #define MP1_BASE__INST6_SEG0 0 747 #define MP1_BASE__INST6_SEG1 0 748 #define MP1_BASE__INST6_SEG2 0 749 #define MP1_BASE__INST6_SEG3 0 750 #define MP1_BASE__INST6_SEG4 0 751 #define MP1_BASE__INST6_SEG5 0 752 753 #define NBIO_BASE__INST0_SEG0 0x00000000 754 #define NBIO_BASE__INST0_SEG1 0x00000014 755 #define NBIO_BASE__INST0_SEG2 0x00000D20 756 #define NBIO_BASE__INST0_SEG3 0x00010400 757 #define NBIO_BASE__INST0_SEG4 0x0241B000 758 #define NBIO_BASE__INST0_SEG5 0x04040000 759 760 #define NBIO_BASE__INST1_SEG0 0 761 #define NBIO_BASE__INST1_SEG1 0 762 #define NBIO_BASE__INST1_SEG2 0 763 #define NBIO_BASE__INST1_SEG3 0 764 #define NBIO_BASE__INST1_SEG4 0 765 #define NBIO_BASE__INST1_SEG5 0 766 767 #define NBIO_BASE__INST2_SEG0 0 768 #define NBIO_BASE__INST2_SEG1 0 769 #define NBIO_BASE__INST2_SEG2 0 770 #define NBIO_BASE__INST2_SEG3 0 771 #define NBIO_BASE__INST2_SEG4 0 772 #define NBIO_BASE__INST2_SEG5 0 773 774 #define NBIO_BASE__INST3_SEG0 0 775 #define NBIO_BASE__INST3_SEG1 0 776 #define NBIO_BASE__INST3_SEG2 0 777 #define NBIO_BASE__INST3_SEG3 0 778 #define NBIO_BASE__INST3_SEG4 0 779 #define NBIO_BASE__INST3_SEG5 0 780 781 #define NBIO_BASE__INST4_SEG0 0 782 #define NBIO_BASE__INST4_SEG1 0 783 #define NBIO_BASE__INST4_SEG2 0 784 #define NBIO_BASE__INST4_SEG3 0 785 #define NBIO_BASE__INST4_SEG4 0 786 #define NBIO_BASE__INST4_SEG5 0 787 788 #define NBIO_BASE__INST5_SEG0 0 789 #define NBIO_BASE__INST5_SEG1 0 790 #define NBIO_BASE__INST5_SEG2 0 791 #define NBIO_BASE__INST5_SEG3 0 792 #define NBIO_BASE__INST5_SEG4 0 793 #define NBIO_BASE__INST5_SEG5 0 794 795 #define NBIO_BASE__INST6_SEG0 0 796 #define NBIO_BASE__INST6_SEG1 0 797 #define NBIO_BASE__INST6_SEG2 0 798 #define NBIO_BASE__INST6_SEG3 0 799 #define NBIO_BASE__INST6_SEG4 0 800 #define NBIO_BASE__INST6_SEG5 0 801 802 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 803 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 804 #define OSSSYS_BASE__INST0_SEG2 0 805 #define OSSSYS_BASE__INST0_SEG3 0 806 #define OSSSYS_BASE__INST0_SEG4 0 807 #define OSSSYS_BASE__INST0_SEG5 0 808 809 #define OSSSYS_BASE__INST1_SEG0 0 810 #define OSSSYS_BASE__INST1_SEG1 0 811 #define OSSSYS_BASE__INST1_SEG2 0 812 #define OSSSYS_BASE__INST1_SEG3 0 813 #define OSSSYS_BASE__INST1_SEG4 0 814 #define OSSSYS_BASE__INST1_SEG5 0 815 816 #define OSSSYS_BASE__INST2_SEG0 0 817 #define OSSSYS_BASE__INST2_SEG1 0 818 #define OSSSYS_BASE__INST2_SEG2 0 819 #define OSSSYS_BASE__INST2_SEG3 0 820 #define OSSSYS_BASE__INST2_SEG4 0 821 #define OSSSYS_BASE__INST2_SEG5 0 822 823 #define OSSSYS_BASE__INST3_SEG0 0 824 #define OSSSYS_BASE__INST3_SEG1 0 825 #define OSSSYS_BASE__INST3_SEG2 0 826 #define OSSSYS_BASE__INST3_SEG3 0 827 #define OSSSYS_BASE__INST3_SEG4 0 828 #define OSSSYS_BASE__INST3_SEG5 0 829 830 #define OSSSYS_BASE__INST4_SEG0 0 831 #define OSSSYS_BASE__INST4_SEG1 0 832 #define OSSSYS_BASE__INST4_SEG2 0 833 #define OSSSYS_BASE__INST4_SEG3 0 834 #define OSSSYS_BASE__INST4_SEG4 0 835 #define OSSSYS_BASE__INST4_SEG5 0 836 837 #define OSSSYS_BASE__INST5_SEG0 0 838 #define OSSSYS_BASE__INST5_SEG1 0 839 #define OSSSYS_BASE__INST5_SEG2 0 840 #define OSSSYS_BASE__INST5_SEG3 0 841 #define OSSSYS_BASE__INST5_SEG4 0 842 #define OSSSYS_BASE__INST5_SEG5 0 843 844 #define OSSSYS_BASE__INST6_SEG0 0 845 #define OSSSYS_BASE__INST6_SEG1 0 846 #define OSSSYS_BASE__INST6_SEG2 0 847 #define OSSSYS_BASE__INST6_SEG3 0 848 #define OSSSYS_BASE__INST6_SEG4 0 849 #define OSSSYS_BASE__INST6_SEG5 0 850 851 #define SMUIO_BASE__INST0_SEG0 0x00016800 852 #define SMUIO_BASE__INST0_SEG1 0x00016A00 853 #define SMUIO_BASE__INST0_SEG2 0x00440000 854 #define SMUIO_BASE__INST0_SEG3 0x02401000 855 #define SMUIO_BASE__INST0_SEG4 0 856 #define SMUIO_BASE__INST0_SEG5 0 857 858 #define SMUIO_BASE__INST1_SEG0 0 859 #define SMUIO_BASE__INST1_SEG1 0 860 #define SMUIO_BASE__INST1_SEG2 0 861 #define SMUIO_BASE__INST1_SEG3 0 862 #define SMUIO_BASE__INST1_SEG4 0 863 #define SMUIO_BASE__INST1_SEG5 0 864 865 #define SMUIO_BASE__INST2_SEG0 0 866 #define SMUIO_BASE__INST2_SEG1 0 867 #define SMUIO_BASE__INST2_SEG2 0 868 #define SMUIO_BASE__INST2_SEG3 0 869 #define SMUIO_BASE__INST2_SEG4 0 870 #define SMUIO_BASE__INST2_SEG5 0 871 872 #define SMUIO_BASE__INST3_SEG0 0 873 #define SMUIO_BASE__INST3_SEG1 0 874 #define SMUIO_BASE__INST3_SEG2 0 875 #define SMUIO_BASE__INST3_SEG3 0 876 #define SMUIO_BASE__INST3_SEG4 0 877 #define SMUIO_BASE__INST3_SEG5 0 878 879 #define SMUIO_BASE__INST4_SEG0 0 880 #define SMUIO_BASE__INST4_SEG1 0 881 #define SMUIO_BASE__INST4_SEG2 0 882 #define SMUIO_BASE__INST4_SEG3 0 883 #define SMUIO_BASE__INST4_SEG4 0 884 #define SMUIO_BASE__INST4_SEG5 0 885 886 #define SMUIO_BASE__INST5_SEG0 0 887 #define SMUIO_BASE__INST5_SEG1 0 888 #define SMUIO_BASE__INST5_SEG2 0 889 #define SMUIO_BASE__INST5_SEG3 0 890 #define SMUIO_BASE__INST5_SEG4 0 891 #define SMUIO_BASE__INST5_SEG5 0 892 893 #define SMUIO_BASE__INST6_SEG0 0 894 #define SMUIO_BASE__INST6_SEG1 0 895 #define SMUIO_BASE__INST6_SEG2 0 896 #define SMUIO_BASE__INST6_SEG3 0 897 #define SMUIO_BASE__INST6_SEG4 0 898 #define SMUIO_BASE__INST6_SEG5 0 899 900 #define THM_BASE__INST0_SEG0 0x00016600 901 #define THM_BASE__INST0_SEG1 0x02400C00 902 #define THM_BASE__INST0_SEG2 0 903 #define THM_BASE__INST0_SEG3 0 904 #define THM_BASE__INST0_SEG4 0 905 #define THM_BASE__INST0_SEG5 0 906 907 #define THM_BASE__INST1_SEG0 0 908 #define THM_BASE__INST1_SEG1 0 909 #define THM_BASE__INST1_SEG2 0 910 #define THM_BASE__INST1_SEG3 0 911 #define THM_BASE__INST1_SEG4 0 912 #define THM_BASE__INST1_SEG5 0 913 914 #define THM_BASE__INST2_SEG0 0 915 #define THM_BASE__INST2_SEG1 0 916 #define THM_BASE__INST2_SEG2 0 917 #define THM_BASE__INST2_SEG3 0 918 #define THM_BASE__INST2_SEG4 0 919 #define THM_BASE__INST2_SEG5 0 920 921 #define THM_BASE__INST3_SEG0 0 922 #define THM_BASE__INST3_SEG1 0 923 #define THM_BASE__INST3_SEG2 0 924 #define THM_BASE__INST3_SEG3 0 925 #define THM_BASE__INST3_SEG4 0 926 #define THM_BASE__INST3_SEG5 0 927 928 #define THM_BASE__INST4_SEG0 0 929 #define THM_BASE__INST4_SEG1 0 930 #define THM_BASE__INST4_SEG2 0 931 #define THM_BASE__INST4_SEG3 0 932 #define THM_BASE__INST4_SEG4 0 933 #define THM_BASE__INST4_SEG5 0 934 935 #define THM_BASE__INST5_SEG0 0 936 #define THM_BASE__INST5_SEG1 0 937 #define THM_BASE__INST5_SEG2 0 938 #define THM_BASE__INST5_SEG3 0 939 #define THM_BASE__INST5_SEG4 0 940 #define THM_BASE__INST5_SEG5 0 941 942 #define THM_BASE__INST6_SEG0 0 943 #define THM_BASE__INST6_SEG1 0 944 #define THM_BASE__INST6_SEG2 0 945 #define THM_BASE__INST6_SEG3 0 946 #define THM_BASE__INST6_SEG4 0 947 #define THM_BASE__INST6_SEG5 0 948 949 #define UMC_BASE__INST0_SEG0 0x00014000 950 #define UMC_BASE__INST0_SEG1 0x02425800 951 #define UMC_BASE__INST0_SEG2 0 952 #define UMC_BASE__INST0_SEG3 0 953 #define UMC_BASE__INST0_SEG4 0 954 #define UMC_BASE__INST0_SEG5 0 955 956 #define UMC_BASE__INST1_SEG0 0x00054000 957 #define UMC_BASE__INST1_SEG1 0x02425C00 958 #define UMC_BASE__INST1_SEG2 0 959 #define UMC_BASE__INST1_SEG3 0 960 #define UMC_BASE__INST1_SEG4 0 961 #define UMC_BASE__INST1_SEG5 0 962 963 #define UMC_BASE__INST2_SEG0 0x00094000 964 #define UMC_BASE__INST2_SEG1 0x02426000 965 #define UMC_BASE__INST2_SEG2 0 966 #define UMC_BASE__INST2_SEG3 0 967 #define UMC_BASE__INST2_SEG4 0 968 #define UMC_BASE__INST2_SEG5 0 969 970 #define UMC_BASE__INST3_SEG0 0x000D4000 971 #define UMC_BASE__INST3_SEG1 0x02426400 972 #define UMC_BASE__INST3_SEG2 0 973 #define UMC_BASE__INST3_SEG3 0 974 #define UMC_BASE__INST3_SEG4 0 975 #define UMC_BASE__INST3_SEG5 0 976 977 #define UMC_BASE__INST4_SEG0 0 978 #define UMC_BASE__INST4_SEG1 0 979 #define UMC_BASE__INST4_SEG2 0 980 #define UMC_BASE__INST4_SEG3 0 981 #define UMC_BASE__INST4_SEG4 0 982 #define UMC_BASE__INST4_SEG5 0 983 984 #define UMC_BASE__INST5_SEG0 0 985 #define UMC_BASE__INST5_SEG1 0 986 #define UMC_BASE__INST5_SEG2 0 987 #define UMC_BASE__INST5_SEG3 0 988 #define UMC_BASE__INST5_SEG4 0 989 #define UMC_BASE__INST5_SEG5 0 990 991 #define UMC_BASE__INST6_SEG0 0 992 #define UMC_BASE__INST6_SEG1 0 993 #define UMC_BASE__INST6_SEG2 0 994 #define UMC_BASE__INST6_SEG3 0 995 #define UMC_BASE__INST6_SEG4 0 996 #define UMC_BASE__INST6_SEG5 0 997 998 #define VCN0_BASE__INST0_SEG0 0x00007800 999 #define VCN0_BASE__INST0_SEG1 0x00007E00 1000 #define VCN0_BASE__INST0_SEG2 0x02403000 1001 #define VCN0_BASE__INST0_SEG3 0 1002 #define VCN0_BASE__INST0_SEG4 0 1003 #define VCN0_BASE__INST0_SEG5 0 1004 1005 #define VCN0_BASE__INST1_SEG0 0 1006 #define VCN0_BASE__INST1_SEG1 0 1007 #define VCN0_BASE__INST1_SEG2 0 1008 #define VCN0_BASE__INST1_SEG3 0 1009 #define VCN0_BASE__INST1_SEG4 0 1010 #define VCN0_BASE__INST1_SEG5 0 1011 1012 #define VCN0_BASE__INST2_SEG0 0 1013 #define VCN0_BASE__INST2_SEG1 0 1014 #define VCN0_BASE__INST2_SEG2 0 1015 #define VCN0_BASE__INST2_SEG3 0 1016 #define VCN0_BASE__INST2_SEG4 0 1017 #define VCN0_BASE__INST2_SEG5 0 1018 1019 #define VCN0_BASE__INST3_SEG0 0 1020 #define VCN0_BASE__INST3_SEG1 0 1021 #define VCN0_BASE__INST3_SEG2 0 1022 #define VCN0_BASE__INST3_SEG3 0 1023 #define VCN0_BASE__INST3_SEG4 0 1024 #define VCN0_BASE__INST3_SEG5 0 1025 1026 #define VCN0_BASE__INST4_SEG0 0 1027 #define VCN0_BASE__INST4_SEG1 0 1028 #define VCN0_BASE__INST4_SEG2 0 1029 #define VCN0_BASE__INST4_SEG3 0 1030 #define VCN0_BASE__INST4_SEG4 0 1031 #define VCN0_BASE__INST4_SEG5 0 1032 1033 #define VCN0_BASE__INST5_SEG0 0 1034 #define VCN0_BASE__INST5_SEG1 0 1035 #define VCN0_BASE__INST5_SEG2 0 1036 #define VCN0_BASE__INST5_SEG3 0 1037 #define VCN0_BASE__INST5_SEG4 0 1038 #define VCN0_BASE__INST5_SEG5 0 1039 1040 #define VCN0_BASE__INST6_SEG0 0 1041 #define VCN0_BASE__INST6_SEG1 0 1042 #define VCN0_BASE__INST6_SEG2 0 1043 #define VCN0_BASE__INST6_SEG3 0 1044 #define VCN0_BASE__INST6_SEG4 0 1045 #define VCN0_BASE__INST6_SEG5 0 1046 1047 #endif 1048