1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #ifndef _CGS_COMMON_H 25 #define _CGS_COMMON_H 26 27 #include "amd_shared.h" 28 29 struct cgs_device; 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG__AUDIO_ENDPT 53 }; 54 55 /** 56 * enum cgs_clock - Clocks controlled by the SMU 57 */ 58 enum cgs_clock { 59 CGS_CLOCK__SCLK, 60 CGS_CLOCK__MCLK, 61 CGS_CLOCK__VCLK, 62 CGS_CLOCK__DCLK, 63 CGS_CLOCK__ECLK, 64 CGS_CLOCK__ACLK, 65 CGS_CLOCK__ICLK, 66 /* ... */ 67 }; 68 69 /** 70 * enum cgs_engine - Engines that can be statically power-gated 71 */ 72 enum cgs_engine { 73 CGS_ENGINE__UVD, 74 CGS_ENGINE__VCE, 75 CGS_ENGINE__VP8, 76 CGS_ENGINE__ACP_DMA, 77 CGS_ENGINE__ACP_DSP0, 78 CGS_ENGINE__ACP_DSP1, 79 CGS_ENGINE__ISP, 80 /* ... */ 81 }; 82 83 /** 84 * enum cgs_voltage_planes - Voltage planes for external camera HW 85 */ 86 enum cgs_voltage_planes { 87 CGS_VOLTAGE_PLANE__SENSOR0, 88 CGS_VOLTAGE_PLANE__SENSOR1, 89 /* ... */ 90 }; 91 92 /* 93 * enum cgs_ucode_id - Firmware types for different IPs 94 */ 95 enum cgs_ucode_id { 96 CGS_UCODE_ID_SMU = 0, 97 CGS_UCODE_ID_SDMA0, 98 CGS_UCODE_ID_SDMA1, 99 CGS_UCODE_ID_CP_CE, 100 CGS_UCODE_ID_CP_PFP, 101 CGS_UCODE_ID_CP_ME, 102 CGS_UCODE_ID_CP_MEC, 103 CGS_UCODE_ID_CP_MEC_JT1, 104 CGS_UCODE_ID_CP_MEC_JT2, 105 CGS_UCODE_ID_GMCON_RENG, 106 CGS_UCODE_ID_RLC_G, 107 CGS_UCODE_ID_MAXIMUM, 108 }; 109 110 enum cgs_system_info_id { 111 CGS_SYSTEM_INFO_ADAPTER_BDF_ID = 1, 112 CGS_SYSTEM_INFO_PCIE_GEN_INFO, 113 CGS_SYSTEM_INFO_PCIE_MLW, 114 CGS_SYSTEM_INFO_CG_FLAGS, 115 CGS_SYSTEM_INFO_PG_FLAGS, 116 CGS_SYSTEM_INFO_ID_MAXIMUM, 117 }; 118 119 struct cgs_system_info { 120 uint64_t size; 121 uint64_t info_id; 122 union { 123 void *ptr; 124 uint64_t value; 125 }; 126 uint64_t padding[13]; 127 }; 128 129 /* 130 * enum cgs_resource_type - GPU resource type 131 */ 132 enum cgs_resource_type { 133 CGS_RESOURCE_TYPE_MMIO = 0, 134 CGS_RESOURCE_TYPE_FB, 135 CGS_RESOURCE_TYPE_IO, 136 CGS_RESOURCE_TYPE_DOORBELL, 137 CGS_RESOURCE_TYPE_ROM, 138 }; 139 140 /** 141 * struct cgs_clock_limits - Clock limits 142 * 143 * Clocks are specified in 10KHz units. 144 */ 145 struct cgs_clock_limits { 146 unsigned min; /**< Minimum supported frequency */ 147 unsigned max; /**< Maxumim supported frequency */ 148 unsigned sustainable; /**< Thermally sustainable frequency */ 149 }; 150 151 /** 152 * struct cgs_firmware_info - Firmware information 153 */ 154 struct cgs_firmware_info { 155 uint16_t version; 156 uint16_t feature_version; 157 uint32_t image_size; 158 uint64_t mc_addr; 159 void *kptr; 160 }; 161 162 struct cgs_mode_info { 163 uint32_t refresh_rate; 164 uint32_t ref_clock; 165 uint32_t vblank_time_us; 166 }; 167 168 struct cgs_display_info { 169 uint32_t display_count; 170 uint32_t active_display_mask; 171 struct cgs_mode_info *mode_info; 172 }; 173 174 typedef unsigned long cgs_handle_t; 175 176 #define CGS_ACPI_METHOD_ATCS 0x53435441 177 #define CGS_ACPI_METHOD_ATIF 0x46495441 178 #define CGS_ACPI_METHOD_ATPX 0x58505441 179 #define CGS_ACPI_FIELD_METHOD_NAME 0x00000001 180 #define CGS_ACPI_FIELD_INPUT_ARGUMENT_COUNT 0x00000002 181 #define CGS_ACPI_MAX_BUFFER_SIZE 256 182 #define CGS_ACPI_TYPE_ANY 0x00 183 #define CGS_ACPI_TYPE_INTEGER 0x01 184 #define CGS_ACPI_TYPE_STRING 0x02 185 #define CGS_ACPI_TYPE_BUFFER 0x03 186 #define CGS_ACPI_TYPE_PACKAGE 0x04 187 188 struct cgs_acpi_method_argument { 189 uint32_t type; 190 uint32_t method_length; 191 uint32_t data_length; 192 union{ 193 uint32_t value; 194 void *pointer; 195 }; 196 }; 197 198 struct cgs_acpi_method_info { 199 uint32_t size; 200 uint32_t field; 201 uint32_t input_count; 202 uint32_t name; 203 struct cgs_acpi_method_argument *pinput_argument; 204 uint32_t output_count; 205 struct cgs_acpi_method_argument *poutput_argument; 206 uint32_t padding[9]; 207 }; 208 209 /** 210 * cgs_gpu_mem_info() - Return information about memory heaps 211 * @cgs_device: opaque device handle 212 * @type: memory type 213 * @mc_start: Start MC address of the heap (output) 214 * @mc_size: MC address space size (output) 215 * @mem_size: maximum amount of memory available for allocation (output) 216 * 217 * This function returns information about memory heaps. The type 218 * parameter is used to select the memory heap. The mc_start and 219 * mc_size for GART heaps may be bigger than the memory available for 220 * allocation. 221 * 222 * mc_start and mc_size are undefined for non-contiguous FB memory 223 * types, since buffers allocated with these types may or may not be 224 * GART mapped. 225 * 226 * Return: 0 on success, -errno otherwise 227 */ 228 typedef int (*cgs_gpu_mem_info_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 229 uint64_t *mc_start, uint64_t *mc_size, 230 uint64_t *mem_size); 231 232 /** 233 * cgs_gmap_kmem() - map kernel memory to GART aperture 234 * @cgs_device: opaque device handle 235 * @kmem: pointer to kernel memory 236 * @size: size to map 237 * @min_offset: minimum offset from start of GART aperture 238 * @max_offset: maximum offset from start of GART aperture 239 * @kmem_handle: kernel memory handle (output) 240 * @mcaddr: MC address (output) 241 * 242 * Return: 0 on success, -errno otherwise 243 */ 244 typedef int (*cgs_gmap_kmem_t)(struct cgs_device *cgs_device, void *kmem, uint64_t size, 245 uint64_t min_offset, uint64_t max_offset, 246 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 247 248 /** 249 * cgs_gunmap_kmem() - unmap kernel memory 250 * @cgs_device: opaque device handle 251 * @kmem_handle: kernel memory handle returned by gmap_kmem 252 * 253 * Return: 0 on success, -errno otherwise 254 */ 255 typedef int (*cgs_gunmap_kmem_t)(struct cgs_device *cgs_device, cgs_handle_t kmem_handle); 256 257 /** 258 * cgs_alloc_gpu_mem() - Allocate GPU memory 259 * @cgs_device: opaque device handle 260 * @type: memory type 261 * @size: size in bytes 262 * @align: alignment in bytes 263 * @min_offset: minimum offset from start of heap 264 * @max_offset: maximum offset from start of heap 265 * @handle: memory handle (output) 266 * 267 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 268 * memory allocation. This guarantees that the MC address returned by 269 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 270 * FB memory types may be GART mapped depending on memory 271 * fragmentation and memory allocator policies. 272 * 273 * If min/max_offset are non-0, the allocation will be forced to 274 * reside between these offsets in its respective memory heap. The 275 * base address that the offset relates to, depends on the memory 276 * type. 277 * 278 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 279 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 280 * - others: undefined, don't use with max_offset 281 * 282 * Return: 0 on success, -errno otherwise 283 */ 284 typedef int (*cgs_alloc_gpu_mem_t)(struct cgs_device *cgs_device, enum cgs_gpu_mem_type type, 285 uint64_t size, uint64_t align, 286 uint64_t min_offset, uint64_t max_offset, 287 cgs_handle_t *handle); 288 289 /** 290 * cgs_free_gpu_mem() - Free GPU memory 291 * @cgs_device: opaque device handle 292 * @handle: memory handle returned by alloc or import 293 * 294 * Return: 0 on success, -errno otherwise 295 */ 296 typedef int (*cgs_free_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 297 298 /** 299 * cgs_gmap_gpu_mem() - GPU-map GPU memory 300 * @cgs_device: opaque device handle 301 * @handle: memory handle returned by alloc or import 302 * @mcaddr: MC address (output) 303 * 304 * Ensures that a buffer is GPU accessible and returns its MC address. 305 * 306 * Return: 0 on success, -errno otherwise 307 */ 308 typedef int (*cgs_gmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 309 uint64_t *mcaddr); 310 311 /** 312 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 313 * @cgs_device: opaque device handle 314 * @handle: memory handle returned by alloc or import 315 * 316 * Allows the buffer to be migrated while it's not used by the GPU. 317 * 318 * Return: 0 on success, -errno otherwise 319 */ 320 typedef int (*cgs_gunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 321 322 /** 323 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 324 * 325 * @cgs_device: opaque device handle 326 * @handle: memory handle returned by alloc or import 327 * @map: Kernel virtual address the memory was mapped to (output) 328 * 329 * Return: 0 on success, -errno otherwise 330 */ 331 typedef int (*cgs_kmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle, 332 void **map); 333 334 /** 335 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 336 * @cgs_device: opaque device handle 337 * @handle: memory handle returned by alloc or import 338 * 339 * Return: 0 on success, -errno otherwise 340 */ 341 typedef int (*cgs_kunmap_gpu_mem_t)(struct cgs_device *cgs_device, cgs_handle_t handle); 342 343 /** 344 * cgs_read_register() - Read an MMIO register 345 * @cgs_device: opaque device handle 346 * @offset: register offset 347 * 348 * Return: register value 349 */ 350 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 351 352 /** 353 * cgs_write_register() - Write an MMIO register 354 * @cgs_device: opaque device handle 355 * @offset: register offset 356 * @value: register value 357 */ 358 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 359 uint32_t value); 360 361 /** 362 * cgs_read_ind_register() - Read an indirect register 363 * @cgs_device: opaque device handle 364 * @offset: register offset 365 * 366 * Return: register value 367 */ 368 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 369 unsigned index); 370 371 /** 372 * cgs_write_ind_register() - Write an indirect register 373 * @cgs_device: opaque device handle 374 * @offset: register offset 375 * @value: register value 376 */ 377 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 378 unsigned index, uint32_t value); 379 380 /** 381 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 382 * @cgs_device: opaque device handle 383 * @addr: address 384 * 385 * Return: Value read 386 */ 387 typedef uint8_t (*cgs_read_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr); 388 389 /** 390 * cgs_read_pci_config_word() - Read word from PCI configuration space 391 * @cgs_device: opaque device handle 392 * @addr: address, must be word-aligned 393 * 394 * Return: Value read 395 */ 396 typedef uint16_t (*cgs_read_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr); 397 398 /** 399 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 400 * @cgs_device: opaque device handle 401 * @addr: address, must be dword-aligned 402 * 403 * Return: Value read 404 */ 405 typedef uint32_t (*cgs_read_pci_config_dword_t)(struct cgs_device *cgs_device, 406 unsigned addr); 407 408 /** 409 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 410 * @cgs_device: opaque device handle 411 * @addr: address 412 * @value: value to write 413 */ 414 typedef void (*cgs_write_pci_config_byte_t)(struct cgs_device *cgs_device, unsigned addr, 415 uint8_t value); 416 417 /** 418 * cgs_write_pci_config_word() - Write byte to PCI configuration space 419 * @cgs_device: opaque device handle 420 * @addr: address, must be word-aligned 421 * @value: value to write 422 */ 423 typedef void (*cgs_write_pci_config_word_t)(struct cgs_device *cgs_device, unsigned addr, 424 uint16_t value); 425 426 /** 427 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 428 * @cgs_device: opaque device handle 429 * @addr: address, must be dword-aligned 430 * @value: value to write 431 */ 432 typedef void (*cgs_write_pci_config_dword_t)(struct cgs_device *cgs_device, unsigned addr, 433 uint32_t value); 434 435 436 /** 437 * cgs_get_pci_resource() - provide access to a device resource (PCI BAR) 438 * @cgs_device: opaque device handle 439 * @resource_type: Type of Resource (MMIO, IO, ROM, FB, DOORBELL) 440 * @size: size of the region 441 * @offset: offset from the start of the region 442 * @resource_base: base address (not including offset) returned 443 * 444 * Return: 0 on success, -errno otherwise 445 */ 446 typedef int (*cgs_get_pci_resource_t)(struct cgs_device *cgs_device, 447 enum cgs_resource_type resource_type, 448 uint64_t size, 449 uint64_t offset, 450 uint64_t *resource_base); 451 452 /** 453 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 454 * @cgs_device: opaque device handle 455 * @table: data table index 456 * @size: size of the table (output, may be NULL) 457 * @frev: table format revision (output, may be NULL) 458 * @crev: table content revision (output, may be NULL) 459 * 460 * Return: Pointer to start of the table, or NULL on failure 461 */ 462 typedef const void *(*cgs_atom_get_data_table_t)( 463 struct cgs_device *cgs_device, unsigned table, 464 uint16_t *size, uint8_t *frev, uint8_t *crev); 465 466 /** 467 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 468 * @cgs_device: opaque device handle 469 * @table: data table index 470 * @frev: table format revision (output, may be NULL) 471 * @crev: table content revision (output, may be NULL) 472 * 473 * Return: 0 on success, -errno otherwise 474 */ 475 typedef int (*cgs_atom_get_cmd_table_revs_t)(struct cgs_device *cgs_device, unsigned table, 476 uint8_t *frev, uint8_t *crev); 477 478 /** 479 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 480 * @cgs_device: opaque device handle 481 * @table: command table index 482 * @args: arguments 483 * 484 * Return: 0 on success, -errno otherwise 485 */ 486 typedef int (*cgs_atom_exec_cmd_table_t)(struct cgs_device *cgs_device, 487 unsigned table, void *args); 488 489 /** 490 * cgs_create_pm_request() - Create a power management request 491 * @cgs_device: opaque device handle 492 * @request: handle of created PM request (output) 493 * 494 * Return: 0 on success, -errno otherwise 495 */ 496 typedef int (*cgs_create_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t *request); 497 498 /** 499 * cgs_destroy_pm_request() - Destroy a power management request 500 * @cgs_device: opaque device handle 501 * @request: handle of created PM request 502 * 503 * Return: 0 on success, -errno otherwise 504 */ 505 typedef int (*cgs_destroy_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request); 506 507 /** 508 * cgs_set_pm_request() - Activate or deactiveate a PM request 509 * @cgs_device: opaque device handle 510 * @request: PM request handle 511 * @active: 0 = deactivate, non-0 = activate 512 * 513 * While a PM request is active, its minimum clock requests are taken 514 * into account as the requested engines are powered up. When the 515 * request is inactive, the engines may be powered down and clocks may 516 * be lower, depending on other PM requests by other driver 517 * components. 518 * 519 * Return: 0 on success, -errno otherwise 520 */ 521 typedef int (*cgs_set_pm_request_t)(struct cgs_device *cgs_device, cgs_handle_t request, 522 int active); 523 524 /** 525 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 526 * @cgs_device: opaque device handle 527 * @request: PM request handle 528 * @clock: which clock? 529 * @freq: requested min. frequency in 10KHz units (0 to clear request) 530 * 531 * Return: 0 on success, -errno otherwise 532 */ 533 typedef int (*cgs_pm_request_clock_t)(struct cgs_device *cgs_device, cgs_handle_t request, 534 enum cgs_clock clock, unsigned freq); 535 536 /** 537 * cgs_pm_request_engine() - Request an engine to be powered up 538 * @cgs_device: opaque device handle 539 * @request: PM request handle 540 * @engine: which engine? 541 * @powered: 0 = powered down, non-0 = powered up 542 * 543 * Return: 0 on success, -errno otherwise 544 */ 545 typedef int (*cgs_pm_request_engine_t)(struct cgs_device *cgs_device, cgs_handle_t request, 546 enum cgs_engine engine, int powered); 547 548 /** 549 * cgs_pm_query_clock_limits() - Query clock frequency limits 550 * @cgs_device: opaque device handle 551 * @clock: which clock? 552 * @limits: clock limits 553 * 554 * Return: 0 on success, -errno otherwise 555 */ 556 typedef int (*cgs_pm_query_clock_limits_t)(struct cgs_device *cgs_device, 557 enum cgs_clock clock, 558 struct cgs_clock_limits *limits); 559 560 /** 561 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 562 * @cgs_device: opaque device handle 563 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 564 * @voltages: pointer to array of voltage values in 1mV units 565 * 566 * Return: 0 on success, -errno otherwise 567 */ 568 typedef int (*cgs_set_camera_voltages_t)(struct cgs_device *cgs_device, uint32_t mask, 569 const uint32_t *voltages); 570 /** 571 * cgs_get_firmware_info - Get the firmware information from core driver 572 * @cgs_device: opaque device handle 573 * @type: the firmware type 574 * @info: returend firmware information 575 * 576 * Return: 0 on success, -errno otherwise 577 */ 578 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 579 enum cgs_ucode_id type, 580 struct cgs_firmware_info *info); 581 582 typedef int(*cgs_set_powergating_state)(struct cgs_device *cgs_device, 583 enum amd_ip_block_type block_type, 584 enum amd_powergating_state state); 585 586 typedef int(*cgs_set_clockgating_state)(struct cgs_device *cgs_device, 587 enum amd_ip_block_type block_type, 588 enum amd_clockgating_state state); 589 590 typedef int(*cgs_get_active_displays_info)( 591 struct cgs_device *cgs_device, 592 struct cgs_display_info *info); 593 594 typedef int (*cgs_notify_dpm_enabled)(struct cgs_device *cgs_device, bool enabled); 595 596 typedef int (*cgs_call_acpi_method)(struct cgs_device *cgs_device, 597 uint32_t acpi_method, 598 uint32_t acpi_function, 599 void *pinput, void *poutput, 600 uint32_t output_count, 601 uint32_t input_size, 602 uint32_t output_size); 603 604 typedef int (*cgs_query_system_info)(struct cgs_device *cgs_device, 605 struct cgs_system_info *sys_info); 606 607 struct cgs_ops { 608 /* memory management calls (similar to KFD interface) */ 609 cgs_gpu_mem_info_t gpu_mem_info; 610 cgs_gmap_kmem_t gmap_kmem; 611 cgs_gunmap_kmem_t gunmap_kmem; 612 cgs_alloc_gpu_mem_t alloc_gpu_mem; 613 cgs_free_gpu_mem_t free_gpu_mem; 614 cgs_gmap_gpu_mem_t gmap_gpu_mem; 615 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 616 cgs_kmap_gpu_mem_t kmap_gpu_mem; 617 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 618 /* MMIO access */ 619 cgs_read_register_t read_register; 620 cgs_write_register_t write_register; 621 cgs_read_ind_register_t read_ind_register; 622 cgs_write_ind_register_t write_ind_register; 623 /* PCI configuration space access */ 624 cgs_read_pci_config_byte_t read_pci_config_byte; 625 cgs_read_pci_config_word_t read_pci_config_word; 626 cgs_read_pci_config_dword_t read_pci_config_dword; 627 cgs_write_pci_config_byte_t write_pci_config_byte; 628 cgs_write_pci_config_word_t write_pci_config_word; 629 cgs_write_pci_config_dword_t write_pci_config_dword; 630 /* PCI resources */ 631 cgs_get_pci_resource_t get_pci_resource; 632 /* ATOM BIOS */ 633 cgs_atom_get_data_table_t atom_get_data_table; 634 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 635 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 636 /* Power management */ 637 cgs_create_pm_request_t create_pm_request; 638 cgs_destroy_pm_request_t destroy_pm_request; 639 cgs_set_pm_request_t set_pm_request; 640 cgs_pm_request_clock_t pm_request_clock; 641 cgs_pm_request_engine_t pm_request_engine; 642 cgs_pm_query_clock_limits_t pm_query_clock_limits; 643 cgs_set_camera_voltages_t set_camera_voltages; 644 /* Firmware Info */ 645 cgs_get_firmware_info get_firmware_info; 646 /* cg pg interface*/ 647 cgs_set_powergating_state set_powergating_state; 648 cgs_set_clockgating_state set_clockgating_state; 649 /* display manager */ 650 cgs_get_active_displays_info get_active_displays_info; 651 /* notify dpm enabled */ 652 cgs_notify_dpm_enabled notify_dpm_enabled; 653 /* ACPI */ 654 cgs_call_acpi_method call_acpi_method; 655 /* get system info */ 656 cgs_query_system_info query_system_info; 657 }; 658 659 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 660 661 struct cgs_device 662 { 663 const struct cgs_ops *ops; 664 const struct cgs_os_ops *os_ops; 665 /* to be embedded at the start of driver private structure */ 666 }; 667 668 /* Convenience macros that make CGS indirect function calls look like 669 * normal function calls */ 670 #define CGS_CALL(func,dev,...) \ 671 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 672 #define CGS_OS_CALL(func,dev,...) \ 673 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 674 675 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 676 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 677 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 678 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 679 #define cgs_gunmap_kmem(dev,kmem_handle) \ 680 CGS_CALL(gunmap_kmem,dev,keme_handle) 681 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 682 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 683 #define cgs_free_gpu_mem(dev,handle) \ 684 CGS_CALL(free_gpu_mem,dev,handle) 685 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 686 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 687 #define cgs_gunmap_gpu_mem(dev,handle) \ 688 CGS_CALL(gunmap_gpu_mem,dev,handle) 689 #define cgs_kmap_gpu_mem(dev,handle,map) \ 690 CGS_CALL(kmap_gpu_mem,dev,handle,map) 691 #define cgs_kunmap_gpu_mem(dev,handle) \ 692 CGS_CALL(kunmap_gpu_mem,dev,handle) 693 694 #define cgs_read_register(dev,offset) \ 695 CGS_CALL(read_register,dev,offset) 696 #define cgs_write_register(dev,offset,value) \ 697 CGS_CALL(write_register,dev,offset,value) 698 #define cgs_read_ind_register(dev,space,index) \ 699 CGS_CALL(read_ind_register,dev,space,index) 700 #define cgs_write_ind_register(dev,space,index,value) \ 701 CGS_CALL(write_ind_register,dev,space,index,value) 702 703 #define cgs_read_pci_config_byte(dev,addr) \ 704 CGS_CALL(read_pci_config_byte,dev,addr) 705 #define cgs_read_pci_config_word(dev,addr) \ 706 CGS_CALL(read_pci_config_word,dev,addr) 707 #define cgs_read_pci_config_dword(dev,addr) \ 708 CGS_CALL(read_pci_config_dword,dev,addr) 709 #define cgs_write_pci_config_byte(dev,addr,value) \ 710 CGS_CALL(write_pci_config_byte,dev,addr,value) 711 #define cgs_write_pci_config_word(dev,addr,value) \ 712 CGS_CALL(write_pci_config_word,dev,addr,value) 713 #define cgs_write_pci_config_dword(dev,addr,value) \ 714 CGS_CALL(write_pci_config_dword,dev,addr,value) 715 716 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 717 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 718 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 719 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 720 #define cgs_atom_exec_cmd_table(dev,table,args) \ 721 CGS_CALL(atom_exec_cmd_table,dev,table,args) 722 723 #define cgs_create_pm_request(dev,request) \ 724 CGS_CALL(create_pm_request,dev,request) 725 #define cgs_destroy_pm_request(dev,request) \ 726 CGS_CALL(destroy_pm_request,dev,request) 727 #define cgs_set_pm_request(dev,request,active) \ 728 CGS_CALL(set_pm_request,dev,request,active) 729 #define cgs_pm_request_clock(dev,request,clock,freq) \ 730 CGS_CALL(pm_request_clock,dev,request,clock,freq) 731 #define cgs_pm_request_engine(dev,request,engine,powered) \ 732 CGS_CALL(pm_request_engine,dev,request,engine,powered) 733 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 734 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 735 #define cgs_set_camera_voltages(dev,mask,voltages) \ 736 CGS_CALL(set_camera_voltages,dev,mask,voltages) 737 #define cgs_get_firmware_info(dev, type, info) \ 738 CGS_CALL(get_firmware_info, dev, type, info) 739 #define cgs_set_powergating_state(dev, block_type, state) \ 740 CGS_CALL(set_powergating_state, dev, block_type, state) 741 #define cgs_set_clockgating_state(dev, block_type, state) \ 742 CGS_CALL(set_clockgating_state, dev, block_type, state) 743 #define cgs_notify_dpm_enabled(dev, enabled) \ 744 CGS_CALL(notify_dpm_enabled, dev, enabled) 745 746 #define cgs_get_active_displays_info(dev, info) \ 747 CGS_CALL(get_active_displays_info, dev, info) 748 749 #define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 750 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 751 #define cgs_query_system_info(dev, sys_info) \ 752 CGS_CALL(query_system_info, dev, sys_info) 753 #define cgs_get_pci_resource(cgs_device, resource_type, size, offset, \ 754 resource_base) \ 755 CGS_CALL(get_pci_resource, cgs_device, resource_type, size, offset, \ 756 resource_base) 757 758 #endif /* _CGS_COMMON_H */ 759