1 /* 2 * Copyright (C) 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _beige_goby_ip_offset_HEADER 22 #define _beige_goby_ip_offset_HEADER 23 24 25 #define MAX_INSTANCE 7 26 #define MAX_SEGMENT 6 27 28 29 struct IP_BASE_INSTANCE { 30 unsigned int segment[MAX_SEGMENT]; 31 }; 32 33 struct IP_BASE { 34 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 35 }; 36 37 38 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } }, 39 { { 0, 0, 0, 0, 0, 0 } }, 40 { { 0, 0, 0, 0, 0, 0 } }, 41 { { 0, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } } } }; 45 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 46 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 47 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 48 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 49 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 50 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 51 { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } }; 52 static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } }, 53 { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } } } }; 59 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0, 0 } } } }; 66 static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } } } }; 73 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } } } }; 80 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } } } }; 87 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } }, 89 { { 0, 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } } } }; 94 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } } } }; 101 static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } } } }; 108 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } } } }; 115 static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0, 0 } } } }; 122 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } } } }; 129 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } }, 131 { { 0, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } } } }; 136 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 137 { { 0, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } } } }; 143 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0, 0 } } } }; 150 static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 151 { { 0, 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0, 0 } } } }; 157 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } } } }; 164 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } }, 165 { { 0, 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0, 0 } } } }; 171 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0, 0 } }, 173 { { 0, 0, 0, 0, 0, 0 } }, 174 { { 0, 0, 0, 0, 0, 0 } }, 175 { { 0, 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0, 0 } } } }; 178 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } }, 179 { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } }, 180 { { 0, 0, 0, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0, 0 } } } }; 185 static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0, 0 } }, 187 { { 0, 0, 0, 0, 0, 0 } }, 188 { { 0, 0, 0, 0, 0, 0 } }, 189 { { 0, 0, 0, 0, 0, 0 } }, 190 { { 0, 0, 0, 0, 0, 0 } }, 191 { { 0, 0, 0, 0, 0, 0 } } } }; 192 193 194 #define ATHUB_BASE__INST0_SEG0 0x00000C00 195 #define ATHUB_BASE__INST0_SEG1 0x02408C00 196 #define ATHUB_BASE__INST0_SEG2 0 197 #define ATHUB_BASE__INST0_SEG3 0 198 #define ATHUB_BASE__INST0_SEG4 0 199 #define ATHUB_BASE__INST0_SEG5 0 200 201 #define ATHUB_BASE__INST1_SEG0 0 202 #define ATHUB_BASE__INST1_SEG1 0 203 #define ATHUB_BASE__INST1_SEG2 0 204 #define ATHUB_BASE__INST1_SEG3 0 205 #define ATHUB_BASE__INST1_SEG4 0 206 #define ATHUB_BASE__INST1_SEG5 0 207 208 #define ATHUB_BASE__INST2_SEG0 0 209 #define ATHUB_BASE__INST2_SEG1 0 210 #define ATHUB_BASE__INST2_SEG2 0 211 #define ATHUB_BASE__INST2_SEG3 0 212 #define ATHUB_BASE__INST2_SEG4 0 213 #define ATHUB_BASE__INST2_SEG5 0 214 215 #define ATHUB_BASE__INST3_SEG0 0 216 #define ATHUB_BASE__INST3_SEG1 0 217 #define ATHUB_BASE__INST3_SEG2 0 218 #define ATHUB_BASE__INST3_SEG3 0 219 #define ATHUB_BASE__INST3_SEG4 0 220 #define ATHUB_BASE__INST3_SEG5 0 221 222 #define ATHUB_BASE__INST4_SEG0 0 223 #define ATHUB_BASE__INST4_SEG1 0 224 #define ATHUB_BASE__INST4_SEG2 0 225 #define ATHUB_BASE__INST4_SEG3 0 226 #define ATHUB_BASE__INST4_SEG4 0 227 #define ATHUB_BASE__INST4_SEG5 0 228 229 #define ATHUB_BASE__INST5_SEG0 0 230 #define ATHUB_BASE__INST5_SEG1 0 231 #define ATHUB_BASE__INST5_SEG2 0 232 #define ATHUB_BASE__INST5_SEG3 0 233 #define ATHUB_BASE__INST5_SEG4 0 234 #define ATHUB_BASE__INST5_SEG5 0 235 236 #define ATHUB_BASE__INST6_SEG0 0 237 #define ATHUB_BASE__INST6_SEG1 0 238 #define ATHUB_BASE__INST6_SEG2 0 239 #define ATHUB_BASE__INST6_SEG3 0 240 #define ATHUB_BASE__INST6_SEG4 0 241 #define ATHUB_BASE__INST6_SEG5 0 242 243 #define CLK_BASE__INST0_SEG0 0x00016C00 244 #define CLK_BASE__INST0_SEG1 0x02401800 245 #define CLK_BASE__INST0_SEG2 0 246 #define CLK_BASE__INST0_SEG3 0 247 #define CLK_BASE__INST0_SEG4 0 248 #define CLK_BASE__INST0_SEG5 0 249 250 #define CLK_BASE__INST1_SEG0 0x00016E00 251 #define CLK_BASE__INST1_SEG1 0x02401C00 252 #define CLK_BASE__INST1_SEG2 0 253 #define CLK_BASE__INST1_SEG3 0 254 #define CLK_BASE__INST1_SEG4 0 255 #define CLK_BASE__INST1_SEG5 0 256 257 #define CLK_BASE__INST2_SEG0 0x00017000 258 #define CLK_BASE__INST2_SEG1 0x02402000 259 #define CLK_BASE__INST2_SEG2 0 260 #define CLK_BASE__INST2_SEG3 0 261 #define CLK_BASE__INST2_SEG4 0 262 #define CLK_BASE__INST2_SEG5 0 263 264 #define CLK_BASE__INST3_SEG0 0x00017200 265 #define CLK_BASE__INST3_SEG1 0x02402400 266 #define CLK_BASE__INST3_SEG2 0 267 #define CLK_BASE__INST3_SEG3 0 268 #define CLK_BASE__INST3_SEG4 0 269 #define CLK_BASE__INST3_SEG5 0 270 271 #define CLK_BASE__INST4_SEG0 0x0001B000 272 #define CLK_BASE__INST4_SEG1 0x0242D800 273 #define CLK_BASE__INST4_SEG2 0 274 #define CLK_BASE__INST4_SEG3 0 275 #define CLK_BASE__INST4_SEG4 0 276 #define CLK_BASE__INST4_SEG5 0 277 278 #define CLK_BASE__INST5_SEG0 0x0001B200 279 #define CLK_BASE__INST5_SEG1 0x0242DC00 280 #define CLK_BASE__INST5_SEG2 0 281 #define CLK_BASE__INST5_SEG3 0 282 #define CLK_BASE__INST5_SEG4 0 283 #define CLK_BASE__INST5_SEG5 0 284 285 #define CLK_BASE__INST6_SEG0 0x00017E00 286 #define CLK_BASE__INST6_SEG1 0x0240BC00 287 #define CLK_BASE__INST6_SEG2 0 288 #define CLK_BASE__INST6_SEG3 0 289 #define CLK_BASE__INST6_SEG4 0 290 #define CLK_BASE__INST6_SEG5 0 291 292 #define DBGU_IO0_BASE__INST0_SEG0 0x000001E0 293 #define DBGU_IO0_BASE__INST0_SEG1 0x0240B400 294 #define DBGU_IO0_BASE__INST0_SEG2 0 295 #define DBGU_IO0_BASE__INST0_SEG3 0 296 #define DBGU_IO0_BASE__INST0_SEG4 0 297 #define DBGU_IO0_BASE__INST0_SEG5 0 298 299 #define DBGU_IO0_BASE__INST1_SEG0 0x00000260 300 #define DBGU_IO0_BASE__INST1_SEG1 0x02413C00 301 #define DBGU_IO0_BASE__INST1_SEG2 0 302 #define DBGU_IO0_BASE__INST1_SEG3 0 303 #define DBGU_IO0_BASE__INST1_SEG4 0 304 #define DBGU_IO0_BASE__INST1_SEG5 0 305 306 #define DBGU_IO0_BASE__INST2_SEG0 0 307 #define DBGU_IO0_BASE__INST2_SEG1 0 308 #define DBGU_IO0_BASE__INST2_SEG2 0 309 #define DBGU_IO0_BASE__INST2_SEG3 0 310 #define DBGU_IO0_BASE__INST2_SEG4 0 311 #define DBGU_IO0_BASE__INST2_SEG5 0 312 313 #define DBGU_IO0_BASE__INST3_SEG0 0 314 #define DBGU_IO0_BASE__INST3_SEG1 0 315 #define DBGU_IO0_BASE__INST3_SEG2 0 316 #define DBGU_IO0_BASE__INST3_SEG3 0 317 #define DBGU_IO0_BASE__INST3_SEG4 0 318 #define DBGU_IO0_BASE__INST3_SEG5 0 319 320 #define DBGU_IO0_BASE__INST4_SEG0 0 321 #define DBGU_IO0_BASE__INST4_SEG1 0 322 #define DBGU_IO0_BASE__INST4_SEG2 0 323 #define DBGU_IO0_BASE__INST4_SEG3 0 324 #define DBGU_IO0_BASE__INST4_SEG4 0 325 #define DBGU_IO0_BASE__INST4_SEG5 0 326 327 #define DBGU_IO0_BASE__INST5_SEG0 0 328 #define DBGU_IO0_BASE__INST5_SEG1 0 329 #define DBGU_IO0_BASE__INST5_SEG2 0 330 #define DBGU_IO0_BASE__INST5_SEG3 0 331 #define DBGU_IO0_BASE__INST5_SEG4 0 332 #define DBGU_IO0_BASE__INST5_SEG5 0 333 334 #define DBGU_IO0_BASE__INST6_SEG0 0 335 #define DBGU_IO0_BASE__INST6_SEG1 0 336 #define DBGU_IO0_BASE__INST6_SEG2 0 337 #define DBGU_IO0_BASE__INST6_SEG3 0 338 #define DBGU_IO0_BASE__INST6_SEG4 0 339 #define DBGU_IO0_BASE__INST6_SEG5 0 340 341 #define DF_BASE__INST0_SEG0 0x00007000 342 #define DF_BASE__INST0_SEG1 0x0240B800 343 #define DF_BASE__INST0_SEG2 0 344 #define DF_BASE__INST0_SEG3 0 345 #define DF_BASE__INST0_SEG4 0 346 #define DF_BASE__INST0_SEG5 0 347 348 #define DF_BASE__INST1_SEG0 0 349 #define DF_BASE__INST1_SEG1 0 350 #define DF_BASE__INST1_SEG2 0 351 #define DF_BASE__INST1_SEG3 0 352 #define DF_BASE__INST1_SEG4 0 353 #define DF_BASE__INST1_SEG5 0 354 355 #define DF_BASE__INST2_SEG0 0 356 #define DF_BASE__INST2_SEG1 0 357 #define DF_BASE__INST2_SEG2 0 358 #define DF_BASE__INST2_SEG3 0 359 #define DF_BASE__INST2_SEG4 0 360 #define DF_BASE__INST2_SEG5 0 361 362 #define DF_BASE__INST3_SEG0 0 363 #define DF_BASE__INST3_SEG1 0 364 #define DF_BASE__INST3_SEG2 0 365 #define DF_BASE__INST3_SEG3 0 366 #define DF_BASE__INST3_SEG4 0 367 #define DF_BASE__INST3_SEG5 0 368 369 #define DF_BASE__INST4_SEG0 0 370 #define DF_BASE__INST4_SEG1 0 371 #define DF_BASE__INST4_SEG2 0 372 #define DF_BASE__INST4_SEG3 0 373 #define DF_BASE__INST4_SEG4 0 374 #define DF_BASE__INST4_SEG5 0 375 376 #define DF_BASE__INST5_SEG0 0 377 #define DF_BASE__INST5_SEG1 0 378 #define DF_BASE__INST5_SEG2 0 379 #define DF_BASE__INST5_SEG3 0 380 #define DF_BASE__INST5_SEG4 0 381 #define DF_BASE__INST5_SEG5 0 382 383 #define DF_BASE__INST6_SEG0 0 384 #define DF_BASE__INST6_SEG1 0 385 #define DF_BASE__INST6_SEG2 0 386 #define DF_BASE__INST6_SEG3 0 387 #define DF_BASE__INST6_SEG4 0 388 #define DF_BASE__INST6_SEG5 0 389 390 #define DIO_BASE__INST0_SEG0 0x02404000 391 #define DIO_BASE__INST0_SEG1 0 392 #define DIO_BASE__INST0_SEG2 0 393 #define DIO_BASE__INST0_SEG3 0 394 #define DIO_BASE__INST0_SEG4 0 395 #define DIO_BASE__INST0_SEG5 0 396 397 #define DIO_BASE__INST1_SEG0 0 398 #define DIO_BASE__INST1_SEG1 0 399 #define DIO_BASE__INST1_SEG2 0 400 #define DIO_BASE__INST1_SEG3 0 401 #define DIO_BASE__INST1_SEG4 0 402 #define DIO_BASE__INST1_SEG5 0 403 404 #define DIO_BASE__INST2_SEG0 0 405 #define DIO_BASE__INST2_SEG1 0 406 #define DIO_BASE__INST2_SEG2 0 407 #define DIO_BASE__INST2_SEG3 0 408 #define DIO_BASE__INST2_SEG4 0 409 #define DIO_BASE__INST2_SEG5 0 410 411 #define DIO_BASE__INST3_SEG0 0 412 #define DIO_BASE__INST3_SEG1 0 413 #define DIO_BASE__INST3_SEG2 0 414 #define DIO_BASE__INST3_SEG3 0 415 #define DIO_BASE__INST3_SEG4 0 416 #define DIO_BASE__INST3_SEG5 0 417 418 #define DIO_BASE__INST4_SEG0 0 419 #define DIO_BASE__INST4_SEG1 0 420 #define DIO_BASE__INST4_SEG2 0 421 #define DIO_BASE__INST4_SEG3 0 422 #define DIO_BASE__INST4_SEG4 0 423 #define DIO_BASE__INST4_SEG5 0 424 425 #define DIO_BASE__INST5_SEG0 0 426 #define DIO_BASE__INST5_SEG1 0 427 #define DIO_BASE__INST5_SEG2 0 428 #define DIO_BASE__INST5_SEG3 0 429 #define DIO_BASE__INST5_SEG4 0 430 #define DIO_BASE__INST5_SEG5 0 431 432 #define DIO_BASE__INST6_SEG0 0 433 #define DIO_BASE__INST6_SEG1 0 434 #define DIO_BASE__INST6_SEG2 0 435 #define DIO_BASE__INST6_SEG3 0 436 #define DIO_BASE__INST6_SEG4 0 437 #define DIO_BASE__INST6_SEG5 0 438 439 #define DCN_BASE__INST0_SEG0 0x00000012 440 #define DCN_BASE__INST0_SEG1 0x000000C0 441 #define DCN_BASE__INST0_SEG2 0x000034C0 442 #define DCN_BASE__INST0_SEG3 0x00009000 443 #define DCN_BASE__INST0_SEG4 0x02403C00 444 #define DCN_BASE__INST0_SEG5 0 445 446 #define DCN_BASE__INST1_SEG0 0 447 #define DCN_BASE__INST1_SEG1 0 448 #define DCN_BASE__INST1_SEG2 0 449 #define DCN_BASE__INST1_SEG3 0 450 #define DCN_BASE__INST1_SEG4 0 451 #define DCN_BASE__INST1_SEG5 0 452 453 #define DCN_BASE__INST2_SEG0 0 454 #define DCN_BASE__INST2_SEG1 0 455 #define DCN_BASE__INST2_SEG2 0 456 #define DCN_BASE__INST2_SEG3 0 457 #define DCN_BASE__INST2_SEG4 0 458 #define DCN_BASE__INST2_SEG5 0 459 460 #define DCN_BASE__INST3_SEG0 0 461 #define DCN_BASE__INST3_SEG1 0 462 #define DCN_BASE__INST3_SEG2 0 463 #define DCN_BASE__INST3_SEG3 0 464 #define DCN_BASE__INST3_SEG4 0 465 #define DCN_BASE__INST3_SEG5 0 466 467 #define DCN_BASE__INST4_SEG0 0 468 #define DCN_BASE__INST4_SEG1 0 469 #define DCN_BASE__INST4_SEG2 0 470 #define DCN_BASE__INST4_SEG3 0 471 #define DCN_BASE__INST4_SEG4 0 472 #define DCN_BASE__INST4_SEG5 0 473 474 #define DCN_BASE__INST5_SEG0 0 475 #define DCN_BASE__INST5_SEG1 0 476 #define DCN_BASE__INST5_SEG2 0 477 #define DCN_BASE__INST5_SEG3 0 478 #define DCN_BASE__INST5_SEG4 0 479 #define DCN_BASE__INST5_SEG5 0 480 481 #define DCN_BASE__INST6_SEG0 0 482 #define DCN_BASE__INST6_SEG1 0 483 #define DCN_BASE__INST6_SEG2 0 484 #define DCN_BASE__INST6_SEG3 0 485 #define DCN_BASE__INST6_SEG4 0 486 #define DCN_BASE__INST6_SEG5 0 487 488 #define DPCS_BASE__INST0_SEG0 0x00000012 489 #define DPCS_BASE__INST0_SEG1 0x000000C0 490 #define DPCS_BASE__INST0_SEG2 0x000034C0 491 #define DPCS_BASE__INST0_SEG3 0x00009000 492 #define DPCS_BASE__INST0_SEG4 0x02403C00 493 #define DPCS_BASE__INST0_SEG5 0 494 495 #define DPCS_BASE__INST1_SEG0 0 496 #define DPCS_BASE__INST1_SEG1 0 497 #define DPCS_BASE__INST1_SEG2 0 498 #define DPCS_BASE__INST1_SEG3 0 499 #define DPCS_BASE__INST1_SEG4 0 500 #define DPCS_BASE__INST1_SEG5 0 501 502 #define DPCS_BASE__INST2_SEG0 0 503 #define DPCS_BASE__INST2_SEG1 0 504 #define DPCS_BASE__INST2_SEG2 0 505 #define DPCS_BASE__INST2_SEG3 0 506 #define DPCS_BASE__INST2_SEG4 0 507 #define DPCS_BASE__INST2_SEG5 0 508 509 #define DPCS_BASE__INST3_SEG0 0 510 #define DPCS_BASE__INST3_SEG1 0 511 #define DPCS_BASE__INST3_SEG2 0 512 #define DPCS_BASE__INST3_SEG3 0 513 #define DPCS_BASE__INST3_SEG4 0 514 #define DPCS_BASE__INST3_SEG5 0 515 516 #define DPCS_BASE__INST4_SEG0 0 517 #define DPCS_BASE__INST4_SEG1 0 518 #define DPCS_BASE__INST4_SEG2 0 519 #define DPCS_BASE__INST4_SEG3 0 520 #define DPCS_BASE__INST4_SEG4 0 521 #define DPCS_BASE__INST4_SEG5 0 522 523 #define DPCS_BASE__INST5_SEG0 0 524 #define DPCS_BASE__INST5_SEG1 0 525 #define DPCS_BASE__INST5_SEG2 0 526 #define DPCS_BASE__INST5_SEG3 0 527 #define DPCS_BASE__INST5_SEG4 0 528 #define DPCS_BASE__INST5_SEG5 0 529 530 #define DPCS_BASE__INST6_SEG0 0 531 #define DPCS_BASE__INST6_SEG1 0 532 #define DPCS_BASE__INST6_SEG2 0 533 #define DPCS_BASE__INST6_SEG3 0 534 #define DPCS_BASE__INST6_SEG4 0 535 #define DPCS_BASE__INST6_SEG5 0 536 537 #define FUSE_BASE__INST0_SEG0 0x00017400 538 #define FUSE_BASE__INST0_SEG1 0x02401400 539 #define FUSE_BASE__INST0_SEG2 0 540 #define FUSE_BASE__INST0_SEG3 0 541 #define FUSE_BASE__INST0_SEG4 0 542 #define FUSE_BASE__INST0_SEG5 0 543 544 #define FUSE_BASE__INST1_SEG0 0 545 #define FUSE_BASE__INST1_SEG1 0 546 #define FUSE_BASE__INST1_SEG2 0 547 #define FUSE_BASE__INST1_SEG3 0 548 #define FUSE_BASE__INST1_SEG4 0 549 #define FUSE_BASE__INST1_SEG5 0 550 551 #define FUSE_BASE__INST2_SEG0 0 552 #define FUSE_BASE__INST2_SEG1 0 553 #define FUSE_BASE__INST2_SEG2 0 554 #define FUSE_BASE__INST2_SEG3 0 555 #define FUSE_BASE__INST2_SEG4 0 556 #define FUSE_BASE__INST2_SEG5 0 557 558 #define FUSE_BASE__INST3_SEG0 0 559 #define FUSE_BASE__INST3_SEG1 0 560 #define FUSE_BASE__INST3_SEG2 0 561 #define FUSE_BASE__INST3_SEG3 0 562 #define FUSE_BASE__INST3_SEG4 0 563 #define FUSE_BASE__INST3_SEG5 0 564 565 #define FUSE_BASE__INST4_SEG0 0 566 #define FUSE_BASE__INST4_SEG1 0 567 #define FUSE_BASE__INST4_SEG2 0 568 #define FUSE_BASE__INST4_SEG3 0 569 #define FUSE_BASE__INST4_SEG4 0 570 #define FUSE_BASE__INST4_SEG5 0 571 572 #define FUSE_BASE__INST5_SEG0 0 573 #define FUSE_BASE__INST5_SEG1 0 574 #define FUSE_BASE__INST5_SEG2 0 575 #define FUSE_BASE__INST5_SEG3 0 576 #define FUSE_BASE__INST5_SEG4 0 577 #define FUSE_BASE__INST5_SEG5 0 578 579 #define FUSE_BASE__INST6_SEG0 0 580 #define FUSE_BASE__INST6_SEG1 0 581 #define FUSE_BASE__INST6_SEG2 0 582 #define FUSE_BASE__INST6_SEG3 0 583 #define FUSE_BASE__INST6_SEG4 0 584 #define FUSE_BASE__INST6_SEG5 0 585 586 #define GC_BASE__INST0_SEG0 0x00001260 587 #define GC_BASE__INST0_SEG1 0x0000A000 588 #define GC_BASE__INST0_SEG2 0x0001C000 589 #define GC_BASE__INST0_SEG3 0x02402C00 590 #define GC_BASE__INST0_SEG4 0 591 #define GC_BASE__INST0_SEG5 0 592 593 #define GC_BASE__INST1_SEG0 0 594 #define GC_BASE__INST1_SEG1 0 595 #define GC_BASE__INST1_SEG2 0 596 #define GC_BASE__INST1_SEG3 0 597 #define GC_BASE__INST1_SEG4 0 598 #define GC_BASE__INST1_SEG5 0 599 600 #define GC_BASE__INST2_SEG0 0 601 #define GC_BASE__INST2_SEG1 0 602 #define GC_BASE__INST2_SEG2 0 603 #define GC_BASE__INST2_SEG3 0 604 #define GC_BASE__INST2_SEG4 0 605 #define GC_BASE__INST2_SEG5 0 606 607 #define GC_BASE__INST3_SEG0 0 608 #define GC_BASE__INST3_SEG1 0 609 #define GC_BASE__INST3_SEG2 0 610 #define GC_BASE__INST3_SEG3 0 611 #define GC_BASE__INST3_SEG4 0 612 #define GC_BASE__INST3_SEG5 0 613 614 #define GC_BASE__INST4_SEG0 0 615 #define GC_BASE__INST4_SEG1 0 616 #define GC_BASE__INST4_SEG2 0 617 #define GC_BASE__INST4_SEG3 0 618 #define GC_BASE__INST4_SEG4 0 619 #define GC_BASE__INST4_SEG5 0 620 621 #define GC_BASE__INST5_SEG0 0 622 #define GC_BASE__INST5_SEG1 0 623 #define GC_BASE__INST5_SEG2 0 624 #define GC_BASE__INST5_SEG3 0 625 #define GC_BASE__INST5_SEG4 0 626 #define GC_BASE__INST5_SEG5 0 627 628 #define GC_BASE__INST6_SEG0 0 629 #define GC_BASE__INST6_SEG1 0 630 #define GC_BASE__INST6_SEG2 0 631 #define GC_BASE__INST6_SEG3 0 632 #define GC_BASE__INST6_SEG4 0 633 #define GC_BASE__INST6_SEG5 0 634 635 #define HDA_BASE__INST0_SEG0 0x004C0000 636 #define HDA_BASE__INST0_SEG1 0x02404800 637 #define HDA_BASE__INST0_SEG2 0 638 #define HDA_BASE__INST0_SEG3 0 639 #define HDA_BASE__INST0_SEG4 0 640 #define HDA_BASE__INST0_SEG5 0 641 642 #define HDA_BASE__INST1_SEG0 0 643 #define HDA_BASE__INST1_SEG1 0 644 #define HDA_BASE__INST1_SEG2 0 645 #define HDA_BASE__INST1_SEG3 0 646 #define HDA_BASE__INST1_SEG4 0 647 #define HDA_BASE__INST1_SEG5 0 648 649 #define HDA_BASE__INST2_SEG0 0 650 #define HDA_BASE__INST2_SEG1 0 651 #define HDA_BASE__INST2_SEG2 0 652 #define HDA_BASE__INST2_SEG3 0 653 #define HDA_BASE__INST2_SEG4 0 654 #define HDA_BASE__INST2_SEG5 0 655 656 #define HDA_BASE__INST3_SEG0 0 657 #define HDA_BASE__INST3_SEG1 0 658 #define HDA_BASE__INST3_SEG2 0 659 #define HDA_BASE__INST3_SEG3 0 660 #define HDA_BASE__INST3_SEG4 0 661 #define HDA_BASE__INST3_SEG5 0 662 663 #define HDA_BASE__INST4_SEG0 0 664 #define HDA_BASE__INST4_SEG1 0 665 #define HDA_BASE__INST4_SEG2 0 666 #define HDA_BASE__INST4_SEG3 0 667 #define HDA_BASE__INST4_SEG4 0 668 #define HDA_BASE__INST4_SEG5 0 669 670 #define HDA_BASE__INST5_SEG0 0 671 #define HDA_BASE__INST5_SEG1 0 672 #define HDA_BASE__INST5_SEG2 0 673 #define HDA_BASE__INST5_SEG3 0 674 #define HDA_BASE__INST5_SEG4 0 675 #define HDA_BASE__INST5_SEG5 0 676 677 #define HDA_BASE__INST6_SEG0 0 678 #define HDA_BASE__INST6_SEG1 0 679 #define HDA_BASE__INST6_SEG2 0 680 #define HDA_BASE__INST6_SEG3 0 681 #define HDA_BASE__INST6_SEG4 0 682 #define HDA_BASE__INST6_SEG5 0 683 684 #define HDP_BASE__INST0_SEG0 0x00000F20 685 #define HDP_BASE__INST0_SEG1 0x0240A400 686 #define HDP_BASE__INST0_SEG2 0 687 #define HDP_BASE__INST0_SEG3 0 688 #define HDP_BASE__INST0_SEG4 0 689 #define HDP_BASE__INST0_SEG5 0 690 691 #define HDP_BASE__INST1_SEG0 0 692 #define HDP_BASE__INST1_SEG1 0 693 #define HDP_BASE__INST1_SEG2 0 694 #define HDP_BASE__INST1_SEG3 0 695 #define HDP_BASE__INST1_SEG4 0 696 #define HDP_BASE__INST1_SEG5 0 697 698 #define HDP_BASE__INST2_SEG0 0 699 #define HDP_BASE__INST2_SEG1 0 700 #define HDP_BASE__INST2_SEG2 0 701 #define HDP_BASE__INST2_SEG3 0 702 #define HDP_BASE__INST2_SEG4 0 703 #define HDP_BASE__INST2_SEG5 0 704 705 #define HDP_BASE__INST3_SEG0 0 706 #define HDP_BASE__INST3_SEG1 0 707 #define HDP_BASE__INST3_SEG2 0 708 #define HDP_BASE__INST3_SEG3 0 709 #define HDP_BASE__INST3_SEG4 0 710 #define HDP_BASE__INST3_SEG5 0 711 712 #define HDP_BASE__INST4_SEG0 0 713 #define HDP_BASE__INST4_SEG1 0 714 #define HDP_BASE__INST4_SEG2 0 715 #define HDP_BASE__INST4_SEG3 0 716 #define HDP_BASE__INST4_SEG4 0 717 #define HDP_BASE__INST4_SEG5 0 718 719 #define HDP_BASE__INST5_SEG0 0 720 #define HDP_BASE__INST5_SEG1 0 721 #define HDP_BASE__INST5_SEG2 0 722 #define HDP_BASE__INST5_SEG3 0 723 #define HDP_BASE__INST5_SEG4 0 724 #define HDP_BASE__INST5_SEG5 0 725 726 #define HDP_BASE__INST6_SEG0 0 727 #define HDP_BASE__INST6_SEG1 0 728 #define HDP_BASE__INST6_SEG2 0 729 #define HDP_BASE__INST6_SEG3 0 730 #define HDP_BASE__INST6_SEG4 0 731 #define HDP_BASE__INST6_SEG5 0 732 733 #define MMHUB_BASE__INST0_SEG0 0x0001A000 734 #define MMHUB_BASE__INST0_SEG1 0x02408800 735 #define MMHUB_BASE__INST0_SEG2 0 736 #define MMHUB_BASE__INST0_SEG3 0 737 #define MMHUB_BASE__INST0_SEG4 0 738 #define MMHUB_BASE__INST0_SEG5 0 739 740 #define MMHUB_BASE__INST1_SEG0 0 741 #define MMHUB_BASE__INST1_SEG1 0 742 #define MMHUB_BASE__INST1_SEG2 0 743 #define MMHUB_BASE__INST1_SEG3 0 744 #define MMHUB_BASE__INST1_SEG4 0 745 #define MMHUB_BASE__INST1_SEG5 0 746 747 #define MMHUB_BASE__INST2_SEG0 0 748 #define MMHUB_BASE__INST2_SEG1 0 749 #define MMHUB_BASE__INST2_SEG2 0 750 #define MMHUB_BASE__INST2_SEG3 0 751 #define MMHUB_BASE__INST2_SEG4 0 752 #define MMHUB_BASE__INST2_SEG5 0 753 754 #define MMHUB_BASE__INST3_SEG0 0 755 #define MMHUB_BASE__INST3_SEG1 0 756 #define MMHUB_BASE__INST3_SEG2 0 757 #define MMHUB_BASE__INST3_SEG3 0 758 #define MMHUB_BASE__INST3_SEG4 0 759 #define MMHUB_BASE__INST3_SEG5 0 760 761 #define MMHUB_BASE__INST4_SEG0 0 762 #define MMHUB_BASE__INST4_SEG1 0 763 #define MMHUB_BASE__INST4_SEG2 0 764 #define MMHUB_BASE__INST4_SEG3 0 765 #define MMHUB_BASE__INST4_SEG4 0 766 #define MMHUB_BASE__INST4_SEG5 0 767 768 #define MMHUB_BASE__INST5_SEG0 0 769 #define MMHUB_BASE__INST5_SEG1 0 770 #define MMHUB_BASE__INST5_SEG2 0 771 #define MMHUB_BASE__INST5_SEG3 0 772 #define MMHUB_BASE__INST5_SEG4 0 773 #define MMHUB_BASE__INST5_SEG5 0 774 775 #define MMHUB_BASE__INST6_SEG0 0 776 #define MMHUB_BASE__INST6_SEG1 0 777 #define MMHUB_BASE__INST6_SEG2 0 778 #define MMHUB_BASE__INST6_SEG3 0 779 #define MMHUB_BASE__INST6_SEG4 0 780 #define MMHUB_BASE__INST6_SEG5 0 781 782 #define MP0_BASE__INST0_SEG0 0x00016000 783 #define MP0_BASE__INST0_SEG1 0x00DC0000 784 #define MP0_BASE__INST0_SEG2 0x00E00000 785 #define MP0_BASE__INST0_SEG3 0x00E40000 786 #define MP0_BASE__INST0_SEG4 0x0243FC00 787 #define MP0_BASE__INST0_SEG5 0 788 789 #define MP0_BASE__INST1_SEG0 0 790 #define MP0_BASE__INST1_SEG1 0 791 #define MP0_BASE__INST1_SEG2 0 792 #define MP0_BASE__INST1_SEG3 0 793 #define MP0_BASE__INST1_SEG4 0 794 #define MP0_BASE__INST1_SEG5 0 795 796 #define MP0_BASE__INST2_SEG0 0 797 #define MP0_BASE__INST2_SEG1 0 798 #define MP0_BASE__INST2_SEG2 0 799 #define MP0_BASE__INST2_SEG3 0 800 #define MP0_BASE__INST2_SEG4 0 801 #define MP0_BASE__INST2_SEG5 0 802 803 #define MP0_BASE__INST3_SEG0 0 804 #define MP0_BASE__INST3_SEG1 0 805 #define MP0_BASE__INST3_SEG2 0 806 #define MP0_BASE__INST3_SEG3 0 807 #define MP0_BASE__INST3_SEG4 0 808 #define MP0_BASE__INST3_SEG5 0 809 810 #define MP0_BASE__INST4_SEG0 0 811 #define MP0_BASE__INST4_SEG1 0 812 #define MP0_BASE__INST4_SEG2 0 813 #define MP0_BASE__INST4_SEG3 0 814 #define MP0_BASE__INST4_SEG4 0 815 #define MP0_BASE__INST4_SEG5 0 816 817 #define MP0_BASE__INST5_SEG0 0 818 #define MP0_BASE__INST5_SEG1 0 819 #define MP0_BASE__INST5_SEG2 0 820 #define MP0_BASE__INST5_SEG3 0 821 #define MP0_BASE__INST5_SEG4 0 822 #define MP0_BASE__INST5_SEG5 0 823 824 #define MP0_BASE__INST6_SEG0 0 825 #define MP0_BASE__INST6_SEG1 0 826 #define MP0_BASE__INST6_SEG2 0 827 #define MP0_BASE__INST6_SEG3 0 828 #define MP0_BASE__INST6_SEG4 0 829 #define MP0_BASE__INST6_SEG5 0 830 831 #define MP1_BASE__INST0_SEG0 0x00016000 832 #define MP1_BASE__INST0_SEG1 0x00DC0000 833 #define MP1_BASE__INST0_SEG2 0x00E00000 834 #define MP1_BASE__INST0_SEG3 0x00E40000 835 #define MP1_BASE__INST0_SEG4 0x0243FC00 836 #define MP1_BASE__INST0_SEG5 0 837 838 #define MP1_BASE__INST1_SEG0 0 839 #define MP1_BASE__INST1_SEG1 0 840 #define MP1_BASE__INST1_SEG2 0 841 #define MP1_BASE__INST1_SEG3 0 842 #define MP1_BASE__INST1_SEG4 0 843 #define MP1_BASE__INST1_SEG5 0 844 845 #define MP1_BASE__INST2_SEG0 0 846 #define MP1_BASE__INST2_SEG1 0 847 #define MP1_BASE__INST2_SEG2 0 848 #define MP1_BASE__INST2_SEG3 0 849 #define MP1_BASE__INST2_SEG4 0 850 #define MP1_BASE__INST2_SEG5 0 851 852 #define MP1_BASE__INST3_SEG0 0 853 #define MP1_BASE__INST3_SEG1 0 854 #define MP1_BASE__INST3_SEG2 0 855 #define MP1_BASE__INST3_SEG3 0 856 #define MP1_BASE__INST3_SEG4 0 857 #define MP1_BASE__INST3_SEG5 0 858 859 #define MP1_BASE__INST4_SEG0 0 860 #define MP1_BASE__INST4_SEG1 0 861 #define MP1_BASE__INST4_SEG2 0 862 #define MP1_BASE__INST4_SEG3 0 863 #define MP1_BASE__INST4_SEG4 0 864 #define MP1_BASE__INST4_SEG5 0 865 866 #define MP1_BASE__INST5_SEG0 0 867 #define MP1_BASE__INST5_SEG1 0 868 #define MP1_BASE__INST5_SEG2 0 869 #define MP1_BASE__INST5_SEG3 0 870 #define MP1_BASE__INST5_SEG4 0 871 #define MP1_BASE__INST5_SEG5 0 872 873 #define MP1_BASE__INST6_SEG0 0 874 #define MP1_BASE__INST6_SEG1 0 875 #define MP1_BASE__INST6_SEG2 0 876 #define MP1_BASE__INST6_SEG3 0 877 #define MP1_BASE__INST6_SEG4 0 878 #define MP1_BASE__INST6_SEG5 0 879 880 #define NBIO_BASE__INST0_SEG0 0x00000000 881 #define NBIO_BASE__INST0_SEG1 0x00000014 882 #define NBIO_BASE__INST0_SEG2 0x00000D20 883 #define NBIO_BASE__INST0_SEG3 0x00010400 884 #define NBIO_BASE__INST0_SEG4 0x0241B000 885 #define NBIO_BASE__INST0_SEG5 0x04040000 886 887 #define NBIO_BASE__INST1_SEG0 0 888 #define NBIO_BASE__INST1_SEG1 0 889 #define NBIO_BASE__INST1_SEG2 0 890 #define NBIO_BASE__INST1_SEG3 0 891 #define NBIO_BASE__INST1_SEG4 0 892 #define NBIO_BASE__INST1_SEG5 0 893 894 #define NBIO_BASE__INST2_SEG0 0 895 #define NBIO_BASE__INST2_SEG1 0 896 #define NBIO_BASE__INST2_SEG2 0 897 #define NBIO_BASE__INST2_SEG3 0 898 #define NBIO_BASE__INST2_SEG4 0 899 #define NBIO_BASE__INST2_SEG5 0 900 901 #define NBIO_BASE__INST3_SEG0 0 902 #define NBIO_BASE__INST3_SEG1 0 903 #define NBIO_BASE__INST3_SEG2 0 904 #define NBIO_BASE__INST3_SEG3 0 905 #define NBIO_BASE__INST3_SEG4 0 906 #define NBIO_BASE__INST3_SEG5 0 907 908 #define NBIO_BASE__INST4_SEG0 0 909 #define NBIO_BASE__INST4_SEG1 0 910 #define NBIO_BASE__INST4_SEG2 0 911 #define NBIO_BASE__INST4_SEG3 0 912 #define NBIO_BASE__INST4_SEG4 0 913 #define NBIO_BASE__INST4_SEG5 0 914 915 #define NBIO_BASE__INST5_SEG0 0 916 #define NBIO_BASE__INST5_SEG1 0 917 #define NBIO_BASE__INST5_SEG2 0 918 #define NBIO_BASE__INST5_SEG3 0 919 #define NBIO_BASE__INST5_SEG4 0 920 #define NBIO_BASE__INST5_SEG5 0 921 922 #define NBIO_BASE__INST6_SEG0 0 923 #define NBIO_BASE__INST6_SEG1 0 924 #define NBIO_BASE__INST6_SEG2 0 925 #define NBIO_BASE__INST6_SEG3 0 926 #define NBIO_BASE__INST6_SEG4 0 927 #define NBIO_BASE__INST6_SEG5 0 928 929 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 930 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 931 #define OSSSYS_BASE__INST0_SEG2 0 932 #define OSSSYS_BASE__INST0_SEG3 0 933 #define OSSSYS_BASE__INST0_SEG4 0 934 #define OSSSYS_BASE__INST0_SEG5 0 935 936 #define OSSSYS_BASE__INST1_SEG0 0 937 #define OSSSYS_BASE__INST1_SEG1 0 938 #define OSSSYS_BASE__INST1_SEG2 0 939 #define OSSSYS_BASE__INST1_SEG3 0 940 #define OSSSYS_BASE__INST1_SEG4 0 941 #define OSSSYS_BASE__INST1_SEG5 0 942 943 #define OSSSYS_BASE__INST2_SEG0 0 944 #define OSSSYS_BASE__INST2_SEG1 0 945 #define OSSSYS_BASE__INST2_SEG2 0 946 #define OSSSYS_BASE__INST2_SEG3 0 947 #define OSSSYS_BASE__INST2_SEG4 0 948 #define OSSSYS_BASE__INST2_SEG5 0 949 950 #define OSSSYS_BASE__INST3_SEG0 0 951 #define OSSSYS_BASE__INST3_SEG1 0 952 #define OSSSYS_BASE__INST3_SEG2 0 953 #define OSSSYS_BASE__INST3_SEG3 0 954 #define OSSSYS_BASE__INST3_SEG4 0 955 #define OSSSYS_BASE__INST3_SEG5 0 956 957 #define OSSSYS_BASE__INST4_SEG0 0 958 #define OSSSYS_BASE__INST4_SEG1 0 959 #define OSSSYS_BASE__INST4_SEG2 0 960 #define OSSSYS_BASE__INST4_SEG3 0 961 #define OSSSYS_BASE__INST4_SEG4 0 962 #define OSSSYS_BASE__INST4_SEG5 0 963 964 #define OSSSYS_BASE__INST5_SEG0 0 965 #define OSSSYS_BASE__INST5_SEG1 0 966 #define OSSSYS_BASE__INST5_SEG2 0 967 #define OSSSYS_BASE__INST5_SEG3 0 968 #define OSSSYS_BASE__INST5_SEG4 0 969 #define OSSSYS_BASE__INST5_SEG5 0 970 971 #define OSSSYS_BASE__INST6_SEG0 0 972 #define OSSSYS_BASE__INST6_SEG1 0 973 #define OSSSYS_BASE__INST6_SEG2 0 974 #define OSSSYS_BASE__INST6_SEG3 0 975 #define OSSSYS_BASE__INST6_SEG4 0 976 #define OSSSYS_BASE__INST6_SEG5 0 977 978 #define PCIE0_BASE__INST0_SEG0 0x00000000 979 #define PCIE0_BASE__INST0_SEG1 0x00000014 980 #define PCIE0_BASE__INST0_SEG2 0x00000D20 981 #define PCIE0_BASE__INST0_SEG3 0x00010400 982 #define PCIE0_BASE__INST0_SEG4 0x0241B000 983 #define PCIE0_BASE__INST0_SEG5 0x04040000 984 985 #define PCIE0_BASE__INST1_SEG0 0 986 #define PCIE0_BASE__INST1_SEG1 0 987 #define PCIE0_BASE__INST1_SEG2 0 988 #define PCIE0_BASE__INST1_SEG3 0 989 #define PCIE0_BASE__INST1_SEG4 0 990 #define PCIE0_BASE__INST1_SEG5 0 991 992 #define PCIE0_BASE__INST2_SEG0 0 993 #define PCIE0_BASE__INST2_SEG1 0 994 #define PCIE0_BASE__INST2_SEG2 0 995 #define PCIE0_BASE__INST2_SEG3 0 996 #define PCIE0_BASE__INST2_SEG4 0 997 #define PCIE0_BASE__INST2_SEG5 0 998 999 #define PCIE0_BASE__INST3_SEG0 0 1000 #define PCIE0_BASE__INST3_SEG1 0 1001 #define PCIE0_BASE__INST3_SEG2 0 1002 #define PCIE0_BASE__INST3_SEG3 0 1003 #define PCIE0_BASE__INST3_SEG4 0 1004 #define PCIE0_BASE__INST3_SEG5 0 1005 1006 #define PCIE0_BASE__INST4_SEG0 0 1007 #define PCIE0_BASE__INST4_SEG1 0 1008 #define PCIE0_BASE__INST4_SEG2 0 1009 #define PCIE0_BASE__INST4_SEG3 0 1010 #define PCIE0_BASE__INST4_SEG4 0 1011 #define PCIE0_BASE__INST4_SEG5 0 1012 1013 #define PCIE0_BASE__INST5_SEG0 0 1014 #define PCIE0_BASE__INST5_SEG1 0 1015 #define PCIE0_BASE__INST5_SEG2 0 1016 #define PCIE0_BASE__INST5_SEG3 0 1017 #define PCIE0_BASE__INST5_SEG4 0 1018 #define PCIE0_BASE__INST5_SEG5 0 1019 1020 #define PCIE0_BASE__INST6_SEG0 0 1021 #define PCIE0_BASE__INST6_SEG1 0 1022 #define PCIE0_BASE__INST6_SEG2 0 1023 #define PCIE0_BASE__INST6_SEG3 0 1024 #define PCIE0_BASE__INST6_SEG4 0 1025 #define PCIE0_BASE__INST6_SEG5 0 1026 1027 #define SDMA0_BASE__INST0_SEG0 0x00001260 1028 #define SDMA0_BASE__INST0_SEG1 0x0000A000 1029 #define SDMA0_BASE__INST0_SEG2 0x0001C000 1030 #define SDMA0_BASE__INST0_SEG3 0x02402C00 1031 #define SDMA0_BASE__INST0_SEG4 0 1032 #define SDMA0_BASE__INST0_SEG5 0 1033 1034 #define SDMA0_BASE__INST1_SEG0 0 1035 #define SDMA0_BASE__INST1_SEG1 0 1036 #define SDMA0_BASE__INST1_SEG2 0 1037 #define SDMA0_BASE__INST1_SEG3 0 1038 #define SDMA0_BASE__INST1_SEG4 0 1039 #define SDMA0_BASE__INST1_SEG5 0 1040 1041 #define SDMA0_BASE__INST2_SEG0 0 1042 #define SDMA0_BASE__INST2_SEG1 0 1043 #define SDMA0_BASE__INST2_SEG2 0 1044 #define SDMA0_BASE__INST2_SEG3 0 1045 #define SDMA0_BASE__INST2_SEG4 0 1046 #define SDMA0_BASE__INST2_SEG5 0 1047 1048 #define SDMA0_BASE__INST3_SEG0 0 1049 #define SDMA0_BASE__INST3_SEG1 0 1050 #define SDMA0_BASE__INST3_SEG2 0 1051 #define SDMA0_BASE__INST3_SEG3 0 1052 #define SDMA0_BASE__INST3_SEG4 0 1053 #define SDMA0_BASE__INST3_SEG5 0 1054 1055 #define SDMA0_BASE__INST4_SEG0 0 1056 #define SDMA0_BASE__INST4_SEG1 0 1057 #define SDMA0_BASE__INST4_SEG2 0 1058 #define SDMA0_BASE__INST4_SEG3 0 1059 #define SDMA0_BASE__INST4_SEG4 0 1060 #define SDMA0_BASE__INST4_SEG5 0 1061 1062 #define SDMA0_BASE__INST5_SEG0 0 1063 #define SDMA0_BASE__INST5_SEG1 0 1064 #define SDMA0_BASE__INST5_SEG2 0 1065 #define SDMA0_BASE__INST5_SEG3 0 1066 #define SDMA0_BASE__INST5_SEG4 0 1067 #define SDMA0_BASE__INST5_SEG5 0 1068 1069 #define SDMA0_BASE__INST6_SEG0 0 1070 #define SDMA0_BASE__INST6_SEG1 0 1071 #define SDMA0_BASE__INST6_SEG2 0 1072 #define SDMA0_BASE__INST6_SEG3 0 1073 #define SDMA0_BASE__INST6_SEG4 0 1074 #define SDMA0_BASE__INST6_SEG5 0 1075 1076 #define SMUIO_BASE__INST0_SEG0 0x00016800 1077 #define SMUIO_BASE__INST0_SEG1 0x00016A00 1078 #define SMUIO_BASE__INST0_SEG2 0x00440000 1079 #define SMUIO_BASE__INST0_SEG3 0x02401000 1080 #define SMUIO_BASE__INST0_SEG4 0 1081 #define SMUIO_BASE__INST0_SEG5 0 1082 1083 #define SMUIO_BASE__INST1_SEG0 0 1084 #define SMUIO_BASE__INST1_SEG1 0 1085 #define SMUIO_BASE__INST1_SEG2 0 1086 #define SMUIO_BASE__INST1_SEG3 0 1087 #define SMUIO_BASE__INST1_SEG4 0 1088 #define SMUIO_BASE__INST1_SEG5 0 1089 1090 #define SMUIO_BASE__INST2_SEG0 0 1091 #define SMUIO_BASE__INST2_SEG1 0 1092 #define SMUIO_BASE__INST2_SEG2 0 1093 #define SMUIO_BASE__INST2_SEG3 0 1094 #define SMUIO_BASE__INST2_SEG4 0 1095 #define SMUIO_BASE__INST2_SEG5 0 1096 1097 #define SMUIO_BASE__INST3_SEG0 0 1098 #define SMUIO_BASE__INST3_SEG1 0 1099 #define SMUIO_BASE__INST3_SEG2 0 1100 #define SMUIO_BASE__INST3_SEG3 0 1101 #define SMUIO_BASE__INST3_SEG4 0 1102 #define SMUIO_BASE__INST3_SEG5 0 1103 1104 #define SMUIO_BASE__INST4_SEG0 0 1105 #define SMUIO_BASE__INST4_SEG1 0 1106 #define SMUIO_BASE__INST4_SEG2 0 1107 #define SMUIO_BASE__INST4_SEG3 0 1108 #define SMUIO_BASE__INST4_SEG4 0 1109 #define SMUIO_BASE__INST4_SEG5 0 1110 1111 #define SMUIO_BASE__INST5_SEG0 0 1112 #define SMUIO_BASE__INST5_SEG1 0 1113 #define SMUIO_BASE__INST5_SEG2 0 1114 #define SMUIO_BASE__INST5_SEG3 0 1115 #define SMUIO_BASE__INST5_SEG4 0 1116 #define SMUIO_BASE__INST5_SEG5 0 1117 1118 #define SMUIO_BASE__INST6_SEG0 0 1119 #define SMUIO_BASE__INST6_SEG1 0 1120 #define SMUIO_BASE__INST6_SEG2 0 1121 #define SMUIO_BASE__INST6_SEG3 0 1122 #define SMUIO_BASE__INST6_SEG4 0 1123 #define SMUIO_BASE__INST6_SEG5 0 1124 1125 #define THM_BASE__INST0_SEG0 0x00016600 1126 #define THM_BASE__INST0_SEG1 0x02400C00 1127 #define THM_BASE__INST0_SEG2 0 1128 #define THM_BASE__INST0_SEG3 0 1129 #define THM_BASE__INST0_SEG4 0 1130 #define THM_BASE__INST0_SEG5 0 1131 1132 #define THM_BASE__INST1_SEG0 0 1133 #define THM_BASE__INST1_SEG1 0 1134 #define THM_BASE__INST1_SEG2 0 1135 #define THM_BASE__INST1_SEG3 0 1136 #define THM_BASE__INST1_SEG4 0 1137 #define THM_BASE__INST1_SEG5 0 1138 1139 #define THM_BASE__INST2_SEG0 0 1140 #define THM_BASE__INST2_SEG1 0 1141 #define THM_BASE__INST2_SEG2 0 1142 #define THM_BASE__INST2_SEG3 0 1143 #define THM_BASE__INST2_SEG4 0 1144 #define THM_BASE__INST2_SEG5 0 1145 1146 #define THM_BASE__INST3_SEG0 0 1147 #define THM_BASE__INST3_SEG1 0 1148 #define THM_BASE__INST3_SEG2 0 1149 #define THM_BASE__INST3_SEG3 0 1150 #define THM_BASE__INST3_SEG4 0 1151 #define THM_BASE__INST3_SEG5 0 1152 1153 #define THM_BASE__INST4_SEG0 0 1154 #define THM_BASE__INST4_SEG1 0 1155 #define THM_BASE__INST4_SEG2 0 1156 #define THM_BASE__INST4_SEG3 0 1157 #define THM_BASE__INST4_SEG4 0 1158 #define THM_BASE__INST4_SEG5 0 1159 1160 #define THM_BASE__INST5_SEG0 0 1161 #define THM_BASE__INST5_SEG1 0 1162 #define THM_BASE__INST5_SEG2 0 1163 #define THM_BASE__INST5_SEG3 0 1164 #define THM_BASE__INST5_SEG4 0 1165 #define THM_BASE__INST5_SEG5 0 1166 1167 #define THM_BASE__INST6_SEG0 0 1168 #define THM_BASE__INST6_SEG1 0 1169 #define THM_BASE__INST6_SEG2 0 1170 #define THM_BASE__INST6_SEG3 0 1171 #define THM_BASE__INST6_SEG4 0 1172 #define THM_BASE__INST6_SEG5 0 1173 1174 #define UMC_BASE__INST0_SEG0 0x00014000 1175 #define UMC_BASE__INST0_SEG1 0x02425800 1176 #define UMC_BASE__INST0_SEG2 0 1177 #define UMC_BASE__INST0_SEG3 0 1178 #define UMC_BASE__INST0_SEG4 0 1179 #define UMC_BASE__INST0_SEG5 0 1180 1181 #define UMC_BASE__INST1_SEG0 0x00054000 1182 #define UMC_BASE__INST1_SEG1 0x02425C00 1183 #define UMC_BASE__INST1_SEG2 0 1184 #define UMC_BASE__INST1_SEG3 0 1185 #define UMC_BASE__INST1_SEG4 0 1186 #define UMC_BASE__INST1_SEG5 0 1187 1188 #define UMC_BASE__INST2_SEG0 0 1189 #define UMC_BASE__INST2_SEG1 0 1190 #define UMC_BASE__INST2_SEG2 0 1191 #define UMC_BASE__INST2_SEG3 0 1192 #define UMC_BASE__INST2_SEG4 0 1193 #define UMC_BASE__INST2_SEG5 0 1194 1195 #define UMC_BASE__INST3_SEG0 0 1196 #define UMC_BASE__INST3_SEG1 0 1197 #define UMC_BASE__INST3_SEG2 0 1198 #define UMC_BASE__INST3_SEG3 0 1199 #define UMC_BASE__INST3_SEG4 0 1200 #define UMC_BASE__INST3_SEG5 0 1201 1202 #define UMC_BASE__INST4_SEG0 0 1203 #define UMC_BASE__INST4_SEG1 0 1204 #define UMC_BASE__INST4_SEG2 0 1205 #define UMC_BASE__INST4_SEG3 0 1206 #define UMC_BASE__INST4_SEG4 0 1207 #define UMC_BASE__INST4_SEG5 0 1208 1209 #define UMC_BASE__INST5_SEG0 0 1210 #define UMC_BASE__INST5_SEG1 0 1211 #define UMC_BASE__INST5_SEG2 0 1212 #define UMC_BASE__INST5_SEG3 0 1213 #define UMC_BASE__INST5_SEG4 0 1214 #define UMC_BASE__INST5_SEG5 0 1215 1216 #define UMC_BASE__INST6_SEG0 0 1217 #define UMC_BASE__INST6_SEG1 0 1218 #define UMC_BASE__INST6_SEG2 0 1219 #define UMC_BASE__INST6_SEG3 0 1220 #define UMC_BASE__INST6_SEG4 0 1221 #define UMC_BASE__INST6_SEG5 0 1222 1223 #define VCN0_BASE__INST0_SEG0 0x00007800 1224 #define VCN0_BASE__INST0_SEG1 0x00007E00 1225 #define VCN0_BASE__INST0_SEG2 0x02403000 1226 #define VCN0_BASE__INST0_SEG3 0 1227 #define VCN0_BASE__INST0_SEG4 0 1228 #define VCN0_BASE__INST0_SEG5 0 1229 1230 #define VCN0_BASE__INST1_SEG0 0 1231 #define VCN0_BASE__INST1_SEG1 0 1232 #define VCN0_BASE__INST1_SEG2 0 1233 #define VCN0_BASE__INST1_SEG3 0 1234 #define VCN0_BASE__INST1_SEG4 0 1235 #define VCN0_BASE__INST1_SEG5 0 1236 1237 #define VCN0_BASE__INST2_SEG0 0 1238 #define VCN0_BASE__INST2_SEG1 0 1239 #define VCN0_BASE__INST2_SEG2 0 1240 #define VCN0_BASE__INST2_SEG3 0 1241 #define VCN0_BASE__INST2_SEG4 0 1242 #define VCN0_BASE__INST2_SEG5 0 1243 1244 #define VCN0_BASE__INST3_SEG0 0 1245 #define VCN0_BASE__INST3_SEG1 0 1246 #define VCN0_BASE__INST3_SEG2 0 1247 #define VCN0_BASE__INST3_SEG3 0 1248 #define VCN0_BASE__INST3_SEG4 0 1249 #define VCN0_BASE__INST3_SEG5 0 1250 1251 #define VCN0_BASE__INST4_SEG0 0 1252 #define VCN0_BASE__INST4_SEG1 0 1253 #define VCN0_BASE__INST4_SEG2 0 1254 #define VCN0_BASE__INST4_SEG3 0 1255 #define VCN0_BASE__INST4_SEG4 0 1256 #define VCN0_BASE__INST4_SEG5 0 1257 1258 #define VCN0_BASE__INST5_SEG0 0 1259 #define VCN0_BASE__INST5_SEG1 0 1260 #define VCN0_BASE__INST5_SEG2 0 1261 #define VCN0_BASE__INST5_SEG3 0 1262 #define VCN0_BASE__INST5_SEG4 0 1263 #define VCN0_BASE__INST5_SEG5 0 1264 1265 #define VCN0_BASE__INST6_SEG0 0 1266 #define VCN0_BASE__INST6_SEG1 0 1267 #define VCN0_BASE__INST6_SEG2 0 1268 #define VCN0_BASE__INST6_SEG3 0 1269 #define VCN0_BASE__INST6_SEG4 0 1270 #define VCN0_BASE__INST6_SEG5 0 1271 1272 #endif 1273