1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 184 }; 185 186 enum atom_dp_vs_preemph_def{ 187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 197 }; 198 199 200 /* 201 enum atom_string_def{ 202 asic_bus_type_pcie_string = "PCI_EXPRESS", 203 atom_fire_gl_string = "FGL", 204 atom_bios_string = "ATOM" 205 }; 206 */ 207 208 #pragma pack(1) /* BIOS data must use byte aligment*/ 209 210 enum atombios_image_offset{ 211 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 212 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 213 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 214 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 215 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 216 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 217 }; 218 219 /**************************************************************************** 220 * Common header for all tables (Data table, Command function). 221 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 222 * And the pointer actually points to this header. 223 ****************************************************************************/ 224 225 struct atom_common_table_header 226 { 227 uint16_t structuresize; 228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 230 }; 231 232 /**************************************************************************** 233 * Structure stores the ROM header. 234 ****************************************************************************/ 235 struct atom_rom_header_v2_2 236 { 237 struct atom_common_table_header table_header; 238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 239 uint16_t bios_segment_address; 240 uint16_t protectedmodeoffset; 241 uint16_t configfilenameoffset; 242 uint16_t crc_block_offset; 243 uint16_t vbios_bootupmessageoffset; 244 uint16_t int10_offset; 245 uint16_t pcibusdevinitcode; 246 uint16_t iobaseaddress; 247 uint16_t subsystem_vendor_id; 248 uint16_t subsystem_id; 249 uint16_t pci_info_offset; 250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 252 uint16_t reserved; 253 uint32_t pspdirtableoffset; 254 }; 255 256 /*==============================hw function portion======================================================================*/ 257 258 259 /**************************************************************************** 260 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 261 * The real functionality of each function is associated with the parameter structure version when defined 262 * For all internal cmd function definitions, please reference to atomstruct.h 263 ****************************************************************************/ 264 struct atom_master_list_of_command_functions_v2_1{ 265 uint16_t asic_init; //Function 266 uint16_t cmd_function1; //used as an internal one 267 uint16_t cmd_function2; //used as an internal one 268 uint16_t cmd_function3; //used as an internal one 269 uint16_t digxencodercontrol; //Function 270 uint16_t cmd_function5; //used as an internal one 271 uint16_t cmd_function6; //used as an internal one 272 uint16_t cmd_function7; //used as an internal one 273 uint16_t cmd_function8; //used as an internal one 274 uint16_t cmd_function9; //used as an internal one 275 uint16_t setengineclock; //Function 276 uint16_t setmemoryclock; //Function 277 uint16_t setpixelclock; //Function 278 uint16_t enabledisppowergating; //Function 279 uint16_t cmd_function14; //used as an internal one 280 uint16_t cmd_function15; //used as an internal one 281 uint16_t cmd_function16; //used as an internal one 282 uint16_t cmd_function17; //used as an internal one 283 uint16_t cmd_function18; //used as an internal one 284 uint16_t cmd_function19; //used as an internal one 285 uint16_t cmd_function20; //used as an internal one 286 uint16_t cmd_function21; //used as an internal one 287 uint16_t cmd_function22; //used as an internal one 288 uint16_t cmd_function23; //used as an internal one 289 uint16_t cmd_function24; //used as an internal one 290 uint16_t cmd_function25; //used as an internal one 291 uint16_t cmd_function26; //used as an internal one 292 uint16_t cmd_function27; //used as an internal one 293 uint16_t cmd_function28; //used as an internal one 294 uint16_t cmd_function29; //used as an internal one 295 uint16_t cmd_function30; //used as an internal one 296 uint16_t cmd_function31; //used as an internal one 297 uint16_t cmd_function32; //used as an internal one 298 uint16_t cmd_function33; //used as an internal one 299 uint16_t blankcrtc; //Function 300 uint16_t enablecrtc; //Function 301 uint16_t cmd_function36; //used as an internal one 302 uint16_t cmd_function37; //used as an internal one 303 uint16_t cmd_function38; //used as an internal one 304 uint16_t cmd_function39; //used as an internal one 305 uint16_t cmd_function40; //used as an internal one 306 uint16_t getsmuclockinfo; //Function 307 uint16_t selectcrtc_source; //Function 308 uint16_t cmd_function43; //used as an internal one 309 uint16_t cmd_function44; //used as an internal one 310 uint16_t cmd_function45; //used as an internal one 311 uint16_t setdceclock; //Function 312 uint16_t getmemoryclock; //Function 313 uint16_t getengineclock; //Function 314 uint16_t setcrtc_usingdtdtiming; //Function 315 uint16_t externalencodercontrol; //Function 316 uint16_t cmd_function51; //used as an internal one 317 uint16_t cmd_function52; //used as an internal one 318 uint16_t cmd_function53; //used as an internal one 319 uint16_t processi2cchanneltransaction;//Function 320 uint16_t cmd_function55; //used as an internal one 321 uint16_t cmd_function56; //used as an internal one 322 uint16_t cmd_function57; //used as an internal one 323 uint16_t cmd_function58; //used as an internal one 324 uint16_t cmd_function59; //used as an internal one 325 uint16_t computegpuclockparam; //Function 326 uint16_t cmd_function61; //used as an internal one 327 uint16_t cmd_function62; //used as an internal one 328 uint16_t dynamicmemorysettings; //Function function 329 uint16_t memorytraining; //Function function 330 uint16_t cmd_function65; //used as an internal one 331 uint16_t cmd_function66; //used as an internal one 332 uint16_t setvoltage; //Function 333 uint16_t cmd_function68; //used as an internal one 334 uint16_t readefusevalue; //Function 335 uint16_t cmd_function70; //used as an internal one 336 uint16_t cmd_function71; //used as an internal one 337 uint16_t cmd_function72; //used as an internal one 338 uint16_t cmd_function73; //used as an internal one 339 uint16_t cmd_function74; //used as an internal one 340 uint16_t cmd_function75; //used as an internal one 341 uint16_t dig1transmittercontrol; //Function 342 uint16_t cmd_function77; //used as an internal one 343 uint16_t processauxchanneltransaction;//Function 344 uint16_t cmd_function79; //used as an internal one 345 uint16_t getvoltageinfo; //Function 346 }; 347 348 struct atom_master_command_function_v2_1 349 { 350 struct atom_common_table_header table_header; 351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 352 }; 353 354 /**************************************************************************** 355 * Structures used in every command function 356 ****************************************************************************/ 357 struct atom_function_attribute 358 { 359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 362 }; 363 364 365 /**************************************************************************** 366 * Common header for all hw functions. 367 * Every function pointed by _master_list_of_hw_function has this common header. 368 * And the pointer actually points to this header. 369 ****************************************************************************/ 370 struct atom_rom_hw_function_header 371 { 372 struct atom_common_table_header func_header; 373 struct atom_function_attribute func_attrib; 374 }; 375 376 377 /*==============================sw data table portion======================================================================*/ 378 /**************************************************************************** 379 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 380 * The real name of each table is given when its data structure version is defined 381 ****************************************************************************/ 382 struct atom_master_list_of_data_tables_v2_1{ 383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 384 uint16_t multimedia_info; 385 uint16_t smc_dpm_info; 386 uint16_t sw_datatable3; 387 uint16_t firmwareinfo; /* Shared by various SW components */ 388 uint16_t sw_datatable5; 389 uint16_t lcd_info; /* Shared by various SW components */ 390 uint16_t sw_datatable7; 391 uint16_t smu_info; 392 uint16_t sw_datatable9; 393 uint16_t sw_datatable10; 394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 395 uint16_t gpio_pin_lut; /* Shared by various SW components */ 396 uint16_t sw_datatable13; 397 uint16_t gfx_info; 398 uint16_t powerplayinfo; /* Shared by various SW components */ 399 uint16_t sw_datatable16; 400 uint16_t sw_datatable17; 401 uint16_t sw_datatable18; 402 uint16_t sw_datatable19; 403 uint16_t sw_datatable20; 404 uint16_t sw_datatable21; 405 uint16_t displayobjectinfo; /* Shared by various SW components */ 406 uint16_t indirectioaccess; /* used as an internal one */ 407 uint16_t umc_info; /* Shared by various SW components */ 408 uint16_t sw_datatable25; 409 uint16_t sw_datatable26; 410 uint16_t dce_info; /* Shared by various SW components */ 411 uint16_t vram_info; /* Shared by various SW components */ 412 uint16_t sw_datatable29; 413 uint16_t integratedsysteminfo; /* Shared by various SW components */ 414 uint16_t asic_profiling_info; /* Shared by various SW components */ 415 uint16_t voltageobject_info; /* shared by various SW components */ 416 uint16_t sw_datatable33; 417 uint16_t sw_datatable34; 418 }; 419 420 421 struct atom_master_data_table_v2_1 422 { 423 struct atom_common_table_header table_header; 424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 425 }; 426 427 428 struct atom_dtd_format 429 { 430 uint16_t pixclk; 431 uint16_t h_active; 432 uint16_t h_blanking_time; 433 uint16_t v_active; 434 uint16_t v_blanking_time; 435 uint16_t h_sync_offset; 436 uint16_t h_sync_width; 437 uint16_t v_sync_offset; 438 uint16_t v_syncwidth; 439 uint16_t reserved; 440 uint16_t reserved0; 441 uint8_t h_border; 442 uint8_t v_border; 443 uint16_t miscinfo; 444 uint8_t atom_mode_id; 445 uint8_t refreshrate; 446 }; 447 448 /* atom_dtd_format.modemiscinfo defintion */ 449 enum atom_dtd_format_modemiscinfo{ 450 ATOM_HSYNC_POLARITY = 0x0002, 451 ATOM_VSYNC_POLARITY = 0x0004, 452 ATOM_H_REPLICATIONBY2 = 0x0010, 453 ATOM_V_REPLICATIONBY2 = 0x0020, 454 ATOM_INTERLACE = 0x0080, 455 ATOM_COMPOSITESYNC = 0x0040, 456 }; 457 458 459 /* utilitypipeline 460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 461 * the location of it can't change 462 */ 463 464 465 /* 466 *************************************************************************** 467 Data Table firmwareinfo structure 468 *************************************************************************** 469 */ 470 471 struct atom_firmware_info_v3_1 472 { 473 struct atom_common_table_header table_header; 474 uint32_t firmware_revision; 475 uint32_t bootup_sclk_in10khz; 476 uint32_t bootup_mclk_in10khz; 477 uint32_t firmware_capability; // enum atombios_firmware_capability 478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 480 uint16_t bootup_vddc_mv; 481 uint16_t bootup_vddci_mv; 482 uint16_t bootup_mvddc_mv; 483 uint16_t bootup_vddgfx_mv; 484 uint8_t mem_module_id; 485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 486 uint8_t reserved1[2]; 487 uint32_t mc_baseaddr_high; 488 uint32_t mc_baseaddr_low; 489 uint32_t reserved2[6]; 490 }; 491 492 /* Total 32bit cap indication */ 493 enum atombios_firmware_capability 494 { 495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 501 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 502 ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT = 0x0008000, 503 }; 504 505 enum atom_cooling_solution_id{ 506 AIR_COOLING = 0x00, 507 LIQUID_COOLING = 0x01 508 }; 509 510 struct atom_firmware_info_v3_2 { 511 struct atom_common_table_header table_header; 512 uint32_t firmware_revision; 513 uint32_t bootup_sclk_in10khz; 514 uint32_t bootup_mclk_in10khz; 515 uint32_t firmware_capability; // enum atombios_firmware_capability 516 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 517 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 518 uint16_t bootup_vddc_mv; 519 uint16_t bootup_vddci_mv; 520 uint16_t bootup_mvddc_mv; 521 uint16_t bootup_vddgfx_mv; 522 uint8_t mem_module_id; 523 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 524 uint8_t reserved1[2]; 525 uint32_t mc_baseaddr_high; 526 uint32_t mc_baseaddr_low; 527 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 528 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 529 uint8_t board_i2c_feature_slave_addr; 530 uint8_t reserved3; 531 uint16_t bootup_mvddq_mv; 532 uint16_t bootup_mvpp_mv; 533 uint32_t zfbstartaddrin16mb; 534 uint32_t reserved2[3]; 535 }; 536 537 struct atom_firmware_info_v3_3 538 { 539 struct atom_common_table_header table_header; 540 uint32_t firmware_revision; 541 uint32_t bootup_sclk_in10khz; 542 uint32_t bootup_mclk_in10khz; 543 uint32_t firmware_capability; // enum atombios_firmware_capability 544 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 545 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 546 uint16_t bootup_vddc_mv; 547 uint16_t bootup_vddci_mv; 548 uint16_t bootup_mvddc_mv; 549 uint16_t bootup_vddgfx_mv; 550 uint8_t mem_module_id; 551 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 552 uint8_t reserved1[2]; 553 uint32_t mc_baseaddr_high; 554 uint32_t mc_baseaddr_low; 555 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 556 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 557 uint8_t board_i2c_feature_slave_addr; 558 uint8_t reserved3; 559 uint16_t bootup_mvddq_mv; 560 uint16_t bootup_mvpp_mv; 561 uint32_t zfbstartaddrin16mb; 562 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 563 uint32_t reserved2[2]; 564 }; 565 566 struct atom_firmware_info_v3_4 { 567 struct atom_common_table_header table_header; 568 uint32_t firmware_revision; 569 uint32_t bootup_sclk_in10khz; 570 uint32_t bootup_mclk_in10khz; 571 uint32_t firmware_capability; // enum atombios_firmware_capability 572 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 573 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 574 uint16_t bootup_vddc_mv; 575 uint16_t bootup_vddci_mv; 576 uint16_t bootup_mvddc_mv; 577 uint16_t bootup_vddgfx_mv; 578 uint8_t mem_module_id; 579 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 580 uint8_t reserved1[2]; 581 uint32_t mc_baseaddr_high; 582 uint32_t mc_baseaddr_low; 583 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 584 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 585 uint8_t board_i2c_feature_slave_addr; 586 uint8_t reserved3; 587 uint16_t bootup_mvddq_mv; 588 uint16_t bootup_mvpp_mv; 589 uint32_t zfbstartaddrin16mb; 590 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 591 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 592 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 593 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 594 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 595 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 596 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 597 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 598 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 599 uint32_t reserved[5]; 600 }; 601 602 /* 603 *************************************************************************** 604 Data Table lcd_info structure 605 *************************************************************************** 606 */ 607 608 struct lcd_info_v2_1 609 { 610 struct atom_common_table_header table_header; 611 struct atom_dtd_format lcd_timing; 612 uint16_t backlight_pwm; 613 uint16_t special_handle_cap; 614 uint16_t panel_misc; 615 uint16_t lvds_max_slink_pclk; 616 uint16_t lvds_ss_percentage; 617 uint16_t lvds_ss_rate_10hz; 618 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 619 uint8_t pwr_on_de_to_vary_bl; 620 uint8_t pwr_down_vary_bloff_to_de; 621 uint8_t pwr_down_de_to_digoff; 622 uint8_t pwr_off_delay; 623 uint8_t pwr_on_vary_bl_to_blon; 624 uint8_t pwr_down_bloff_to_vary_bloff; 625 uint8_t panel_bpc; 626 uint8_t dpcd_edp_config_cap; 627 uint8_t dpcd_max_link_rate; 628 uint8_t dpcd_max_lane_count; 629 uint8_t dpcd_max_downspread; 630 uint8_t min_allowed_bl_level; 631 uint8_t max_allowed_bl_level; 632 uint8_t bootup_bl_level; 633 uint8_t dplvdsrxid; 634 uint32_t reserved1[8]; 635 }; 636 637 /* lcd_info_v2_1.panel_misc defintion */ 638 enum atom_lcd_info_panel_misc{ 639 ATOM_PANEL_MISC_FPDI =0x0002, 640 }; 641 642 //uceDPToLVDSRxId 643 enum atom_lcd_info_dptolvds_rx_id 644 { 645 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 646 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 647 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 648 }; 649 650 651 /* 652 *************************************************************************** 653 Data Table gpio_pin_lut structure 654 *************************************************************************** 655 */ 656 657 struct atom_gpio_pin_assignment 658 { 659 uint32_t data_a_reg_index; 660 uint8_t gpio_bitshift; 661 uint8_t gpio_mask_bitshift; 662 uint8_t gpio_id; 663 uint8_t reserved; 664 }; 665 666 /* atom_gpio_pin_assignment.gpio_id definition */ 667 enum atom_gpio_pin_assignment_gpio_id { 668 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 669 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 670 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 671 672 /* gpio_id pre-define id for multiple usage */ 673 /* GPIO use to control PCIE_VDDC in certain SLT board */ 674 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 675 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 676 PP_AC_DC_SWITCH_GPIO_PINID = 60, 677 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 678 VDDC_VRHOT_GPIO_PINID = 61, 679 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 680 VDDC_PCC_GPIO_PINID = 62, 681 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 682 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 683 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 684 DRAM_SELF_REFRESH_GPIO_PINID = 64, 685 /* Thermal interrupt output->system thermal chip GPIO pin */ 686 THERMAL_INT_OUTPUT_GPIO_PINID =65, 687 }; 688 689 690 struct atom_gpio_pin_lut_v2_1 691 { 692 struct atom_common_table_header table_header; 693 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 694 struct atom_gpio_pin_assignment gpio_pin[8]; 695 }; 696 697 698 /* 699 *************************************************************************** 700 Data Table vram_usagebyfirmware structure 701 *************************************************************************** 702 */ 703 704 struct vram_usagebyfirmware_v2_1 705 { 706 struct atom_common_table_header table_header; 707 uint32_t start_address_in_kb; 708 uint16_t used_by_firmware_in_kb; 709 uint16_t used_by_driver_in_kb; 710 }; 711 712 713 /* 714 *************************************************************************** 715 Data Table displayobjectinfo structure 716 *************************************************************************** 717 */ 718 719 enum atom_object_record_type_id 720 { 721 ATOM_I2C_RECORD_TYPE =1, 722 ATOM_HPD_INT_RECORD_TYPE =2, 723 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 724 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 725 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 726 ATOM_ENCODER_CAP_RECORD_TYPE=20, 727 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 728 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 729 ATOM_DISP_CONNECTOR_CAPS_RECORD_TYPE=23, 730 ATOM_RECORD_END_TYPE =0xFF, 731 }; 732 733 struct atom_common_record_header 734 { 735 uint8_t record_type; //An emun to indicate the record type 736 uint8_t record_size; //The size of the whole record in byte 737 }; 738 739 struct atom_i2c_record 740 { 741 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 742 uint8_t i2c_id; 743 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 744 }; 745 746 struct atom_hpd_int_record 747 { 748 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 749 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 750 uint8_t plugin_pin_state; 751 }; 752 753 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 754 enum atom_encoder_caps_def 755 { 756 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 757 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 758 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 759 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 760 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 761 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 762 }; 763 764 struct atom_encoder_caps_record 765 { 766 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 767 uint32_t encodercaps; 768 }; 769 770 enum atom_connector_caps_def 771 { 772 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 773 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 774 }; 775 776 struct atom_disp_connector_caps_record 777 { 778 struct atom_common_record_header record_header; 779 uint32_t connectcaps; 780 }; 781 782 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 783 struct atom_gpio_pin_control_pair 784 { 785 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 786 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 787 }; 788 789 struct atom_object_gpio_cntl_record 790 { 791 struct atom_common_record_header record_header; 792 uint8_t flag; // Future expnadibility 793 uint8_t number_of_pins; // Number of GPIO pins used to control the object 794 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 795 }; 796 797 //Definitions for GPIO pin state 798 enum atom_gpio_pin_control_pinstate_def 799 { 800 GPIO_PIN_TYPE_INPUT = 0x00, 801 GPIO_PIN_TYPE_OUTPUT = 0x10, 802 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 803 804 //For GPIO_PIN_TYPE_OUTPUT the following is defined 805 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 806 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 807 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 808 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 809 }; 810 811 // Indexes to GPIO array in GLSync record 812 // GLSync record is for Frame Lock/Gen Lock feature. 813 enum atom_glsync_record_gpio_index_def 814 { 815 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 816 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 817 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 818 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 819 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 820 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 821 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 822 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 823 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 824 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 825 }; 826 827 828 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 829 { 830 struct atom_common_record_header record_header; 831 uint8_t hpd_pin_map[8]; 832 }; 833 834 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 835 { 836 struct atom_common_record_header record_header; 837 uint8_t aux_ddc_map[8]; 838 }; 839 840 struct atom_connector_forced_tmds_cap_record 841 { 842 struct atom_common_record_header record_header; 843 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 844 uint8_t maxtmdsclkrate_in2_5mhz; 845 uint8_t reserved; 846 }; 847 848 struct atom_connector_layout_info 849 { 850 uint16_t connectorobjid; 851 uint8_t connector_type; 852 uint8_t position; 853 }; 854 855 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 856 enum atom_connector_layout_info_connector_type_def 857 { 858 CONNECTOR_TYPE_DVI_D = 1, 859 860 CONNECTOR_TYPE_HDMI = 4, 861 CONNECTOR_TYPE_DISPLAY_PORT = 5, 862 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 863 }; 864 865 struct atom_bracket_layout_record 866 { 867 struct atom_common_record_header record_header; 868 uint8_t bracketlen; 869 uint8_t bracketwidth; 870 uint8_t conn_num; 871 uint8_t reserved; 872 struct atom_connector_layout_info conn_info[1]; 873 }; 874 875 enum atom_display_device_tag_def{ 876 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 877 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 878 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 879 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 880 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 881 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 882 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 883 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 884 }; 885 886 struct atom_display_object_path_v2 887 { 888 uint16_t display_objid; //Connector Object ID or Misc Object ID 889 uint16_t disp_recordoffset; 890 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 891 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 892 uint16_t encoder_recordoffset; 893 uint16_t extencoder_recordoffset; 894 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 895 uint8_t priority_id; 896 uint8_t reserved; 897 }; 898 899 struct display_object_info_table_v1_4 900 { 901 struct atom_common_table_header table_header; 902 uint16_t supporteddevices; 903 uint8_t number_of_path; 904 uint8_t reserved; 905 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 906 }; 907 908 909 /* 910 *************************************************************************** 911 Data Table dce_info structure 912 *************************************************************************** 913 */ 914 struct atom_display_controller_info_v4_1 915 { 916 struct atom_common_table_header table_header; 917 uint32_t display_caps; 918 uint32_t bootup_dispclk_10khz; 919 uint16_t dce_refclk_10khz; 920 uint16_t i2c_engine_refclk_10khz; 921 uint16_t dvi_ss_percentage; // in unit of 0.001% 922 uint16_t dvi_ss_rate_10hz; 923 uint16_t hdmi_ss_percentage; // in unit of 0.001% 924 uint16_t hdmi_ss_rate_10hz; 925 uint16_t dp_ss_percentage; // in unit of 0.001% 926 uint16_t dp_ss_rate_10hz; 927 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 928 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 929 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 930 uint8_t ss_reserved; 931 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 932 uint8_t reserved1[3]; 933 uint16_t dpphy_refclk_10khz; 934 uint16_t reserved2; 935 uint8_t dceip_min_ver; 936 uint8_t dceip_max_ver; 937 uint8_t max_disp_pipe_num; 938 uint8_t max_vbios_active_disp_pipe_num; 939 uint8_t max_ppll_num; 940 uint8_t max_disp_phy_num; 941 uint8_t max_aux_pairs; 942 uint8_t remotedisplayconfig; 943 uint8_t reserved3[8]; 944 }; 945 946 struct atom_display_controller_info_v4_2 947 { 948 struct atom_common_table_header table_header; 949 uint32_t display_caps; 950 uint32_t bootup_dispclk_10khz; 951 uint16_t dce_refclk_10khz; 952 uint16_t i2c_engine_refclk_10khz; 953 uint16_t dvi_ss_percentage; // in unit of 0.001% 954 uint16_t dvi_ss_rate_10hz; 955 uint16_t hdmi_ss_percentage; // in unit of 0.001% 956 uint16_t hdmi_ss_rate_10hz; 957 uint16_t dp_ss_percentage; // in unit of 0.001% 958 uint16_t dp_ss_rate_10hz; 959 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 960 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 961 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 962 uint8_t ss_reserved; 963 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 964 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 965 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 966 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 967 uint16_t dpphy_refclk_10khz; 968 uint16_t reserved2; 969 uint8_t dcnip_min_ver; 970 uint8_t dcnip_max_ver; 971 uint8_t max_disp_pipe_num; 972 uint8_t max_vbios_active_disp_pipe_num; 973 uint8_t max_ppll_num; 974 uint8_t max_disp_phy_num; 975 uint8_t max_aux_pairs; 976 uint8_t remotedisplayconfig; 977 uint8_t reserved3[8]; 978 }; 979 980 struct atom_display_controller_info_v4_4 { 981 struct atom_common_table_header table_header; 982 uint32_t display_caps; 983 uint32_t bootup_dispclk_10khz; 984 uint16_t dce_refclk_10khz; 985 uint16_t i2c_engine_refclk_10khz; 986 uint16_t dvi_ss_percentage; // in unit of 0.001% 987 uint16_t dvi_ss_rate_10hz; 988 uint16_t hdmi_ss_percentage; // in unit of 0.001% 989 uint16_t hdmi_ss_rate_10hz; 990 uint16_t dp_ss_percentage; // in unit of 0.001% 991 uint16_t dp_ss_rate_10hz; 992 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 993 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 994 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 995 uint8_t ss_reserved; 996 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 997 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 998 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 999 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 1000 uint16_t dpphy_refclk_10khz; 1001 uint16_t hw_chip_id; 1002 uint8_t dcnip_min_ver; 1003 uint8_t dcnip_max_ver; 1004 uint8_t max_disp_pipe_num; 1005 uint8_t max_vbios_active_disp_pipum; 1006 uint8_t max_ppll_num; 1007 uint8_t max_disp_phy_num; 1008 uint8_t max_aux_pairs; 1009 uint8_t remotedisplayconfig; 1010 uint32_t dispclk_pll_vco_freq; 1011 uint32_t dp_ref_clk_freq; 1012 uint32_t max_mclk_chg_lat; // Worst case blackout duration for a memory clock frequency (p-state) change, units of 100s of ns (0.1 us) 1013 uint32_t max_sr_exit_lat; // Worst case memory self refresh exit time, units of 100ns of ns (0.1us) 1014 uint32_t max_sr_enter_exit_lat; // Worst case memory self refresh entry followed by immediate exit time, units of 100ns of ns (0.1us) 1015 uint16_t dc_golden_table_offset; // point of struct of atom_dc_golden_table_vxx 1016 uint16_t dc_golden_table_ver; 1017 uint32_t reserved3[3]; 1018 }; 1019 1020 struct atom_dc_golden_table_v1 1021 { 1022 uint32_t aux_dphy_rx_control0_val; 1023 uint32_t aux_dphy_tx_control_val; 1024 uint32_t aux_dphy_rx_control1_val; 1025 uint32_t dc_gpio_aux_ctrl_0_val; 1026 uint32_t dc_gpio_aux_ctrl_1_val; 1027 uint32_t dc_gpio_aux_ctrl_2_val; 1028 uint32_t dc_gpio_aux_ctrl_3_val; 1029 uint32_t dc_gpio_aux_ctrl_4_val; 1030 uint32_t dc_gpio_aux_ctrl_5_val; 1031 uint32_t reserved[23]; 1032 }; 1033 1034 enum dce_info_caps_def 1035 { 1036 // only for VBIOS 1037 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 1038 // only for VBIOS 1039 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 1040 // only for VBIOS 1041 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 1042 1043 }; 1044 1045 /* 1046 *************************************************************************** 1047 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 1048 *************************************************************************** 1049 */ 1050 struct atom_ext_display_path 1051 { 1052 uint16_t device_tag; //A bit vector to show what devices are supported 1053 uint16_t device_acpi_enum; //16bit device ACPI id. 1054 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1055 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1056 uint8_t hpdlut_index; //An index into external HPD pin LUT 1057 uint16_t ext_encoder_objid; //external encoder object id 1058 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1059 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1060 uint16_t caps; 1061 uint16_t reserved; 1062 }; 1063 1064 //usCaps 1065 enum ext_display_path_cap_def { 1066 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1067 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1068 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1069 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1070 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1071 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1072 }; 1073 1074 struct atom_external_display_connection_info 1075 { 1076 struct atom_common_table_header table_header; 1077 uint8_t guid[16]; // a GUID is a 16 byte long string 1078 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1079 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1080 uint8_t stereopinid; // use for eDP panel 1081 uint8_t remotedisplayconfig; 1082 uint8_t edptolvdsrxid; 1083 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1084 uint8_t reserved[3]; // for potential expansion 1085 }; 1086 1087 /* 1088 *************************************************************************** 1089 Data Table integratedsysteminfo structure 1090 *************************************************************************** 1091 */ 1092 1093 struct atom_camera_dphy_timing_param 1094 { 1095 uint8_t profile_id; // SENSOR_PROFILES 1096 uint32_t param; 1097 }; 1098 1099 struct atom_camera_dphy_elec_param 1100 { 1101 uint16_t param[3]; 1102 }; 1103 1104 struct atom_camera_module_info 1105 { 1106 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1107 uint8_t module_name[8]; 1108 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1109 }; 1110 1111 struct atom_camera_flashlight_info 1112 { 1113 uint8_t flashlight_id; // 0: Rear, 1: Front 1114 uint8_t name[8]; 1115 }; 1116 1117 struct atom_camera_data 1118 { 1119 uint32_t versionCode; 1120 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1121 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1122 struct atom_camera_dphy_elec_param dphy_param; 1123 uint32_t crc_val; // CRC 1124 }; 1125 1126 1127 struct atom_14nm_dpphy_dvihdmi_tuningset 1128 { 1129 uint32_t max_symclk_in10khz; 1130 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1131 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1132 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1133 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1134 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1135 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1136 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1137 }; 1138 1139 struct atom_14nm_dpphy_dp_setting{ 1140 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1141 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1142 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1143 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1144 }; 1145 1146 struct atom_14nm_dpphy_dp_tuningset{ 1147 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1148 uint8_t version; 1149 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1150 uint16_t reserved; 1151 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1152 }; 1153 1154 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1155 struct atom_common_table_header table_header; 1156 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1157 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1158 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1159 }; 1160 1161 struct atom_14nm_combphy_tmds_vs_set 1162 { 1163 uint8_t sym_clk; 1164 uint8_t dig_mode; 1165 uint8_t phy_sel; 1166 uint16_t common_mar_deemph_nom__margin_deemph_val; 1167 uint8_t common_seldeemph60__deemph_6db_4_val; 1168 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1169 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1170 uint8_t margin_deemph_lane0__deemph_sel_val; 1171 }; 1172 1173 struct atom_DCN_dpphy_dvihdmi_tuningset 1174 { 1175 uint32_t max_symclk_in10khz; 1176 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1177 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1178 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1179 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1180 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1181 uint8_t reserved1; 1182 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1183 uint8_t reserved2; 1184 }; 1185 1186 struct atom_DCN_dpphy_dp_setting{ 1187 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1188 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1189 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1190 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1191 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1192 }; 1193 1194 struct atom_DCN_dpphy_dp_tuningset{ 1195 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1196 uint8_t version; 1197 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1198 uint16_t reserved; 1199 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1200 }; 1201 1202 struct atom_i2c_reg_info { 1203 uint8_t ucI2cRegIndex; 1204 uint8_t ucI2cRegVal; 1205 }; 1206 1207 struct atom_hdmi_retimer_redriver_set { 1208 uint8_t HdmiSlvAddr; 1209 uint8_t HdmiRegNum; 1210 uint8_t Hdmi6GRegNum; 1211 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1212 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1213 }; 1214 1215 struct atom_integrated_system_info_v1_11 1216 { 1217 struct atom_common_table_header table_header; 1218 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1219 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1220 uint32_t system_config; 1221 uint32_t cpucapinfo; 1222 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1223 uint16_t gpuclk_ss_type; 1224 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1225 uint16_t lvds_ss_rate_10hz; 1226 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1227 uint16_t hdmi_ss_rate_10hz; 1228 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1229 uint16_t dvi_ss_rate_10hz; 1230 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1231 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1232 uint16_t backlight_pwm_hz; // pwm frequency in hz 1233 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1234 uint8_t umachannelnumber; // number of memory channels 1235 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1236 uint8_t pwr_on_de_to_vary_bl; 1237 uint8_t pwr_down_vary_bloff_to_de; 1238 uint8_t pwr_down_de_to_digoff; 1239 uint8_t pwr_off_delay; 1240 uint8_t pwr_on_vary_bl_to_blon; 1241 uint8_t pwr_down_bloff_to_vary_bloff; 1242 uint8_t min_allowed_bl_level; 1243 uint8_t htc_hyst_limit; 1244 uint8_t htc_tmp_limit; 1245 uint8_t reserved1; 1246 uint8_t reserved2; 1247 struct atom_external_display_connection_info extdispconninfo; 1248 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1249 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1250 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1251 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1252 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1253 struct atom_camera_data camera_info; 1254 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1255 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1256 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1257 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1258 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1259 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1260 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1261 uint32_t reserved[66]; 1262 }; 1263 1264 struct atom_integrated_system_info_v1_12 1265 { 1266 struct atom_common_table_header table_header; 1267 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1268 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1269 uint32_t system_config; 1270 uint32_t cpucapinfo; 1271 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1272 uint16_t gpuclk_ss_type; 1273 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1274 uint16_t lvds_ss_rate_10hz; 1275 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1276 uint16_t hdmi_ss_rate_10hz; 1277 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1278 uint16_t dvi_ss_rate_10hz; 1279 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1280 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1281 uint16_t backlight_pwm_hz; // pwm frequency in hz 1282 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1283 uint8_t umachannelnumber; // number of memory channels 1284 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1285 uint8_t pwr_on_de_to_vary_bl; 1286 uint8_t pwr_down_vary_bloff_to_de; 1287 uint8_t pwr_down_de_to_digoff; 1288 uint8_t pwr_off_delay; 1289 uint8_t pwr_on_vary_bl_to_blon; 1290 uint8_t pwr_down_bloff_to_vary_bloff; 1291 uint8_t min_allowed_bl_level; 1292 uint8_t htc_hyst_limit; 1293 uint8_t htc_tmp_limit; 1294 uint8_t reserved1; 1295 uint8_t reserved2; 1296 struct atom_external_display_connection_info extdispconninfo; 1297 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1298 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1299 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1300 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1301 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1302 struct atom_camera_data camera_info; 1303 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1304 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1305 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1306 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1307 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1308 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1309 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1310 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1311 uint32_t reserved[63]; 1312 }; 1313 1314 struct edp_info_table 1315 { 1316 uint16_t edp_backlight_pwm_hz; 1317 uint16_t edp_ss_percentage; 1318 uint16_t edp_ss_rate_10hz; 1319 uint16_t reserved1; 1320 uint32_t reserved2; 1321 uint8_t edp_pwr_on_off_delay; 1322 uint8_t edp_pwr_on_vary_bl_to_blon; 1323 uint8_t edp_pwr_down_bloff_to_vary_bloff; 1324 uint8_t edp_panel_bpc; 1325 uint8_t edp_bootup_bl_level; 1326 uint8_t reserved3[3]; 1327 uint32_t reserved4[3]; 1328 }; 1329 1330 struct atom_integrated_system_info_v2_1 1331 { 1332 struct atom_common_table_header table_header; 1333 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1334 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1335 uint32_t system_config; 1336 uint32_t cpucapinfo; 1337 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1338 uint16_t gpuclk_ss_type; 1339 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1340 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1341 uint8_t umachannelnumber; // number of memory channels 1342 uint8_t htc_hyst_limit; 1343 uint8_t htc_tmp_limit; 1344 uint8_t reserved1; 1345 uint8_t reserved2; 1346 struct edp_info_table edp1_info; 1347 struct edp_info_table edp2_info; 1348 uint32_t reserved3[8]; 1349 struct atom_external_display_connection_info extdispconninfo; 1350 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1351 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; //add clk6 1352 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1353 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1354 uint32_t reserved4[6];//reserve 2*sizeof(atom_DCN_dpphy_dvihdmi_tuningset) 1355 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1356 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1357 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1358 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1359 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1360 uint32_t reserved5[28];//reserve 2*sizeof(atom_DCN_dpphy_dp_tuningset) 1361 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1362 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1363 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1364 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1365 uint32_t reserved6[30];// reserve size of(atom_camera_data) for camera_info 1366 uint32_t reserved7[32]; 1367 1368 }; 1369 1370 // system_config 1371 enum atom_system_vbiosmisc_def{ 1372 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1373 }; 1374 1375 1376 // gpucapinfo 1377 enum atom_system_gpucapinf_def{ 1378 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1379 }; 1380 1381 //dpphy_override 1382 enum atom_sysinfo_dpphy_override_def{ 1383 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1384 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1385 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1386 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1387 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1388 }; 1389 1390 //lvds_misc 1391 enum atom_sys_info_lvds_misc_def 1392 { 1393 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1394 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1395 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1396 }; 1397 1398 1399 //memorytype DMI Type 17 offset 12h - Memory Type 1400 enum atom_dmi_t17_mem_type_def{ 1401 OtherMemType = 0x01, ///< Assign 01 to Other 1402 UnknownMemType, ///< Assign 02 to Unknown 1403 DramMemType, ///< Assign 03 to DRAM 1404 EdramMemType, ///< Assign 04 to EDRAM 1405 VramMemType, ///< Assign 05 to VRAM 1406 SramMemType, ///< Assign 06 to SRAM 1407 RamMemType, ///< Assign 07 to RAM 1408 RomMemType, ///< Assign 08 to ROM 1409 FlashMemType, ///< Assign 09 to Flash 1410 EepromMemType, ///< Assign 10 to EEPROM 1411 FepromMemType, ///< Assign 11 to FEPROM 1412 EpromMemType, ///< Assign 12 to EPROM 1413 CdramMemType, ///< Assign 13 to CDRAM 1414 ThreeDramMemType, ///< Assign 14 to 3DRAM 1415 SdramMemType, ///< Assign 15 to SDRAM 1416 SgramMemType, ///< Assign 16 to SGRAM 1417 RdramMemType, ///< Assign 17 to RDRAM 1418 DdrMemType, ///< Assign 18 to DDR 1419 Ddr2MemType, ///< Assign 19 to DDR2 1420 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1421 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1422 Fbd2MemType, ///< Assign 25 to FBD2 1423 Ddr4MemType, ///< Assign 26 to DDR4 1424 LpDdrMemType, ///< Assign 27 to LPDDR 1425 LpDdr2MemType, ///< Assign 28 to LPDDR2 1426 LpDdr3MemType, ///< Assign 29 to LPDDR3 1427 LpDdr4MemType, ///< Assign 30 to LPDDR4 1428 GDdr6MemType, ///< Assign 31 to GDDR6 1429 HbmMemType, ///< Assign 32 to HBM 1430 Hbm2MemType, ///< Assign 33 to HBM2 1431 Ddr5MemType, ///< Assign 34 to DDR5 1432 LpDdr5MemType, ///< Assign 35 to LPDDR5 1433 }; 1434 1435 1436 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1437 struct atom_fusion_system_info_v4 1438 { 1439 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1440 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1441 }; 1442 1443 1444 /* 1445 *************************************************************************** 1446 Data Table gfx_info structure 1447 *************************************************************************** 1448 */ 1449 1450 struct atom_gfx_info_v2_2 1451 { 1452 struct atom_common_table_header table_header; 1453 uint8_t gfxip_min_ver; 1454 uint8_t gfxip_max_ver; 1455 uint8_t max_shader_engines; 1456 uint8_t max_tile_pipes; 1457 uint8_t max_cu_per_sh; 1458 uint8_t max_sh_per_se; 1459 uint8_t max_backends_per_se; 1460 uint8_t max_texture_channel_caches; 1461 uint32_t regaddr_cp_dma_src_addr; 1462 uint32_t regaddr_cp_dma_src_addr_hi; 1463 uint32_t regaddr_cp_dma_dst_addr; 1464 uint32_t regaddr_cp_dma_dst_addr_hi; 1465 uint32_t regaddr_cp_dma_command; 1466 uint32_t regaddr_cp_status; 1467 uint32_t regaddr_rlc_gpu_clock_32; 1468 uint32_t rlc_gpu_timer_refclk; 1469 }; 1470 1471 struct atom_gfx_info_v2_3 { 1472 struct atom_common_table_header table_header; 1473 uint8_t gfxip_min_ver; 1474 uint8_t gfxip_max_ver; 1475 uint8_t max_shader_engines; 1476 uint8_t max_tile_pipes; 1477 uint8_t max_cu_per_sh; 1478 uint8_t max_sh_per_se; 1479 uint8_t max_backends_per_se; 1480 uint8_t max_texture_channel_caches; 1481 uint32_t regaddr_cp_dma_src_addr; 1482 uint32_t regaddr_cp_dma_src_addr_hi; 1483 uint32_t regaddr_cp_dma_dst_addr; 1484 uint32_t regaddr_cp_dma_dst_addr_hi; 1485 uint32_t regaddr_cp_dma_command; 1486 uint32_t regaddr_cp_status; 1487 uint32_t regaddr_rlc_gpu_clock_32; 1488 uint32_t rlc_gpu_timer_refclk; 1489 uint8_t active_cu_per_sh; 1490 uint8_t active_rb_per_se; 1491 uint16_t gcgoldenoffset; 1492 uint32_t rm21_sram_vmin_value; 1493 }; 1494 1495 struct atom_gfx_info_v2_4 1496 { 1497 struct atom_common_table_header table_header; 1498 uint8_t gfxip_min_ver; 1499 uint8_t gfxip_max_ver; 1500 uint8_t max_shader_engines; 1501 uint8_t reserved; 1502 uint8_t max_cu_per_sh; 1503 uint8_t max_sh_per_se; 1504 uint8_t max_backends_per_se; 1505 uint8_t max_texture_channel_caches; 1506 uint32_t regaddr_cp_dma_src_addr; 1507 uint32_t regaddr_cp_dma_src_addr_hi; 1508 uint32_t regaddr_cp_dma_dst_addr; 1509 uint32_t regaddr_cp_dma_dst_addr_hi; 1510 uint32_t regaddr_cp_dma_command; 1511 uint32_t regaddr_cp_status; 1512 uint32_t regaddr_rlc_gpu_clock_32; 1513 uint32_t rlc_gpu_timer_refclk; 1514 uint8_t active_cu_per_sh; 1515 uint8_t active_rb_per_se; 1516 uint16_t gcgoldenoffset; 1517 uint16_t gc_num_gprs; 1518 uint16_t gc_gsprim_buff_depth; 1519 uint16_t gc_parameter_cache_depth; 1520 uint16_t gc_wave_size; 1521 uint16_t gc_max_waves_per_simd; 1522 uint16_t gc_lds_size; 1523 uint8_t gc_num_max_gs_thds; 1524 uint8_t gc_gs_table_depth; 1525 uint8_t gc_double_offchip_lds_buffer; 1526 uint8_t gc_max_scratch_slots_per_cu; 1527 uint32_t sram_rm_fuses_val; 1528 uint32_t sram_custom_rm_fuses_val; 1529 }; 1530 1531 /* 1532 *************************************************************************** 1533 Data Table smu_info structure 1534 *************************************************************************** 1535 */ 1536 struct atom_smu_info_v3_1 1537 { 1538 struct atom_common_table_header table_header; 1539 uint8_t smuip_min_ver; 1540 uint8_t smuip_max_ver; 1541 uint8_t smu_rsd1; 1542 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1543 uint16_t sclk_ss_percentage; 1544 uint16_t sclk_ss_rate_10hz; 1545 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1546 uint16_t gpuclk_ss_rate_10hz; 1547 uint32_t core_refclk_10khz; 1548 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1549 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1550 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1551 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1552 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1553 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1554 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1555 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1556 }; 1557 1558 struct atom_smu_info_v3_2 { 1559 struct atom_common_table_header table_header; 1560 uint8_t smuip_min_ver; 1561 uint8_t smuip_max_ver; 1562 uint8_t smu_rsd1; 1563 uint8_t gpuclk_ss_mode; 1564 uint16_t sclk_ss_percentage; 1565 uint16_t sclk_ss_rate_10hz; 1566 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1567 uint16_t gpuclk_ss_rate_10hz; 1568 uint32_t core_refclk_10khz; 1569 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1570 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1571 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1572 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1573 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1574 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1575 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1576 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1577 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1578 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1579 uint16_t smugoldenoffset; 1580 uint32_t gpupll_vco_freq_10khz; 1581 uint32_t bootup_smnclk_10khz; 1582 uint32_t bootup_socclk_10khz; 1583 uint32_t bootup_mp0clk_10khz; 1584 uint32_t bootup_mp1clk_10khz; 1585 uint32_t bootup_lclk_10khz; 1586 uint32_t bootup_dcefclk_10khz; 1587 uint32_t ctf_threshold_override_value; 1588 uint32_t reserved[5]; 1589 }; 1590 1591 struct atom_smu_info_v3_3 { 1592 struct atom_common_table_header table_header; 1593 uint8_t smuip_min_ver; 1594 uint8_t smuip_max_ver; 1595 uint8_t waflclk_ss_mode; 1596 uint8_t gpuclk_ss_mode; 1597 uint16_t sclk_ss_percentage; 1598 uint16_t sclk_ss_rate_10hz; 1599 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1600 uint16_t gpuclk_ss_rate_10hz; 1601 uint32_t core_refclk_10khz; 1602 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1603 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1604 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1605 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1606 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1607 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1608 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1609 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1610 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1611 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1612 uint16_t smugoldenoffset; 1613 uint32_t gpupll_vco_freq_10khz; 1614 uint32_t bootup_smnclk_10khz; 1615 uint32_t bootup_socclk_10khz; 1616 uint32_t bootup_mp0clk_10khz; 1617 uint32_t bootup_mp1clk_10khz; 1618 uint32_t bootup_lclk_10khz; 1619 uint32_t bootup_dcefclk_10khz; 1620 uint32_t ctf_threshold_override_value; 1621 uint32_t syspll3_0_vco_freq_10khz; 1622 uint32_t syspll3_1_vco_freq_10khz; 1623 uint32_t bootup_fclk_10khz; 1624 uint32_t bootup_waflclk_10khz; 1625 uint32_t smu_info_caps; 1626 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1627 uint16_t smuinitoffset; 1628 uint32_t reserved; 1629 }; 1630 1631 /* 1632 *************************************************************************** 1633 Data Table smc_dpm_info structure 1634 *************************************************************************** 1635 */ 1636 struct atom_smc_dpm_info_v4_1 1637 { 1638 struct atom_common_table_header table_header; 1639 uint8_t liquid1_i2c_address; 1640 uint8_t liquid2_i2c_address; 1641 uint8_t vr_i2c_address; 1642 uint8_t plx_i2c_address; 1643 1644 uint8_t liquid_i2c_linescl; 1645 uint8_t liquid_i2c_linesda; 1646 uint8_t vr_i2c_linescl; 1647 uint8_t vr_i2c_linesda; 1648 1649 uint8_t plx_i2c_linescl; 1650 uint8_t plx_i2c_linesda; 1651 uint8_t vrsensorpresent; 1652 uint8_t liquidsensorpresent; 1653 1654 uint16_t maxvoltagestepgfx; 1655 uint16_t maxvoltagestepsoc; 1656 1657 uint8_t vddgfxvrmapping; 1658 uint8_t vddsocvrmapping; 1659 uint8_t vddmem0vrmapping; 1660 uint8_t vddmem1vrmapping; 1661 1662 uint8_t gfxulvphasesheddingmask; 1663 uint8_t soculvphasesheddingmask; 1664 uint8_t padding8_v[2]; 1665 1666 uint16_t gfxmaxcurrent; 1667 uint8_t gfxoffset; 1668 uint8_t padding_telemetrygfx; 1669 1670 uint16_t socmaxcurrent; 1671 uint8_t socoffset; 1672 uint8_t padding_telemetrysoc; 1673 1674 uint16_t mem0maxcurrent; 1675 uint8_t mem0offset; 1676 uint8_t padding_telemetrymem0; 1677 1678 uint16_t mem1maxcurrent; 1679 uint8_t mem1offset; 1680 uint8_t padding_telemetrymem1; 1681 1682 uint8_t acdcgpio; 1683 uint8_t acdcpolarity; 1684 uint8_t vr0hotgpio; 1685 uint8_t vr0hotpolarity; 1686 1687 uint8_t vr1hotgpio; 1688 uint8_t vr1hotpolarity; 1689 uint8_t padding1; 1690 uint8_t padding2; 1691 1692 uint8_t ledpin0; 1693 uint8_t ledpin1; 1694 uint8_t ledpin2; 1695 uint8_t padding8_4; 1696 1697 uint8_t pllgfxclkspreadenabled; 1698 uint8_t pllgfxclkspreadpercent; 1699 uint16_t pllgfxclkspreadfreq; 1700 1701 uint8_t uclkspreadenabled; 1702 uint8_t uclkspreadpercent; 1703 uint16_t uclkspreadfreq; 1704 1705 uint8_t socclkspreadenabled; 1706 uint8_t socclkspreadpercent; 1707 uint16_t socclkspreadfreq; 1708 1709 uint8_t acggfxclkspreadenabled; 1710 uint8_t acggfxclkspreadpercent; 1711 uint16_t acggfxclkspreadfreq; 1712 1713 uint8_t Vr2_I2C_address; 1714 uint8_t padding_vr2[3]; 1715 1716 uint32_t boardreserved[9]; 1717 }; 1718 1719 /* 1720 *************************************************************************** 1721 Data Table smc_dpm_info structure 1722 *************************************************************************** 1723 */ 1724 struct atom_smc_dpm_info_v4_3 1725 { 1726 struct atom_common_table_header table_header; 1727 uint8_t liquid1_i2c_address; 1728 uint8_t liquid2_i2c_address; 1729 uint8_t vr_i2c_address; 1730 uint8_t plx_i2c_address; 1731 1732 uint8_t liquid_i2c_linescl; 1733 uint8_t liquid_i2c_linesda; 1734 uint8_t vr_i2c_linescl; 1735 uint8_t vr_i2c_linesda; 1736 1737 uint8_t plx_i2c_linescl; 1738 uint8_t plx_i2c_linesda; 1739 uint8_t vrsensorpresent; 1740 uint8_t liquidsensorpresent; 1741 1742 uint16_t maxvoltagestepgfx; 1743 uint16_t maxvoltagestepsoc; 1744 1745 uint8_t vddgfxvrmapping; 1746 uint8_t vddsocvrmapping; 1747 uint8_t vddmem0vrmapping; 1748 uint8_t vddmem1vrmapping; 1749 1750 uint8_t gfxulvphasesheddingmask; 1751 uint8_t soculvphasesheddingmask; 1752 uint8_t externalsensorpresent; 1753 uint8_t padding8_v; 1754 1755 uint16_t gfxmaxcurrent; 1756 uint8_t gfxoffset; 1757 uint8_t padding_telemetrygfx; 1758 1759 uint16_t socmaxcurrent; 1760 uint8_t socoffset; 1761 uint8_t padding_telemetrysoc; 1762 1763 uint16_t mem0maxcurrent; 1764 uint8_t mem0offset; 1765 uint8_t padding_telemetrymem0; 1766 1767 uint16_t mem1maxcurrent; 1768 uint8_t mem1offset; 1769 uint8_t padding_telemetrymem1; 1770 1771 uint8_t acdcgpio; 1772 uint8_t acdcpolarity; 1773 uint8_t vr0hotgpio; 1774 uint8_t vr0hotpolarity; 1775 1776 uint8_t vr1hotgpio; 1777 uint8_t vr1hotpolarity; 1778 uint8_t padding1; 1779 uint8_t padding2; 1780 1781 uint8_t ledpin0; 1782 uint8_t ledpin1; 1783 uint8_t ledpin2; 1784 uint8_t padding8_4; 1785 1786 uint8_t pllgfxclkspreadenabled; 1787 uint8_t pllgfxclkspreadpercent; 1788 uint16_t pllgfxclkspreadfreq; 1789 1790 uint8_t uclkspreadenabled; 1791 uint8_t uclkspreadpercent; 1792 uint16_t uclkspreadfreq; 1793 1794 uint8_t fclkspreadenabled; 1795 uint8_t fclkspreadpercent; 1796 uint16_t fclkspreadfreq; 1797 1798 uint8_t fllgfxclkspreadenabled; 1799 uint8_t fllgfxclkspreadpercent; 1800 uint16_t fllgfxclkspreadfreq; 1801 1802 uint32_t boardreserved[10]; 1803 }; 1804 1805 struct smudpm_i2ccontrollerconfig_t { 1806 uint32_t enabled; 1807 uint32_t slaveaddress; 1808 uint32_t controllerport; 1809 uint32_t controllername; 1810 uint32_t thermalthrottler; 1811 uint32_t i2cprotocol; 1812 uint32_t i2cspeed; 1813 }; 1814 1815 struct atom_smc_dpm_info_v4_4 1816 { 1817 struct atom_common_table_header table_header; 1818 uint32_t i2c_padding[3]; 1819 1820 uint16_t maxvoltagestepgfx; 1821 uint16_t maxvoltagestepsoc; 1822 1823 uint8_t vddgfxvrmapping; 1824 uint8_t vddsocvrmapping; 1825 uint8_t vddmem0vrmapping; 1826 uint8_t vddmem1vrmapping; 1827 1828 uint8_t gfxulvphasesheddingmask; 1829 uint8_t soculvphasesheddingmask; 1830 uint8_t externalsensorpresent; 1831 uint8_t padding8_v; 1832 1833 uint16_t gfxmaxcurrent; 1834 uint8_t gfxoffset; 1835 uint8_t padding_telemetrygfx; 1836 1837 uint16_t socmaxcurrent; 1838 uint8_t socoffset; 1839 uint8_t padding_telemetrysoc; 1840 1841 uint16_t mem0maxcurrent; 1842 uint8_t mem0offset; 1843 uint8_t padding_telemetrymem0; 1844 1845 uint16_t mem1maxcurrent; 1846 uint8_t mem1offset; 1847 uint8_t padding_telemetrymem1; 1848 1849 1850 uint8_t acdcgpio; 1851 uint8_t acdcpolarity; 1852 uint8_t vr0hotgpio; 1853 uint8_t vr0hotpolarity; 1854 1855 uint8_t vr1hotgpio; 1856 uint8_t vr1hotpolarity; 1857 uint8_t padding1; 1858 uint8_t padding2; 1859 1860 1861 uint8_t ledpin0; 1862 uint8_t ledpin1; 1863 uint8_t ledpin2; 1864 uint8_t padding8_4; 1865 1866 1867 uint8_t pllgfxclkspreadenabled; 1868 uint8_t pllgfxclkspreadpercent; 1869 uint16_t pllgfxclkspreadfreq; 1870 1871 1872 uint8_t uclkspreadenabled; 1873 uint8_t uclkspreadpercent; 1874 uint16_t uclkspreadfreq; 1875 1876 1877 uint8_t fclkspreadenabled; 1878 uint8_t fclkspreadpercent; 1879 uint16_t fclkspreadfreq; 1880 1881 1882 uint8_t fllgfxclkspreadenabled; 1883 uint8_t fllgfxclkspreadpercent; 1884 uint16_t fllgfxclkspreadfreq; 1885 1886 1887 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1888 1889 1890 uint32_t boardreserved[10]; 1891 }; 1892 1893 enum smudpm_v4_5_i2ccontrollername_e{ 1894 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1895 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1896 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1897 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1898 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1899 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1900 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1901 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1902 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1903 }; 1904 1905 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1906 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1907 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1908 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1909 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1910 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1911 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1912 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1913 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1914 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1915 }; 1916 1917 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 1918 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 1919 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 1920 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 1921 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 1922 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 1923 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 1924 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 1925 }; 1926 1927 struct smudpm_i2c_controller_config_v2 1928 { 1929 uint8_t Enabled; 1930 uint8_t Speed; 1931 uint8_t Padding[2]; 1932 uint32_t SlaveAddress; 1933 uint8_t ControllerPort; 1934 uint8_t ControllerName; 1935 uint8_t ThermalThrotter; 1936 uint8_t I2cProtocol; 1937 }; 1938 1939 struct atom_smc_dpm_info_v4_5 1940 { 1941 struct atom_common_table_header table_header; 1942 // SECTION: BOARD PARAMETERS 1943 // I2C Control 1944 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 1945 1946 // SVI2 Board Parameters 1947 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1948 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1949 1950 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1951 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1952 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1953 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1954 1955 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1956 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1957 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 1958 uint8_t Padding8_V; 1959 1960 // Telemetry Settings 1961 uint16_t GfxMaxCurrent; // in Amps 1962 uint8_t GfxOffset; // in Amps 1963 uint8_t Padding_TelemetryGfx; 1964 uint16_t SocMaxCurrent; // in Amps 1965 uint8_t SocOffset; // in Amps 1966 uint8_t Padding_TelemetrySoc; 1967 1968 uint16_t Mem0MaxCurrent; // in Amps 1969 uint8_t Mem0Offset; // in Amps 1970 uint8_t Padding_TelemetryMem0; 1971 1972 uint16_t Mem1MaxCurrent; // in Amps 1973 uint8_t Mem1Offset; // in Amps 1974 uint8_t Padding_TelemetryMem1; 1975 1976 // GPIO Settings 1977 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1978 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1979 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1980 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1981 1982 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1983 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1984 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1985 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1986 1987 // LED Display Settings 1988 uint8_t LedPin0; // GPIO number for LedPin[0] 1989 uint8_t LedPin1; // GPIO number for LedPin[1] 1990 uint8_t LedPin2; // GPIO number for LedPin[2] 1991 uint8_t padding8_4; 1992 1993 // GFXCLK PLL Spread Spectrum 1994 uint8_t PllGfxclkSpreadEnabled; // on or off 1995 uint8_t PllGfxclkSpreadPercent; // Q4.4 1996 uint16_t PllGfxclkSpreadFreq; // kHz 1997 1998 // GFXCLK DFLL Spread Spectrum 1999 uint8_t DfllGfxclkSpreadEnabled; // on or off 2000 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2001 uint16_t DfllGfxclkSpreadFreq; // kHz 2002 2003 // UCLK Spread Spectrum 2004 uint8_t UclkSpreadEnabled; // on or off 2005 uint8_t UclkSpreadPercent; // Q4.4 2006 uint16_t UclkSpreadFreq; // kHz 2007 2008 // SOCCLK Spread Spectrum 2009 uint8_t SoclkSpreadEnabled; // on or off 2010 uint8_t SocclkSpreadPercent; // Q4.4 2011 uint16_t SocclkSpreadFreq; // kHz 2012 2013 // Total board power 2014 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2015 uint16_t BoardPadding; 2016 2017 // Mvdd Svi2 Div Ratio Setting 2018 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2019 2020 uint32_t BoardReserved[9]; 2021 2022 }; 2023 2024 struct atom_smc_dpm_info_v4_6 2025 { 2026 struct atom_common_table_header table_header; 2027 // section: board parameters 2028 uint32_t i2c_padding[3]; // old i2c control are moved to new area 2029 2030 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2031 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 2032 2033 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 2034 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 2035 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 2036 uint8_t boardvrmapping; // use vr_mapping* bitfields 2037 2038 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 2039 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 2040 uint8_t padding8_v[2]; 2041 2042 // telemetry settings 2043 uint16_t gfxmaxcurrent; // in amps 2044 uint8_t gfxoffset; // in amps 2045 uint8_t padding_telemetrygfx; 2046 2047 uint16_t socmaxcurrent; // in amps 2048 uint8_t socoffset; // in amps 2049 uint8_t padding_telemetrysoc; 2050 2051 uint16_t memmaxcurrent; // in amps 2052 uint8_t memoffset; // in amps 2053 uint8_t padding_telemetrymem; 2054 2055 uint16_t boardmaxcurrent; // in amps 2056 uint8_t boardoffset; // in amps 2057 uint8_t padding_telemetryboardinput; 2058 2059 // gpio settings 2060 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 2061 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 2062 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 2063 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 2064 2065 // gfxclk pll spread spectrum 2066 uint8_t pllgfxclkspreadenabled; // on or off 2067 uint8_t pllgfxclkspreadpercent; // q4.4 2068 uint16_t pllgfxclkspreadfreq; // khz 2069 2070 // uclk spread spectrum 2071 uint8_t uclkspreadenabled; // on or off 2072 uint8_t uclkspreadpercent; // q4.4 2073 uint16_t uclkspreadfreq; // khz 2074 2075 // fclk spread spectrum 2076 uint8_t fclkspreadenabled; // on or off 2077 uint8_t fclkspreadpercent; // q4.4 2078 uint16_t fclkspreadfreq; // khz 2079 2080 2081 // gfxclk fll spread spectrum 2082 uint8_t fllgfxclkspreadenabled; // on or off 2083 uint8_t fllgfxclkspreadpercent; // q4.4 2084 uint16_t fllgfxclkspreadfreq; // khz 2085 2086 // i2c controller structure 2087 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 2088 2089 // memory section 2090 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 2091 2092 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 2093 uint8_t paddingmem[3]; 2094 2095 // total board power 2096 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 2097 uint16_t boardpadding; 2098 2099 // section: xgmi training 2100 uint8_t xgmilinkspeed[4]; 2101 uint8_t xgmilinkwidth[4]; 2102 2103 uint16_t xgmifclkfreq[4]; 2104 uint16_t xgmisocvoltage[4]; 2105 2106 // reserved 2107 uint32_t boardreserved[10]; 2108 }; 2109 2110 struct atom_smc_dpm_info_v4_7 2111 { 2112 struct atom_common_table_header table_header; 2113 // SECTION: BOARD PARAMETERS 2114 // I2C Control 2115 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2116 2117 // SVI2 Board Parameters 2118 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2119 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2120 2121 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2122 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2123 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2124 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2125 2126 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2127 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2128 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2129 uint8_t Padding8_V; 2130 2131 // Telemetry Settings 2132 uint16_t GfxMaxCurrent; // in Amps 2133 uint8_t GfxOffset; // in Amps 2134 uint8_t Padding_TelemetryGfx; 2135 uint16_t SocMaxCurrent; // in Amps 2136 uint8_t SocOffset; // in Amps 2137 uint8_t Padding_TelemetrySoc; 2138 2139 uint16_t Mem0MaxCurrent; // in Amps 2140 uint8_t Mem0Offset; // in Amps 2141 uint8_t Padding_TelemetryMem0; 2142 2143 uint16_t Mem1MaxCurrent; // in Amps 2144 uint8_t Mem1Offset; // in Amps 2145 uint8_t Padding_TelemetryMem1; 2146 2147 // GPIO Settings 2148 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2149 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2150 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2151 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2152 2153 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2154 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2155 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2156 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2157 2158 // LED Display Settings 2159 uint8_t LedPin0; // GPIO number for LedPin[0] 2160 uint8_t LedPin1; // GPIO number for LedPin[1] 2161 uint8_t LedPin2; // GPIO number for LedPin[2] 2162 uint8_t padding8_4; 2163 2164 // GFXCLK PLL Spread Spectrum 2165 uint8_t PllGfxclkSpreadEnabled; // on or off 2166 uint8_t PllGfxclkSpreadPercent; // Q4.4 2167 uint16_t PllGfxclkSpreadFreq; // kHz 2168 2169 // GFXCLK DFLL Spread Spectrum 2170 uint8_t DfllGfxclkSpreadEnabled; // on or off 2171 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2172 uint16_t DfllGfxclkSpreadFreq; // kHz 2173 2174 // UCLK Spread Spectrum 2175 uint8_t UclkSpreadEnabled; // on or off 2176 uint8_t UclkSpreadPercent; // Q4.4 2177 uint16_t UclkSpreadFreq; // kHz 2178 2179 // SOCCLK Spread Spectrum 2180 uint8_t SoclkSpreadEnabled; // on or off 2181 uint8_t SocclkSpreadPercent; // Q4.4 2182 uint16_t SocclkSpreadFreq; // kHz 2183 2184 // Total board power 2185 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2186 uint16_t BoardPadding; 2187 2188 // Mvdd Svi2 Div Ratio Setting 2189 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2190 2191 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2192 uint8_t GpioI2cScl; // Serial Clock 2193 uint8_t GpioI2cSda; // Serial Data 2194 uint16_t GpioPadding; 2195 2196 // Additional LED Display Settings 2197 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2198 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2199 uint16_t LedEnableMask; 2200 2201 // Power Limit Scalars 2202 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2203 2204 uint8_t MvddUlvPhaseSheddingMask; 2205 uint8_t VddciUlvPhaseSheddingMask; 2206 uint8_t Padding8_Psi1; 2207 uint8_t Padding8_Psi2; 2208 2209 uint32_t BoardReserved[5]; 2210 }; 2211 2212 struct smudpm_i2c_controller_config_v3 2213 { 2214 uint8_t Enabled; 2215 uint8_t Speed; 2216 uint8_t SlaveAddress; 2217 uint8_t ControllerPort; 2218 uint8_t ControllerName; 2219 uint8_t ThermalThrotter; 2220 uint8_t I2cProtocol; 2221 uint8_t PaddingConfig; 2222 }; 2223 2224 struct atom_smc_dpm_info_v4_9 2225 { 2226 struct atom_common_table_header table_header; 2227 2228 //SECTION: Gaming Clocks 2229 //uint32_t GamingClk[6]; 2230 2231 // SECTION: I2C Control 2232 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2233 2234 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2235 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2236 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2237 uint8_t I2cSpare; 2238 2239 // SECTION: SVI2 Board Parameters 2240 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2241 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2242 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2243 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2244 2245 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2246 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2247 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2248 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2249 2250 // SECTION: Telemetry Settings 2251 uint16_t GfxMaxCurrent; // in Amps 2252 uint8_t GfxOffset; // in Amps 2253 uint8_t Padding_TelemetryGfx; 2254 2255 uint16_t SocMaxCurrent; // in Amps 2256 uint8_t SocOffset; // in Amps 2257 uint8_t Padding_TelemetrySoc; 2258 2259 uint16_t Mem0MaxCurrent; // in Amps 2260 uint8_t Mem0Offset; // in Amps 2261 uint8_t Padding_TelemetryMem0; 2262 2263 uint16_t Mem1MaxCurrent; // in Amps 2264 uint8_t Mem1Offset; // in Amps 2265 uint8_t Padding_TelemetryMem1; 2266 2267 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2268 2269 // SECTION: GPIO Settings 2270 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2271 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2272 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2273 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2274 2275 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2276 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2277 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2278 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2279 2280 // LED Display Settings 2281 uint8_t LedPin0; // GPIO number for LedPin[0] 2282 uint8_t LedPin1; // GPIO number for LedPin[1] 2283 uint8_t LedPin2; // GPIO number for LedPin[2] 2284 uint8_t LedEnableMask; 2285 2286 uint8_t LedPcie; // GPIO number for PCIE results 2287 uint8_t LedError; // GPIO number for Error Cases 2288 uint8_t LedSpare1[2]; 2289 2290 // SECTION: Clock Spread Spectrum 2291 2292 // GFXCLK PLL Spread Spectrum 2293 uint8_t PllGfxclkSpreadEnabled; // on or off 2294 uint8_t PllGfxclkSpreadPercent; // Q4.4 2295 uint16_t PllGfxclkSpreadFreq; // kHz 2296 2297 // GFXCLK DFLL Spread Spectrum 2298 uint8_t DfllGfxclkSpreadEnabled; // on or off 2299 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2300 uint16_t DfllGfxclkSpreadFreq; // kHz 2301 2302 // UCLK Spread Spectrum 2303 uint8_t UclkSpreadEnabled; // on or off 2304 uint8_t UclkSpreadPercent; // Q4.4 2305 uint16_t UclkSpreadFreq; // kHz 2306 2307 // FCLK Spread Spectrum 2308 uint8_t FclkSpreadEnabled; // on or off 2309 uint8_t FclkSpreadPercent; // Q4.4 2310 uint16_t FclkSpreadFreq; // kHz 2311 2312 // Section: Memory Config 2313 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2314 2315 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2316 uint8_t PaddingMem1[3]; 2317 2318 // Section: Total Board Power 2319 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2320 uint16_t BoardPowerPadding; 2321 2322 // SECTION: XGMI Training 2323 uint8_t XgmiLinkSpeed [4]; 2324 uint8_t XgmiLinkWidth [4]; 2325 2326 uint16_t XgmiFclkFreq [4]; 2327 uint16_t XgmiSocVoltage [4]; 2328 2329 // SECTION: Board Reserved 2330 2331 uint32_t BoardReserved[16]; 2332 2333 }; 2334 2335 /* 2336 *************************************************************************** 2337 Data Table asic_profiling_info structure 2338 *************************************************************************** 2339 */ 2340 struct atom_asic_profiling_info_v4_1 2341 { 2342 struct atom_common_table_header table_header; 2343 uint32_t maxvddc; 2344 uint32_t minvddc; 2345 uint32_t avfs_meannsigma_acontant0; 2346 uint32_t avfs_meannsigma_acontant1; 2347 uint32_t avfs_meannsigma_acontant2; 2348 uint16_t avfs_meannsigma_dc_tol_sigma; 2349 uint16_t avfs_meannsigma_platform_mean; 2350 uint16_t avfs_meannsigma_platform_sigma; 2351 uint32_t gb_vdroop_table_cksoff_a0; 2352 uint32_t gb_vdroop_table_cksoff_a1; 2353 uint32_t gb_vdroop_table_cksoff_a2; 2354 uint32_t gb_vdroop_table_ckson_a0; 2355 uint32_t gb_vdroop_table_ckson_a1; 2356 uint32_t gb_vdroop_table_ckson_a2; 2357 uint32_t avfsgb_fuse_table_cksoff_m1; 2358 uint32_t avfsgb_fuse_table_cksoff_m2; 2359 uint32_t avfsgb_fuse_table_cksoff_b; 2360 uint32_t avfsgb_fuse_table_ckson_m1; 2361 uint32_t avfsgb_fuse_table_ckson_m2; 2362 uint32_t avfsgb_fuse_table_ckson_b; 2363 uint16_t max_voltage_0_25mv; 2364 uint8_t enable_gb_vdroop_table_cksoff; 2365 uint8_t enable_gb_vdroop_table_ckson; 2366 uint8_t enable_gb_fuse_table_cksoff; 2367 uint8_t enable_gb_fuse_table_ckson; 2368 uint16_t psm_age_comfactor; 2369 uint8_t enable_apply_avfs_cksoff_voltage; 2370 uint8_t reserved; 2371 uint32_t dispclk2gfxclk_a; 2372 uint32_t dispclk2gfxclk_b; 2373 uint32_t dispclk2gfxclk_c; 2374 uint32_t pixclk2gfxclk_a; 2375 uint32_t pixclk2gfxclk_b; 2376 uint32_t pixclk2gfxclk_c; 2377 uint32_t dcefclk2gfxclk_a; 2378 uint32_t dcefclk2gfxclk_b; 2379 uint32_t dcefclk2gfxclk_c; 2380 uint32_t phyclk2gfxclk_a; 2381 uint32_t phyclk2gfxclk_b; 2382 uint32_t phyclk2gfxclk_c; 2383 }; 2384 2385 struct atom_asic_profiling_info_v4_2 { 2386 struct atom_common_table_header table_header; 2387 uint32_t maxvddc; 2388 uint32_t minvddc; 2389 uint32_t avfs_meannsigma_acontant0; 2390 uint32_t avfs_meannsigma_acontant1; 2391 uint32_t avfs_meannsigma_acontant2; 2392 uint16_t avfs_meannsigma_dc_tol_sigma; 2393 uint16_t avfs_meannsigma_platform_mean; 2394 uint16_t avfs_meannsigma_platform_sigma; 2395 uint32_t gb_vdroop_table_cksoff_a0; 2396 uint32_t gb_vdroop_table_cksoff_a1; 2397 uint32_t gb_vdroop_table_cksoff_a2; 2398 uint32_t gb_vdroop_table_ckson_a0; 2399 uint32_t gb_vdroop_table_ckson_a1; 2400 uint32_t gb_vdroop_table_ckson_a2; 2401 uint32_t avfsgb_fuse_table_cksoff_m1; 2402 uint32_t avfsgb_fuse_table_cksoff_m2; 2403 uint32_t avfsgb_fuse_table_cksoff_b; 2404 uint32_t avfsgb_fuse_table_ckson_m1; 2405 uint32_t avfsgb_fuse_table_ckson_m2; 2406 uint32_t avfsgb_fuse_table_ckson_b; 2407 uint16_t max_voltage_0_25mv; 2408 uint8_t enable_gb_vdroop_table_cksoff; 2409 uint8_t enable_gb_vdroop_table_ckson; 2410 uint8_t enable_gb_fuse_table_cksoff; 2411 uint8_t enable_gb_fuse_table_ckson; 2412 uint16_t psm_age_comfactor; 2413 uint8_t enable_apply_avfs_cksoff_voltage; 2414 uint8_t reserved; 2415 uint32_t dispclk2gfxclk_a; 2416 uint32_t dispclk2gfxclk_b; 2417 uint32_t dispclk2gfxclk_c; 2418 uint32_t pixclk2gfxclk_a; 2419 uint32_t pixclk2gfxclk_b; 2420 uint32_t pixclk2gfxclk_c; 2421 uint32_t dcefclk2gfxclk_a; 2422 uint32_t dcefclk2gfxclk_b; 2423 uint32_t dcefclk2gfxclk_c; 2424 uint32_t phyclk2gfxclk_a; 2425 uint32_t phyclk2gfxclk_b; 2426 uint32_t phyclk2gfxclk_c; 2427 uint32_t acg_gb_vdroop_table_a0; 2428 uint32_t acg_gb_vdroop_table_a1; 2429 uint32_t acg_gb_vdroop_table_a2; 2430 uint32_t acg_avfsgb_fuse_table_m1; 2431 uint32_t acg_avfsgb_fuse_table_m2; 2432 uint32_t acg_avfsgb_fuse_table_b; 2433 uint8_t enable_acg_gb_vdroop_table; 2434 uint8_t enable_acg_gb_fuse_table; 2435 uint32_t acg_dispclk2gfxclk_a; 2436 uint32_t acg_dispclk2gfxclk_b; 2437 uint32_t acg_dispclk2gfxclk_c; 2438 uint32_t acg_pixclk2gfxclk_a; 2439 uint32_t acg_pixclk2gfxclk_b; 2440 uint32_t acg_pixclk2gfxclk_c; 2441 uint32_t acg_dcefclk2gfxclk_a; 2442 uint32_t acg_dcefclk2gfxclk_b; 2443 uint32_t acg_dcefclk2gfxclk_c; 2444 uint32_t acg_phyclk2gfxclk_a; 2445 uint32_t acg_phyclk2gfxclk_b; 2446 uint32_t acg_phyclk2gfxclk_c; 2447 }; 2448 2449 /* 2450 *************************************************************************** 2451 Data Table multimedia_info structure 2452 *************************************************************************** 2453 */ 2454 struct atom_multimedia_info_v2_1 2455 { 2456 struct atom_common_table_header table_header; 2457 uint8_t uvdip_min_ver; 2458 uint8_t uvdip_max_ver; 2459 uint8_t vceip_min_ver; 2460 uint8_t vceip_max_ver; 2461 uint16_t uvd_enc_max_input_width_pixels; 2462 uint16_t uvd_enc_max_input_height_pixels; 2463 uint16_t vce_enc_max_input_width_pixels; 2464 uint16_t vce_enc_max_input_height_pixels; 2465 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2466 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2467 }; 2468 2469 2470 /* 2471 *************************************************************************** 2472 Data Table umc_info structure 2473 *************************************************************************** 2474 */ 2475 struct atom_umc_info_v3_1 2476 { 2477 struct atom_common_table_header table_header; 2478 uint32_t ucode_version; 2479 uint32_t ucode_rom_startaddr; 2480 uint32_t ucode_length; 2481 uint16_t umc_reg_init_offset; 2482 uint16_t customer_ucode_name_offset; 2483 uint16_t mclk_ss_percentage; 2484 uint16_t mclk_ss_rate_10hz; 2485 uint8_t umcip_min_ver; 2486 uint8_t umcip_max_ver; 2487 uint8_t vram_type; //enum of atom_dgpu_vram_type 2488 uint8_t umc_config; 2489 uint32_t mem_refclk_10khz; 2490 }; 2491 2492 // umc_info.umc_config 2493 enum atom_umc_config_def { 2494 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2495 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2496 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2497 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2498 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2499 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2500 }; 2501 2502 struct atom_umc_info_v3_2 2503 { 2504 struct atom_common_table_header table_header; 2505 uint32_t ucode_version; 2506 uint32_t ucode_rom_startaddr; 2507 uint32_t ucode_length; 2508 uint16_t umc_reg_init_offset; 2509 uint16_t customer_ucode_name_offset; 2510 uint16_t mclk_ss_percentage; 2511 uint16_t mclk_ss_rate_10hz; 2512 uint8_t umcip_min_ver; 2513 uint8_t umcip_max_ver; 2514 uint8_t vram_type; //enum of atom_dgpu_vram_type 2515 uint8_t umc_config; 2516 uint32_t mem_refclk_10khz; 2517 uint32_t pstate_uclk_10khz[4]; 2518 uint16_t umcgoldenoffset; 2519 uint16_t densitygoldenoffset; 2520 }; 2521 2522 struct atom_umc_info_v3_3 2523 { 2524 struct atom_common_table_header table_header; 2525 uint32_t ucode_reserved; 2526 uint32_t ucode_rom_startaddr; 2527 uint32_t ucode_length; 2528 uint16_t umc_reg_init_offset; 2529 uint16_t customer_ucode_name_offset; 2530 uint16_t mclk_ss_percentage; 2531 uint16_t mclk_ss_rate_10hz; 2532 uint8_t umcip_min_ver; 2533 uint8_t umcip_max_ver; 2534 uint8_t vram_type; //enum of atom_dgpu_vram_type 2535 uint8_t umc_config; 2536 uint32_t mem_refclk_10khz; 2537 uint32_t pstate_uclk_10khz[4]; 2538 uint16_t umcgoldenoffset; 2539 uint16_t densitygoldenoffset; 2540 uint32_t reserved[4]; 2541 }; 2542 2543 /* 2544 *************************************************************************** 2545 Data Table vram_info structure 2546 *************************************************************************** 2547 */ 2548 struct atom_vram_module_v9 { 2549 // Design Specific Values 2550 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2551 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2552 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2553 uint16_t reserved[3]; 2554 uint16_t mem_voltage; // mem_voltage 2555 uint16_t vram_module_size; // Size of atom_vram_module_v9 2556 uint8_t ext_memory_id; // Current memory module ID 2557 uint8_t memory_type; // enum of atom_dgpu_vram_type 2558 uint8_t channel_num; // Number of mem. channels supported in this module 2559 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2560 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2561 uint8_t tunningset_id; // MC phy registers set per. 2562 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2563 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2564 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2565 uint8_t vram_rsd2; // reserved 2566 char dram_pnstring[20]; // part number end with '0'. 2567 }; 2568 2569 struct atom_vram_info_header_v2_3 { 2570 struct atom_common_table_header table_header; 2571 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2572 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2573 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2574 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2575 uint16_t dram_data_remap_tbloffset; // reserved for now 2576 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2577 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2578 uint16_t vram_rsd2; 2579 uint8_t vram_module_num; // indicate number of VRAM module 2580 uint8_t umcip_min_ver; 2581 uint8_t umcip_max_ver; 2582 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2583 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2584 }; 2585 2586 struct atom_umc_register_addr_info{ 2587 uint32_t umc_register_addr:24; 2588 uint32_t umc_reg_type_ind:1; 2589 uint32_t umc_reg_rsvd:7; 2590 }; 2591 2592 //atom_umc_register_addr_info. 2593 enum atom_umc_register_addr_info_flag{ 2594 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2595 }; 2596 2597 union atom_umc_register_addr_info_access 2598 { 2599 struct atom_umc_register_addr_info umc_reg_addr; 2600 uint32_t u32umc_reg_addr; 2601 }; 2602 2603 struct atom_umc_reg_setting_id_config{ 2604 uint32_t memclockrange:24; 2605 uint32_t mem_blk_id:8; 2606 }; 2607 2608 union atom_umc_reg_setting_id_config_access 2609 { 2610 struct atom_umc_reg_setting_id_config umc_id_access; 2611 uint32_t u32umc_id_access; 2612 }; 2613 2614 struct atom_umc_reg_setting_data_block{ 2615 union atom_umc_reg_setting_id_config_access block_id; 2616 uint32_t u32umc_reg_data[1]; 2617 }; 2618 2619 struct atom_umc_init_reg_block{ 2620 uint16_t umc_reg_num; 2621 uint16_t reserved; 2622 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2623 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2624 }; 2625 2626 struct atom_vram_module_v10 { 2627 // Design Specific Values 2628 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2629 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2630 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2631 uint16_t reserved[3]; 2632 uint16_t mem_voltage; // mem_voltage 2633 uint16_t vram_module_size; // Size of atom_vram_module_v9 2634 uint8_t ext_memory_id; // Current memory module ID 2635 uint8_t memory_type; // enum of atom_dgpu_vram_type 2636 uint8_t channel_num; // Number of mem. channels supported in this module 2637 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2638 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2639 uint8_t tunningset_id; // MC phy registers set per 2640 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2641 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2642 uint8_t vram_flags; // bit0= bankgroup enable 2643 uint8_t vram_rsd2; // reserved 2644 uint16_t gddr6_mr10; // gddr6 mode register10 value 2645 uint16_t gddr6_mr1; // gddr6 mode register1 value 2646 uint16_t gddr6_mr2; // gddr6 mode register2 value 2647 uint16_t gddr6_mr7; // gddr6 mode register7 value 2648 char dram_pnstring[20]; // part number end with '0' 2649 }; 2650 2651 struct atom_vram_info_header_v2_4 { 2652 struct atom_common_table_header table_header; 2653 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2654 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2655 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2656 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2657 uint16_t dram_data_remap_tbloffset; // reserved for now 2658 uint16_t reserved; // offset of reserved 2659 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2660 uint16_t vram_rsd2; 2661 uint8_t vram_module_num; // indicate number of VRAM module 2662 uint8_t umcip_min_ver; 2663 uint8_t umcip_max_ver; 2664 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2665 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2666 }; 2667 2668 struct atom_vram_module_v11 { 2669 // Design Specific Values 2670 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2671 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2672 uint16_t mem_voltage; // mem_voltage 2673 uint16_t vram_module_size; // Size of atom_vram_module_v9 2674 uint8_t ext_memory_id; // Current memory module ID 2675 uint8_t memory_type; // enum of atom_dgpu_vram_type 2676 uint8_t channel_num; // Number of mem. channels supported in this module 2677 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2678 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2679 uint8_t tunningset_id; // MC phy registers set per. 2680 uint16_t reserved[4]; // reserved 2681 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2682 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2683 uint8_t vram_flags; // bit0= bankgroup enable 2684 uint8_t vram_rsd2; // reserved 2685 uint16_t gddr6_mr10; // gddr6 mode register10 value 2686 uint16_t gddr6_mr0; // gddr6 mode register0 value 2687 uint16_t gddr6_mr1; // gddr6 mode register1 value 2688 uint16_t gddr6_mr2; // gddr6 mode register2 value 2689 uint16_t gddr6_mr4; // gddr6 mode register4 value 2690 uint16_t gddr6_mr7; // gddr6 mode register7 value 2691 uint16_t gddr6_mr8; // gddr6 mode register8 value 2692 char dram_pnstring[40]; // part number end with '0'. 2693 }; 2694 2695 struct atom_gddr6_ac_timing_v2_5 { 2696 uint32_t u32umc_id_access; 2697 uint8_t RL; 2698 uint8_t WL; 2699 uint8_t tRAS; 2700 uint8_t tRC; 2701 2702 uint16_t tREFI; 2703 uint8_t tRFC; 2704 uint8_t tRFCpb; 2705 2706 uint8_t tRREFD; 2707 uint8_t tRCDRD; 2708 uint8_t tRCDWR; 2709 uint8_t tRP; 2710 2711 uint8_t tRRDS; 2712 uint8_t tRRDL; 2713 uint8_t tWR; 2714 uint8_t tWTRS; 2715 2716 uint8_t tWTRL; 2717 uint8_t tFAW; 2718 uint8_t tCCDS; 2719 uint8_t tCCDL; 2720 2721 uint8_t tCRCRL; 2722 uint8_t tCRCWL; 2723 uint8_t tCKE; 2724 uint8_t tCKSRE; 2725 2726 uint8_t tCKSRX; 2727 uint8_t tRTPS; 2728 uint8_t tRTPL; 2729 uint8_t tMRD; 2730 2731 uint8_t tMOD; 2732 uint8_t tXS; 2733 uint8_t tXHP; 2734 uint8_t tXSMRS; 2735 2736 uint32_t tXSH; 2737 2738 uint8_t tPD; 2739 uint8_t tXP; 2740 uint8_t tCPDED; 2741 uint8_t tACTPDE; 2742 2743 uint8_t tPREPDE; 2744 uint8_t tREFPDE; 2745 uint8_t tMRSPDEN; 2746 uint8_t tRDSRE; 2747 2748 uint8_t tWRSRE; 2749 uint8_t tPPD; 2750 uint8_t tCCDMW; 2751 uint8_t tWTRTR; 2752 2753 uint8_t tLTLTR; 2754 uint8_t tREFTR; 2755 uint8_t VNDR; 2756 uint8_t reserved[9]; 2757 }; 2758 2759 struct atom_gddr6_bit_byte_remap { 2760 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 2761 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 2762 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 2763 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 2764 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 2765 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 2766 uint32_t phy_dram; //mmUMC_PHY_DRAM 2767 }; 2768 2769 struct atom_gddr6_dram_data_remap { 2770 uint32_t table_size; 2771 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 2772 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 2773 }; 2774 2775 struct atom_vram_info_header_v2_5 { 2776 struct atom_common_table_header table_header; 2777 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 2778 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 2779 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2780 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2781 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 2782 uint16_t reserved; // offset of reserved 2783 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2784 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 2785 uint8_t vram_module_num; // indicate number of VRAM module 2786 uint8_t umcip_min_ver; 2787 uint8_t umcip_max_ver; 2788 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2789 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2790 }; 2791 2792 /* 2793 *************************************************************************** 2794 Data Table voltageobject_info structure 2795 *************************************************************************** 2796 */ 2797 struct atom_i2c_data_entry 2798 { 2799 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2800 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2801 }; 2802 2803 struct atom_voltage_object_header_v4{ 2804 uint8_t voltage_type; //enum atom_voltage_type 2805 uint8_t voltage_mode; //enum atom_voltage_object_mode 2806 uint16_t object_size; //Size of Object 2807 }; 2808 2809 // atom_voltage_object_header_v4.voltage_mode 2810 enum atom_voltage_object_mode 2811 { 2812 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2813 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2814 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2815 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2816 VOLTAGE_OBJ_EVV = 8, 2817 VOLTAGE_OBJ_MERGED_POWER = 9, 2818 }; 2819 2820 struct atom_i2c_voltage_object_v4 2821 { 2822 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2823 uint8_t regulator_id; //Indicate Voltage Regulator Id 2824 uint8_t i2c_id; 2825 uint8_t i2c_slave_addr; 2826 uint8_t i2c_control_offset; 2827 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2828 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2829 uint8_t reserved[2]; 2830 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2831 }; 2832 2833 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2834 enum atom_i2c_voltage_control_flag 2835 { 2836 VOLTAGE_DATA_ONE_BYTE = 0, 2837 VOLTAGE_DATA_TWO_BYTE = 1, 2838 }; 2839 2840 2841 struct atom_voltage_gpio_map_lut 2842 { 2843 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2844 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2845 }; 2846 2847 struct atom_gpio_voltage_object_v4 2848 { 2849 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2850 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2851 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2852 uint8_t phase_delay_us; // phase delay in unit of micro second 2853 uint8_t reserved; 2854 uint32_t gpio_mask_val; // GPIO Mask value 2855 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2856 }; 2857 2858 struct atom_svid2_voltage_object_v4 2859 { 2860 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2861 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2862 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2863 uint8_t psi0_enable; // 2864 uint8_t maxvstep; 2865 uint8_t telemetry_offset; 2866 uint8_t telemetry_gain; 2867 uint16_t reserved1; 2868 }; 2869 2870 struct atom_merged_voltage_object_v4 2871 { 2872 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2873 uint8_t merged_powerrail_type; //enum atom_voltage_type 2874 uint8_t reserved[3]; 2875 }; 2876 2877 union atom_voltage_object_v4{ 2878 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 2879 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 2880 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 2881 struct atom_merged_voltage_object_v4 merged_voltage_obj; 2882 }; 2883 2884 struct atom_voltage_objects_info_v4_1 2885 { 2886 struct atom_common_table_header table_header; 2887 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 2888 }; 2889 2890 2891 /* 2892 *************************************************************************** 2893 All Command Function structure definition 2894 *************************************************************************** 2895 */ 2896 2897 /* 2898 *************************************************************************** 2899 Structures used by asic_init 2900 *************************************************************************** 2901 */ 2902 2903 struct asic_init_engine_parameters 2904 { 2905 uint32_t sclkfreqin10khz:24; 2906 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 2907 }; 2908 2909 struct asic_init_mem_parameters 2910 { 2911 uint32_t mclkfreqin10khz:24; 2912 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 2913 }; 2914 2915 struct asic_init_parameters_v2_1 2916 { 2917 struct asic_init_engine_parameters engineparam; 2918 struct asic_init_mem_parameters memparam; 2919 }; 2920 2921 struct asic_init_ps_allocation_v2_1 2922 { 2923 struct asic_init_parameters_v2_1 param; 2924 uint32_t reserved[16]; 2925 }; 2926 2927 2928 enum atom_asic_init_engine_flag 2929 { 2930 b3NORMAL_ENGINE_INIT = 0, 2931 b3SRIOV_SKIP_ASIC_INIT = 0x02, 2932 b3SRIOV_LOAD_UCODE = 0x40, 2933 }; 2934 2935 enum atom_asic_init_mem_flag 2936 { 2937 b3NORMAL_MEM_INIT = 0, 2938 b3DRAM_SELF_REFRESH_EXIT =0x20, 2939 }; 2940 2941 /* 2942 *************************************************************************** 2943 Structures used by setengineclock 2944 *************************************************************************** 2945 */ 2946 2947 struct set_engine_clock_parameters_v2_1 2948 { 2949 uint32_t sclkfreqin10khz:24; 2950 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2951 uint32_t reserved[10]; 2952 }; 2953 2954 struct set_engine_clock_ps_allocation_v2_1 2955 { 2956 struct set_engine_clock_parameters_v2_1 clockinfo; 2957 uint32_t reserved[10]; 2958 }; 2959 2960 2961 enum atom_set_engine_mem_clock_flag 2962 { 2963 b3NORMAL_CHANGE_CLOCK = 0, 2964 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 2965 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 2966 }; 2967 2968 /* 2969 *************************************************************************** 2970 Structures used by getengineclock 2971 *************************************************************************** 2972 */ 2973 struct get_engine_clock_parameter 2974 { 2975 uint32_t sclk_10khz; // current engine speed in 10KHz unit 2976 uint32_t reserved; 2977 }; 2978 2979 /* 2980 *************************************************************************** 2981 Structures used by setmemoryclock 2982 *************************************************************************** 2983 */ 2984 struct set_memory_clock_parameters_v2_1 2985 { 2986 uint32_t mclkfreqin10khz:24; 2987 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2988 uint32_t reserved[10]; 2989 }; 2990 2991 struct set_memory_clock_ps_allocation_v2_1 2992 { 2993 struct set_memory_clock_parameters_v2_1 clockinfo; 2994 uint32_t reserved[10]; 2995 }; 2996 2997 2998 /* 2999 *************************************************************************** 3000 Structures used by getmemoryclock 3001 *************************************************************************** 3002 */ 3003 struct get_memory_clock_parameter 3004 { 3005 uint32_t mclk_10khz; // current engine speed in 10KHz unit 3006 uint32_t reserved; 3007 }; 3008 3009 3010 3011 /* 3012 *************************************************************************** 3013 Structures used by setvoltage 3014 *************************************************************************** 3015 */ 3016 3017 struct set_voltage_parameters_v1_4 3018 { 3019 uint8_t voltagetype; /* enum atom_voltage_type */ 3020 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 3021 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 3022 }; 3023 3024 //set_voltage_parameters_v2_1.voltagemode 3025 enum atom_set_voltage_command{ 3026 ATOM_SET_VOLTAGE = 0, 3027 ATOM_INIT_VOLTAGE_REGULATOR = 3, 3028 ATOM_SET_VOLTAGE_PHASE = 4, 3029 ATOM_GET_LEAKAGE_ID = 8, 3030 }; 3031 3032 struct set_voltage_ps_allocation_v1_4 3033 { 3034 struct set_voltage_parameters_v1_4 setvoltageparam; 3035 uint32_t reserved[10]; 3036 }; 3037 3038 3039 /* 3040 *************************************************************************** 3041 Structures used by computegpuclockparam 3042 *************************************************************************** 3043 */ 3044 3045 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 3046 enum atom_gpu_clock_type 3047 { 3048 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 3049 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 3050 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 3051 }; 3052 3053 struct compute_gpu_clock_input_parameter_v1_8 3054 { 3055 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3056 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 3057 uint32_t reserved[5]; 3058 }; 3059 3060 3061 struct compute_gpu_clock_output_parameter_v1_8 3062 { 3063 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 3064 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 3065 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 3066 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 3067 uint16_t pll_ss_slew_frac; 3068 uint8_t pll_ss_enable; 3069 uint8_t reserved; 3070 uint32_t reserved1[2]; 3071 }; 3072 3073 3074 3075 /* 3076 *************************************************************************** 3077 Structures used by ReadEfuseValue 3078 *************************************************************************** 3079 */ 3080 3081 struct read_efuse_input_parameters_v3_1 3082 { 3083 uint16_t efuse_start_index; 3084 uint8_t reserved; 3085 uint8_t bitslen; 3086 }; 3087 3088 // ReadEfuseValue input/output parameter 3089 union read_efuse_value_parameters_v3_1 3090 { 3091 struct read_efuse_input_parameters_v3_1 efuse_info; 3092 uint32_t efusevalue; 3093 }; 3094 3095 3096 /* 3097 *************************************************************************** 3098 Structures used by getsmuclockinfo 3099 *************************************************************************** 3100 */ 3101 struct atom_get_smu_clock_info_parameters_v3_1 3102 { 3103 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 3104 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3105 uint8_t command; // enum of atom_get_smu_clock_info_command 3106 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 3107 }; 3108 3109 enum atom_get_smu_clock_info_command 3110 { 3111 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 3112 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 3113 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 3114 }; 3115 3116 enum atom_smu9_syspll0_clock_id 3117 { 3118 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3119 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3120 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3121 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3122 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3123 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3124 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3125 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3126 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3127 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3128 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3129 }; 3130 3131 enum atom_smu11_syspll_id { 3132 SMU11_SYSPLL0_ID = 0, 3133 SMU11_SYSPLL1_0_ID = 1, 3134 SMU11_SYSPLL1_1_ID = 2, 3135 SMU11_SYSPLL1_2_ID = 3, 3136 SMU11_SYSPLL2_ID = 4, 3137 SMU11_SYSPLL3_0_ID = 5, 3138 SMU11_SYSPLL3_1_ID = 6, 3139 }; 3140 3141 enum atom_smu11_syspll0_clock_id { 3142 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3143 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3144 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3145 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3146 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3147 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3148 }; 3149 3150 enum atom_smu11_syspll1_0_clock_id { 3151 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3152 }; 3153 3154 enum atom_smu11_syspll1_1_clock_id { 3155 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3156 }; 3157 3158 enum atom_smu11_syspll1_2_clock_id { 3159 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3160 }; 3161 3162 enum atom_smu11_syspll2_clock_id { 3163 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3164 }; 3165 3166 enum atom_smu11_syspll3_0_clock_id { 3167 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3168 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3169 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3170 }; 3171 3172 enum atom_smu11_syspll3_1_clock_id { 3173 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3174 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3175 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3176 }; 3177 3178 struct atom_get_smu_clock_info_output_parameters_v3_1 3179 { 3180 union { 3181 uint32_t smu_clock_freq_hz; 3182 uint32_t syspllvcofreq_10khz; 3183 uint32_t sysspllrefclk_10khz; 3184 }atom_smu_outputclkfreq; 3185 }; 3186 3187 3188 3189 /* 3190 *************************************************************************** 3191 Structures used by dynamicmemorysettings 3192 *************************************************************************** 3193 */ 3194 3195 enum atom_dynamic_memory_setting_command 3196 { 3197 COMPUTE_MEMORY_PLL_PARAM = 1, 3198 COMPUTE_ENGINE_PLL_PARAM = 2, 3199 ADJUST_MC_SETTING_PARAM = 3, 3200 }; 3201 3202 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3203 struct dynamic_mclk_settings_parameters_v2_1 3204 { 3205 uint32_t mclk_10khz:24; //Input= target mclk 3206 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3207 uint32_t reserved; 3208 }; 3209 3210 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3211 struct dynamic_sclk_settings_parameters_v2_1 3212 { 3213 uint32_t sclk_10khz:24; //Input= target mclk 3214 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3215 uint32_t mclk_10khz; 3216 uint32_t reserved; 3217 }; 3218 3219 union dynamic_memory_settings_parameters_v2_1 3220 { 3221 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3222 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3223 }; 3224 3225 3226 3227 /* 3228 *************************************************************************** 3229 Structures used by memorytraining 3230 *************************************************************************** 3231 */ 3232 3233 enum atom_umc6_0_ucode_function_call_enum_id 3234 { 3235 UMC60_UCODE_FUNC_ID_REINIT = 0, 3236 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3237 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3238 }; 3239 3240 3241 struct memory_training_parameters_v2_1 3242 { 3243 uint8_t ucode_func_id; 3244 uint8_t ucode_reserved[3]; 3245 uint32_t reserved[5]; 3246 }; 3247 3248 3249 /* 3250 *************************************************************************** 3251 Structures used by setpixelclock 3252 *************************************************************************** 3253 */ 3254 3255 struct set_pixel_clock_parameter_v1_7 3256 { 3257 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3258 3259 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3260 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3261 // indicate which graphic encoder will be used. 3262 uint8_t encoder_mode; // Encoder mode: 3263 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3264 uint8_t crtc_id; // enum of atom_crtc_def 3265 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3266 uint8_t reserved1[2]; 3267 uint32_t reserved2; 3268 }; 3269 3270 //ucMiscInfo 3271 enum atom_set_pixel_clock_v1_7_misc_info 3272 { 3273 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3274 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3275 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3276 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3277 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3278 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3279 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3280 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3281 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3282 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3283 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3284 }; 3285 3286 /* deep_color_ratio */ 3287 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3288 { 3289 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3290 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3291 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3292 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3293 }; 3294 3295 /* 3296 *************************************************************************** 3297 Structures used by setdceclock 3298 *************************************************************************** 3299 */ 3300 3301 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3302 struct set_dce_clock_parameters_v2_1 3303 { 3304 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3305 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3306 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3307 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3308 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3309 }; 3310 3311 //ucDCEClkType 3312 enum atom_set_dce_clock_clock_type 3313 { 3314 DCE_CLOCK_TYPE_DISPCLK = 0, 3315 DCE_CLOCK_TYPE_DPREFCLK = 1, 3316 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3317 }; 3318 3319 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3320 enum atom_set_dce_clock_dprefclk_flag 3321 { 3322 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 3323 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 3324 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 3325 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 3326 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 3327 }; 3328 3329 //ucDCEClkFlag when ucDCEClkType == PIXCLK 3330 enum atom_set_dce_clock_pixclk_flag 3331 { 3332 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 3333 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3334 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3335 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3336 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3337 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 3338 }; 3339 3340 struct set_dce_clock_ps_allocation_v2_1 3341 { 3342 struct set_dce_clock_parameters_v2_1 param; 3343 uint32_t ulReserved[2]; 3344 }; 3345 3346 3347 /****************************************************************************/ 3348 // Structures used by BlankCRTC 3349 /****************************************************************************/ 3350 struct blank_crtc_parameters 3351 { 3352 uint8_t crtc_id; // enum atom_crtc_def 3353 uint8_t blanking; // enum atom_blank_crtc_command 3354 uint16_t reserved; 3355 uint32_t reserved1; 3356 }; 3357 3358 enum atom_blank_crtc_command 3359 { 3360 ATOM_BLANKING = 1, 3361 ATOM_BLANKING_OFF = 0, 3362 }; 3363 3364 /****************************************************************************/ 3365 // Structures used by enablecrtc 3366 /****************************************************************************/ 3367 struct enable_crtc_parameters 3368 { 3369 uint8_t crtc_id; // enum atom_crtc_def 3370 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3371 uint8_t padding[2]; 3372 }; 3373 3374 3375 /****************************************************************************/ 3376 // Structure used by EnableDispPowerGating 3377 /****************************************************************************/ 3378 struct enable_disp_power_gating_parameters_v2_1 3379 { 3380 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 3381 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3382 uint8_t padding[2]; 3383 }; 3384 3385 struct enable_disp_power_gating_ps_allocation 3386 { 3387 struct enable_disp_power_gating_parameters_v2_1 param; 3388 uint32_t ulReserved[4]; 3389 }; 3390 3391 /****************************************************************************/ 3392 // Structure used in setcrtc_usingdtdtiming 3393 /****************************************************************************/ 3394 struct set_crtc_using_dtd_timing_parameters 3395 { 3396 uint16_t h_size; 3397 uint16_t h_blanking_time; 3398 uint16_t v_size; 3399 uint16_t v_blanking_time; 3400 uint16_t h_syncoffset; 3401 uint16_t h_syncwidth; 3402 uint16_t v_syncoffset; 3403 uint16_t v_syncwidth; 3404 uint16_t modemiscinfo; 3405 uint8_t h_border; 3406 uint8_t v_border; 3407 uint8_t crtc_id; // enum atom_crtc_def 3408 uint8_t encoder_mode; // atom_encode_mode_def 3409 uint8_t padding[2]; 3410 }; 3411 3412 3413 /****************************************************************************/ 3414 // Structures used by processi2cchanneltransaction 3415 /****************************************************************************/ 3416 struct process_i2c_channel_transaction_parameters 3417 { 3418 uint8_t i2cspeed_khz; 3419 union { 3420 uint8_t regindex; 3421 uint8_t status; /* enum atom_process_i2c_flag */ 3422 } regind_status; 3423 uint16_t i2c_data_out; 3424 uint8_t flag; /* enum atom_process_i2c_status */ 3425 uint8_t trans_bytes; 3426 uint8_t slave_addr; 3427 uint8_t i2c_id; 3428 }; 3429 3430 //ucFlag 3431 enum atom_process_i2c_flag 3432 { 3433 HW_I2C_WRITE = 1, 3434 HW_I2C_READ = 0, 3435 I2C_2BYTE_ADDR = 0x02, 3436 HW_I2C_SMBUS_BYTE_WR = 0x04, 3437 }; 3438 3439 //status 3440 enum atom_process_i2c_status 3441 { 3442 HW_ASSISTED_I2C_STATUS_FAILURE =2, 3443 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 3444 }; 3445 3446 3447 /****************************************************************************/ 3448 // Structures used by processauxchanneltransaction 3449 /****************************************************************************/ 3450 3451 struct process_aux_channel_transaction_parameters_v1_2 3452 { 3453 uint16_t aux_request; 3454 uint16_t dataout; 3455 uint8_t channelid; 3456 union { 3457 uint8_t reply_status; 3458 uint8_t aux_delay; 3459 } aux_status_delay; 3460 uint8_t dataout_len; 3461 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 3462 }; 3463 3464 3465 /****************************************************************************/ 3466 // Structures used by selectcrtc_source 3467 /****************************************************************************/ 3468 3469 struct select_crtc_source_parameters_v2_3 3470 { 3471 uint8_t crtc_id; // enum atom_crtc_def 3472 uint8_t encoder_id; // enum atom_dig_def 3473 uint8_t encode_mode; // enum atom_encode_mode_def 3474 uint8_t dst_bpc; // enum atom_panel_bit_per_color 3475 }; 3476 3477 3478 /****************************************************************************/ 3479 // Structures used by digxencodercontrol 3480 /****************************************************************************/ 3481 3482 // ucAction: 3483 enum atom_dig_encoder_control_action 3484 { 3485 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 3486 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 3487 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 3488 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 3489 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 3490 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 3491 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 3492 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 3493 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 3494 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 3495 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 3496 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 3497 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 3498 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 3499 }; 3500 3501 //define ucPanelMode 3502 enum atom_dig_encoder_control_panelmode 3503 { 3504 DP_PANEL_MODE_DISABLE = 0x00, 3505 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 3506 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 3507 }; 3508 3509 //ucDigId 3510 enum atom_dig_encoder_control_v5_digid 3511 { 3512 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 3513 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 3514 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 3515 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 3516 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 3517 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 3518 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 3519 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 3520 }; 3521 3522 struct dig_encoder_stream_setup_parameters_v1_5 3523 { 3524 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3525 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 3526 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3527 uint8_t lanenum; // Lane number 3528 uint32_t pclk_10khz; // Pixel Clock in 10Khz 3529 uint8_t bitpercolor; 3530 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 3531 uint8_t reserved[2]; 3532 }; 3533 3534 struct dig_encoder_link_setup_parameters_v1_5 3535 { 3536 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3537 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 3538 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3539 uint8_t lanenum; // Lane number 3540 uint8_t symclk_10khz; // Symbol Clock in 10Khz 3541 uint8_t hpd_sel; 3542 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3543 uint8_t reserved[2]; 3544 }; 3545 3546 struct dp_panel_mode_set_parameters_v1_5 3547 { 3548 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3549 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 3550 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 3551 uint8_t reserved1; 3552 uint32_t reserved2[2]; 3553 }; 3554 3555 struct dig_encoder_generic_cmd_parameters_v1_5 3556 { 3557 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3558 uint8_t action; // = rest of generic encoder command which does not carry any parameters 3559 uint8_t reserved1[2]; 3560 uint32_t reserved2[2]; 3561 }; 3562 3563 union dig_encoder_control_parameters_v1_5 3564 { 3565 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 3566 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 3567 struct dig_encoder_link_setup_parameters_v1_5 link_param; 3568 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 3569 }; 3570 3571 /* 3572 *************************************************************************** 3573 Structures used by dig1transmittercontrol 3574 *************************************************************************** 3575 */ 3576 struct dig_transmitter_control_parameters_v1_6 3577 { 3578 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 3579 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 3580 union { 3581 uint8_t digmode; // enum atom_encode_mode_def 3582 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3583 } mode_laneset; 3584 uint8_t lanenum; // Lane number 1, 2, 4, 8 3585 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3586 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3587 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3588 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3589 uint8_t reserved; 3590 uint32_t reserved1; 3591 }; 3592 3593 struct dig_transmitter_control_ps_allocation_v1_6 3594 { 3595 struct dig_transmitter_control_parameters_v1_6 param; 3596 uint32_t reserved[4]; 3597 }; 3598 3599 //ucAction 3600 enum atom_dig_transmitter_control_action 3601 { 3602 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3603 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3604 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3605 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3606 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3607 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3608 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3609 ATOM_TRANSMITTER_ACTION_INIT = 7, 3610 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3611 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3612 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3613 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3614 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3615 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3616 }; 3617 3618 // digfe_sel 3619 enum atom_dig_transmitter_control_digfe_sel 3620 { 3621 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3622 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3623 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3624 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3625 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3626 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3627 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3628 }; 3629 3630 3631 //ucHPDSel 3632 enum atom_dig_transmitter_control_hpd_sel 3633 { 3634 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3635 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3636 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3637 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3638 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3639 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3640 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3641 }; 3642 3643 // ucDPLaneSet 3644 enum atom_dig_transmitter_control_dplaneset 3645 { 3646 DP_LANE_SET__0DB_0_4V = 0x00, 3647 DP_LANE_SET__0DB_0_6V = 0x01, 3648 DP_LANE_SET__0DB_0_8V = 0x02, 3649 DP_LANE_SET__0DB_1_2V = 0x03, 3650 DP_LANE_SET__3_5DB_0_4V = 0x08, 3651 DP_LANE_SET__3_5DB_0_6V = 0x09, 3652 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3653 DP_LANE_SET__6DB_0_4V = 0x10, 3654 DP_LANE_SET__6DB_0_6V = 0x11, 3655 DP_LANE_SET__9_5DB_0_4V = 0x18, 3656 }; 3657 3658 3659 3660 /****************************************************************************/ 3661 // Structures used by ExternalEncoderControl V2.4 3662 /****************************************************************************/ 3663 3664 struct external_encoder_control_parameters_v2_4 3665 { 3666 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3667 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3668 uint8_t action; // 3669 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3670 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3671 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3672 uint8_t hpd_id; 3673 }; 3674 3675 3676 // ucAction 3677 enum external_encoder_control_action_def 3678 { 3679 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3680 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3681 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3682 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3683 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3684 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3685 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3686 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3687 }; 3688 3689 // ucConfig 3690 enum external_encoder_control_v2_4_config_def 3691 { 3692 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3693 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3694 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3695 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3696 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3697 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3698 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3699 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3700 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3701 }; 3702 3703 struct external_encoder_control_ps_allocation_v2_4 3704 { 3705 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3706 uint32_t reserved[2]; 3707 }; 3708 3709 3710 /* 3711 *************************************************************************** 3712 AMD ACPI Table 3713 3714 *************************************************************************** 3715 */ 3716 3717 struct amd_acpi_description_header{ 3718 uint32_t signature; 3719 uint32_t tableLength; //Length 3720 uint8_t revision; 3721 uint8_t checksum; 3722 uint8_t oemId[6]; 3723 uint8_t oemTableId[8]; //UINT64 OemTableId; 3724 uint32_t oemRevision; 3725 uint32_t creatorId; 3726 uint32_t creatorRevision; 3727 }; 3728 3729 struct uefi_acpi_vfct{ 3730 struct amd_acpi_description_header sheader; 3731 uint8_t tableUUID[16]; //0x24 3732 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3733 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3734 uint32_t reserved[4]; //0x3C 3735 }; 3736 3737 struct vfct_image_header{ 3738 uint32_t pcibus; //0x4C 3739 uint32_t pcidevice; //0x50 3740 uint32_t pcifunction; //0x54 3741 uint16_t vendorid; //0x58 3742 uint16_t deviceid; //0x5A 3743 uint16_t ssvid; //0x5C 3744 uint16_t ssid; //0x5E 3745 uint32_t revision; //0x60 3746 uint32_t imagelength; //0x64 3747 }; 3748 3749 3750 struct gop_vbios_content { 3751 struct vfct_image_header vbiosheader; 3752 uint8_t vbioscontent[1]; 3753 }; 3754 3755 struct gop_lib1_content { 3756 struct vfct_image_header lib1header; 3757 uint8_t lib1content[1]; 3758 }; 3759 3760 3761 3762 /* 3763 *************************************************************************** 3764 Scratch Register definitions 3765 Each number below indicates which scratch regiser request, Active and 3766 Connect all share the same definitions as display_device_tag defines 3767 *************************************************************************** 3768 */ 3769 3770 enum scratch_register_def{ 3771 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3772 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3773 ATOM_ACTIVE_INFO_DEF = 3, 3774 ATOM_LCD_INFO_DEF = 4, 3775 ATOM_DEVICE_REQ_INFO_DEF = 5, 3776 ATOM_ACC_CHANGE_INFO_DEF = 6, 3777 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3778 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3779 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3780 }; 3781 3782 enum scratch_device_connect_info_bit_def{ 3783 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3784 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3785 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3786 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3787 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3788 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3789 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3790 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3791 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3792 }; 3793 3794 enum scratch_bl_bri_level_info_bit_def{ 3795 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3796 #ifndef _H2INC 3797 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 3798 ATOM_DEVICE_DPMS_STATE =0x00010000, 3799 #endif 3800 }; 3801 3802 enum scratch_active_info_bits_def{ 3803 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 3804 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 3805 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 3806 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 3807 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 3808 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 3809 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 3810 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 3811 }; 3812 3813 enum scratch_device_req_info_bits_def{ 3814 ATOM_DISPLAY_LCD1_REQ =0x0002, 3815 ATOM_DISPLAY_DFP1_REQ =0x0008, 3816 ATOM_DISPLAY_DFP2_REQ =0x0080, 3817 ATOM_DISPLAY_DFP3_REQ =0x0200, 3818 ATOM_DISPLAY_DFP4_REQ =0x0400, 3819 ATOM_DISPLAY_DFP5_REQ =0x0800, 3820 ATOM_DISPLAY_DFP6_REQ =0x0040, 3821 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 3822 }; 3823 3824 enum scratch_acc_change_info_bitshift_def{ 3825 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 3826 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 3827 }; 3828 3829 enum scratch_acc_change_info_bits_def{ 3830 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 3831 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 3832 }; 3833 3834 enum scratch_pre_os_mode_info_bits_def{ 3835 ATOM_PRE_OS_MODE_MASK =0x00000003, 3836 ATOM_PRE_OS_MODE_VGA =0x00000000, 3837 ATOM_PRE_OS_MODE_VESA =0x00000001, 3838 ATOM_PRE_OS_MODE_GOP =0x00000002, 3839 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3840 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3841 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3842 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3843 #ifndef _H2INC 3844 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3845 #endif 3846 }; 3847 3848 3849 3850 /* 3851 *************************************************************************** 3852 ATOM firmware ID header file 3853 !! Please keep it at end of the atomfirmware.h !! 3854 *************************************************************************** 3855 */ 3856 #include "atomfirmwareid.h" 3857 #pragma pack() 3858 3859 #endif 3860 3861