1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 184 }; 185 186 enum atom_dp_vs_preemph_def{ 187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 197 }; 198 199 200 /* 201 enum atom_string_def{ 202 asic_bus_type_pcie_string = "PCI_EXPRESS", 203 atom_fire_gl_string = "FGL", 204 atom_bios_string = "ATOM" 205 }; 206 */ 207 208 #pragma pack(1) /* BIOS data must use byte aligment*/ 209 210 enum atombios_image_offset{ 211 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 212 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 213 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 214 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 215 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 216 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 217 }; 218 219 /**************************************************************************** 220 * Common header for all tables (Data table, Command function). 221 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 222 * And the pointer actually points to this header. 223 ****************************************************************************/ 224 225 struct atom_common_table_header 226 { 227 uint16_t structuresize; 228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 230 }; 231 232 /**************************************************************************** 233 * Structure stores the ROM header. 234 ****************************************************************************/ 235 struct atom_rom_header_v2_2 236 { 237 struct atom_common_table_header table_header; 238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 239 uint16_t bios_segment_address; 240 uint16_t protectedmodeoffset; 241 uint16_t configfilenameoffset; 242 uint16_t crc_block_offset; 243 uint16_t vbios_bootupmessageoffset; 244 uint16_t int10_offset; 245 uint16_t pcibusdevinitcode; 246 uint16_t iobaseaddress; 247 uint16_t subsystem_vendor_id; 248 uint16_t subsystem_id; 249 uint16_t pci_info_offset; 250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 252 uint16_t reserved; 253 uint32_t pspdirtableoffset; 254 }; 255 256 /*==============================hw function portion======================================================================*/ 257 258 259 /**************************************************************************** 260 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 261 * The real functionality of each function is associated with the parameter structure version when defined 262 * For all internal cmd function definitions, please reference to atomstruct.h 263 ****************************************************************************/ 264 struct atom_master_list_of_command_functions_v2_1{ 265 uint16_t asic_init; //Function 266 uint16_t cmd_function1; //used as an internal one 267 uint16_t cmd_function2; //used as an internal one 268 uint16_t cmd_function3; //used as an internal one 269 uint16_t digxencodercontrol; //Function 270 uint16_t cmd_function5; //used as an internal one 271 uint16_t cmd_function6; //used as an internal one 272 uint16_t cmd_function7; //used as an internal one 273 uint16_t cmd_function8; //used as an internal one 274 uint16_t cmd_function9; //used as an internal one 275 uint16_t setengineclock; //Function 276 uint16_t setmemoryclock; //Function 277 uint16_t setpixelclock; //Function 278 uint16_t enabledisppowergating; //Function 279 uint16_t cmd_function14; //used as an internal one 280 uint16_t cmd_function15; //used as an internal one 281 uint16_t cmd_function16; //used as an internal one 282 uint16_t cmd_function17; //used as an internal one 283 uint16_t cmd_function18; //used as an internal one 284 uint16_t cmd_function19; //used as an internal one 285 uint16_t cmd_function20; //used as an internal one 286 uint16_t cmd_function21; //used as an internal one 287 uint16_t cmd_function22; //used as an internal one 288 uint16_t cmd_function23; //used as an internal one 289 uint16_t cmd_function24; //used as an internal one 290 uint16_t cmd_function25; //used as an internal one 291 uint16_t cmd_function26; //used as an internal one 292 uint16_t cmd_function27; //used as an internal one 293 uint16_t cmd_function28; //used as an internal one 294 uint16_t cmd_function29; //used as an internal one 295 uint16_t cmd_function30; //used as an internal one 296 uint16_t cmd_function31; //used as an internal one 297 uint16_t cmd_function32; //used as an internal one 298 uint16_t cmd_function33; //used as an internal one 299 uint16_t blankcrtc; //Function 300 uint16_t enablecrtc; //Function 301 uint16_t cmd_function36; //used as an internal one 302 uint16_t cmd_function37; //used as an internal one 303 uint16_t cmd_function38; //used as an internal one 304 uint16_t cmd_function39; //used as an internal one 305 uint16_t cmd_function40; //used as an internal one 306 uint16_t getsmuclockinfo; //Function 307 uint16_t selectcrtc_source; //Function 308 uint16_t cmd_function43; //used as an internal one 309 uint16_t cmd_function44; //used as an internal one 310 uint16_t cmd_function45; //used as an internal one 311 uint16_t setdceclock; //Function 312 uint16_t getmemoryclock; //Function 313 uint16_t getengineclock; //Function 314 uint16_t setcrtc_usingdtdtiming; //Function 315 uint16_t externalencodercontrol; //Function 316 uint16_t cmd_function51; //used as an internal one 317 uint16_t cmd_function52; //used as an internal one 318 uint16_t cmd_function53; //used as an internal one 319 uint16_t processi2cchanneltransaction;//Function 320 uint16_t cmd_function55; //used as an internal one 321 uint16_t cmd_function56; //used as an internal one 322 uint16_t cmd_function57; //used as an internal one 323 uint16_t cmd_function58; //used as an internal one 324 uint16_t cmd_function59; //used as an internal one 325 uint16_t computegpuclockparam; //Function 326 uint16_t cmd_function61; //used as an internal one 327 uint16_t cmd_function62; //used as an internal one 328 uint16_t dynamicmemorysettings; //Function function 329 uint16_t memorytraining; //Function function 330 uint16_t cmd_function65; //used as an internal one 331 uint16_t cmd_function66; //used as an internal one 332 uint16_t setvoltage; //Function 333 uint16_t cmd_function68; //used as an internal one 334 uint16_t readefusevalue; //Function 335 uint16_t cmd_function70; //used as an internal one 336 uint16_t cmd_function71; //used as an internal one 337 uint16_t cmd_function72; //used as an internal one 338 uint16_t cmd_function73; //used as an internal one 339 uint16_t cmd_function74; //used as an internal one 340 uint16_t cmd_function75; //used as an internal one 341 uint16_t dig1transmittercontrol; //Function 342 uint16_t cmd_function77; //used as an internal one 343 uint16_t processauxchanneltransaction;//Function 344 uint16_t cmd_function79; //used as an internal one 345 uint16_t getvoltageinfo; //Function 346 }; 347 348 struct atom_master_command_function_v2_1 349 { 350 struct atom_common_table_header table_header; 351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 352 }; 353 354 /**************************************************************************** 355 * Structures used in every command function 356 ****************************************************************************/ 357 struct atom_function_attribute 358 { 359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 362 }; 363 364 365 /**************************************************************************** 366 * Common header for all hw functions. 367 * Every function pointed by _master_list_of_hw_function has this common header. 368 * And the pointer actually points to this header. 369 ****************************************************************************/ 370 struct atom_rom_hw_function_header 371 { 372 struct atom_common_table_header func_header; 373 struct atom_function_attribute func_attrib; 374 }; 375 376 377 /*==============================sw data table portion======================================================================*/ 378 /**************************************************************************** 379 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 380 * The real name of each table is given when its data structure version is defined 381 ****************************************************************************/ 382 struct atom_master_list_of_data_tables_v2_1{ 383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 384 uint16_t multimedia_info; 385 uint16_t smc_dpm_info; 386 uint16_t sw_datatable3; 387 uint16_t firmwareinfo; /* Shared by various SW components */ 388 uint16_t sw_datatable5; 389 uint16_t lcd_info; /* Shared by various SW components */ 390 uint16_t sw_datatable7; 391 uint16_t smu_info; 392 uint16_t sw_datatable9; 393 uint16_t sw_datatable10; 394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 395 uint16_t gpio_pin_lut; /* Shared by various SW components */ 396 uint16_t sw_datatable13; 397 uint16_t gfx_info; 398 uint16_t powerplayinfo; /* Shared by various SW components */ 399 uint16_t sw_datatable16; 400 uint16_t sw_datatable17; 401 uint16_t sw_datatable18; 402 uint16_t sw_datatable19; 403 uint16_t sw_datatable20; 404 uint16_t sw_datatable21; 405 uint16_t displayobjectinfo; /* Shared by various SW components */ 406 uint16_t indirectioaccess; /* used as an internal one */ 407 uint16_t umc_info; /* Shared by various SW components */ 408 uint16_t sw_datatable25; 409 uint16_t sw_datatable26; 410 uint16_t dce_info; /* Shared by various SW components */ 411 uint16_t vram_info; /* Shared by various SW components */ 412 uint16_t sw_datatable29; 413 uint16_t integratedsysteminfo; /* Shared by various SW components */ 414 uint16_t asic_profiling_info; /* Shared by various SW components */ 415 uint16_t voltageobject_info; /* shared by various SW components */ 416 uint16_t sw_datatable33; 417 uint16_t sw_datatable34; 418 }; 419 420 421 struct atom_master_data_table_v2_1 422 { 423 struct atom_common_table_header table_header; 424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 425 }; 426 427 428 struct atom_dtd_format 429 { 430 uint16_t pixclk; 431 uint16_t h_active; 432 uint16_t h_blanking_time; 433 uint16_t v_active; 434 uint16_t v_blanking_time; 435 uint16_t h_sync_offset; 436 uint16_t h_sync_width; 437 uint16_t v_sync_offset; 438 uint16_t v_syncwidth; 439 uint16_t reserved; 440 uint16_t reserved0; 441 uint8_t h_border; 442 uint8_t v_border; 443 uint16_t miscinfo; 444 uint8_t atom_mode_id; 445 uint8_t refreshrate; 446 }; 447 448 /* atom_dtd_format.modemiscinfo defintion */ 449 enum atom_dtd_format_modemiscinfo{ 450 ATOM_HSYNC_POLARITY = 0x0002, 451 ATOM_VSYNC_POLARITY = 0x0004, 452 ATOM_H_REPLICATIONBY2 = 0x0010, 453 ATOM_V_REPLICATIONBY2 = 0x0020, 454 ATOM_INTERLACE = 0x0080, 455 ATOM_COMPOSITESYNC = 0x0040, 456 }; 457 458 459 /* utilitypipeline 460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 461 * the location of it can't change 462 */ 463 464 465 /* 466 *************************************************************************** 467 Data Table firmwareinfo structure 468 *************************************************************************** 469 */ 470 471 struct atom_firmware_info_v3_1 472 { 473 struct atom_common_table_header table_header; 474 uint32_t firmware_revision; 475 uint32_t bootup_sclk_in10khz; 476 uint32_t bootup_mclk_in10khz; 477 uint32_t firmware_capability; // enum atombios_firmware_capability 478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 480 uint16_t bootup_vddc_mv; 481 uint16_t bootup_vddci_mv; 482 uint16_t bootup_mvddc_mv; 483 uint16_t bootup_vddgfx_mv; 484 uint8_t mem_module_id; 485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 486 uint8_t reserved1[2]; 487 uint32_t mc_baseaddr_high; 488 uint32_t mc_baseaddr_low; 489 uint32_t reserved2[6]; 490 }; 491 492 /* Total 32bit cap indication */ 493 enum atombios_firmware_capability 494 { 495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 501 ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING = 0x00000400, 502 }; 503 504 enum atom_cooling_solution_id{ 505 AIR_COOLING = 0x00, 506 LIQUID_COOLING = 0x01 507 }; 508 509 struct atom_firmware_info_v3_2 { 510 struct atom_common_table_header table_header; 511 uint32_t firmware_revision; 512 uint32_t bootup_sclk_in10khz; 513 uint32_t bootup_mclk_in10khz; 514 uint32_t firmware_capability; // enum atombios_firmware_capability 515 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 516 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 517 uint16_t bootup_vddc_mv; 518 uint16_t bootup_vddci_mv; 519 uint16_t bootup_mvddc_mv; 520 uint16_t bootup_vddgfx_mv; 521 uint8_t mem_module_id; 522 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 523 uint8_t reserved1[2]; 524 uint32_t mc_baseaddr_high; 525 uint32_t mc_baseaddr_low; 526 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 527 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 528 uint8_t board_i2c_feature_slave_addr; 529 uint8_t reserved3; 530 uint16_t bootup_mvddq_mv; 531 uint16_t bootup_mvpp_mv; 532 uint32_t zfbstartaddrin16mb; 533 uint32_t reserved2[3]; 534 }; 535 536 struct atom_firmware_info_v3_3 537 { 538 struct atom_common_table_header table_header; 539 uint32_t firmware_revision; 540 uint32_t bootup_sclk_in10khz; 541 uint32_t bootup_mclk_in10khz; 542 uint32_t firmware_capability; // enum atombios_firmware_capability 543 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 544 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 545 uint16_t bootup_vddc_mv; 546 uint16_t bootup_vddci_mv; 547 uint16_t bootup_mvddc_mv; 548 uint16_t bootup_vddgfx_mv; 549 uint8_t mem_module_id; 550 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 551 uint8_t reserved1[2]; 552 uint32_t mc_baseaddr_high; 553 uint32_t mc_baseaddr_low; 554 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 555 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 556 uint8_t board_i2c_feature_slave_addr; 557 uint8_t reserved3; 558 uint16_t bootup_mvddq_mv; 559 uint16_t bootup_mvpp_mv; 560 uint32_t zfbstartaddrin16mb; 561 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 562 uint32_t reserved2[2]; 563 }; 564 565 struct atom_firmware_info_v3_4 { 566 struct atom_common_table_header table_header; 567 uint32_t firmware_revision; 568 uint32_t bootup_sclk_in10khz; 569 uint32_t bootup_mclk_in10khz; 570 uint32_t firmware_capability; // enum atombios_firmware_capability 571 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 572 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 573 uint16_t bootup_vddc_mv; 574 uint16_t bootup_vddci_mv; 575 uint16_t bootup_mvddc_mv; 576 uint16_t bootup_vddgfx_mv; 577 uint8_t mem_module_id; 578 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 579 uint8_t reserved1[2]; 580 uint32_t mc_baseaddr_high; 581 uint32_t mc_baseaddr_low; 582 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 583 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 584 uint8_t board_i2c_feature_slave_addr; 585 uint8_t reserved3; 586 uint16_t bootup_mvddq_mv; 587 uint16_t bootup_mvpp_mv; 588 uint32_t zfbstartaddrin16mb; 589 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 590 uint32_t mvdd_ratio; // mvdd_raio = (real mvdd in power rail)*1000/(mvdd_output_from_svi2) 591 uint16_t hw_bootup_vddgfx_mv; // hw default vddgfx voltage level decide by board strap 592 uint16_t hw_bootup_vddc_mv; // hw default vddc voltage level decide by board strap 593 uint16_t hw_bootup_mvddc_mv; // hw default mvddc voltage level decide by board strap 594 uint16_t hw_bootup_vddci_mv; // hw default vddci voltage level decide by board strap 595 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt 596 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt 597 uint32_t fw_reserved_size_in_kb; // VBIOS reserved extra fw size in unit of kb. 598 uint32_t reserved[5]; 599 }; 600 601 /* 602 *************************************************************************** 603 Data Table lcd_info structure 604 *************************************************************************** 605 */ 606 607 struct lcd_info_v2_1 608 { 609 struct atom_common_table_header table_header; 610 struct atom_dtd_format lcd_timing; 611 uint16_t backlight_pwm; 612 uint16_t special_handle_cap; 613 uint16_t panel_misc; 614 uint16_t lvds_max_slink_pclk; 615 uint16_t lvds_ss_percentage; 616 uint16_t lvds_ss_rate_10hz; 617 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 618 uint8_t pwr_on_de_to_vary_bl; 619 uint8_t pwr_down_vary_bloff_to_de; 620 uint8_t pwr_down_de_to_digoff; 621 uint8_t pwr_off_delay; 622 uint8_t pwr_on_vary_bl_to_blon; 623 uint8_t pwr_down_bloff_to_vary_bloff; 624 uint8_t panel_bpc; 625 uint8_t dpcd_edp_config_cap; 626 uint8_t dpcd_max_link_rate; 627 uint8_t dpcd_max_lane_count; 628 uint8_t dpcd_max_downspread; 629 uint8_t min_allowed_bl_level; 630 uint8_t max_allowed_bl_level; 631 uint8_t bootup_bl_level; 632 uint8_t dplvdsrxid; 633 uint32_t reserved1[8]; 634 }; 635 636 /* lcd_info_v2_1.panel_misc defintion */ 637 enum atom_lcd_info_panel_misc{ 638 ATOM_PANEL_MISC_FPDI =0x0002, 639 }; 640 641 //uceDPToLVDSRxId 642 enum atom_lcd_info_dptolvds_rx_id 643 { 644 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 645 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 646 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 647 }; 648 649 650 /* 651 *************************************************************************** 652 Data Table gpio_pin_lut structure 653 *************************************************************************** 654 */ 655 656 struct atom_gpio_pin_assignment 657 { 658 uint32_t data_a_reg_index; 659 uint8_t gpio_bitshift; 660 uint8_t gpio_mask_bitshift; 661 uint8_t gpio_id; 662 uint8_t reserved; 663 }; 664 665 /* atom_gpio_pin_assignment.gpio_id definition */ 666 enum atom_gpio_pin_assignment_gpio_id { 667 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 668 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 669 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 670 671 /* gpio_id pre-define id for multiple usage */ 672 /* GPIO use to control PCIE_VDDC in certain SLT board */ 673 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 674 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 675 PP_AC_DC_SWITCH_GPIO_PINID = 60, 676 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 677 VDDC_VRHOT_GPIO_PINID = 61, 678 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 679 VDDC_PCC_GPIO_PINID = 62, 680 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 681 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 682 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 683 DRAM_SELF_REFRESH_GPIO_PINID = 64, 684 /* Thermal interrupt output->system thermal chip GPIO pin */ 685 THERMAL_INT_OUTPUT_GPIO_PINID =65, 686 }; 687 688 689 struct atom_gpio_pin_lut_v2_1 690 { 691 struct atom_common_table_header table_header; 692 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 693 struct atom_gpio_pin_assignment gpio_pin[8]; 694 }; 695 696 697 /* 698 *************************************************************************** 699 Data Table vram_usagebyfirmware structure 700 *************************************************************************** 701 */ 702 703 struct vram_usagebyfirmware_v2_1 704 { 705 struct atom_common_table_header table_header; 706 uint32_t start_address_in_kb; 707 uint16_t used_by_firmware_in_kb; 708 uint16_t used_by_driver_in_kb; 709 }; 710 711 712 /* 713 *************************************************************************** 714 Data Table displayobjectinfo structure 715 *************************************************************************** 716 */ 717 718 enum atom_object_record_type_id 719 { 720 ATOM_I2C_RECORD_TYPE =1, 721 ATOM_HPD_INT_RECORD_TYPE =2, 722 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 723 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 724 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 725 ATOM_ENCODER_CAP_RECORD_TYPE=20, 726 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 727 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 728 ATOM_RECORD_END_TYPE =0xFF, 729 }; 730 731 struct atom_common_record_header 732 { 733 uint8_t record_type; //An emun to indicate the record type 734 uint8_t record_size; //The size of the whole record in byte 735 }; 736 737 struct atom_i2c_record 738 { 739 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 740 uint8_t i2c_id; 741 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 742 }; 743 744 struct atom_hpd_int_record 745 { 746 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 747 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 748 uint8_t plugin_pin_state; 749 }; 750 751 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 752 enum atom_encoder_caps_def 753 { 754 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 755 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 756 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 757 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 758 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 759 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 760 }; 761 762 struct atom_encoder_caps_record 763 { 764 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 765 uint32_t encodercaps; 766 }; 767 768 enum atom_connector_caps_def 769 { 770 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 771 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 772 }; 773 774 struct atom_disp_connector_caps_record 775 { 776 struct atom_common_record_header record_header; 777 uint32_t connectcaps; 778 }; 779 780 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 781 struct atom_gpio_pin_control_pair 782 { 783 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 784 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 785 }; 786 787 struct atom_object_gpio_cntl_record 788 { 789 struct atom_common_record_header record_header; 790 uint8_t flag; // Future expnadibility 791 uint8_t number_of_pins; // Number of GPIO pins used to control the object 792 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 793 }; 794 795 //Definitions for GPIO pin state 796 enum atom_gpio_pin_control_pinstate_def 797 { 798 GPIO_PIN_TYPE_INPUT = 0x00, 799 GPIO_PIN_TYPE_OUTPUT = 0x10, 800 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 801 802 //For GPIO_PIN_TYPE_OUTPUT the following is defined 803 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 804 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 805 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 806 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 807 }; 808 809 // Indexes to GPIO array in GLSync record 810 // GLSync record is for Frame Lock/Gen Lock feature. 811 enum atom_glsync_record_gpio_index_def 812 { 813 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 814 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 815 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 816 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 817 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 818 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 819 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 820 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 821 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 822 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 823 }; 824 825 826 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 827 { 828 struct atom_common_record_header record_header; 829 uint8_t hpd_pin_map[8]; 830 }; 831 832 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 833 { 834 struct atom_common_record_header record_header; 835 uint8_t aux_ddc_map[8]; 836 }; 837 838 struct atom_connector_forced_tmds_cap_record 839 { 840 struct atom_common_record_header record_header; 841 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 842 uint8_t maxtmdsclkrate_in2_5mhz; 843 uint8_t reserved; 844 }; 845 846 struct atom_connector_layout_info 847 { 848 uint16_t connectorobjid; 849 uint8_t connector_type; 850 uint8_t position; 851 }; 852 853 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 854 enum atom_connector_layout_info_connector_type_def 855 { 856 CONNECTOR_TYPE_DVI_D = 1, 857 858 CONNECTOR_TYPE_HDMI = 4, 859 CONNECTOR_TYPE_DISPLAY_PORT = 5, 860 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 861 }; 862 863 struct atom_bracket_layout_record 864 { 865 struct atom_common_record_header record_header; 866 uint8_t bracketlen; 867 uint8_t bracketwidth; 868 uint8_t conn_num; 869 uint8_t reserved; 870 struct atom_connector_layout_info conn_info[1]; 871 }; 872 873 enum atom_display_device_tag_def{ 874 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 875 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 876 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 877 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 878 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 879 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 880 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 881 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 882 }; 883 884 struct atom_display_object_path_v2 885 { 886 uint16_t display_objid; //Connector Object ID or Misc Object ID 887 uint16_t disp_recordoffset; 888 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 889 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 890 uint16_t encoder_recordoffset; 891 uint16_t extencoder_recordoffset; 892 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 893 uint8_t priority_id; 894 uint8_t reserved; 895 }; 896 897 struct display_object_info_table_v1_4 898 { 899 struct atom_common_table_header table_header; 900 uint16_t supporteddevices; 901 uint8_t number_of_path; 902 uint8_t reserved; 903 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 904 }; 905 906 907 /* 908 *************************************************************************** 909 Data Table dce_info structure 910 *************************************************************************** 911 */ 912 struct atom_display_controller_info_v4_1 913 { 914 struct atom_common_table_header table_header; 915 uint32_t display_caps; 916 uint32_t bootup_dispclk_10khz; 917 uint16_t dce_refclk_10khz; 918 uint16_t i2c_engine_refclk_10khz; 919 uint16_t dvi_ss_percentage; // in unit of 0.001% 920 uint16_t dvi_ss_rate_10hz; 921 uint16_t hdmi_ss_percentage; // in unit of 0.001% 922 uint16_t hdmi_ss_rate_10hz; 923 uint16_t dp_ss_percentage; // in unit of 0.001% 924 uint16_t dp_ss_rate_10hz; 925 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 926 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 927 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 928 uint8_t ss_reserved; 929 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 930 uint8_t reserved1[3]; 931 uint16_t dpphy_refclk_10khz; 932 uint16_t reserved2; 933 uint8_t dceip_min_ver; 934 uint8_t dceip_max_ver; 935 uint8_t max_disp_pipe_num; 936 uint8_t max_vbios_active_disp_pipe_num; 937 uint8_t max_ppll_num; 938 uint8_t max_disp_phy_num; 939 uint8_t max_aux_pairs; 940 uint8_t remotedisplayconfig; 941 uint8_t reserved3[8]; 942 }; 943 944 945 struct atom_display_controller_info_v4_2 946 { 947 struct atom_common_table_header table_header; 948 uint32_t display_caps; 949 uint32_t bootup_dispclk_10khz; 950 uint16_t dce_refclk_10khz; 951 uint16_t i2c_engine_refclk_10khz; 952 uint16_t dvi_ss_percentage; // in unit of 0.001% 953 uint16_t dvi_ss_rate_10hz; 954 uint16_t hdmi_ss_percentage; // in unit of 0.001% 955 uint16_t hdmi_ss_rate_10hz; 956 uint16_t dp_ss_percentage; // in unit of 0.001% 957 uint16_t dp_ss_rate_10hz; 958 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 959 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 960 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 961 uint8_t ss_reserved; 962 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 963 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 964 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 965 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 966 uint16_t dpphy_refclk_10khz; 967 uint16_t reserved2; 968 uint8_t dcnip_min_ver; 969 uint8_t dcnip_max_ver; 970 uint8_t max_disp_pipe_num; 971 uint8_t max_vbios_active_disp_pipe_num; 972 uint8_t max_ppll_num; 973 uint8_t max_disp_phy_num; 974 uint8_t max_aux_pairs; 975 uint8_t remotedisplayconfig; 976 uint8_t reserved3[8]; 977 }; 978 979 980 enum dce_info_caps_def 981 { 982 // only for VBIOS 983 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 984 // only for VBIOS 985 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 986 // only for VBIOS 987 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 988 989 }; 990 991 /* 992 *************************************************************************** 993 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 994 *************************************************************************** 995 */ 996 struct atom_ext_display_path 997 { 998 uint16_t device_tag; //A bit vector to show what devices are supported 999 uint16_t device_acpi_enum; //16bit device ACPI id. 1000 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 1001 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 1002 uint8_t hpdlut_index; //An index into external HPD pin LUT 1003 uint16_t ext_encoder_objid; //external encoder object id 1004 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 1005 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 1006 uint16_t caps; 1007 uint16_t reserved; 1008 }; 1009 1010 //usCaps 1011 enum ext_display_path_cap_def { 1012 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE = 0x0001, 1013 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN = 0x0002, 1014 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK = 0x007C, 1015 EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 = (0x01 << 2), //PI redriver chip 1016 EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT = (0x02 << 2), //TI retimer chip 1017 EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 = (0x03 << 2) //Parade DP->HDMI recoverter chip 1018 }; 1019 1020 struct atom_external_display_connection_info 1021 { 1022 struct atom_common_table_header table_header; 1023 uint8_t guid[16]; // a GUID is a 16 byte long string 1024 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 1025 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 1026 uint8_t stereopinid; // use for eDP panel 1027 uint8_t remotedisplayconfig; 1028 uint8_t edptolvdsrxid; 1029 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 1030 uint8_t reserved[3]; // for potential expansion 1031 }; 1032 1033 /* 1034 *************************************************************************** 1035 Data Table integratedsysteminfo structure 1036 *************************************************************************** 1037 */ 1038 1039 struct atom_camera_dphy_timing_param 1040 { 1041 uint8_t profile_id; // SENSOR_PROFILES 1042 uint32_t param; 1043 }; 1044 1045 struct atom_camera_dphy_elec_param 1046 { 1047 uint16_t param[3]; 1048 }; 1049 1050 struct atom_camera_module_info 1051 { 1052 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1053 uint8_t module_name[8]; 1054 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1055 }; 1056 1057 struct atom_camera_flashlight_info 1058 { 1059 uint8_t flashlight_id; // 0: Rear, 1: Front 1060 uint8_t name[8]; 1061 }; 1062 1063 struct atom_camera_data 1064 { 1065 uint32_t versionCode; 1066 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1067 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1068 struct atom_camera_dphy_elec_param dphy_param; 1069 uint32_t crc_val; // CRC 1070 }; 1071 1072 1073 struct atom_14nm_dpphy_dvihdmi_tuningset 1074 { 1075 uint32_t max_symclk_in10khz; 1076 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1077 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1078 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1079 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1080 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1081 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1082 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1083 }; 1084 1085 struct atom_14nm_dpphy_dp_setting{ 1086 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1087 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1088 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1089 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1090 }; 1091 1092 struct atom_14nm_dpphy_dp_tuningset{ 1093 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1094 uint8_t version; 1095 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1096 uint16_t reserved; 1097 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1098 }; 1099 1100 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1101 struct atom_common_table_header table_header; 1102 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1103 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1104 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1105 }; 1106 1107 struct atom_14nm_combphy_tmds_vs_set 1108 { 1109 uint8_t sym_clk; 1110 uint8_t dig_mode; 1111 uint8_t phy_sel; 1112 uint16_t common_mar_deemph_nom__margin_deemph_val; 1113 uint8_t common_seldeemph60__deemph_6db_4_val; 1114 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1115 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1116 uint8_t margin_deemph_lane0__deemph_sel_val; 1117 }; 1118 1119 struct atom_DCN_dpphy_dvihdmi_tuningset 1120 { 1121 uint32_t max_symclk_in10khz; 1122 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1123 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1124 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1125 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1126 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1127 uint8_t reserved1; 1128 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1129 uint8_t reserved2; 1130 }; 1131 1132 struct atom_DCN_dpphy_dp_setting{ 1133 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1134 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN) 1135 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE) 1136 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST) 1137 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL 1138 }; 1139 1140 struct atom_DCN_dpphy_dp_tuningset{ 1141 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1142 uint8_t version; 1143 uint16_t table_size; // size of atom_14nm_dpphy_dp_setting 1144 uint16_t reserved; 1145 struct atom_DCN_dpphy_dp_setting dptunings[10]; 1146 }; 1147 1148 struct atom_i2c_reg_info { 1149 uint8_t ucI2cRegIndex; 1150 uint8_t ucI2cRegVal; 1151 }; 1152 1153 struct atom_hdmi_retimer_redriver_set { 1154 uint8_t HdmiSlvAddr; 1155 uint8_t HdmiRegNum; 1156 uint8_t Hdmi6GRegNum; 1157 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1158 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1159 }; 1160 1161 struct atom_integrated_system_info_v1_11 1162 { 1163 struct atom_common_table_header table_header; 1164 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1165 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1166 uint32_t system_config; 1167 uint32_t cpucapinfo; 1168 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1169 uint16_t gpuclk_ss_type; 1170 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1171 uint16_t lvds_ss_rate_10hz; 1172 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1173 uint16_t hdmi_ss_rate_10hz; 1174 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1175 uint16_t dvi_ss_rate_10hz; 1176 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1177 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1178 uint16_t backlight_pwm_hz; // pwm frequency in hz 1179 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1180 uint8_t umachannelnumber; // number of memory channels 1181 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1182 uint8_t pwr_on_de_to_vary_bl; 1183 uint8_t pwr_down_vary_bloff_to_de; 1184 uint8_t pwr_down_de_to_digoff; 1185 uint8_t pwr_off_delay; 1186 uint8_t pwr_on_vary_bl_to_blon; 1187 uint8_t pwr_down_bloff_to_vary_bloff; 1188 uint8_t min_allowed_bl_level; 1189 uint8_t htc_hyst_limit; 1190 uint8_t htc_tmp_limit; 1191 uint8_t reserved1; 1192 uint8_t reserved2; 1193 struct atom_external_display_connection_info extdispconninfo; 1194 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1195 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1196 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1197 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1198 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1199 struct atom_camera_data camera_info; 1200 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1201 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1202 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1203 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1204 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1205 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1206 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1207 uint32_t reserved[66]; 1208 }; 1209 1210 struct atom_integrated_system_info_v1_12 1211 { 1212 struct atom_common_table_header table_header; 1213 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1214 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1215 uint32_t system_config; 1216 uint32_t cpucapinfo; 1217 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1218 uint16_t gpuclk_ss_type; 1219 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1220 uint16_t lvds_ss_rate_10hz; 1221 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1222 uint16_t hdmi_ss_rate_10hz; 1223 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1224 uint16_t dvi_ss_rate_10hz; 1225 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1226 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1227 uint16_t backlight_pwm_hz; // pwm frequency in hz 1228 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1229 uint8_t umachannelnumber; // number of memory channels 1230 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms // 1231 uint8_t pwr_on_de_to_vary_bl; 1232 uint8_t pwr_down_vary_bloff_to_de; 1233 uint8_t pwr_down_de_to_digoff; 1234 uint8_t pwr_off_delay; 1235 uint8_t pwr_on_vary_bl_to_blon; 1236 uint8_t pwr_down_bloff_to_vary_bloff; 1237 uint8_t min_allowed_bl_level; 1238 uint8_t htc_hyst_limit; 1239 uint8_t htc_tmp_limit; 1240 uint8_t reserved1; 1241 uint8_t reserved2; 1242 struct atom_external_display_connection_info extdispconninfo; 1243 struct atom_DCN_dpphy_dvihdmi_tuningset TMDS_tuningset; 1244 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK5_tuningset; 1245 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK8_tuningset; 1246 struct atom_DCN_dpphy_dp_tuningset rbr_tuningset; // rbr 1.62G dp tuning set 1247 struct atom_DCN_dpphy_dp_tuningset hbr3_tuningset; // HBR3 dp tuning set 1248 struct atom_camera_data camera_info; 1249 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1250 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1251 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1252 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1253 struct atom_DCN_dpphy_dp_tuningset hbr_tuningset; //hbr 2.7G dp tuning set 1254 struct atom_DCN_dpphy_dp_tuningset hbr2_tuningset; //hbr2 5.4G dp turnig set 1255 struct atom_DCN_dpphy_dp_tuningset edp_tunings; //edp tuning set 1256 struct atom_DCN_dpphy_dvihdmi_tuningset hdmiCLK6_tuningset; 1257 uint32_t reserved[63]; 1258 }; 1259 1260 // system_config 1261 enum atom_system_vbiosmisc_def{ 1262 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1263 }; 1264 1265 1266 // gpucapinfo 1267 enum atom_system_gpucapinf_def{ 1268 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1269 }; 1270 1271 //dpphy_override 1272 enum atom_sysinfo_dpphy_override_def{ 1273 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1274 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1275 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1276 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1277 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1278 }; 1279 1280 //lvds_misc 1281 enum atom_sys_info_lvds_misc_def 1282 { 1283 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1284 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1285 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1286 }; 1287 1288 1289 //memorytype DMI Type 17 offset 12h - Memory Type 1290 enum atom_dmi_t17_mem_type_def{ 1291 OtherMemType = 0x01, ///< Assign 01 to Other 1292 UnknownMemType, ///< Assign 02 to Unknown 1293 DramMemType, ///< Assign 03 to DRAM 1294 EdramMemType, ///< Assign 04 to EDRAM 1295 VramMemType, ///< Assign 05 to VRAM 1296 SramMemType, ///< Assign 06 to SRAM 1297 RamMemType, ///< Assign 07 to RAM 1298 RomMemType, ///< Assign 08 to ROM 1299 FlashMemType, ///< Assign 09 to Flash 1300 EepromMemType, ///< Assign 10 to EEPROM 1301 FepromMemType, ///< Assign 11 to FEPROM 1302 EpromMemType, ///< Assign 12 to EPROM 1303 CdramMemType, ///< Assign 13 to CDRAM 1304 ThreeDramMemType, ///< Assign 14 to 3DRAM 1305 SdramMemType, ///< Assign 15 to SDRAM 1306 SgramMemType, ///< Assign 16 to SGRAM 1307 RdramMemType, ///< Assign 17 to RDRAM 1308 DdrMemType, ///< Assign 18 to DDR 1309 Ddr2MemType, ///< Assign 19 to DDR2 1310 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1311 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1312 Fbd2MemType, ///< Assign 25 to FBD2 1313 Ddr4MemType, ///< Assign 26 to DDR4 1314 LpDdrMemType, ///< Assign 27 to LPDDR 1315 LpDdr2MemType, ///< Assign 28 to LPDDR2 1316 LpDdr3MemType, ///< Assign 29 to LPDDR3 1317 LpDdr4MemType, ///< Assign 30 to LPDDR4 1318 }; 1319 1320 1321 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1322 struct atom_fusion_system_info_v4 1323 { 1324 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1325 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1326 }; 1327 1328 1329 /* 1330 *************************************************************************** 1331 Data Table gfx_info structure 1332 *************************************************************************** 1333 */ 1334 1335 struct atom_gfx_info_v2_2 1336 { 1337 struct atom_common_table_header table_header; 1338 uint8_t gfxip_min_ver; 1339 uint8_t gfxip_max_ver; 1340 uint8_t max_shader_engines; 1341 uint8_t max_tile_pipes; 1342 uint8_t max_cu_per_sh; 1343 uint8_t max_sh_per_se; 1344 uint8_t max_backends_per_se; 1345 uint8_t max_texture_channel_caches; 1346 uint32_t regaddr_cp_dma_src_addr; 1347 uint32_t regaddr_cp_dma_src_addr_hi; 1348 uint32_t regaddr_cp_dma_dst_addr; 1349 uint32_t regaddr_cp_dma_dst_addr_hi; 1350 uint32_t regaddr_cp_dma_command; 1351 uint32_t regaddr_cp_status; 1352 uint32_t regaddr_rlc_gpu_clock_32; 1353 uint32_t rlc_gpu_timer_refclk; 1354 }; 1355 1356 struct atom_gfx_info_v2_3 { 1357 struct atom_common_table_header table_header; 1358 uint8_t gfxip_min_ver; 1359 uint8_t gfxip_max_ver; 1360 uint8_t max_shader_engines; 1361 uint8_t max_tile_pipes; 1362 uint8_t max_cu_per_sh; 1363 uint8_t max_sh_per_se; 1364 uint8_t max_backends_per_se; 1365 uint8_t max_texture_channel_caches; 1366 uint32_t regaddr_cp_dma_src_addr; 1367 uint32_t regaddr_cp_dma_src_addr_hi; 1368 uint32_t regaddr_cp_dma_dst_addr; 1369 uint32_t regaddr_cp_dma_dst_addr_hi; 1370 uint32_t regaddr_cp_dma_command; 1371 uint32_t regaddr_cp_status; 1372 uint32_t regaddr_rlc_gpu_clock_32; 1373 uint32_t rlc_gpu_timer_refclk; 1374 uint8_t active_cu_per_sh; 1375 uint8_t active_rb_per_se; 1376 uint16_t gcgoldenoffset; 1377 uint32_t rm21_sram_vmin_value; 1378 }; 1379 1380 struct atom_gfx_info_v2_4 1381 { 1382 struct atom_common_table_header table_header; 1383 uint8_t gfxip_min_ver; 1384 uint8_t gfxip_max_ver; 1385 uint8_t max_shader_engines; 1386 uint8_t reserved; 1387 uint8_t max_cu_per_sh; 1388 uint8_t max_sh_per_se; 1389 uint8_t max_backends_per_se; 1390 uint8_t max_texture_channel_caches; 1391 uint32_t regaddr_cp_dma_src_addr; 1392 uint32_t regaddr_cp_dma_src_addr_hi; 1393 uint32_t regaddr_cp_dma_dst_addr; 1394 uint32_t regaddr_cp_dma_dst_addr_hi; 1395 uint32_t regaddr_cp_dma_command; 1396 uint32_t regaddr_cp_status; 1397 uint32_t regaddr_rlc_gpu_clock_32; 1398 uint32_t rlc_gpu_timer_refclk; 1399 uint8_t active_cu_per_sh; 1400 uint8_t active_rb_per_se; 1401 uint16_t gcgoldenoffset; 1402 uint16_t gc_num_gprs; 1403 uint16_t gc_gsprim_buff_depth; 1404 uint16_t gc_parameter_cache_depth; 1405 uint16_t gc_wave_size; 1406 uint16_t gc_max_waves_per_simd; 1407 uint16_t gc_lds_size; 1408 uint8_t gc_num_max_gs_thds; 1409 uint8_t gc_gs_table_depth; 1410 uint8_t gc_double_offchip_lds_buffer; 1411 uint8_t gc_max_scratch_slots_per_cu; 1412 uint32_t sram_rm_fuses_val; 1413 uint32_t sram_custom_rm_fuses_val; 1414 }; 1415 1416 /* 1417 *************************************************************************** 1418 Data Table smu_info structure 1419 *************************************************************************** 1420 */ 1421 struct atom_smu_info_v3_1 1422 { 1423 struct atom_common_table_header table_header; 1424 uint8_t smuip_min_ver; 1425 uint8_t smuip_max_ver; 1426 uint8_t smu_rsd1; 1427 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1428 uint16_t sclk_ss_percentage; 1429 uint16_t sclk_ss_rate_10hz; 1430 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1431 uint16_t gpuclk_ss_rate_10hz; 1432 uint32_t core_refclk_10khz; 1433 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1434 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1435 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1436 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1437 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1438 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1439 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1440 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1441 }; 1442 1443 struct atom_smu_info_v3_2 { 1444 struct atom_common_table_header table_header; 1445 uint8_t smuip_min_ver; 1446 uint8_t smuip_max_ver; 1447 uint8_t smu_rsd1; 1448 uint8_t gpuclk_ss_mode; 1449 uint16_t sclk_ss_percentage; 1450 uint16_t sclk_ss_rate_10hz; 1451 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1452 uint16_t gpuclk_ss_rate_10hz; 1453 uint32_t core_refclk_10khz; 1454 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1455 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1456 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1457 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1458 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1459 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1460 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1461 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1462 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1463 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1464 uint16_t smugoldenoffset; 1465 uint32_t gpupll_vco_freq_10khz; 1466 uint32_t bootup_smnclk_10khz; 1467 uint32_t bootup_socclk_10khz; 1468 uint32_t bootup_mp0clk_10khz; 1469 uint32_t bootup_mp1clk_10khz; 1470 uint32_t bootup_lclk_10khz; 1471 uint32_t bootup_dcefclk_10khz; 1472 uint32_t ctf_threshold_override_value; 1473 uint32_t reserved[5]; 1474 }; 1475 1476 struct atom_smu_info_v3_3 { 1477 struct atom_common_table_header table_header; 1478 uint8_t smuip_min_ver; 1479 uint8_t smuip_max_ver; 1480 uint8_t waflclk_ss_mode; 1481 uint8_t gpuclk_ss_mode; 1482 uint16_t sclk_ss_percentage; 1483 uint16_t sclk_ss_rate_10hz; 1484 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1485 uint16_t gpuclk_ss_rate_10hz; 1486 uint32_t core_refclk_10khz; 1487 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1488 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1489 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1490 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1491 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1492 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1493 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1494 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1495 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1496 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1497 uint16_t smugoldenoffset; 1498 uint32_t gpupll_vco_freq_10khz; 1499 uint32_t bootup_smnclk_10khz; 1500 uint32_t bootup_socclk_10khz; 1501 uint32_t bootup_mp0clk_10khz; 1502 uint32_t bootup_mp1clk_10khz; 1503 uint32_t bootup_lclk_10khz; 1504 uint32_t bootup_dcefclk_10khz; 1505 uint32_t ctf_threshold_override_value; 1506 uint32_t syspll3_0_vco_freq_10khz; 1507 uint32_t syspll3_1_vco_freq_10khz; 1508 uint32_t bootup_fclk_10khz; 1509 uint32_t bootup_waflclk_10khz; 1510 uint32_t smu_info_caps; 1511 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1512 uint16_t smuinitoffset; 1513 uint32_t reserved; 1514 }; 1515 1516 /* 1517 *************************************************************************** 1518 Data Table smc_dpm_info structure 1519 *************************************************************************** 1520 */ 1521 struct atom_smc_dpm_info_v4_1 1522 { 1523 struct atom_common_table_header table_header; 1524 uint8_t liquid1_i2c_address; 1525 uint8_t liquid2_i2c_address; 1526 uint8_t vr_i2c_address; 1527 uint8_t plx_i2c_address; 1528 1529 uint8_t liquid_i2c_linescl; 1530 uint8_t liquid_i2c_linesda; 1531 uint8_t vr_i2c_linescl; 1532 uint8_t vr_i2c_linesda; 1533 1534 uint8_t plx_i2c_linescl; 1535 uint8_t plx_i2c_linesda; 1536 uint8_t vrsensorpresent; 1537 uint8_t liquidsensorpresent; 1538 1539 uint16_t maxvoltagestepgfx; 1540 uint16_t maxvoltagestepsoc; 1541 1542 uint8_t vddgfxvrmapping; 1543 uint8_t vddsocvrmapping; 1544 uint8_t vddmem0vrmapping; 1545 uint8_t vddmem1vrmapping; 1546 1547 uint8_t gfxulvphasesheddingmask; 1548 uint8_t soculvphasesheddingmask; 1549 uint8_t padding8_v[2]; 1550 1551 uint16_t gfxmaxcurrent; 1552 uint8_t gfxoffset; 1553 uint8_t padding_telemetrygfx; 1554 1555 uint16_t socmaxcurrent; 1556 uint8_t socoffset; 1557 uint8_t padding_telemetrysoc; 1558 1559 uint16_t mem0maxcurrent; 1560 uint8_t mem0offset; 1561 uint8_t padding_telemetrymem0; 1562 1563 uint16_t mem1maxcurrent; 1564 uint8_t mem1offset; 1565 uint8_t padding_telemetrymem1; 1566 1567 uint8_t acdcgpio; 1568 uint8_t acdcpolarity; 1569 uint8_t vr0hotgpio; 1570 uint8_t vr0hotpolarity; 1571 1572 uint8_t vr1hotgpio; 1573 uint8_t vr1hotpolarity; 1574 uint8_t padding1; 1575 uint8_t padding2; 1576 1577 uint8_t ledpin0; 1578 uint8_t ledpin1; 1579 uint8_t ledpin2; 1580 uint8_t padding8_4; 1581 1582 uint8_t pllgfxclkspreadenabled; 1583 uint8_t pllgfxclkspreadpercent; 1584 uint16_t pllgfxclkspreadfreq; 1585 1586 uint8_t uclkspreadenabled; 1587 uint8_t uclkspreadpercent; 1588 uint16_t uclkspreadfreq; 1589 1590 uint8_t socclkspreadenabled; 1591 uint8_t socclkspreadpercent; 1592 uint16_t socclkspreadfreq; 1593 1594 uint8_t acggfxclkspreadenabled; 1595 uint8_t acggfxclkspreadpercent; 1596 uint16_t acggfxclkspreadfreq; 1597 1598 uint8_t Vr2_I2C_address; 1599 uint8_t padding_vr2[3]; 1600 1601 uint32_t boardreserved[9]; 1602 }; 1603 1604 /* 1605 *************************************************************************** 1606 Data Table smc_dpm_info structure 1607 *************************************************************************** 1608 */ 1609 struct atom_smc_dpm_info_v4_3 1610 { 1611 struct atom_common_table_header table_header; 1612 uint8_t liquid1_i2c_address; 1613 uint8_t liquid2_i2c_address; 1614 uint8_t vr_i2c_address; 1615 uint8_t plx_i2c_address; 1616 1617 uint8_t liquid_i2c_linescl; 1618 uint8_t liquid_i2c_linesda; 1619 uint8_t vr_i2c_linescl; 1620 uint8_t vr_i2c_linesda; 1621 1622 uint8_t plx_i2c_linescl; 1623 uint8_t plx_i2c_linesda; 1624 uint8_t vrsensorpresent; 1625 uint8_t liquidsensorpresent; 1626 1627 uint16_t maxvoltagestepgfx; 1628 uint16_t maxvoltagestepsoc; 1629 1630 uint8_t vddgfxvrmapping; 1631 uint8_t vddsocvrmapping; 1632 uint8_t vddmem0vrmapping; 1633 uint8_t vddmem1vrmapping; 1634 1635 uint8_t gfxulvphasesheddingmask; 1636 uint8_t soculvphasesheddingmask; 1637 uint8_t externalsensorpresent; 1638 uint8_t padding8_v; 1639 1640 uint16_t gfxmaxcurrent; 1641 uint8_t gfxoffset; 1642 uint8_t padding_telemetrygfx; 1643 1644 uint16_t socmaxcurrent; 1645 uint8_t socoffset; 1646 uint8_t padding_telemetrysoc; 1647 1648 uint16_t mem0maxcurrent; 1649 uint8_t mem0offset; 1650 uint8_t padding_telemetrymem0; 1651 1652 uint16_t mem1maxcurrent; 1653 uint8_t mem1offset; 1654 uint8_t padding_telemetrymem1; 1655 1656 uint8_t acdcgpio; 1657 uint8_t acdcpolarity; 1658 uint8_t vr0hotgpio; 1659 uint8_t vr0hotpolarity; 1660 1661 uint8_t vr1hotgpio; 1662 uint8_t vr1hotpolarity; 1663 uint8_t padding1; 1664 uint8_t padding2; 1665 1666 uint8_t ledpin0; 1667 uint8_t ledpin1; 1668 uint8_t ledpin2; 1669 uint8_t padding8_4; 1670 1671 uint8_t pllgfxclkspreadenabled; 1672 uint8_t pllgfxclkspreadpercent; 1673 uint16_t pllgfxclkspreadfreq; 1674 1675 uint8_t uclkspreadenabled; 1676 uint8_t uclkspreadpercent; 1677 uint16_t uclkspreadfreq; 1678 1679 uint8_t fclkspreadenabled; 1680 uint8_t fclkspreadpercent; 1681 uint16_t fclkspreadfreq; 1682 1683 uint8_t fllgfxclkspreadenabled; 1684 uint8_t fllgfxclkspreadpercent; 1685 uint16_t fllgfxclkspreadfreq; 1686 1687 uint32_t boardreserved[10]; 1688 }; 1689 1690 struct smudpm_i2ccontrollerconfig_t { 1691 uint32_t enabled; 1692 uint32_t slaveaddress; 1693 uint32_t controllerport; 1694 uint32_t controllername; 1695 uint32_t thermalthrottler; 1696 uint32_t i2cprotocol; 1697 uint32_t i2cspeed; 1698 }; 1699 1700 struct atom_smc_dpm_info_v4_4 1701 { 1702 struct atom_common_table_header table_header; 1703 uint32_t i2c_padding[3]; 1704 1705 uint16_t maxvoltagestepgfx; 1706 uint16_t maxvoltagestepsoc; 1707 1708 uint8_t vddgfxvrmapping; 1709 uint8_t vddsocvrmapping; 1710 uint8_t vddmem0vrmapping; 1711 uint8_t vddmem1vrmapping; 1712 1713 uint8_t gfxulvphasesheddingmask; 1714 uint8_t soculvphasesheddingmask; 1715 uint8_t externalsensorpresent; 1716 uint8_t padding8_v; 1717 1718 uint16_t gfxmaxcurrent; 1719 uint8_t gfxoffset; 1720 uint8_t padding_telemetrygfx; 1721 1722 uint16_t socmaxcurrent; 1723 uint8_t socoffset; 1724 uint8_t padding_telemetrysoc; 1725 1726 uint16_t mem0maxcurrent; 1727 uint8_t mem0offset; 1728 uint8_t padding_telemetrymem0; 1729 1730 uint16_t mem1maxcurrent; 1731 uint8_t mem1offset; 1732 uint8_t padding_telemetrymem1; 1733 1734 1735 uint8_t acdcgpio; 1736 uint8_t acdcpolarity; 1737 uint8_t vr0hotgpio; 1738 uint8_t vr0hotpolarity; 1739 1740 uint8_t vr1hotgpio; 1741 uint8_t vr1hotpolarity; 1742 uint8_t padding1; 1743 uint8_t padding2; 1744 1745 1746 uint8_t ledpin0; 1747 uint8_t ledpin1; 1748 uint8_t ledpin2; 1749 uint8_t padding8_4; 1750 1751 1752 uint8_t pllgfxclkspreadenabled; 1753 uint8_t pllgfxclkspreadpercent; 1754 uint16_t pllgfxclkspreadfreq; 1755 1756 1757 uint8_t uclkspreadenabled; 1758 uint8_t uclkspreadpercent; 1759 uint16_t uclkspreadfreq; 1760 1761 1762 uint8_t fclkspreadenabled; 1763 uint8_t fclkspreadpercent; 1764 uint16_t fclkspreadfreq; 1765 1766 1767 uint8_t fllgfxclkspreadenabled; 1768 uint8_t fllgfxclkspreadpercent; 1769 uint16_t fllgfxclkspreadfreq; 1770 1771 1772 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1773 1774 1775 uint32_t boardreserved[10]; 1776 }; 1777 1778 enum smudpm_v4_5_i2ccontrollername_e{ 1779 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1780 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1781 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1782 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1783 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1784 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1785 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1786 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1787 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1788 }; 1789 1790 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1791 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1792 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1793 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1794 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1795 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1796 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1797 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1798 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1799 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1800 }; 1801 1802 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 1803 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 1804 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 1805 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 1806 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 1807 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 1808 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 1809 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 1810 }; 1811 1812 struct smudpm_i2c_controller_config_v2 1813 { 1814 uint8_t Enabled; 1815 uint8_t Speed; 1816 uint8_t Padding[2]; 1817 uint32_t SlaveAddress; 1818 uint8_t ControllerPort; 1819 uint8_t ControllerName; 1820 uint8_t ThermalThrotter; 1821 uint8_t I2cProtocol; 1822 }; 1823 1824 struct atom_smc_dpm_info_v4_5 1825 { 1826 struct atom_common_table_header table_header; 1827 // SECTION: BOARD PARAMETERS 1828 // I2C Control 1829 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 1830 1831 // SVI2 Board Parameters 1832 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1833 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1834 1835 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1836 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1837 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1838 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1839 1840 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1841 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1842 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 1843 uint8_t Padding8_V; 1844 1845 // Telemetry Settings 1846 uint16_t GfxMaxCurrent; // in Amps 1847 uint8_t GfxOffset; // in Amps 1848 uint8_t Padding_TelemetryGfx; 1849 uint16_t SocMaxCurrent; // in Amps 1850 uint8_t SocOffset; // in Amps 1851 uint8_t Padding_TelemetrySoc; 1852 1853 uint16_t Mem0MaxCurrent; // in Amps 1854 uint8_t Mem0Offset; // in Amps 1855 uint8_t Padding_TelemetryMem0; 1856 1857 uint16_t Mem1MaxCurrent; // in Amps 1858 uint8_t Mem1Offset; // in Amps 1859 uint8_t Padding_TelemetryMem1; 1860 1861 // GPIO Settings 1862 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1863 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1864 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1865 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1866 1867 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1868 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1869 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1870 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1871 1872 // LED Display Settings 1873 uint8_t LedPin0; // GPIO number for LedPin[0] 1874 uint8_t LedPin1; // GPIO number for LedPin[1] 1875 uint8_t LedPin2; // GPIO number for LedPin[2] 1876 uint8_t padding8_4; 1877 1878 // GFXCLK PLL Spread Spectrum 1879 uint8_t PllGfxclkSpreadEnabled; // on or off 1880 uint8_t PllGfxclkSpreadPercent; // Q4.4 1881 uint16_t PllGfxclkSpreadFreq; // kHz 1882 1883 // GFXCLK DFLL Spread Spectrum 1884 uint8_t DfllGfxclkSpreadEnabled; // on or off 1885 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1886 uint16_t DfllGfxclkSpreadFreq; // kHz 1887 1888 // UCLK Spread Spectrum 1889 uint8_t UclkSpreadEnabled; // on or off 1890 uint8_t UclkSpreadPercent; // Q4.4 1891 uint16_t UclkSpreadFreq; // kHz 1892 1893 // SOCCLK Spread Spectrum 1894 uint8_t SoclkSpreadEnabled; // on or off 1895 uint8_t SocclkSpreadPercent; // Q4.4 1896 uint16_t SocclkSpreadFreq; // kHz 1897 1898 // Total board power 1899 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1900 uint16_t BoardPadding; 1901 1902 // Mvdd Svi2 Div Ratio Setting 1903 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 1904 1905 uint32_t BoardReserved[9]; 1906 1907 }; 1908 1909 struct atom_smc_dpm_info_v4_6 1910 { 1911 struct atom_common_table_header table_header; 1912 // section: board parameters 1913 uint32_t i2c_padding[3]; // old i2c control are moved to new area 1914 1915 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1916 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1917 1918 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 1919 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 1920 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 1921 uint8_t boardvrmapping; // use vr_mapping* bitfields 1922 1923 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 1924 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 1925 uint8_t padding8_v[2]; 1926 1927 // telemetry settings 1928 uint16_t gfxmaxcurrent; // in amps 1929 uint8_t gfxoffset; // in amps 1930 uint8_t padding_telemetrygfx; 1931 1932 uint16_t socmaxcurrent; // in amps 1933 uint8_t socoffset; // in amps 1934 uint8_t padding_telemetrysoc; 1935 1936 uint16_t memmaxcurrent; // in amps 1937 uint8_t memoffset; // in amps 1938 uint8_t padding_telemetrymem; 1939 1940 uint16_t boardmaxcurrent; // in amps 1941 uint8_t boardoffset; // in amps 1942 uint8_t padding_telemetryboardinput; 1943 1944 // gpio settings 1945 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 1946 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 1947 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 1948 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 1949 1950 // gfxclk pll spread spectrum 1951 uint8_t pllgfxclkspreadenabled; // on or off 1952 uint8_t pllgfxclkspreadpercent; // q4.4 1953 uint16_t pllgfxclkspreadfreq; // khz 1954 1955 // uclk spread spectrum 1956 uint8_t uclkspreadenabled; // on or off 1957 uint8_t uclkspreadpercent; // q4.4 1958 uint16_t uclkspreadfreq; // khz 1959 1960 // fclk spread spectrum 1961 uint8_t fclkspreadenabled; // on or off 1962 uint8_t fclkspreadpercent; // q4.4 1963 uint16_t fclkspreadfreq; // khz 1964 1965 1966 // gfxclk fll spread spectrum 1967 uint8_t fllgfxclkspreadenabled; // on or off 1968 uint8_t fllgfxclkspreadpercent; // q4.4 1969 uint16_t fllgfxclkspreadfreq; // khz 1970 1971 // i2c controller structure 1972 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 1973 1974 // memory section 1975 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 1976 1977 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 1978 uint8_t paddingmem[3]; 1979 1980 // total board power 1981 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 1982 uint16_t boardpadding; 1983 1984 // section: xgmi training 1985 uint8_t xgmilinkspeed[4]; 1986 uint8_t xgmilinkwidth[4]; 1987 1988 uint16_t xgmifclkfreq[4]; 1989 uint16_t xgmisocvoltage[4]; 1990 1991 // reserved 1992 uint32_t boardreserved[10]; 1993 }; 1994 1995 struct atom_smc_dpm_info_v4_7 1996 { 1997 struct atom_common_table_header table_header; 1998 // SECTION: BOARD PARAMETERS 1999 // I2C Control 2000 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 2001 2002 // SVI2 Board Parameters 2003 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2004 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 2005 2006 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2007 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2008 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2009 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2010 2011 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2012 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2013 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 2014 uint8_t Padding8_V; 2015 2016 // Telemetry Settings 2017 uint16_t GfxMaxCurrent; // in Amps 2018 uint8_t GfxOffset; // in Amps 2019 uint8_t Padding_TelemetryGfx; 2020 uint16_t SocMaxCurrent; // in Amps 2021 uint8_t SocOffset; // in Amps 2022 uint8_t Padding_TelemetrySoc; 2023 2024 uint16_t Mem0MaxCurrent; // in Amps 2025 uint8_t Mem0Offset; // in Amps 2026 uint8_t Padding_TelemetryMem0; 2027 2028 uint16_t Mem1MaxCurrent; // in Amps 2029 uint8_t Mem1Offset; // in Amps 2030 uint8_t Padding_TelemetryMem1; 2031 2032 // GPIO Settings 2033 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2034 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2035 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2036 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2037 2038 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2039 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2040 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2041 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2042 2043 // LED Display Settings 2044 uint8_t LedPin0; // GPIO number for LedPin[0] 2045 uint8_t LedPin1; // GPIO number for LedPin[1] 2046 uint8_t LedPin2; // GPIO number for LedPin[2] 2047 uint8_t padding8_4; 2048 2049 // GFXCLK PLL Spread Spectrum 2050 uint8_t PllGfxclkSpreadEnabled; // on or off 2051 uint8_t PllGfxclkSpreadPercent; // Q4.4 2052 uint16_t PllGfxclkSpreadFreq; // kHz 2053 2054 // GFXCLK DFLL Spread Spectrum 2055 uint8_t DfllGfxclkSpreadEnabled; // on or off 2056 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2057 uint16_t DfllGfxclkSpreadFreq; // kHz 2058 2059 // UCLK Spread Spectrum 2060 uint8_t UclkSpreadEnabled; // on or off 2061 uint8_t UclkSpreadPercent; // Q4.4 2062 uint16_t UclkSpreadFreq; // kHz 2063 2064 // SOCCLK Spread Spectrum 2065 uint8_t SoclkSpreadEnabled; // on or off 2066 uint8_t SocclkSpreadPercent; // Q4.4 2067 uint16_t SocclkSpreadFreq; // kHz 2068 2069 // Total board power 2070 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2071 uint16_t BoardPadding; 2072 2073 // Mvdd Svi2 Div Ratio Setting 2074 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 2075 2076 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence 2077 uint8_t GpioI2cScl; // Serial Clock 2078 uint8_t GpioI2cSda; // Serial Data 2079 uint16_t GpioPadding; 2080 2081 // Additional LED Display Settings 2082 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed 2083 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status 2084 uint16_t LedEnableMask; 2085 2086 // Power Limit Scalars 2087 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT] 2088 2089 uint8_t MvddUlvPhaseSheddingMask; 2090 uint8_t VddciUlvPhaseSheddingMask; 2091 uint8_t Padding8_Psi1; 2092 uint8_t Padding8_Psi2; 2093 2094 uint32_t BoardReserved[5]; 2095 }; 2096 2097 struct smudpm_i2c_controller_config_v3 2098 { 2099 uint8_t Enabled; 2100 uint8_t Speed; 2101 uint8_t SlaveAddress; 2102 uint8_t ControllerPort; 2103 uint8_t ControllerName; 2104 uint8_t ThermalThrotter; 2105 uint8_t I2cProtocol; 2106 uint8_t PaddingConfig; 2107 }; 2108 2109 struct atom_smc_dpm_info_v4_9 2110 { 2111 struct atom_common_table_header table_header; 2112 2113 //SECTION: Gaming Clocks 2114 //uint32_t GamingClk[6]; 2115 2116 // SECTION: I2C Control 2117 struct smudpm_i2c_controller_config_v3 I2cControllers[16]; 2118 2119 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1 2120 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1 2121 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off 2122 uint8_t I2cSpare; 2123 2124 // SECTION: SVI2 Board Parameters 2125 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 2126 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 2127 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 2128 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 2129 2130 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2131 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2132 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2133 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 2134 2135 // SECTION: Telemetry Settings 2136 uint16_t GfxMaxCurrent; // in Amps 2137 uint8_t GfxOffset; // in Amps 2138 uint8_t Padding_TelemetryGfx; 2139 2140 uint16_t SocMaxCurrent; // in Amps 2141 uint8_t SocOffset; // in Amps 2142 uint8_t Padding_TelemetrySoc; 2143 2144 uint16_t Mem0MaxCurrent; // in Amps 2145 uint8_t Mem0Offset; // in Amps 2146 uint8_t Padding_TelemetryMem0; 2147 2148 uint16_t Mem1MaxCurrent; // in Amps 2149 uint8_t Mem1Offset; // in Amps 2150 uint8_t Padding_TelemetryMem1; 2151 2152 uint32_t MvddRatio; // This is used for MVDD Svi2 Div Ratio workaround. It has 16 fractional bits (Q16.16) 2153 2154 // SECTION: GPIO Settings 2155 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 2156 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 2157 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 2158 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 2159 2160 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 2161 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 2162 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 2163 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 2164 2165 // LED Display Settings 2166 uint8_t LedPin0; // GPIO number for LedPin[0] 2167 uint8_t LedPin1; // GPIO number for LedPin[1] 2168 uint8_t LedPin2; // GPIO number for LedPin[2] 2169 uint8_t LedEnableMask; 2170 2171 uint8_t LedPcie; // GPIO number for PCIE results 2172 uint8_t LedError; // GPIO number for Error Cases 2173 uint8_t LedSpare1[2]; 2174 2175 // SECTION: Clock Spread Spectrum 2176 2177 // GFXCLK PLL Spread Spectrum 2178 uint8_t PllGfxclkSpreadEnabled; // on or off 2179 uint8_t PllGfxclkSpreadPercent; // Q4.4 2180 uint16_t PllGfxclkSpreadFreq; // kHz 2181 2182 // GFXCLK DFLL Spread Spectrum 2183 uint8_t DfllGfxclkSpreadEnabled; // on or off 2184 uint8_t DfllGfxclkSpreadPercent; // Q4.4 2185 uint16_t DfllGfxclkSpreadFreq; // kHz 2186 2187 // UCLK Spread Spectrum 2188 uint8_t UclkSpreadEnabled; // on or off 2189 uint8_t UclkSpreadPercent; // Q4.4 2190 uint16_t UclkSpreadFreq; // kHz 2191 2192 // FCLK Spread Spectrum 2193 uint8_t FclkSpreadEnabled; // on or off 2194 uint8_t FclkSpreadPercent; // Q4.4 2195 uint16_t FclkSpreadFreq; // kHz 2196 2197 // Section: Memory Config 2198 uint32_t MemoryChannelEnabled; // For DRAM use only, Max 32 channels enabled bit mask. 2199 2200 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines 2201 uint8_t PaddingMem1[3]; 2202 2203 // Section: Total Board Power 2204 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 2205 uint16_t BoardPowerPadding; 2206 2207 // SECTION: XGMI Training 2208 uint8_t XgmiLinkSpeed [4]; 2209 uint8_t XgmiLinkWidth [4]; 2210 2211 uint16_t XgmiFclkFreq [4]; 2212 uint16_t XgmiSocVoltage [4]; 2213 2214 // SECTION: Board Reserved 2215 2216 uint32_t BoardReserved[16]; 2217 2218 }; 2219 2220 /* 2221 *************************************************************************** 2222 Data Table asic_profiling_info structure 2223 *************************************************************************** 2224 */ 2225 struct atom_asic_profiling_info_v4_1 2226 { 2227 struct atom_common_table_header table_header; 2228 uint32_t maxvddc; 2229 uint32_t minvddc; 2230 uint32_t avfs_meannsigma_acontant0; 2231 uint32_t avfs_meannsigma_acontant1; 2232 uint32_t avfs_meannsigma_acontant2; 2233 uint16_t avfs_meannsigma_dc_tol_sigma; 2234 uint16_t avfs_meannsigma_platform_mean; 2235 uint16_t avfs_meannsigma_platform_sigma; 2236 uint32_t gb_vdroop_table_cksoff_a0; 2237 uint32_t gb_vdroop_table_cksoff_a1; 2238 uint32_t gb_vdroop_table_cksoff_a2; 2239 uint32_t gb_vdroop_table_ckson_a0; 2240 uint32_t gb_vdroop_table_ckson_a1; 2241 uint32_t gb_vdroop_table_ckson_a2; 2242 uint32_t avfsgb_fuse_table_cksoff_m1; 2243 uint32_t avfsgb_fuse_table_cksoff_m2; 2244 uint32_t avfsgb_fuse_table_cksoff_b; 2245 uint32_t avfsgb_fuse_table_ckson_m1; 2246 uint32_t avfsgb_fuse_table_ckson_m2; 2247 uint32_t avfsgb_fuse_table_ckson_b; 2248 uint16_t max_voltage_0_25mv; 2249 uint8_t enable_gb_vdroop_table_cksoff; 2250 uint8_t enable_gb_vdroop_table_ckson; 2251 uint8_t enable_gb_fuse_table_cksoff; 2252 uint8_t enable_gb_fuse_table_ckson; 2253 uint16_t psm_age_comfactor; 2254 uint8_t enable_apply_avfs_cksoff_voltage; 2255 uint8_t reserved; 2256 uint32_t dispclk2gfxclk_a; 2257 uint32_t dispclk2gfxclk_b; 2258 uint32_t dispclk2gfxclk_c; 2259 uint32_t pixclk2gfxclk_a; 2260 uint32_t pixclk2gfxclk_b; 2261 uint32_t pixclk2gfxclk_c; 2262 uint32_t dcefclk2gfxclk_a; 2263 uint32_t dcefclk2gfxclk_b; 2264 uint32_t dcefclk2gfxclk_c; 2265 uint32_t phyclk2gfxclk_a; 2266 uint32_t phyclk2gfxclk_b; 2267 uint32_t phyclk2gfxclk_c; 2268 }; 2269 2270 struct atom_asic_profiling_info_v4_2 { 2271 struct atom_common_table_header table_header; 2272 uint32_t maxvddc; 2273 uint32_t minvddc; 2274 uint32_t avfs_meannsigma_acontant0; 2275 uint32_t avfs_meannsigma_acontant1; 2276 uint32_t avfs_meannsigma_acontant2; 2277 uint16_t avfs_meannsigma_dc_tol_sigma; 2278 uint16_t avfs_meannsigma_platform_mean; 2279 uint16_t avfs_meannsigma_platform_sigma; 2280 uint32_t gb_vdroop_table_cksoff_a0; 2281 uint32_t gb_vdroop_table_cksoff_a1; 2282 uint32_t gb_vdroop_table_cksoff_a2; 2283 uint32_t gb_vdroop_table_ckson_a0; 2284 uint32_t gb_vdroop_table_ckson_a1; 2285 uint32_t gb_vdroop_table_ckson_a2; 2286 uint32_t avfsgb_fuse_table_cksoff_m1; 2287 uint32_t avfsgb_fuse_table_cksoff_m2; 2288 uint32_t avfsgb_fuse_table_cksoff_b; 2289 uint32_t avfsgb_fuse_table_ckson_m1; 2290 uint32_t avfsgb_fuse_table_ckson_m2; 2291 uint32_t avfsgb_fuse_table_ckson_b; 2292 uint16_t max_voltage_0_25mv; 2293 uint8_t enable_gb_vdroop_table_cksoff; 2294 uint8_t enable_gb_vdroop_table_ckson; 2295 uint8_t enable_gb_fuse_table_cksoff; 2296 uint8_t enable_gb_fuse_table_ckson; 2297 uint16_t psm_age_comfactor; 2298 uint8_t enable_apply_avfs_cksoff_voltage; 2299 uint8_t reserved; 2300 uint32_t dispclk2gfxclk_a; 2301 uint32_t dispclk2gfxclk_b; 2302 uint32_t dispclk2gfxclk_c; 2303 uint32_t pixclk2gfxclk_a; 2304 uint32_t pixclk2gfxclk_b; 2305 uint32_t pixclk2gfxclk_c; 2306 uint32_t dcefclk2gfxclk_a; 2307 uint32_t dcefclk2gfxclk_b; 2308 uint32_t dcefclk2gfxclk_c; 2309 uint32_t phyclk2gfxclk_a; 2310 uint32_t phyclk2gfxclk_b; 2311 uint32_t phyclk2gfxclk_c; 2312 uint32_t acg_gb_vdroop_table_a0; 2313 uint32_t acg_gb_vdroop_table_a1; 2314 uint32_t acg_gb_vdroop_table_a2; 2315 uint32_t acg_avfsgb_fuse_table_m1; 2316 uint32_t acg_avfsgb_fuse_table_m2; 2317 uint32_t acg_avfsgb_fuse_table_b; 2318 uint8_t enable_acg_gb_vdroop_table; 2319 uint8_t enable_acg_gb_fuse_table; 2320 uint32_t acg_dispclk2gfxclk_a; 2321 uint32_t acg_dispclk2gfxclk_b; 2322 uint32_t acg_dispclk2gfxclk_c; 2323 uint32_t acg_pixclk2gfxclk_a; 2324 uint32_t acg_pixclk2gfxclk_b; 2325 uint32_t acg_pixclk2gfxclk_c; 2326 uint32_t acg_dcefclk2gfxclk_a; 2327 uint32_t acg_dcefclk2gfxclk_b; 2328 uint32_t acg_dcefclk2gfxclk_c; 2329 uint32_t acg_phyclk2gfxclk_a; 2330 uint32_t acg_phyclk2gfxclk_b; 2331 uint32_t acg_phyclk2gfxclk_c; 2332 }; 2333 2334 /* 2335 *************************************************************************** 2336 Data Table multimedia_info structure 2337 *************************************************************************** 2338 */ 2339 struct atom_multimedia_info_v2_1 2340 { 2341 struct atom_common_table_header table_header; 2342 uint8_t uvdip_min_ver; 2343 uint8_t uvdip_max_ver; 2344 uint8_t vceip_min_ver; 2345 uint8_t vceip_max_ver; 2346 uint16_t uvd_enc_max_input_width_pixels; 2347 uint16_t uvd_enc_max_input_height_pixels; 2348 uint16_t vce_enc_max_input_width_pixels; 2349 uint16_t vce_enc_max_input_height_pixels; 2350 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2351 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2352 }; 2353 2354 2355 /* 2356 *************************************************************************** 2357 Data Table umc_info structure 2358 *************************************************************************** 2359 */ 2360 struct atom_umc_info_v3_1 2361 { 2362 struct atom_common_table_header table_header; 2363 uint32_t ucode_version; 2364 uint32_t ucode_rom_startaddr; 2365 uint32_t ucode_length; 2366 uint16_t umc_reg_init_offset; 2367 uint16_t customer_ucode_name_offset; 2368 uint16_t mclk_ss_percentage; 2369 uint16_t mclk_ss_rate_10hz; 2370 uint8_t umcip_min_ver; 2371 uint8_t umcip_max_ver; 2372 uint8_t vram_type; //enum of atom_dgpu_vram_type 2373 uint8_t umc_config; 2374 uint32_t mem_refclk_10khz; 2375 }; 2376 2377 // umc_info.umc_config 2378 enum atom_umc_config_def { 2379 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2380 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2381 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2382 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2383 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2384 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2385 }; 2386 2387 struct atom_umc_info_v3_2 2388 { 2389 struct atom_common_table_header table_header; 2390 uint32_t ucode_version; 2391 uint32_t ucode_rom_startaddr; 2392 uint32_t ucode_length; 2393 uint16_t umc_reg_init_offset; 2394 uint16_t customer_ucode_name_offset; 2395 uint16_t mclk_ss_percentage; 2396 uint16_t mclk_ss_rate_10hz; 2397 uint8_t umcip_min_ver; 2398 uint8_t umcip_max_ver; 2399 uint8_t vram_type; //enum of atom_dgpu_vram_type 2400 uint8_t umc_config; 2401 uint32_t mem_refclk_10khz; 2402 uint32_t pstate_uclk_10khz[4]; 2403 uint16_t umcgoldenoffset; 2404 uint16_t densitygoldenoffset; 2405 }; 2406 2407 struct atom_umc_info_v3_3 2408 { 2409 struct atom_common_table_header table_header; 2410 uint32_t ucode_reserved; 2411 uint32_t ucode_rom_startaddr; 2412 uint32_t ucode_length; 2413 uint16_t umc_reg_init_offset; 2414 uint16_t customer_ucode_name_offset; 2415 uint16_t mclk_ss_percentage; 2416 uint16_t mclk_ss_rate_10hz; 2417 uint8_t umcip_min_ver; 2418 uint8_t umcip_max_ver; 2419 uint8_t vram_type; //enum of atom_dgpu_vram_type 2420 uint8_t umc_config; 2421 uint32_t mem_refclk_10khz; 2422 uint32_t pstate_uclk_10khz[4]; 2423 uint16_t umcgoldenoffset; 2424 uint16_t densitygoldenoffset; 2425 uint32_t reserved[4]; 2426 }; 2427 2428 /* 2429 *************************************************************************** 2430 Data Table vram_info structure 2431 *************************************************************************** 2432 */ 2433 struct atom_vram_module_v9 { 2434 // Design Specific Values 2435 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2436 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2437 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2438 uint16_t reserved[3]; 2439 uint16_t mem_voltage; // mem_voltage 2440 uint16_t vram_module_size; // Size of atom_vram_module_v9 2441 uint8_t ext_memory_id; // Current memory module ID 2442 uint8_t memory_type; // enum of atom_dgpu_vram_type 2443 uint8_t channel_num; // Number of mem. channels supported in this module 2444 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2445 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2446 uint8_t tunningset_id; // MC phy registers set per. 2447 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2448 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2449 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2450 uint8_t vram_rsd2; // reserved 2451 char dram_pnstring[20]; // part number end with '0'. 2452 }; 2453 2454 struct atom_vram_info_header_v2_3 { 2455 struct atom_common_table_header table_header; 2456 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2457 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2458 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2459 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2460 uint16_t dram_data_remap_tbloffset; // reserved for now 2461 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2462 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2463 uint16_t vram_rsd2; 2464 uint8_t vram_module_num; // indicate number of VRAM module 2465 uint8_t umcip_min_ver; 2466 uint8_t umcip_max_ver; 2467 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2468 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2469 }; 2470 2471 struct atom_umc_register_addr_info{ 2472 uint32_t umc_register_addr:24; 2473 uint32_t umc_reg_type_ind:1; 2474 uint32_t umc_reg_rsvd:7; 2475 }; 2476 2477 //atom_umc_register_addr_info. 2478 enum atom_umc_register_addr_info_flag{ 2479 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2480 }; 2481 2482 union atom_umc_register_addr_info_access 2483 { 2484 struct atom_umc_register_addr_info umc_reg_addr; 2485 uint32_t u32umc_reg_addr; 2486 }; 2487 2488 struct atom_umc_reg_setting_id_config{ 2489 uint32_t memclockrange:24; 2490 uint32_t mem_blk_id:8; 2491 }; 2492 2493 union atom_umc_reg_setting_id_config_access 2494 { 2495 struct atom_umc_reg_setting_id_config umc_id_access; 2496 uint32_t u32umc_id_access; 2497 }; 2498 2499 struct atom_umc_reg_setting_data_block{ 2500 union atom_umc_reg_setting_id_config_access block_id; 2501 uint32_t u32umc_reg_data[1]; 2502 }; 2503 2504 struct atom_umc_init_reg_block{ 2505 uint16_t umc_reg_num; 2506 uint16_t reserved; 2507 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2508 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2509 }; 2510 2511 struct atom_vram_module_v10 { 2512 // Design Specific Values 2513 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2514 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2515 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2516 uint16_t reserved[3]; 2517 uint16_t mem_voltage; // mem_voltage 2518 uint16_t vram_module_size; // Size of atom_vram_module_v9 2519 uint8_t ext_memory_id; // Current memory module ID 2520 uint8_t memory_type; // enum of atom_dgpu_vram_type 2521 uint8_t channel_num; // Number of mem. channels supported in this module 2522 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2523 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2524 uint8_t tunningset_id; // MC phy registers set per 2525 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2526 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2527 uint8_t vram_flags; // bit0= bankgroup enable 2528 uint8_t vram_rsd2; // reserved 2529 uint16_t gddr6_mr10; // gddr6 mode register10 value 2530 uint16_t gddr6_mr1; // gddr6 mode register1 value 2531 uint16_t gddr6_mr2; // gddr6 mode register2 value 2532 uint16_t gddr6_mr7; // gddr6 mode register7 value 2533 char dram_pnstring[20]; // part number end with '0' 2534 }; 2535 2536 struct atom_vram_info_header_v2_4 { 2537 struct atom_common_table_header table_header; 2538 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2539 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2540 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2541 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2542 uint16_t dram_data_remap_tbloffset; // reserved for now 2543 uint16_t reserved; // offset of reserved 2544 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2545 uint16_t vram_rsd2; 2546 uint8_t vram_module_num; // indicate number of VRAM module 2547 uint8_t umcip_min_ver; 2548 uint8_t umcip_max_ver; 2549 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2550 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2551 }; 2552 2553 struct atom_vram_module_v11 { 2554 // Design Specific Values 2555 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2556 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2557 uint16_t mem_voltage; // mem_voltage 2558 uint16_t vram_module_size; // Size of atom_vram_module_v9 2559 uint8_t ext_memory_id; // Current memory module ID 2560 uint8_t memory_type; // enum of atom_dgpu_vram_type 2561 uint8_t channel_num; // Number of mem. channels supported in this module 2562 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2563 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2564 uint8_t tunningset_id; // MC phy registers set per. 2565 uint16_t reserved[4]; // reserved 2566 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2567 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2568 uint8_t vram_flags; // bit0= bankgroup enable 2569 uint8_t vram_rsd2; // reserved 2570 uint16_t gddr6_mr10; // gddr6 mode register10 value 2571 uint16_t gddr6_mr0; // gddr6 mode register0 value 2572 uint16_t gddr6_mr1; // gddr6 mode register1 value 2573 uint16_t gddr6_mr2; // gddr6 mode register2 value 2574 uint16_t gddr6_mr4; // gddr6 mode register4 value 2575 uint16_t gddr6_mr7; // gddr6 mode register7 value 2576 uint16_t gddr6_mr8; // gddr6 mode register8 value 2577 char dram_pnstring[40]; // part number end with '0'. 2578 }; 2579 2580 struct atom_gddr6_ac_timing_v2_5 { 2581 uint32_t u32umc_id_access; 2582 uint8_t RL; 2583 uint8_t WL; 2584 uint8_t tRAS; 2585 uint8_t tRC; 2586 2587 uint16_t tREFI; 2588 uint8_t tRFC; 2589 uint8_t tRFCpb; 2590 2591 uint8_t tRREFD; 2592 uint8_t tRCDRD; 2593 uint8_t tRCDWR; 2594 uint8_t tRP; 2595 2596 uint8_t tRRDS; 2597 uint8_t tRRDL; 2598 uint8_t tWR; 2599 uint8_t tWTRS; 2600 2601 uint8_t tWTRL; 2602 uint8_t tFAW; 2603 uint8_t tCCDS; 2604 uint8_t tCCDL; 2605 2606 uint8_t tCRCRL; 2607 uint8_t tCRCWL; 2608 uint8_t tCKE; 2609 uint8_t tCKSRE; 2610 2611 uint8_t tCKSRX; 2612 uint8_t tRTPS; 2613 uint8_t tRTPL; 2614 uint8_t tMRD; 2615 2616 uint8_t tMOD; 2617 uint8_t tXS; 2618 uint8_t tXHP; 2619 uint8_t tXSMRS; 2620 2621 uint32_t tXSH; 2622 2623 uint8_t tPD; 2624 uint8_t tXP; 2625 uint8_t tCPDED; 2626 uint8_t tACTPDE; 2627 2628 uint8_t tPREPDE; 2629 uint8_t tREFPDE; 2630 uint8_t tMRSPDEN; 2631 uint8_t tRDSRE; 2632 2633 uint8_t tWRSRE; 2634 uint8_t tPPD; 2635 uint8_t tCCDMW; 2636 uint8_t tWTRTR; 2637 2638 uint8_t tLTLTR; 2639 uint8_t tREFTR; 2640 uint8_t VNDR; 2641 uint8_t reserved[9]; 2642 }; 2643 2644 struct atom_gddr6_bit_byte_remap { 2645 uint32_t dphy_byteremap; //mmUMC_DPHY_ByteRemap 2646 uint32_t dphy_bitremap0; //mmUMC_DPHY_BitRemap0 2647 uint32_t dphy_bitremap1; //mmUMC_DPHY_BitRemap1 2648 uint32_t dphy_bitremap2; //mmUMC_DPHY_BitRemap2 2649 uint32_t aphy_bitremap0; //mmUMC_APHY_BitRemap0 2650 uint32_t aphy_bitremap1; //mmUMC_APHY_BitRemap1 2651 uint32_t phy_dram; //mmUMC_PHY_DRAM 2652 }; 2653 2654 struct atom_gddr6_dram_data_remap { 2655 uint32_t table_size; 2656 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK 2657 struct atom_gddr6_bit_byte_remap bit_byte_remap[16]; 2658 }; 2659 2660 struct atom_vram_info_header_v2_5 { 2661 struct atom_common_table_header table_header; 2662 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust settings 2663 uint16_t gddr6_ac_timing_offset; // offset of atom_gddr6_ac_timing_v2_5 structure for memory clock specific UMC settings 2664 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2665 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2666 uint16_t dram_data_remap_tbloffset; // offset of atom_gddr6_dram_data_remap array to indicate DRAM data lane to GPU mapping 2667 uint16_t reserved; // offset of reserved 2668 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2669 uint16_t strobe_mode_patch_tbloffset; // offset of atom_umc_init_reg_block structure for Strobe Mode memory clock specific UMC settings 2670 uint8_t vram_module_num; // indicate number of VRAM module 2671 uint8_t umcip_min_ver; 2672 uint8_t umcip_max_ver; 2673 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2674 struct atom_vram_module_v11 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2675 }; 2676 2677 /* 2678 *************************************************************************** 2679 Data Table voltageobject_info structure 2680 *************************************************************************** 2681 */ 2682 struct atom_i2c_data_entry 2683 { 2684 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2685 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2686 }; 2687 2688 struct atom_voltage_object_header_v4{ 2689 uint8_t voltage_type; //enum atom_voltage_type 2690 uint8_t voltage_mode; //enum atom_voltage_object_mode 2691 uint16_t object_size; //Size of Object 2692 }; 2693 2694 // atom_voltage_object_header_v4.voltage_mode 2695 enum atom_voltage_object_mode 2696 { 2697 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2698 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2699 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2700 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2701 VOLTAGE_OBJ_EVV = 8, 2702 VOLTAGE_OBJ_MERGED_POWER = 9, 2703 }; 2704 2705 struct atom_i2c_voltage_object_v4 2706 { 2707 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2708 uint8_t regulator_id; //Indicate Voltage Regulator Id 2709 uint8_t i2c_id; 2710 uint8_t i2c_slave_addr; 2711 uint8_t i2c_control_offset; 2712 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2713 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2714 uint8_t reserved[2]; 2715 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2716 }; 2717 2718 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2719 enum atom_i2c_voltage_control_flag 2720 { 2721 VOLTAGE_DATA_ONE_BYTE = 0, 2722 VOLTAGE_DATA_TWO_BYTE = 1, 2723 }; 2724 2725 2726 struct atom_voltage_gpio_map_lut 2727 { 2728 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2729 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2730 }; 2731 2732 struct atom_gpio_voltage_object_v4 2733 { 2734 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2735 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2736 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2737 uint8_t phase_delay_us; // phase delay in unit of micro second 2738 uint8_t reserved; 2739 uint32_t gpio_mask_val; // GPIO Mask value 2740 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2741 }; 2742 2743 struct atom_svid2_voltage_object_v4 2744 { 2745 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2746 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2747 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2748 uint8_t psi0_enable; // 2749 uint8_t maxvstep; 2750 uint8_t telemetry_offset; 2751 uint8_t telemetry_gain; 2752 uint16_t reserved1; 2753 }; 2754 2755 struct atom_merged_voltage_object_v4 2756 { 2757 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2758 uint8_t merged_powerrail_type; //enum atom_voltage_type 2759 uint8_t reserved[3]; 2760 }; 2761 2762 union atom_voltage_object_v4{ 2763 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 2764 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 2765 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 2766 struct atom_merged_voltage_object_v4 merged_voltage_obj; 2767 }; 2768 2769 struct atom_voltage_objects_info_v4_1 2770 { 2771 struct atom_common_table_header table_header; 2772 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 2773 }; 2774 2775 2776 /* 2777 *************************************************************************** 2778 All Command Function structure definition 2779 *************************************************************************** 2780 */ 2781 2782 /* 2783 *************************************************************************** 2784 Structures used by asic_init 2785 *************************************************************************** 2786 */ 2787 2788 struct asic_init_engine_parameters 2789 { 2790 uint32_t sclkfreqin10khz:24; 2791 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 2792 }; 2793 2794 struct asic_init_mem_parameters 2795 { 2796 uint32_t mclkfreqin10khz:24; 2797 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 2798 }; 2799 2800 struct asic_init_parameters_v2_1 2801 { 2802 struct asic_init_engine_parameters engineparam; 2803 struct asic_init_mem_parameters memparam; 2804 }; 2805 2806 struct asic_init_ps_allocation_v2_1 2807 { 2808 struct asic_init_parameters_v2_1 param; 2809 uint32_t reserved[16]; 2810 }; 2811 2812 2813 enum atom_asic_init_engine_flag 2814 { 2815 b3NORMAL_ENGINE_INIT = 0, 2816 b3SRIOV_SKIP_ASIC_INIT = 0x02, 2817 b3SRIOV_LOAD_UCODE = 0x40, 2818 }; 2819 2820 enum atom_asic_init_mem_flag 2821 { 2822 b3NORMAL_MEM_INIT = 0, 2823 b3DRAM_SELF_REFRESH_EXIT =0x20, 2824 }; 2825 2826 /* 2827 *************************************************************************** 2828 Structures used by setengineclock 2829 *************************************************************************** 2830 */ 2831 2832 struct set_engine_clock_parameters_v2_1 2833 { 2834 uint32_t sclkfreqin10khz:24; 2835 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2836 uint32_t reserved[10]; 2837 }; 2838 2839 struct set_engine_clock_ps_allocation_v2_1 2840 { 2841 struct set_engine_clock_parameters_v2_1 clockinfo; 2842 uint32_t reserved[10]; 2843 }; 2844 2845 2846 enum atom_set_engine_mem_clock_flag 2847 { 2848 b3NORMAL_CHANGE_CLOCK = 0, 2849 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 2850 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 2851 }; 2852 2853 /* 2854 *************************************************************************** 2855 Structures used by getengineclock 2856 *************************************************************************** 2857 */ 2858 struct get_engine_clock_parameter 2859 { 2860 uint32_t sclk_10khz; // current engine speed in 10KHz unit 2861 uint32_t reserved; 2862 }; 2863 2864 /* 2865 *************************************************************************** 2866 Structures used by setmemoryclock 2867 *************************************************************************** 2868 */ 2869 struct set_memory_clock_parameters_v2_1 2870 { 2871 uint32_t mclkfreqin10khz:24; 2872 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2873 uint32_t reserved[10]; 2874 }; 2875 2876 struct set_memory_clock_ps_allocation_v2_1 2877 { 2878 struct set_memory_clock_parameters_v2_1 clockinfo; 2879 uint32_t reserved[10]; 2880 }; 2881 2882 2883 /* 2884 *************************************************************************** 2885 Structures used by getmemoryclock 2886 *************************************************************************** 2887 */ 2888 struct get_memory_clock_parameter 2889 { 2890 uint32_t mclk_10khz; // current engine speed in 10KHz unit 2891 uint32_t reserved; 2892 }; 2893 2894 2895 2896 /* 2897 *************************************************************************** 2898 Structures used by setvoltage 2899 *************************************************************************** 2900 */ 2901 2902 struct set_voltage_parameters_v1_4 2903 { 2904 uint8_t voltagetype; /* enum atom_voltage_type */ 2905 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 2906 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 2907 }; 2908 2909 //set_voltage_parameters_v2_1.voltagemode 2910 enum atom_set_voltage_command{ 2911 ATOM_SET_VOLTAGE = 0, 2912 ATOM_INIT_VOLTAGE_REGULATOR = 3, 2913 ATOM_SET_VOLTAGE_PHASE = 4, 2914 ATOM_GET_LEAKAGE_ID = 8, 2915 }; 2916 2917 struct set_voltage_ps_allocation_v1_4 2918 { 2919 struct set_voltage_parameters_v1_4 setvoltageparam; 2920 uint32_t reserved[10]; 2921 }; 2922 2923 2924 /* 2925 *************************************************************************** 2926 Structures used by computegpuclockparam 2927 *************************************************************************** 2928 */ 2929 2930 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 2931 enum atom_gpu_clock_type 2932 { 2933 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 2934 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 2935 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 2936 }; 2937 2938 struct compute_gpu_clock_input_parameter_v1_8 2939 { 2940 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2941 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 2942 uint32_t reserved[5]; 2943 }; 2944 2945 2946 struct compute_gpu_clock_output_parameter_v1_8 2947 { 2948 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2949 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 2950 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 2951 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 2952 uint16_t pll_ss_slew_frac; 2953 uint8_t pll_ss_enable; 2954 uint8_t reserved; 2955 uint32_t reserved1[2]; 2956 }; 2957 2958 2959 2960 /* 2961 *************************************************************************** 2962 Structures used by ReadEfuseValue 2963 *************************************************************************** 2964 */ 2965 2966 struct read_efuse_input_parameters_v3_1 2967 { 2968 uint16_t efuse_start_index; 2969 uint8_t reserved; 2970 uint8_t bitslen; 2971 }; 2972 2973 // ReadEfuseValue input/output parameter 2974 union read_efuse_value_parameters_v3_1 2975 { 2976 struct read_efuse_input_parameters_v3_1 efuse_info; 2977 uint32_t efusevalue; 2978 }; 2979 2980 2981 /* 2982 *************************************************************************** 2983 Structures used by getsmuclockinfo 2984 *************************************************************************** 2985 */ 2986 struct atom_get_smu_clock_info_parameters_v3_1 2987 { 2988 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 2989 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2990 uint8_t command; // enum of atom_get_smu_clock_info_command 2991 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2992 }; 2993 2994 enum atom_get_smu_clock_info_command 2995 { 2996 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 2997 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 2998 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 2999 }; 3000 3001 enum atom_smu9_syspll0_clock_id 3002 { 3003 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 3004 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 3005 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3006 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 3007 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 3008 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 3009 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 3010 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 3011 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 3012 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 3013 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 3014 }; 3015 3016 enum atom_smu11_syspll_id { 3017 SMU11_SYSPLL0_ID = 0, 3018 SMU11_SYSPLL1_0_ID = 1, 3019 SMU11_SYSPLL1_1_ID = 2, 3020 SMU11_SYSPLL1_2_ID = 3, 3021 SMU11_SYSPLL2_ID = 4, 3022 SMU11_SYSPLL3_0_ID = 5, 3023 SMU11_SYSPLL3_1_ID = 6, 3024 }; 3025 3026 enum atom_smu11_syspll0_clock_id { 3027 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 3028 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 3029 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 3030 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 3031 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 3032 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 3033 }; 3034 3035 enum atom_smu11_syspll1_0_clock_id { 3036 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 3037 }; 3038 3039 enum atom_smu11_syspll1_1_clock_id { 3040 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 3041 }; 3042 3043 enum atom_smu11_syspll1_2_clock_id { 3044 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 3045 }; 3046 3047 enum atom_smu11_syspll2_clock_id { 3048 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 3049 }; 3050 3051 enum atom_smu11_syspll3_0_clock_id { 3052 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 3053 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 3054 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 3055 }; 3056 3057 enum atom_smu11_syspll3_1_clock_id { 3058 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 3059 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 3060 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 3061 }; 3062 3063 struct atom_get_smu_clock_info_output_parameters_v3_1 3064 { 3065 union { 3066 uint32_t smu_clock_freq_hz; 3067 uint32_t syspllvcofreq_10khz; 3068 uint32_t sysspllrefclk_10khz; 3069 }atom_smu_outputclkfreq; 3070 }; 3071 3072 3073 3074 /* 3075 *************************************************************************** 3076 Structures used by dynamicmemorysettings 3077 *************************************************************************** 3078 */ 3079 3080 enum atom_dynamic_memory_setting_command 3081 { 3082 COMPUTE_MEMORY_PLL_PARAM = 1, 3083 COMPUTE_ENGINE_PLL_PARAM = 2, 3084 ADJUST_MC_SETTING_PARAM = 3, 3085 }; 3086 3087 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 3088 struct dynamic_mclk_settings_parameters_v2_1 3089 { 3090 uint32_t mclk_10khz:24; //Input= target mclk 3091 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3092 uint32_t reserved; 3093 }; 3094 3095 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 3096 struct dynamic_sclk_settings_parameters_v2_1 3097 { 3098 uint32_t sclk_10khz:24; //Input= target mclk 3099 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 3100 uint32_t mclk_10khz; 3101 uint32_t reserved; 3102 }; 3103 3104 union dynamic_memory_settings_parameters_v2_1 3105 { 3106 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 3107 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 3108 }; 3109 3110 3111 3112 /* 3113 *************************************************************************** 3114 Structures used by memorytraining 3115 *************************************************************************** 3116 */ 3117 3118 enum atom_umc6_0_ucode_function_call_enum_id 3119 { 3120 UMC60_UCODE_FUNC_ID_REINIT = 0, 3121 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 3122 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 3123 }; 3124 3125 3126 struct memory_training_parameters_v2_1 3127 { 3128 uint8_t ucode_func_id; 3129 uint8_t ucode_reserved[3]; 3130 uint32_t reserved[5]; 3131 }; 3132 3133 3134 /* 3135 *************************************************************************** 3136 Structures used by setpixelclock 3137 *************************************************************************** 3138 */ 3139 3140 struct set_pixel_clock_parameter_v1_7 3141 { 3142 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 3143 3144 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 3145 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 3146 // indicate which graphic encoder will be used. 3147 uint8_t encoder_mode; // Encoder mode: 3148 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 3149 uint8_t crtc_id; // enum of atom_crtc_def 3150 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3151 uint8_t reserved1[2]; 3152 uint32_t reserved2; 3153 }; 3154 3155 //ucMiscInfo 3156 enum atom_set_pixel_clock_v1_7_misc_info 3157 { 3158 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 3159 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 3160 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 3161 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 3162 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 3163 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 3164 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 3165 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 3166 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 3167 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 3168 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 3169 }; 3170 3171 /* deep_color_ratio */ 3172 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 3173 { 3174 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3175 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3176 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3177 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3178 }; 3179 3180 /* 3181 *************************************************************************** 3182 Structures used by setdceclock 3183 *************************************************************************** 3184 */ 3185 3186 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 3187 struct set_dce_clock_parameters_v2_1 3188 { 3189 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 3190 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 3191 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 3192 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 3193 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 3194 }; 3195 3196 //ucDCEClkType 3197 enum atom_set_dce_clock_clock_type 3198 { 3199 DCE_CLOCK_TYPE_DISPCLK = 0, 3200 DCE_CLOCK_TYPE_DPREFCLK = 1, 3201 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 3202 }; 3203 3204 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 3205 enum atom_set_dce_clock_dprefclk_flag 3206 { 3207 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 3208 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 3209 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 3210 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 3211 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 3212 }; 3213 3214 //ucDCEClkFlag when ucDCEClkType == PIXCLK 3215 enum atom_set_dce_clock_pixclk_flag 3216 { 3217 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 3218 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 3219 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 3220 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 3221 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 3222 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 3223 }; 3224 3225 struct set_dce_clock_ps_allocation_v2_1 3226 { 3227 struct set_dce_clock_parameters_v2_1 param; 3228 uint32_t ulReserved[2]; 3229 }; 3230 3231 3232 /****************************************************************************/ 3233 // Structures used by BlankCRTC 3234 /****************************************************************************/ 3235 struct blank_crtc_parameters 3236 { 3237 uint8_t crtc_id; // enum atom_crtc_def 3238 uint8_t blanking; // enum atom_blank_crtc_command 3239 uint16_t reserved; 3240 uint32_t reserved1; 3241 }; 3242 3243 enum atom_blank_crtc_command 3244 { 3245 ATOM_BLANKING = 1, 3246 ATOM_BLANKING_OFF = 0, 3247 }; 3248 3249 /****************************************************************************/ 3250 // Structures used by enablecrtc 3251 /****************************************************************************/ 3252 struct enable_crtc_parameters 3253 { 3254 uint8_t crtc_id; // enum atom_crtc_def 3255 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3256 uint8_t padding[2]; 3257 }; 3258 3259 3260 /****************************************************************************/ 3261 // Structure used by EnableDispPowerGating 3262 /****************************************************************************/ 3263 struct enable_disp_power_gating_parameters_v2_1 3264 { 3265 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 3266 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 3267 uint8_t padding[2]; 3268 }; 3269 3270 struct enable_disp_power_gating_ps_allocation 3271 { 3272 struct enable_disp_power_gating_parameters_v2_1 param; 3273 uint32_t ulReserved[4]; 3274 }; 3275 3276 /****************************************************************************/ 3277 // Structure used in setcrtc_usingdtdtiming 3278 /****************************************************************************/ 3279 struct set_crtc_using_dtd_timing_parameters 3280 { 3281 uint16_t h_size; 3282 uint16_t h_blanking_time; 3283 uint16_t v_size; 3284 uint16_t v_blanking_time; 3285 uint16_t h_syncoffset; 3286 uint16_t h_syncwidth; 3287 uint16_t v_syncoffset; 3288 uint16_t v_syncwidth; 3289 uint16_t modemiscinfo; 3290 uint8_t h_border; 3291 uint8_t v_border; 3292 uint8_t crtc_id; // enum atom_crtc_def 3293 uint8_t encoder_mode; // atom_encode_mode_def 3294 uint8_t padding[2]; 3295 }; 3296 3297 3298 /****************************************************************************/ 3299 // Structures used by processi2cchanneltransaction 3300 /****************************************************************************/ 3301 struct process_i2c_channel_transaction_parameters 3302 { 3303 uint8_t i2cspeed_khz; 3304 union { 3305 uint8_t regindex; 3306 uint8_t status; /* enum atom_process_i2c_flag */ 3307 } regind_status; 3308 uint16_t i2c_data_out; 3309 uint8_t flag; /* enum atom_process_i2c_status */ 3310 uint8_t trans_bytes; 3311 uint8_t slave_addr; 3312 uint8_t i2c_id; 3313 }; 3314 3315 //ucFlag 3316 enum atom_process_i2c_flag 3317 { 3318 HW_I2C_WRITE = 1, 3319 HW_I2C_READ = 0, 3320 I2C_2BYTE_ADDR = 0x02, 3321 HW_I2C_SMBUS_BYTE_WR = 0x04, 3322 }; 3323 3324 //status 3325 enum atom_process_i2c_status 3326 { 3327 HW_ASSISTED_I2C_STATUS_FAILURE =2, 3328 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 3329 }; 3330 3331 3332 /****************************************************************************/ 3333 // Structures used by processauxchanneltransaction 3334 /****************************************************************************/ 3335 3336 struct process_aux_channel_transaction_parameters_v1_2 3337 { 3338 uint16_t aux_request; 3339 uint16_t dataout; 3340 uint8_t channelid; 3341 union { 3342 uint8_t reply_status; 3343 uint8_t aux_delay; 3344 } aux_status_delay; 3345 uint8_t dataout_len; 3346 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 3347 }; 3348 3349 3350 /****************************************************************************/ 3351 // Structures used by selectcrtc_source 3352 /****************************************************************************/ 3353 3354 struct select_crtc_source_parameters_v2_3 3355 { 3356 uint8_t crtc_id; // enum atom_crtc_def 3357 uint8_t encoder_id; // enum atom_dig_def 3358 uint8_t encode_mode; // enum atom_encode_mode_def 3359 uint8_t dst_bpc; // enum atom_panel_bit_per_color 3360 }; 3361 3362 3363 /****************************************************************************/ 3364 // Structures used by digxencodercontrol 3365 /****************************************************************************/ 3366 3367 // ucAction: 3368 enum atom_dig_encoder_control_action 3369 { 3370 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 3371 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 3372 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 3373 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 3374 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 3375 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 3376 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 3377 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 3378 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 3379 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 3380 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 3381 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 3382 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 3383 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 3384 }; 3385 3386 //define ucPanelMode 3387 enum atom_dig_encoder_control_panelmode 3388 { 3389 DP_PANEL_MODE_DISABLE = 0x00, 3390 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 3391 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 3392 }; 3393 3394 //ucDigId 3395 enum atom_dig_encoder_control_v5_digid 3396 { 3397 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 3398 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 3399 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 3400 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 3401 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 3402 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 3403 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 3404 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 3405 }; 3406 3407 struct dig_encoder_stream_setup_parameters_v1_5 3408 { 3409 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3410 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 3411 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3412 uint8_t lanenum; // Lane number 3413 uint32_t pclk_10khz; // Pixel Clock in 10Khz 3414 uint8_t bitpercolor; 3415 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 3416 uint8_t reserved[2]; 3417 }; 3418 3419 struct dig_encoder_link_setup_parameters_v1_5 3420 { 3421 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3422 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 3423 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 3424 uint8_t lanenum; // Lane number 3425 uint8_t symclk_10khz; // Symbol Clock in 10Khz 3426 uint8_t hpd_sel; 3427 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3428 uint8_t reserved[2]; 3429 }; 3430 3431 struct dp_panel_mode_set_parameters_v1_5 3432 { 3433 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3434 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 3435 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 3436 uint8_t reserved1; 3437 uint32_t reserved2[2]; 3438 }; 3439 3440 struct dig_encoder_generic_cmd_parameters_v1_5 3441 { 3442 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 3443 uint8_t action; // = rest of generic encoder command which does not carry any parameters 3444 uint8_t reserved1[2]; 3445 uint32_t reserved2[2]; 3446 }; 3447 3448 union dig_encoder_control_parameters_v1_5 3449 { 3450 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 3451 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 3452 struct dig_encoder_link_setup_parameters_v1_5 link_param; 3453 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 3454 }; 3455 3456 /* 3457 *************************************************************************** 3458 Structures used by dig1transmittercontrol 3459 *************************************************************************** 3460 */ 3461 struct dig_transmitter_control_parameters_v1_6 3462 { 3463 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 3464 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 3465 union { 3466 uint8_t digmode; // enum atom_encode_mode_def 3467 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3468 } mode_laneset; 3469 uint8_t lanenum; // Lane number 1, 2, 4, 8 3470 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3471 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3472 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3473 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3474 uint8_t reserved; 3475 uint32_t reserved1; 3476 }; 3477 3478 struct dig_transmitter_control_ps_allocation_v1_6 3479 { 3480 struct dig_transmitter_control_parameters_v1_6 param; 3481 uint32_t reserved[4]; 3482 }; 3483 3484 //ucAction 3485 enum atom_dig_transmitter_control_action 3486 { 3487 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3488 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3489 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3490 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3491 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3492 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3493 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3494 ATOM_TRANSMITTER_ACTION_INIT = 7, 3495 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3496 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3497 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3498 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3499 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3500 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3501 }; 3502 3503 // digfe_sel 3504 enum atom_dig_transmitter_control_digfe_sel 3505 { 3506 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3507 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3508 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3509 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3510 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3511 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3512 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3513 }; 3514 3515 3516 //ucHPDSel 3517 enum atom_dig_transmitter_control_hpd_sel 3518 { 3519 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3520 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3521 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3522 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3523 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3524 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3525 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3526 }; 3527 3528 // ucDPLaneSet 3529 enum atom_dig_transmitter_control_dplaneset 3530 { 3531 DP_LANE_SET__0DB_0_4V = 0x00, 3532 DP_LANE_SET__0DB_0_6V = 0x01, 3533 DP_LANE_SET__0DB_0_8V = 0x02, 3534 DP_LANE_SET__0DB_1_2V = 0x03, 3535 DP_LANE_SET__3_5DB_0_4V = 0x08, 3536 DP_LANE_SET__3_5DB_0_6V = 0x09, 3537 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3538 DP_LANE_SET__6DB_0_4V = 0x10, 3539 DP_LANE_SET__6DB_0_6V = 0x11, 3540 DP_LANE_SET__9_5DB_0_4V = 0x18, 3541 }; 3542 3543 3544 3545 /****************************************************************************/ 3546 // Structures used by ExternalEncoderControl V2.4 3547 /****************************************************************************/ 3548 3549 struct external_encoder_control_parameters_v2_4 3550 { 3551 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3552 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3553 uint8_t action; // 3554 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3555 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3556 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3557 uint8_t hpd_id; 3558 }; 3559 3560 3561 // ucAction 3562 enum external_encoder_control_action_def 3563 { 3564 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3565 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3566 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3567 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3568 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3569 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3570 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3571 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3572 }; 3573 3574 // ucConfig 3575 enum external_encoder_control_v2_4_config_def 3576 { 3577 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3578 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3579 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3580 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3581 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3582 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3583 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3584 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3585 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3586 }; 3587 3588 struct external_encoder_control_ps_allocation_v2_4 3589 { 3590 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3591 uint32_t reserved[2]; 3592 }; 3593 3594 3595 /* 3596 *************************************************************************** 3597 AMD ACPI Table 3598 3599 *************************************************************************** 3600 */ 3601 3602 struct amd_acpi_description_header{ 3603 uint32_t signature; 3604 uint32_t tableLength; //Length 3605 uint8_t revision; 3606 uint8_t checksum; 3607 uint8_t oemId[6]; 3608 uint8_t oemTableId[8]; //UINT64 OemTableId; 3609 uint32_t oemRevision; 3610 uint32_t creatorId; 3611 uint32_t creatorRevision; 3612 }; 3613 3614 struct uefi_acpi_vfct{ 3615 struct amd_acpi_description_header sheader; 3616 uint8_t tableUUID[16]; //0x24 3617 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3618 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3619 uint32_t reserved[4]; //0x3C 3620 }; 3621 3622 struct vfct_image_header{ 3623 uint32_t pcibus; //0x4C 3624 uint32_t pcidevice; //0x50 3625 uint32_t pcifunction; //0x54 3626 uint16_t vendorid; //0x58 3627 uint16_t deviceid; //0x5A 3628 uint16_t ssvid; //0x5C 3629 uint16_t ssid; //0x5E 3630 uint32_t revision; //0x60 3631 uint32_t imagelength; //0x64 3632 }; 3633 3634 3635 struct gop_vbios_content { 3636 struct vfct_image_header vbiosheader; 3637 uint8_t vbioscontent[1]; 3638 }; 3639 3640 struct gop_lib1_content { 3641 struct vfct_image_header lib1header; 3642 uint8_t lib1content[1]; 3643 }; 3644 3645 3646 3647 /* 3648 *************************************************************************** 3649 Scratch Register definitions 3650 Each number below indicates which scratch regiser request, Active and 3651 Connect all share the same definitions as display_device_tag defines 3652 *************************************************************************** 3653 */ 3654 3655 enum scratch_register_def{ 3656 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3657 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3658 ATOM_ACTIVE_INFO_DEF = 3, 3659 ATOM_LCD_INFO_DEF = 4, 3660 ATOM_DEVICE_REQ_INFO_DEF = 5, 3661 ATOM_ACC_CHANGE_INFO_DEF = 6, 3662 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3663 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3664 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3665 }; 3666 3667 enum scratch_device_connect_info_bit_def{ 3668 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3669 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3670 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3671 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3672 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3673 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3674 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3675 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3676 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3677 }; 3678 3679 enum scratch_bl_bri_level_info_bit_def{ 3680 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3681 #ifndef _H2INC 3682 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 3683 ATOM_DEVICE_DPMS_STATE =0x00010000, 3684 #endif 3685 }; 3686 3687 enum scratch_active_info_bits_def{ 3688 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 3689 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 3690 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 3691 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 3692 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 3693 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 3694 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 3695 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 3696 }; 3697 3698 enum scratch_device_req_info_bits_def{ 3699 ATOM_DISPLAY_LCD1_REQ =0x0002, 3700 ATOM_DISPLAY_DFP1_REQ =0x0008, 3701 ATOM_DISPLAY_DFP2_REQ =0x0080, 3702 ATOM_DISPLAY_DFP3_REQ =0x0200, 3703 ATOM_DISPLAY_DFP4_REQ =0x0400, 3704 ATOM_DISPLAY_DFP5_REQ =0x0800, 3705 ATOM_DISPLAY_DFP6_REQ =0x0040, 3706 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 3707 }; 3708 3709 enum scratch_acc_change_info_bitshift_def{ 3710 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 3711 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 3712 }; 3713 3714 enum scratch_acc_change_info_bits_def{ 3715 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 3716 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 3717 }; 3718 3719 enum scratch_pre_os_mode_info_bits_def{ 3720 ATOM_PRE_OS_MODE_MASK =0x00000003, 3721 ATOM_PRE_OS_MODE_VGA =0x00000000, 3722 ATOM_PRE_OS_MODE_VESA =0x00000001, 3723 ATOM_PRE_OS_MODE_GOP =0x00000002, 3724 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3725 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3726 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3727 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3728 #ifndef _H2INC 3729 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3730 #endif 3731 }; 3732 3733 3734 3735 /* 3736 *************************************************************************** 3737 ATOM firmware ID header file 3738 !! Please keep it at end of the atomfirmware.h !! 3739 *************************************************************************** 3740 */ 3741 #include "atomfirmwareid.h" 3742 #pragma pack() 3743 3744 #endif 3745 3746