1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #ifndef __AMD_SHARED_H__ 24 #define __AMD_SHARED_H__ 25 26 #include <drm/amd_asic_type.h> 27 #include <drm/drm_print.h> 28 29 30 #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ 31 struct amdgpu_ip_block; 32 33 34 /* 35 * Chip flags 36 */ 37 enum amd_chip_flags { 38 AMD_ASIC_MASK = 0x0000ffffUL, 39 AMD_FLAGS_MASK = 0xffff0000UL, 40 AMD_IS_MOBILITY = 0x00010000UL, 41 AMD_IS_APU = 0x00020000UL, 42 AMD_IS_PX = 0x00040000UL, 43 AMD_EXP_HW_SUPPORT = 0x00080000UL, 44 }; 45 46 enum amd_apu_flags { 47 AMD_APU_IS_RAVEN = 0x00000001UL, 48 AMD_APU_IS_RAVEN2 = 0x00000002UL, 49 AMD_APU_IS_PICASSO = 0x00000004UL, 50 AMD_APU_IS_RENOIR = 0x00000008UL, 51 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL, 52 AMD_APU_IS_VANGOGH = 0x00000020UL, 53 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL, 54 }; 55 56 /** 57 * DOC: IP Blocks 58 * 59 * GPUs are composed of IP (intellectual property) blocks. These 60 * IP blocks provide various functionalities: display, graphics, 61 * video decode, etc. The IP blocks that comprise a particular GPU 62 * are listed in the GPU's respective SoC file. amdgpu_device.c 63 * acquires the list of IP blocks for the GPU in use on initialization. 64 * It can then operate on this list to perform standard driver operations 65 * such as: init, fini, suspend, resume, etc. 66 * 67 * 68 * IP block implementations are named using the following convention: 69 * <functionality>_v<version> (E.g.: gfx_v6_0). 70 */ 71 72 /** 73 * enum amd_ip_block_type - Used to classify IP blocks by functionality. 74 * 75 * @AMD_IP_BLOCK_TYPE_COMMON: GPU Family 76 * @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller 77 * @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler 78 * @AMD_IP_BLOCK_TYPE_SMC: System Management Controller 79 * @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor 80 * @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine 81 * @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine 82 * @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine 83 * @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder 84 * @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine 85 * @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor 86 * @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next 87 * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler 88 * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine 89 * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine 90 * @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia 91 * @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor 92 * @AMD_IP_BLOCK_TYPE_RAS: Reliability, Availability, Serviceability 93 * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types 94 */ 95 enum amd_ip_block_type { 96 AMD_IP_BLOCK_TYPE_COMMON, 97 AMD_IP_BLOCK_TYPE_GMC, 98 AMD_IP_BLOCK_TYPE_IH, 99 AMD_IP_BLOCK_TYPE_SMC, 100 AMD_IP_BLOCK_TYPE_PSP, 101 AMD_IP_BLOCK_TYPE_DCE, 102 AMD_IP_BLOCK_TYPE_GFX, 103 AMD_IP_BLOCK_TYPE_SDMA, 104 AMD_IP_BLOCK_TYPE_UVD, 105 AMD_IP_BLOCK_TYPE_VCE, 106 AMD_IP_BLOCK_TYPE_ACP, 107 AMD_IP_BLOCK_TYPE_VCN, 108 AMD_IP_BLOCK_TYPE_MES, 109 AMD_IP_BLOCK_TYPE_JPEG, 110 AMD_IP_BLOCK_TYPE_VPE, 111 AMD_IP_BLOCK_TYPE_UMSCH_MM, 112 AMD_IP_BLOCK_TYPE_ISP, 113 AMD_IP_BLOCK_TYPE_RAS, 114 AMD_IP_BLOCK_TYPE_NUM, 115 }; 116 117 enum amd_clockgating_state { 118 AMD_CG_STATE_GATE = 0, 119 AMD_CG_STATE_UNGATE, 120 }; 121 122 123 enum amd_powergating_state { 124 AMD_PG_STATE_GATE = 0, 125 AMD_PG_STATE_UNGATE, 126 }; 127 128 129 /* CG flags */ 130 #define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0) 131 #define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1) 132 #define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2) 133 #define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3) 134 #define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4) 135 #define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5) 136 #define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6) 137 #define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7) 138 #define AMD_CG_SUPPORT_MC_LS (1ULL << 8) 139 #define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9) 140 #define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10) 141 #define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11) 142 #define AMD_CG_SUPPORT_BIF_LS (1ULL << 12) 143 #define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13) 144 #define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14) 145 #define AMD_CG_SUPPORT_HDP_LS (1ULL << 15) 146 #define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16) 147 #define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17) 148 #define AMD_CG_SUPPORT_DRM_LS (1ULL << 18) 149 #define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19) 150 #define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20) 151 #define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21) 152 #define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22) 153 #define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23) 154 #define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24) 155 #define AMD_CG_SUPPORT_HDP_DS (1ULL << 25) 156 #define AMD_CG_SUPPORT_HDP_SD (1ULL << 26) 157 #define AMD_CG_SUPPORT_IH_CG (1ULL << 27) 158 #define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28) 159 #define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29) 160 #define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30) 161 #define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31) 162 #define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32) 163 #define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33) 164 /* PG flags */ 165 #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 166 #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 167 #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 168 #define AMD_PG_SUPPORT_UVD (1 << 3) 169 #define AMD_PG_SUPPORT_VCE (1 << 4) 170 #define AMD_PG_SUPPORT_CP (1 << 5) 171 #define AMD_PG_SUPPORT_GDS (1 << 6) 172 #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 173 #define AMD_PG_SUPPORT_SDMA (1 << 8) 174 #define AMD_PG_SUPPORT_ACP (1 << 9) 175 #define AMD_PG_SUPPORT_SAMU (1 << 10) 176 #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 177 #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 178 #define AMD_PG_SUPPORT_MMHUB (1 << 13) 179 #define AMD_PG_SUPPORT_VCN (1 << 14) 180 #define AMD_PG_SUPPORT_VCN_DPG (1 << 15) 181 #define AMD_PG_SUPPORT_ATHUB (1 << 16) 182 #define AMD_PG_SUPPORT_JPEG (1 << 17) 183 #define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18) 184 #define AMD_PG_SUPPORT_JPEG_DPG (1 << 19) 185 186 /** 187 * enum PP_FEATURE_MASK - Used to mask power play features. 188 * 189 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock. 190 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock. 191 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes. 192 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep. 193 * @PP_POWER_CONTAINMENT_MASK: Power containment. 194 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake. 195 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control. 196 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support. 197 * @PP_ULV_MASK: Ultra low voltage. 198 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating. 199 * @PP_CLOCK_STRETCH_MASK: Clock stretching. 200 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control. 201 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock. 202 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock. 203 * @PP_OVERDRIVE_MASK: Over- and under-clocking support. 204 * @PP_GFXOFF_MASK: Dynamic graphics engine power control. 205 * @PP_ACG_MASK: Adaptive clock generator. 206 * @PP_STUTTER_MODE: Stutter mode. 207 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling. 208 * @PP_GFX_DCS_MASK: GFX Async DCS. 209 * 210 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to 211 * the kernel's command line parameters. This is usually done through a system's 212 * boot loader (E.g. GRUB). If manually loading the driver, pass 213 * ppfeaturemask=<mask> as a modprobe parameter. 214 */ 215 enum PP_FEATURE_MASK { 216 PP_SCLK_DPM_MASK = 0x1, 217 PP_MCLK_DPM_MASK = 0x2, 218 PP_PCIE_DPM_MASK = 0x4, 219 PP_SCLK_DEEP_SLEEP_MASK = 0x8, 220 PP_POWER_CONTAINMENT_MASK = 0x10, 221 PP_UVD_HANDSHAKE_MASK = 0x20, 222 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 223 PP_VBI_TIME_SUPPORT_MASK = 0x80, 224 PP_ULV_MASK = 0x100, 225 PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 226 PP_CLOCK_STRETCH_MASK = 0x400, 227 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 228 PP_SOCCLK_DPM_MASK = 0x1000, 229 PP_DCEFCLK_DPM_MASK = 0x2000, 230 PP_OVERDRIVE_MASK = 0x4000, 231 PP_GFXOFF_MASK = 0x8000, 232 PP_ACG_MASK = 0x10000, 233 PP_STUTTER_MODE = 0x20000, 234 PP_AVFS_MASK = 0x40000, 235 PP_GFX_DCS_MASK = 0x80000, 236 }; 237 238 enum amd_harvest_ip_mask { 239 AMD_HARVEST_IP_VCN_MASK = 0x1, 240 AMD_HARVEST_IP_JPEG_MASK = 0x2, 241 AMD_HARVEST_IP_DMU_MASK = 0x4, 242 }; 243 244 /** 245 * enum DC_FEATURE_MASK - Bits that control DC feature defaults 246 */ 247 enum DC_FEATURE_MASK { 248 //Default value can be found at "uint amdgpu_dc_feature_mask" 249 /** 250 * @DC_FBC_MASK: (0x1) disabled by default 251 */ 252 DC_FBC_MASK = (1 << 0), 253 /** 254 * @DC_MULTI_MON_PP_MCLK_SWITCH_MASK: (0x2) enabled by default 255 */ 256 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), 257 /** 258 * @DC_DISABLE_FRACTIONAL_PWM_MASK: (0x4) disabled by default 259 */ 260 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), 261 /** 262 * @DC_PSR_MASK: (0x8) disabled by default for DCN < 3.1 263 */ 264 DC_PSR_MASK = (1 << 3), 265 /** 266 * @DC_EDP_NO_POWER_SEQUENCING: (0x10) disabled by default 267 */ 268 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), 269 /** 270 * @DC_DISABLE_LTTPR_DP1_4A: (0x20) disabled by default 271 */ 272 DC_DISABLE_LTTPR_DP1_4A = (1 << 5), 273 /** 274 * @DC_DISABLE_LTTPR_DP2_0: (0x40) disabled by default 275 */ 276 DC_DISABLE_LTTPR_DP2_0 = (1 << 6), 277 /** 278 * @DC_PSR_ALLOW_SMU_OPT: (0x80) disabled by default 279 */ 280 DC_PSR_ALLOW_SMU_OPT = (1 << 7), 281 /** 282 * @DC_PSR_ALLOW_MULTI_DISP_OPT: (0x100) disabled by default 283 */ 284 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), 285 /** 286 * @DC_REPLAY_MASK: (0x200) disabled by default for DCN < 3.1.4 287 */ 288 DC_REPLAY_MASK = (1 << 9), 289 }; 290 291 /** 292 * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP 293 */ 294 enum DC_DEBUG_MASK { 295 /** 296 * @DC_DISABLE_PIPE_SPLIT: (0x1) If set, disable pipe-splitting 297 */ 298 DC_DISABLE_PIPE_SPLIT = 0x1, 299 300 /** 301 * @DC_DISABLE_STUTTER: (0x2) If set, disable memory stutter mode 302 */ 303 DC_DISABLE_STUTTER = 0x2, 304 305 /** 306 * @DC_DISABLE_DSC: (0x4) If set, disable display stream compression 307 */ 308 DC_DISABLE_DSC = 0x4, 309 310 /** 311 * @DC_DISABLE_CLOCK_GATING: (0x8) If set, disable clock gating optimizations 312 */ 313 DC_DISABLE_CLOCK_GATING = 0x8, 314 315 /** 316 * @DC_DISABLE_PSR: (0x10) If set, disable Panel self refresh v1 and PSR-SU 317 */ 318 DC_DISABLE_PSR = 0x10, 319 320 /** 321 * @DC_FORCE_SUBVP_MCLK_SWITCH: (0x20) If set, force mclk switch in subvp, even 322 * if mclk switch in vblank is possible 323 */ 324 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, 325 326 /** 327 * @DC_DISABLE_MPO: (0x40) If set, disable multi-plane offloading 328 */ 329 DC_DISABLE_MPO = 0x40, 330 331 /** 332 * @DC_ENABLE_DPIA_TRACE: (0x80) If set, enable trace logging for DPIA 333 */ 334 DC_ENABLE_DPIA_TRACE = 0x80, 335 336 /** 337 * @DC_ENABLE_DML2: (0x100) If set, force usage of DML2, even if the DCN version 338 * does not default to it. 339 */ 340 DC_ENABLE_DML2 = 0x100, 341 342 /** 343 * @DC_DISABLE_PSR_SU: (0x200) If set, disable PSR SU 344 */ 345 DC_DISABLE_PSR_SU = 0x200, 346 347 /** 348 * @DC_DISABLE_REPLAY: (0x400) If set, disable Panel Replay 349 */ 350 DC_DISABLE_REPLAY = 0x400, 351 352 /** 353 * @DC_DISABLE_IPS: (0x800) If set, disable all Idle Power States, all the time. 354 * If more than one IPS debug bit is set, the lowest bit takes 355 * precedence. For example, if DC_FORCE_IPS_ENABLE and 356 * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes 357 * precedence. 358 */ 359 DC_DISABLE_IPS = 0x800, 360 361 /** 362 * @DC_DISABLE_IPS_DYNAMIC: (0x1000) If set, disable all IPS, all the time, 363 * *except* when driver goes into suspend. 364 */ 365 DC_DISABLE_IPS_DYNAMIC = 0x1000, 366 367 /** 368 * @DC_DISABLE_IPS2_DYNAMIC: (0x2000) If set, disable IPS2 (IPS1 allowed) if 369 * there is an enabled display. Otherwise, enable all IPS. 370 */ 371 DC_DISABLE_IPS2_DYNAMIC = 0x2000, 372 373 /** 374 * @DC_FORCE_IPS_ENABLE: (0x4000) If set, force enable all IPS, all the time. 375 */ 376 DC_FORCE_IPS_ENABLE = 0x4000, 377 /** 378 * @DC_DISABLE_ACPI_EDID: (0x8000) If set, don't attempt to fetch EDID for 379 * eDP display from ACPI _DDC method. 380 */ 381 DC_DISABLE_ACPI_EDID = 0x8000, 382 383 /** 384 * @DC_DISABLE_HDMI_CEC: (0x10000) If set, disable HDMI-CEC feature in amdgpu driver. 385 */ 386 DC_DISABLE_HDMI_CEC = 0x10000, 387 388 /** 389 * @DC_DISABLE_SUBVP_FAMS: (0x20000) If set, disable DCN Sub-Viewport & Firmware Assisted 390 * Memory Clock Switching (FAMS) feature in amdgpu driver. 391 */ 392 DC_DISABLE_SUBVP_FAMS = 0x20000, 393 /** 394 * @DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE: (0x40000) If set, disable support for custom 395 * brightness curves 396 */ 397 DC_DISABLE_CUSTOM_BRIGHTNESS_CURVE = 0x40000, 398 399 /** 400 * @DC_HDCP_LC_FORCE_FW_ENABLE: (0x80000) If set, use HDCP Locality Check FW 401 * path regardless of reported HW capabilities. 402 */ 403 DC_HDCP_LC_FORCE_FW_ENABLE = 0x80000, 404 405 /** 406 * @DC_HDCP_LC_ENABLE_SW_FALLBACK: (0x100000) If set, upon HDCP Locality Check FW 407 * path failure, retry using legacy SW path. 408 */ 409 DC_HDCP_LC_ENABLE_SW_FALLBACK = 0x100000, 410 411 /** 412 * @DC_SKIP_DETECTION_LT: (0x200000) If set, skip detection link training 413 */ 414 DC_SKIP_DETECTION_LT = 0x200000, 415 }; 416 417 enum amd_dpm_forced_level; 418 419 /** 420 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 421 * @name: Name of IP block 422 * @early_init: sets up early driver state (pre sw_init), 423 * does not configure hw - Optional 424 * @late_init: sets up late driver/hw state (post hw_init) - Optional 425 * @sw_init: sets up driver state, does not configure hw 426 * @sw_fini: tears down driver state, does not configure hw 427 * @early_fini: tears down stuff before dev detached from driver 428 * @hw_init: sets up the hw state 429 * @hw_fini: tears down the hw state 430 * @late_fini: final cleanup 431 * @prepare_suspend: handle IP specific changes to prepare for suspend 432 * (such as allocating any required memory) 433 * @suspend: handles IP specific hw/sw changes for suspend 434 * @resume: handles IP specific hw/sw changes for resume 435 * @complete: handles IP specific changes after resume 436 * @is_idle: returns current IP block idle status 437 * @wait_for_idle: poll for idle 438 * @check_soft_reset: check soft reset the IP block 439 * @pre_soft_reset: pre soft reset the IP block 440 * @soft_reset: soft reset the IP block 441 * @post_soft_reset: post soft reset the IP block 442 * @set_clockgating_state: enable/disable cg for the IP block 443 * @set_powergating_state: enable/disable pg for the IP block 444 * @get_clockgating_state: get current clockgating status 445 * @dump_ip_state: dump the IP state of the ASIC during a gpu hang 446 * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC 447 * 448 * These hooks provide an interface for controlling the operational state 449 * of IP blocks. After acquiring a list of IP blocks for the GPU in use, 450 * the driver can make chip-wide state changes by walking this list and 451 * making calls to hooks from each IP block. This list is ordered to ensure 452 * that the driver initializes the IP blocks in a safe sequence. 453 */ 454 struct amd_ip_funcs { 455 char *name; 456 int (*early_init)(struct amdgpu_ip_block *ip_block); 457 int (*late_init)(struct amdgpu_ip_block *ip_block); 458 int (*sw_init)(struct amdgpu_ip_block *ip_block); 459 int (*sw_fini)(struct amdgpu_ip_block *ip_block); 460 int (*early_fini)(struct amdgpu_ip_block *ip_block); 461 int (*hw_init)(struct amdgpu_ip_block *ip_block); 462 int (*hw_fini)(struct amdgpu_ip_block *ip_block); 463 void (*late_fini)(struct amdgpu_ip_block *ip_block); 464 int (*prepare_suspend)(struct amdgpu_ip_block *ip_block); 465 int (*suspend)(struct amdgpu_ip_block *ip_block); 466 int (*resume)(struct amdgpu_ip_block *ip_block); 467 void (*complete)(struct amdgpu_ip_block *ip_block); 468 bool (*is_idle)(struct amdgpu_ip_block *ip_block); 469 int (*wait_for_idle)(struct amdgpu_ip_block *ip_block); 470 bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block); 471 int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block); 472 int (*soft_reset)(struct amdgpu_ip_block *ip_block); 473 int (*post_soft_reset)(struct amdgpu_ip_block *ip_block); 474 int (*set_clockgating_state)(struct amdgpu_ip_block *ip_block, 475 enum amd_clockgating_state state); 476 int (*set_powergating_state)(struct amdgpu_ip_block *ip_block, 477 enum amd_powergating_state state); 478 void (*get_clockgating_state)(struct amdgpu_ip_block *ip_block, u64 *flags); 479 void (*dump_ip_state)(struct amdgpu_ip_block *ip_block); 480 void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p); 481 }; 482 483 484 #endif /* __AMD_SHARED_H__ */ 485