xref: /linux/drivers/gpu/drm/amd/display/modules/power/power_helpers.c (revision 2f28f0063a117d55dfa1672a1698cfe8fb2ee5c3)
1 /* Copyright 2018 Advanced Micro Devices, Inc.
2  *
3  * Permission is hereby granted, free of charge, to any person obtaining a
4  * copy of this software and associated documentation files (the "Software"),
5  * to deal in the Software without restriction, including without limitation
6  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7  * and/or sell copies of the Software, and to permit persons to whom the
8  * Software is furnished to do so, subject to the following conditions:
9  *
10  * The above copyright notice and this permission notice shall be included in
11  * all copies or substantial portions of the Software.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19  * OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * Authors: AMD
22  *
23  */
24 
25 #include "power_helpers.h"
26 #include "dc/inc/hw/dmcu.h"
27 #include "dc/inc/hw/abm.h"
28 #include "dc.h"
29 #include "core_types.h"
30 #include "dmub_cmd.h"
31 
32 #define DIV_ROUNDUP(a, b) (((a)+((b)/2))/(b))
33 #define bswap16_based_on_endian(big_endian, value) \
34 	((big_endian) ? cpu_to_be16(value) : cpu_to_le16(value))
35 
36 void init_replay_config(struct dc_link *link, struct replay_config *pr_config)
37 {
38 	link->replay_settings.config = *pr_config;
39 }
40 
41 bool mod_power_only_edp(const struct dc_state *context, const struct dc_stream_state *stream)
42 {
43 	return context && context->stream_count == 1 && dc_is_embedded_signal(stream->signal);
44 }
45 
46 void set_replay_frame_skip_number(struct dc_link *link,
47 	enum replay_coasting_vtotal_type type,
48 	uint32_t coasting_vtotal_refresh_rate_uhz,
49 	uint32_t flicker_free_refresh_rate_uhz,
50 	bool is_defer)
51 {
52 	uint32_t *frame_skip_number_array = NULL;
53 	uint32_t frame_skip_number = 0;
54 
55 	if (link == NULL)
56 		return;
57 
58 	if (false == link->replay_settings.config.frame_skip_supported)
59 		return;
60 
61 	if (flicker_free_refresh_rate_uhz == 0 || coasting_vtotal_refresh_rate_uhz == 0)
62 		return;
63 
64 	if (is_defer)
65 		frame_skip_number_array = link->replay_settings.defer_frame_skip_number_table;
66 	else
67 		frame_skip_number_array = link->replay_settings.frame_skip_number_table;
68 
69 	if (frame_skip_number_array == NULL)
70 		return;
71 
72 	frame_skip_number = (coasting_vtotal_refresh_rate_uhz + 500000) / flicker_free_refresh_rate_uhz;
73 
74 	if (frame_skip_number >= 1)
75 		frame_skip_number_array[type] = frame_skip_number - 1;
76 	else
77 		frame_skip_number_array[type] = 0;
78 }
79 
80 void set_replay_defer_update_coasting_vtotal(struct dc_link *link,
81 	enum replay_coasting_vtotal_type type,
82 	uint32_t vtotal)
83 {
84 	link->replay_settings.defer_update_coasting_vtotal_table[type] = vtotal;
85 }
86 
87 void update_replay_coasting_vtotal_from_defer(struct dc_link *link,
88 	enum replay_coasting_vtotal_type type)
89 {
90 	link->replay_settings.coasting_vtotal_table[type] =
91 		link->replay_settings.defer_update_coasting_vtotal_table[type];
92 	link->replay_settings.frame_skip_number_table[type] =
93 		link->replay_settings.defer_frame_skip_number_table[type];
94 }
95 
96 void set_replay_coasting_vtotal(struct dc_link *link,
97 	enum replay_coasting_vtotal_type type,
98 	uint32_t vtotal)
99 {
100 	link->replay_settings.coasting_vtotal_table[type] = vtotal;
101 }
102 
103 void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16_t vtotal)
104 {
105 	link->replay_settings.low_rr_full_screen_video_pseudo_vtotal = vtotal;
106 }
107 
108 void calculate_replay_link_off_frame_count(struct dc_link *link,
109 	uint16_t vtotal, uint16_t htotal)
110 {
111 	uint32_t max_link_off_frame_count = 0;
112 	uint16_t max_deviation_line = 0,  pixel_deviation_per_line = 0;
113 
114 	if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY)
115 		return;
116 
117 	max_deviation_line = link->dpcd_caps.pr_info.max_deviation_line;
118 	pixel_deviation_per_line = link->dpcd_caps.pr_info.pixel_deviation_per_line;
119 
120 	if (htotal != 0 && vtotal != 0 && pixel_deviation_per_line != 0)
121 		max_link_off_frame_count = htotal * max_deviation_line / (pixel_deviation_per_line * vtotal);
122 	else
123 		ASSERT(0);
124 
125 	link->replay_settings.link_off_frame_count = max_link_off_frame_count;
126 }
127 
128 void reset_replay_dsync_error_count(struct dc_link *link)
129 {
130 	link->replay_settings.replay_desync_error_fail_count = 0;
131 }
132