xref: /linux/drivers/gpu/drm/amd/display/modules/freesync/freesync.c (revision b9c8ad73480dc692b9d0c7b50da4964628a733fd)
1 /*
2  * Copyright 2016-2023 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "mod_freesync.h"
29 #include "core_types.h"
30 
31 #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS  32
32 
33 #define MIN_REFRESH_RANGE 10
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
35 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65)
36 /* Number of elements in the render times cache array */
37 #define RENDER_TIMES_MAX_COUNT 10
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
39 #define BTR_MAX_MARGIN 2500
40 /* Threshold to change BTR multiplier (to avoid frequent changes) */
41 #define BTR_DRIFT_MARGIN 2000
42 /* Threshold to exit fixed refresh rate */
43 #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
45 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5
46 #define FIXED_REFRESH_EXIT_FRAME_COUNT 10
47 /* Flip interval workaround constants */
48 #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2
49 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5
50 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500
51 #define MICRO_HZ_TO_HZ(x) (x / 1000000)
52 
53 struct core_freesync {
54 	struct mod_freesync public;
55 	struct dc *dc;
56 };
57 
58 #define MOD_FREESYNC_TO_CORE(mod_freesync)\
59 		container_of(mod_freesync, struct core_freesync, public)
60 
61 struct mod_freesync *mod_freesync_create(struct dc *dc)
62 {
63 	struct core_freesync *core_freesync =
64 			kzalloc(sizeof(struct core_freesync), GFP_KERNEL);
65 
66 	if (core_freesync == NULL)
67 		goto fail_alloc_context;
68 
69 	if (dc == NULL)
70 		goto fail_construct;
71 
72 	core_freesync->dc = dc;
73 	return &core_freesync->public;
74 
75 fail_construct:
76 	kfree(core_freesync);
77 
78 fail_alloc_context:
79 	return NULL;
80 }
81 
82 void mod_freesync_destroy(struct mod_freesync *mod_freesync)
83 {
84 	struct core_freesync *core_freesync = NULL;
85 
86 	if (mod_freesync == NULL)
87 		return;
88 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
89 	kfree(core_freesync);
90 }
91 
92 #if 0 /* Unused currently */
93 static unsigned int calc_refresh_in_uhz_from_duration(
94 		unsigned int duration_in_ns)
95 {
96 	unsigned int refresh_in_uhz =
97 			((unsigned int)(div64_u64((1000000000ULL * 1000000),
98 					duration_in_ns)));
99 	return refresh_in_uhz;
100 }
101 #endif
102 
103 static unsigned int calc_duration_in_us_from_refresh_in_uhz(
104 		unsigned int refresh_in_uhz)
105 {
106 	unsigned int duration_in_us =
107 			((unsigned int)(div64_u64((1000000000ULL * 1000),
108 					refresh_in_uhz)));
109 	return duration_in_us;
110 }
111 
112 static unsigned int calc_duration_in_us_from_v_total(
113 		const struct dc_stream_state *stream,
114 		const struct mod_vrr_params *in_vrr,
115 		unsigned int v_total)
116 {
117 	unsigned int duration_in_us =
118 			(unsigned int)(div64_u64(((unsigned long long)(v_total)
119 				* 10000) * stream->timing.h_total,
120 					stream->timing.pix_clk_100hz));
121 
122 	return duration_in_us;
123 }
124 
125 unsigned int mod_freesync_calc_v_total_from_refresh(
126 		const struct dc_stream_state *stream,
127 		unsigned int refresh_in_uhz)
128 {
129 	unsigned int v_total;
130 	unsigned int frame_duration_in_ns;
131 
132 	frame_duration_in_ns =
133 			((unsigned int)(div64_u64((1000000000ULL * 1000000),
134 					refresh_in_uhz)));
135 
136 	if (MICRO_HZ_TO_HZ(refresh_in_uhz) <= stream->timing.min_refresh_in_uhz) {
137 		/* When the target refresh rate is the minimum panel refresh rate,
138 		 * round down the vtotal value to avoid stretching vblank over
139 		 * panel's vtotal boundary.
140 		 */
141 		v_total = div64_u64(div64_u64(((unsigned long long)(
142 				frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
143 				stream->timing.h_total), 1000000);
144 	} else {
145 		v_total = div64_u64(div64_u64(((unsigned long long)(
146 				frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)),
147 				stream->timing.h_total) + 500000, 1000000);
148 	}
149 
150 	/* v_total cannot be less than nominal */
151 	if (v_total < stream->timing.v_total) {
152 		ASSERT(v_total < stream->timing.v_total);
153 		v_total = stream->timing.v_total;
154 	}
155 
156 	return v_total;
157 }
158 
159 static unsigned int calc_v_total_from_duration(
160 		const struct dc_stream_state *stream,
161 		const struct mod_vrr_params *vrr,
162 		unsigned int duration_in_us)
163 {
164 	unsigned int v_total = 0;
165 
166 	if (duration_in_us < vrr->min_duration_in_us)
167 		duration_in_us = vrr->min_duration_in_us;
168 
169 	if (duration_in_us > vrr->max_duration_in_us)
170 		duration_in_us = vrr->max_duration_in_us;
171 
172 	if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec
173 		uint32_t h_total_up_scaled;
174 
175 		h_total_up_scaled = stream->timing.h_total * 10000;
176 		v_total = div_u64((unsigned long long)duration_in_us
177 					* stream->timing.pix_clk_100hz + (h_total_up_scaled - 1),
178 					h_total_up_scaled); //ceiling for MMax and MMin for MVRR
179 	} else {
180 		v_total = div64_u64(div64_u64(((unsigned long long)(
181 					duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
182 					stream->timing.h_total), 1000);
183 	}
184 
185 	/* v_total cannot be less than nominal */
186 	if (v_total < stream->timing.v_total) {
187 		ASSERT(v_total < stream->timing.v_total);
188 		v_total = stream->timing.v_total;
189 	}
190 
191 	return v_total;
192 }
193 
194 static void update_v_total_for_static_ramp(
195 		struct core_freesync *core_freesync,
196 		const struct dc_stream_state *stream,
197 		struct mod_vrr_params *in_out_vrr)
198 {
199 	unsigned int v_total = 0;
200 	unsigned int current_duration_in_us =
201 			calc_duration_in_us_from_v_total(
202 				stream, in_out_vrr,
203 				in_out_vrr->adjust.v_total_max);
204 	unsigned int target_duration_in_us =
205 			calc_duration_in_us_from_refresh_in_uhz(
206 				in_out_vrr->fixed.target_refresh_in_uhz);
207 	bool ramp_direction_is_up = (current_duration_in_us >
208 				target_duration_in_us) ? true : false;
209 
210 	/* Calculate ratio between new and current frame duration with 3 digit */
211 	unsigned int frame_duration_ratio = div64_u64(1000000,
212 		(1000 +  div64_u64(((unsigned long long)(
213 		STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) *
214 		current_duration_in_us),
215 		1000000)));
216 
217 	/* Calculate delta between new and current frame duration in us */
218 	unsigned int frame_duration_delta = div64_u64(((unsigned long long)(
219 		current_duration_in_us) *
220 		(1000 - frame_duration_ratio)), 1000);
221 
222 	/* Adjust frame duration delta based on ratio between current and
223 	 * standard frame duration (frame duration at 60 Hz refresh rate).
224 	 */
225 	unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)(
226 		frame_duration_delta) * current_duration_in_us), 16666);
227 
228 	/* Going to a higher refresh rate (lower frame duration) */
229 	if (ramp_direction_is_up) {
230 		/* Reduce frame duration */
231 		current_duration_in_us -= ramp_rate_interpolated;
232 
233 		/* Adjust for frame duration below min */
234 		if (current_duration_in_us <= target_duration_in_us) {
235 			in_out_vrr->fixed.ramping_active = false;
236 			in_out_vrr->fixed.ramping_done = true;
237 			current_duration_in_us =
238 				calc_duration_in_us_from_refresh_in_uhz(
239 				in_out_vrr->fixed.target_refresh_in_uhz);
240 		}
241 	/* Going to a lower refresh rate (larger frame duration) */
242 	} else {
243 		/* Increase frame duration */
244 		current_duration_in_us += ramp_rate_interpolated;
245 
246 		/* Adjust for frame duration above max */
247 		if (current_duration_in_us >= target_duration_in_us) {
248 			in_out_vrr->fixed.ramping_active = false;
249 			in_out_vrr->fixed.ramping_done = true;
250 			current_duration_in_us =
251 				calc_duration_in_us_from_refresh_in_uhz(
252 				in_out_vrr->fixed.target_refresh_in_uhz);
253 		}
254 	}
255 
256 	v_total = div64_u64(div64_u64(((unsigned long long)(
257 			current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)),
258 				stream->timing.h_total), 1000);
259 
260 	/* v_total cannot be less than nominal */
261 	if (v_total < stream->timing.v_total)
262 		v_total = stream->timing.v_total;
263 
264 	in_out_vrr->adjust.v_total_min = v_total;
265 	in_out_vrr->adjust.v_total_max = v_total;
266 }
267 
268 static void apply_below_the_range(struct core_freesync *core_freesync,
269 		const struct dc_stream_state *stream,
270 		unsigned int last_render_time_in_us,
271 		struct mod_vrr_params *in_out_vrr)
272 {
273 	unsigned int inserted_frame_duration_in_us = 0;
274 	unsigned int mid_point_frames_ceil = 0;
275 	unsigned int mid_point_frames_floor = 0;
276 	unsigned int frame_time_in_us = 0;
277 	unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF;
278 	unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF;
279 	unsigned int frames_to_insert = 0;
280 	unsigned int delta_from_mid_point_delta_in_us;
281 	unsigned int max_render_time_in_us =
282 			in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us;
283 
284 	/* Program BTR */
285 	if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) {
286 		/* Exit Below the Range */
287 		if (in_out_vrr->btr.btr_active) {
288 			in_out_vrr->btr.frame_counter = 0;
289 			in_out_vrr->btr.btr_active = false;
290 		}
291 	} else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) {
292 		/* Enter Below the Range */
293 		if (!in_out_vrr->btr.btr_active)
294 			in_out_vrr->btr.btr_active = true;
295 	}
296 
297 	/* BTR set to "not active" so disengage */
298 	if (!in_out_vrr->btr.btr_active) {
299 		in_out_vrr->btr.inserted_duration_in_us = 0;
300 		in_out_vrr->btr.frames_to_insert = 0;
301 		in_out_vrr->btr.frame_counter = 0;
302 
303 		/* Restore FreeSync */
304 		in_out_vrr->adjust.v_total_min =
305 			mod_freesync_calc_v_total_from_refresh(stream,
306 				in_out_vrr->max_refresh_in_uhz);
307 		in_out_vrr->adjust.v_total_max =
308 			mod_freesync_calc_v_total_from_refresh(stream,
309 				in_out_vrr->min_refresh_in_uhz);
310 	/* BTR set to "active" so engage */
311 	} else {
312 
313 		/* Calculate number of midPoint frames that could fit within
314 		 * the render time interval - take ceil of this value
315 		 */
316 		mid_point_frames_ceil = (last_render_time_in_us +
317 				in_out_vrr->btr.mid_point_in_us - 1) /
318 					in_out_vrr->btr.mid_point_in_us;
319 
320 		if (mid_point_frames_ceil > 0) {
321 			frame_time_in_us = last_render_time_in_us /
322 				mid_point_frames_ceil;
323 			delta_from_mid_point_in_us_1 =
324 				(in_out_vrr->btr.mid_point_in_us >
325 				frame_time_in_us) ?
326 				(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
327 				(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
328 		}
329 
330 		/* Calculate number of midPoint frames that could fit within
331 		 * the render time interval - take floor of this value
332 		 */
333 		mid_point_frames_floor = last_render_time_in_us /
334 				in_out_vrr->btr.mid_point_in_us;
335 
336 		if (mid_point_frames_floor > 0) {
337 
338 			frame_time_in_us = last_render_time_in_us /
339 				mid_point_frames_floor;
340 			delta_from_mid_point_in_us_2 =
341 				(in_out_vrr->btr.mid_point_in_us >
342 				frame_time_in_us) ?
343 				(in_out_vrr->btr.mid_point_in_us - frame_time_in_us) :
344 				(frame_time_in_us - in_out_vrr->btr.mid_point_in_us);
345 		}
346 
347 		/* Choose number of frames to insert based on how close it
348 		 * can get to the mid point of the variable range.
349 		 *  - Delta for CEIL: delta_from_mid_point_in_us_1
350 		 *  - Delta for FLOOR: delta_from_mid_point_in_us_2
351 		 */
352 		if (mid_point_frames_ceil &&
353 		    (last_render_time_in_us / mid_point_frames_ceil) <
354 		    in_out_vrr->min_duration_in_us) {
355 			/* Check for out of range.
356 			 * If using CEIL produces a value that is out of range,
357 			 * then we are forced to use FLOOR.
358 			 */
359 			frames_to_insert = mid_point_frames_floor;
360 		} else if (mid_point_frames_floor < 2) {
361 			/* Check if FLOOR would result in non-LFC. In this case
362 			 * choose to use CEIL
363 			 */
364 			frames_to_insert = mid_point_frames_ceil;
365 		} else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
366 			/* If choosing CEIL results in a frame duration that is
367 			 * closer to the mid point of the range.
368 			 * Choose CEIL
369 			 */
370 			frames_to_insert = mid_point_frames_ceil;
371 		} else {
372 			/* If choosing FLOOR results in a frame duration that is
373 			 * closer to the mid point of the range.
374 			 * Choose FLOOR
375 			 */
376 			frames_to_insert = mid_point_frames_floor;
377 		}
378 
379 		/* Prefer current frame multiplier when BTR is enabled unless it drifts
380 		 * too far from the midpoint
381 		 */
382 		if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) {
383 			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 -
384 					delta_from_mid_point_in_us_1;
385 		} else {
386 			delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 -
387 					delta_from_mid_point_in_us_2;
388 		}
389 		if (in_out_vrr->btr.frames_to_insert != 0 &&
390 				delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) {
391 			if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) <
392 					max_render_time_in_us) &&
393 				((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) >
394 					in_out_vrr->min_duration_in_us))
395 				frames_to_insert = in_out_vrr->btr.frames_to_insert;
396 		}
397 
398 		/* Either we've calculated the number of frames to insert,
399 		 * or we need to insert min duration frames
400 		 */
401 		if (frames_to_insert &&
402 		    (last_render_time_in_us / frames_to_insert) <
403 		    in_out_vrr->min_duration_in_us){
404 			frames_to_insert -= (frames_to_insert > 1) ?
405 					1 : 0;
406 		}
407 
408 		if (frames_to_insert > 0)
409 			inserted_frame_duration_in_us = last_render_time_in_us /
410 							frames_to_insert;
411 
412 		if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us)
413 			inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us;
414 
415 		/* Cache the calculated variables */
416 		in_out_vrr->btr.inserted_duration_in_us =
417 			inserted_frame_duration_in_us;
418 		in_out_vrr->btr.frames_to_insert = frames_to_insert;
419 		in_out_vrr->btr.frame_counter = frames_to_insert;
420 	}
421 }
422 
423 static void apply_fixed_refresh(struct core_freesync *core_freesync,
424 		const struct dc_stream_state *stream,
425 		unsigned int last_render_time_in_us,
426 		struct mod_vrr_params *in_out_vrr)
427 {
428 	bool update = false;
429 	unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us;
430 
431 	/* Compute the exit refresh rate and exit frame duration */
432 	unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us)
433 			+ (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ));
434 	unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz;
435 
436 	if (last_render_time_in_us < exit_frame_duration_in_us) {
437 		/* Exit Fixed Refresh mode */
438 		if (in_out_vrr->fixed.fixed_active) {
439 			in_out_vrr->fixed.frame_counter++;
440 
441 			if (in_out_vrr->fixed.frame_counter >
442 					FIXED_REFRESH_EXIT_FRAME_COUNT) {
443 				in_out_vrr->fixed.frame_counter = 0;
444 				in_out_vrr->fixed.fixed_active = false;
445 				in_out_vrr->fixed.target_refresh_in_uhz = 0;
446 				update = true;
447 			}
448 		} else
449 			in_out_vrr->fixed.frame_counter = 0;
450 	} else if (last_render_time_in_us > max_render_time_in_us) {
451 		/* Enter Fixed Refresh mode */
452 		if (!in_out_vrr->fixed.fixed_active) {
453 			in_out_vrr->fixed.frame_counter++;
454 
455 			if (in_out_vrr->fixed.frame_counter >
456 					FIXED_REFRESH_ENTER_FRAME_COUNT) {
457 				in_out_vrr->fixed.frame_counter = 0;
458 				in_out_vrr->fixed.fixed_active = true;
459 				in_out_vrr->fixed.target_refresh_in_uhz =
460 						in_out_vrr->max_refresh_in_uhz;
461 				update = true;
462 			}
463 		} else
464 			in_out_vrr->fixed.frame_counter = 0;
465 	}
466 
467 	if (update) {
468 		if (in_out_vrr->fixed.fixed_active) {
469 			in_out_vrr->adjust.v_total_min =
470 				mod_freesync_calc_v_total_from_refresh(
471 				stream, in_out_vrr->max_refresh_in_uhz);
472 			in_out_vrr->adjust.v_total_max =
473 					in_out_vrr->adjust.v_total_min;
474 		} else {
475 			in_out_vrr->adjust.v_total_min =
476 				mod_freesync_calc_v_total_from_refresh(stream,
477 					in_out_vrr->max_refresh_in_uhz);
478 			in_out_vrr->adjust.v_total_max =
479 				mod_freesync_calc_v_total_from_refresh(stream,
480 					in_out_vrr->min_refresh_in_uhz);
481 		}
482 	}
483 }
484 
485 static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr,
486 		unsigned int curr_time_stamp_in_us)
487 {
488 	in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us -
489 			in_vrr->flip_interval.v_update_timestamp_in_us;
490 
491 	/* Determine conditions for stopping workaround */
492 	if (in_vrr->flip_interval.flip_interval_workaround_active &&
493 			in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD &&
494 			in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
495 		in_vrr->flip_interval.flip_interval_detect_counter = 0;
496 		in_vrr->flip_interval.program_flip_interval_workaround = true;
497 		in_vrr->flip_interval.flip_interval_workaround_active = false;
498 	} else {
499 		/* Determine conditions for starting workaround */
500 		if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD &&
501 				in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) {
502 			/* Increase flip interval counter we have 2 vsyncs between flips and
503 			 * vsync to flip interval is less than 500us
504 			 */
505 			in_vrr->flip_interval.flip_interval_detect_counter++;
506 			if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) {
507 				/* Start workaround if we detect 5 consecutive instances of the above case */
508 				in_vrr->flip_interval.program_flip_interval_workaround = true;
509 				in_vrr->flip_interval.flip_interval_workaround_active = true;
510 			}
511 		} else {
512 			/* Reset the flip interval counter if we condition is no longer met */
513 			in_vrr->flip_interval.flip_interval_detect_counter = 0;
514 		}
515 	}
516 
517 	in_vrr->flip_interval.vsyncs_between_flip = 0;
518 }
519 
520 static bool vrr_settings_require_update(struct core_freesync *core_freesync,
521 		struct mod_freesync_config *in_config,
522 		unsigned int min_refresh_in_uhz,
523 		unsigned int max_refresh_in_uhz,
524 		struct mod_vrr_params *in_vrr)
525 {
526 	if (in_vrr->state != in_config->state) {
527 		return true;
528 	} else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED &&
529 			in_vrr->fixed.target_refresh_in_uhz !=
530 					in_config->fixed_refresh_in_uhz) {
531 		return true;
532 	} else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) {
533 		return true;
534 	} else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) {
535 		return true;
536 	}
537 
538 	return false;
539 }
540 
541 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
542 		const struct dc_stream_state *stream,
543 		unsigned int *vmin,
544 		unsigned int *vmax)
545 {
546 	*vmin = stream->adjust.v_total_min;
547 	*vmax = stream->adjust.v_total_max;
548 
549 	return true;
550 }
551 
552 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
553 		struct dc_stream_state *stream,
554 		unsigned int *nom_v_pos,
555 		unsigned int *v_pos)
556 {
557 	struct core_freesync *core_freesync = NULL;
558 	struct crtc_position position;
559 
560 	if (mod_freesync == NULL)
561 		return false;
562 
563 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
564 
565 	if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1,
566 					&position.vertical_count,
567 					&position.nominal_vcount)) {
568 
569 		*nom_v_pos = position.nominal_vcount;
570 		*v_pos = position.vertical_count;
571 
572 		return true;
573 	}
574 
575 	return false;
576 }
577 
578 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr,
579 		struct dc_info_packet *infopacket,
580 		bool freesync_on_desktop)
581 {
582 	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
583 	infopacket->sb[1] = 0x1A;
584 
585 	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
586 	infopacket->sb[2] = 0x00;
587 
588 	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
589 	infopacket->sb[3] = 0x00;
590 
591 	/* PB4 = Reserved */
592 
593 	/* PB5 = Reserved */
594 
595 	/* PB6 = [Bits 7:3 = Reserved] */
596 
597 	/* PB6 = [Bit 0 = FreeSync Supported] */
598 	if (vrr->state != VRR_STATE_UNSUPPORTED)
599 		infopacket->sb[6] |= 0x01;
600 
601 	/* PB6 = [Bit 1 = FreeSync Enabled] */
602 	if (vrr->state != VRR_STATE_DISABLED &&
603 			vrr->state != VRR_STATE_UNSUPPORTED)
604 		infopacket->sb[6] |= 0x02;
605 
606 	if (freesync_on_desktop) {
607 		/* PB6 = [Bit 2 = FreeSync Active] */
608 		if (vrr->state != VRR_STATE_DISABLED &&
609 			vrr->state != VRR_STATE_UNSUPPORTED)
610 			infopacket->sb[6] |= 0x04;
611 	} else {
612 		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
613 			vrr->state == VRR_STATE_ACTIVE_FIXED)
614 			infopacket->sb[6] |= 0x04;
615 	}
616 
617 	// For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range
618 	/* PB7 = FreeSync Minimum refresh rate (Hz) */
619 	if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
620 			vrr->state == VRR_STATE_ACTIVE_FIXED) {
621 		infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000);
622 	} else {
623 		infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
624 	}
625 
626 	/* PB8 = FreeSync Maximum refresh rate (Hz)
627 	 * Note: We should never go above the field rate of the mode timing set.
628 	 */
629 	infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000);
630 }
631 
632 static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr,
633 		struct dc_info_packet *infopacket,
634 		bool freesync_on_desktop)
635 {
636 	unsigned int min_refresh;
637 	unsigned int max_refresh;
638 	unsigned int fixed_refresh;
639 	unsigned int min_programmed;
640 
641 	/* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */
642 	infopacket->sb[1] = 0x1A;
643 
644 	/* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */
645 	infopacket->sb[2] = 0x00;
646 
647 	/* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */
648 	infopacket->sb[3] = 0x00;
649 
650 	/* PB4 = Reserved */
651 
652 	/* PB5 = Reserved */
653 
654 	/* PB6 = [Bits 7:3 = Reserved] */
655 
656 	/* PB6 = [Bit 0 = FreeSync Supported] */
657 	if (vrr->state != VRR_STATE_UNSUPPORTED)
658 		infopacket->sb[6] |= 0x01;
659 
660 	/* PB6 = [Bit 1 = FreeSync Enabled] */
661 	if (vrr->state != VRR_STATE_DISABLED &&
662 			vrr->state != VRR_STATE_UNSUPPORTED)
663 		infopacket->sb[6] |= 0x02;
664 
665 	/* PB6 = [Bit 2 = FreeSync Active] */
666 	if (freesync_on_desktop) {
667 		if (vrr->state != VRR_STATE_DISABLED &&
668 			vrr->state != VRR_STATE_UNSUPPORTED)
669 			infopacket->sb[6] |= 0x04;
670 	} else {
671 		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE ||
672 			vrr->state == VRR_STATE_ACTIVE_FIXED)
673 			infopacket->sb[6] |= 0x04;
674 	}
675 
676 	min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000;
677 	max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000;
678 	fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000;
679 
680 	min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh :
681 			(vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh :
682 			(vrr->state == VRR_STATE_INACTIVE) ? min_refresh :
683 			max_refresh; // Non-fs case, program nominal range
684 
685 	/* PB7 = FreeSync Minimum refresh rate (Hz) */
686 	infopacket->sb[7] = min_programmed & 0xFF;
687 
688 	/* PB8 = FreeSync Maximum refresh rate (Hz) */
689 	infopacket->sb[8] = max_refresh & 0xFF;
690 
691 	/* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */
692 	infopacket->sb[11] = (min_programmed >> 8) & 0x03;
693 
694 	/* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */
695 	infopacket->sb[12] = (max_refresh >> 8) & 0x03;
696 
697 	/* PB16 : Reserved bits 7:1, FixedRate bit 0 */
698 	infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0;
699 }
700 
701 static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf,
702 		struct dc_info_packet *infopacket)
703 {
704 	if (app_tf != TRANSFER_FUNC_UNKNOWN) {
705 		infopacket->valid = true;
706 
707 		if (app_tf == TRANSFER_FUNC_PQ2084)
708 			infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active]
709 		else {
710 			infopacket->sb[6] |= 0x08;  // PB6 = [Bit 3 = Native Color Active]
711 			if (app_tf == TRANSFER_FUNC_GAMMA_22)
712 				infopacket->sb[9] |= 0x04;  // PB9 = [Bit 2 = Gamma 2.2 EOTF Active]
713 		}
714 	}
715 }
716 
717 static void build_vrr_infopacket_header_v1(enum signal_type signal,
718 		struct dc_info_packet *infopacket,
719 		unsigned int *payload_size)
720 {
721 	if (dc_is_hdmi_signal(signal)) {
722 
723 		/* HEADER */
724 
725 		/* HB0  = Packet Type = 0x83 (Source Product
726 		 *	  Descriptor InfoFrame)
727 		 */
728 		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
729 
730 		/* HB1  = Version = 0x01 */
731 		infopacket->hb1 = 0x01;
732 
733 		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */
734 		infopacket->hb2 = 0x08;
735 
736 		*payload_size = 0x08;
737 
738 	} else if (dc_is_dp_signal(signal)) {
739 
740 		/* HEADER */
741 
742 		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
743 		 *	  when used to associate audio related info packets
744 		 */
745 		infopacket->hb0 = 0x00;
746 
747 		/* HB1  = Packet Type = 0x83 (Source Product
748 		 *	  Descriptor InfoFrame)
749 		 */
750 		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
751 
752 		/* HB2  = [Bits 7:0 = Least significant eight bits -
753 		 *	  For INFOFRAME, the value must be 1Bh]
754 		 */
755 		infopacket->hb2 = 0x1B;
756 
757 		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1]
758 		 *	  [Bits 1:0 = Most significant two bits = 0x00]
759 		 */
760 		infopacket->hb3 = 0x04;
761 
762 		*payload_size = 0x1B;
763 	}
764 }
765 
766 static void build_vrr_infopacket_header_v2(enum signal_type signal,
767 		struct dc_info_packet *infopacket,
768 		unsigned int *payload_size)
769 {
770 	if (dc_is_hdmi_signal(signal)) {
771 
772 		/* HEADER */
773 
774 		/* HB0  = Packet Type = 0x83 (Source Product
775 		 *	  Descriptor InfoFrame)
776 		 */
777 		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
778 
779 		/* HB1  = Version = 0x02 */
780 		infopacket->hb1 = 0x02;
781 
782 		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */
783 		infopacket->hb2 = 0x09;
784 
785 		*payload_size = 0x09;
786 	} else if (dc_is_dp_signal(signal)) {
787 
788 		/* HEADER */
789 
790 		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
791 		 *	  when used to associate audio related info packets
792 		 */
793 		infopacket->hb0 = 0x00;
794 
795 		/* HB1  = Packet Type = 0x83 (Source Product
796 		 *	  Descriptor InfoFrame)
797 		 */
798 		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
799 
800 		/* HB2  = [Bits 7:0 = Least significant eight bits -
801 		 *	  For INFOFRAME, the value must be 1Bh]
802 		 */
803 		infopacket->hb2 = 0x1B;
804 
805 		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
806 		 *	  [Bits 1:0 = Most significant two bits = 0x00]
807 		 */
808 		infopacket->hb3 = 0x08;
809 
810 		*payload_size = 0x1B;
811 	}
812 }
813 
814 static void build_vrr_infopacket_header_v3(enum signal_type signal,
815 		struct dc_info_packet *infopacket,
816 		unsigned int *payload_size)
817 {
818 	unsigned char version;
819 
820 	version = 3;
821 	if (dc_is_hdmi_signal(signal)) {
822 
823 		/* HEADER */
824 
825 		/* HB0  = Packet Type = 0x83 (Source Product
826 		 *	  Descriptor InfoFrame)
827 		 */
828 		infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD;
829 
830 		/* HB1  = Version = 0x03 */
831 		infopacket->hb1 = version;
832 
833 		/* HB2  = [Bits 7:5 = 0] [Bits 4:0 = Length] */
834 		infopacket->hb2 = 0x10;
835 
836 		*payload_size = 0x10;
837 	} else if (dc_is_dp_signal(signal)) {
838 
839 		/* HEADER */
840 
841 		/* HB0  = Secondary-data Packet ID = 0 - Only non-zero
842 		 *	  when used to associate audio related info packets
843 		 */
844 		infopacket->hb0 = 0x00;
845 
846 		/* HB1  = Packet Type = 0x83 (Source Product
847 		 *	  Descriptor InfoFrame)
848 		 */
849 		infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD;
850 
851 		/* HB2  = [Bits 7:0 = Least significant eight bits -
852 		 *	  For INFOFRAME, the value must be 1Bh]
853 		 */
854 		infopacket->hb2 = 0x1B;
855 
856 		/* HB3  = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2]
857 		 *	  [Bits 1:0 = Most significant two bits = 0x00]
858 		 */
859 
860 		infopacket->hb3 = (version & 0x3F) << 2;
861 
862 		*payload_size = 0x1B;
863 	}
864 }
865 
866 static void build_vrr_infopacket_checksum(unsigned int *payload_size,
867 		struct dc_info_packet *infopacket)
868 {
869 	/* Calculate checksum */
870 	unsigned int idx = 0;
871 	unsigned char checksum = 0;
872 
873 	checksum += infopacket->hb0;
874 	checksum += infopacket->hb1;
875 	checksum += infopacket->hb2;
876 	checksum += infopacket->hb3;
877 
878 	for (idx = 1; idx <= *payload_size; idx++)
879 		checksum += infopacket->sb[idx];
880 
881 	/* PB0 = Checksum (one byte complement) */
882 	infopacket->sb[0] = (unsigned char)(0x100 - checksum);
883 
884 	infopacket->valid = true;
885 }
886 
887 static void build_vrr_infopacket_v1(enum signal_type signal,
888 		const struct mod_vrr_params *vrr,
889 		struct dc_info_packet *infopacket,
890 		bool freesync_on_desktop)
891 {
892 	/* SPD info packet for FreeSync */
893 	unsigned int payload_size = 0;
894 
895 	build_vrr_infopacket_header_v1(signal, infopacket, &payload_size);
896 	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
897 	build_vrr_infopacket_checksum(&payload_size, infopacket);
898 
899 	infopacket->valid = true;
900 }
901 
902 static void build_vrr_infopacket_v2(enum signal_type signal,
903 		const struct mod_vrr_params *vrr,
904 		enum color_transfer_func app_tf,
905 		struct dc_info_packet *infopacket,
906 		bool freesync_on_desktop)
907 {
908 	unsigned int payload_size = 0;
909 
910 	build_vrr_infopacket_header_v2(signal, infopacket, &payload_size);
911 	build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop);
912 
913 	build_vrr_infopacket_fs2_data(app_tf, infopacket);
914 
915 	build_vrr_infopacket_checksum(&payload_size, infopacket);
916 
917 	infopacket->valid = true;
918 }
919 
920 static void build_vrr_infopacket_v3(enum signal_type signal,
921 		const struct mod_vrr_params *vrr,
922 		enum color_transfer_func app_tf,
923 		struct dc_info_packet *infopacket,
924 		bool freesync_on_desktop)
925 {
926 	unsigned int payload_size = 0;
927 
928 	build_vrr_infopacket_header_v3(signal, infopacket, &payload_size);
929 	build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop);
930 
931 	build_vrr_infopacket_fs2_data(app_tf, infopacket);
932 
933 	build_vrr_infopacket_checksum(&payload_size, infopacket);
934 
935 	infopacket->valid = true;
936 }
937 
938 static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type,
939 										struct dc_info_packet *infopacket)
940 {
941 	uint8_t idx = 0, size = 0;
942 
943 	size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 :
944 			(packet_type == PACKET_TYPE_FS_V3) ? 0x10 :
945 												0x09);
946 
947 	for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B
948 		infopacket->sb[idx] = infopacket->sb[idx-1];
949 
950 	infopacket->sb[1] = size;                         // Length
951 	infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version
952 	infopacket->hb3   = (0x13 << 2);                  // Header,SDP 1.3
953 	infopacket->hb2   = 0x1D;
954 }
955 
956 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync,
957 		const struct dc_stream_state *stream,
958 		const struct mod_vrr_params *vrr,
959 		enum vrr_packet_type packet_type,
960 		enum color_transfer_func app_tf,
961 		struct dc_info_packet *infopacket,
962 		bool pack_sdp_v1_3)
963 {
964 	/* SPD info packet for FreeSync
965 	 * VTEM info packet for HdmiVRR
966 	 * Check if Freesync is supported. Return if false. If true,
967 	 * set the corresponding bit in the info packet
968 	 */
969 	if (!vrr->send_info_frame)
970 		return;
971 
972 	switch (packet_type) {
973 	case PACKET_TYPE_FS_V3:
974 		build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
975 		break;
976 	case PACKET_TYPE_FS_V2:
977 		build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop);
978 		break;
979 	case PACKET_TYPE_VRR:
980 	case PACKET_TYPE_FS_V1:
981 	default:
982 		build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop);
983 	}
984 
985 	if (true == pack_sdp_v1_3 &&
986 		true == dc_is_dp_signal(stream->signal) &&
987 		packet_type != PACKET_TYPE_VRR &&
988 		packet_type != PACKET_TYPE_VTEM)
989 		build_vrr_infopacket_sdp_v1_3(packet_type, infopacket);
990 }
991 
992 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync,
993 		const struct dc_stream_state *stream,
994 		struct mod_freesync_config *in_config,
995 		struct mod_vrr_params *in_out_vrr)
996 {
997 	struct core_freesync *core_freesync = NULL;
998 	unsigned long long nominal_field_rate_in_uhz = 0;
999 	unsigned long long rounded_nominal_in_uhz = 0;
1000 	unsigned int refresh_range = 0;
1001 	unsigned long long min_refresh_in_uhz = 0;
1002 	unsigned long long max_refresh_in_uhz = 0;
1003 	unsigned long long min_hardware_refresh_in_uhz = 0;
1004 
1005 	if (mod_freesync == NULL)
1006 		return;
1007 
1008 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1009 
1010 	/* Calculate nominal field rate for stream */
1011 	nominal_field_rate_in_uhz =
1012 			mod_freesync_calc_nominal_field_rate(stream);
1013 
1014 	if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) {
1015 		min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL),
1016 			(stream->timing.h_total * (long long)stream->ctx->dc->caps.max_v_total));
1017 	}
1018 	/* Limit minimum refresh rate to what can be supported by hardware */
1019 	min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ?
1020 		min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz;
1021 	max_refresh_in_uhz = in_config->max_refresh_in_uhz;
1022 
1023 	/* Full range may be larger than current video timing, so cap at nominal */
1024 	if (max_refresh_in_uhz > nominal_field_rate_in_uhz)
1025 		max_refresh_in_uhz = nominal_field_rate_in_uhz;
1026 
1027 	/* Full range may be larger than current video timing, so cap at nominal */
1028 	if (min_refresh_in_uhz > max_refresh_in_uhz)
1029 		min_refresh_in_uhz = max_refresh_in_uhz;
1030 
1031 	/* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */
1032 	rounded_nominal_in_uhz =
1033 			div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000;
1034 	if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) &&
1035 		in_config->max_refresh_in_uhz == rounded_nominal_in_uhz)
1036 		min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2);
1037 
1038 	if (!vrr_settings_require_update(core_freesync,
1039 			in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz,
1040 			in_out_vrr))
1041 		return;
1042 
1043 	in_out_vrr->state = in_config->state;
1044 	in_out_vrr->send_info_frame = in_config->vsif_supported;
1045 
1046 	if (in_config->state == VRR_STATE_UNSUPPORTED) {
1047 		in_out_vrr->state = VRR_STATE_UNSUPPORTED;
1048 		in_out_vrr->supported = false;
1049 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1050 		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1051 
1052 		return;
1053 
1054 	} else {
1055 		in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz;
1056 		in_out_vrr->max_duration_in_us =
1057 				calc_duration_in_us_from_refresh_in_uhz(
1058 						(unsigned int)min_refresh_in_uhz);
1059 
1060 		in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz;
1061 		in_out_vrr->min_duration_in_us =
1062 				calc_duration_in_us_from_refresh_in_uhz(
1063 						(unsigned int)max_refresh_in_uhz);
1064 
1065 		if (in_config->state == VRR_STATE_ACTIVE_FIXED)
1066 			in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz;
1067 		else
1068 			in_out_vrr->fixed_refresh_in_uhz = 0;
1069 
1070 		refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) -
1071 				div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000);
1072 
1073 		in_out_vrr->supported = true;
1074 	}
1075 
1076 	in_out_vrr->fixed.ramping_active = in_config->ramping;
1077 
1078 	in_out_vrr->btr.btr_enabled = in_config->btr;
1079 
1080 	if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz))
1081 		in_out_vrr->btr.btr_enabled = false;
1082 	else {
1083 		in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us -
1084 				2 * in_out_vrr->min_duration_in_us;
1085 		if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN)
1086 			in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN;
1087 	}
1088 
1089 	in_out_vrr->btr.btr_active = false;
1090 	in_out_vrr->btr.inserted_duration_in_us = 0;
1091 	in_out_vrr->btr.frames_to_insert = 0;
1092 	in_out_vrr->btr.frame_counter = 0;
1093 	in_out_vrr->fixed.fixed_active = false;
1094 	in_out_vrr->fixed.target_refresh_in_uhz = 0;
1095 
1096 	in_out_vrr->btr.mid_point_in_us =
1097 				(in_out_vrr->min_duration_in_us +
1098 				 in_out_vrr->max_duration_in_us) / 2;
1099 
1100 	if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) {
1101 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1102 		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1103 	} else if (in_out_vrr->state == VRR_STATE_DISABLED) {
1104 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1105 		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1106 	} else if (in_out_vrr->state == VRR_STATE_INACTIVE) {
1107 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1108 		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1109 	} else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1110 			refresh_range >= MIN_REFRESH_RANGE) {
1111 
1112 		in_out_vrr->adjust.v_total_min =
1113 			mod_freesync_calc_v_total_from_refresh(stream,
1114 				in_out_vrr->max_refresh_in_uhz);
1115 		in_out_vrr->adjust.v_total_max =
1116 			mod_freesync_calc_v_total_from_refresh(stream,
1117 				in_out_vrr->min_refresh_in_uhz);
1118 	} else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) {
1119 		in_out_vrr->fixed.target_refresh_in_uhz =
1120 				in_out_vrr->fixed_refresh_in_uhz;
1121 		if (in_out_vrr->fixed.ramping_active &&
1122 				in_out_vrr->fixed.fixed_active) {
1123 			/* Do not update vtotals if ramping is already active
1124 			 * in order to continue ramp from current refresh.
1125 			 */
1126 			in_out_vrr->fixed.fixed_active = true;
1127 		} else {
1128 			in_out_vrr->fixed.fixed_active = true;
1129 			in_out_vrr->adjust.v_total_min =
1130 				mod_freesync_calc_v_total_from_refresh(stream,
1131 					in_out_vrr->fixed.target_refresh_in_uhz);
1132 			in_out_vrr->adjust.v_total_max =
1133 				in_out_vrr->adjust.v_total_min;
1134 		}
1135 	} else {
1136 		in_out_vrr->state = VRR_STATE_INACTIVE;
1137 		in_out_vrr->adjust.v_total_min = stream->timing.v_total;
1138 		in_out_vrr->adjust.v_total_max = stream->timing.v_total;
1139 	}
1140 
1141 	in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false;
1142 }
1143 
1144 void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync,
1145 		const struct dc_plane_state *plane,
1146 		const struct dc_stream_state *stream,
1147 		unsigned int curr_time_stamp_in_us,
1148 		struct mod_vrr_params *in_out_vrr)
1149 {
1150 	struct core_freesync *core_freesync = NULL;
1151 	unsigned int last_render_time_in_us = 0;
1152 
1153 	if (mod_freesync == NULL)
1154 		return;
1155 
1156 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1157 
1158 	if (in_out_vrr->supported &&
1159 			in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) {
1160 
1161 		last_render_time_in_us = curr_time_stamp_in_us -
1162 				plane->time.prev_update_time_in_us;
1163 
1164 		if (in_out_vrr->btr.btr_enabled) {
1165 			apply_below_the_range(core_freesync,
1166 					stream,
1167 					last_render_time_in_us,
1168 					in_out_vrr);
1169 		} else {
1170 			apply_fixed_refresh(core_freesync,
1171 				stream,
1172 				last_render_time_in_us,
1173 				in_out_vrr);
1174 		}
1175 
1176 		determine_flip_interval_workaround_req(in_out_vrr,
1177 				curr_time_stamp_in_us);
1178 
1179 	}
1180 }
1181 
1182 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
1183 		const struct dc_stream_state *stream,
1184 		struct mod_vrr_params *in_out_vrr)
1185 {
1186 	struct core_freesync *core_freesync = NULL;
1187 	unsigned int cur_timestamp_in_us;
1188 	unsigned long long cur_tick;
1189 
1190 	if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL))
1191 		return;
1192 
1193 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
1194 
1195 	if (in_out_vrr->supported == false)
1196 		return;
1197 
1198 	cur_tick = dm_get_timestamp(core_freesync->dc->ctx);
1199 	cur_timestamp_in_us = (unsigned int)
1200 			div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000);
1201 
1202 	in_out_vrr->flip_interval.vsyncs_between_flip++;
1203 	in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us;
1204 
1205 	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1206 			(in_out_vrr->flip_interval.flip_interval_workaround_active ||
1207 			(!in_out_vrr->flip_interval.flip_interval_workaround_active &&
1208 			in_out_vrr->flip_interval.program_flip_interval_workaround))) {
1209 		// set freesync vmin vmax to nominal for workaround
1210 		in_out_vrr->adjust.v_total_min =
1211 			mod_freesync_calc_v_total_from_refresh(
1212 			stream, in_out_vrr->max_refresh_in_uhz);
1213 		in_out_vrr->adjust.v_total_max =
1214 				in_out_vrr->adjust.v_total_min;
1215 		in_out_vrr->flip_interval.program_flip_interval_workaround = false;
1216 		in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true;
1217 		return;
1218 	}
1219 
1220 	if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE &&
1221 			in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) {
1222 		in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false;
1223 		in_out_vrr->flip_interval.flip_interval_detect_counter = 0;
1224 		in_out_vrr->flip_interval.vsyncs_between_flip = 0;
1225 		in_out_vrr->flip_interval.vsync_to_flip_in_us = 0;
1226 	}
1227 
1228 	/* Below the Range Logic */
1229 
1230 	/* Only execute if in fullscreen mode */
1231 	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE &&
1232 					in_out_vrr->btr.btr_active) {
1233 		/* TODO: pass in flag for Pre-DCE12 ASIC
1234 		 * in order for frame variable duration to take affect,
1235 		 * it needs to be done one VSYNC early, which is at
1236 		 * frameCounter == 1.
1237 		 * For DCE12 and newer updates to V_TOTAL_MIN/MAX
1238 		 * will take affect on current frame
1239 		 */
1240 		if (in_out_vrr->btr.frames_to_insert ==
1241 				in_out_vrr->btr.frame_counter) {
1242 			in_out_vrr->adjust.v_total_min =
1243 				calc_v_total_from_duration(stream,
1244 				in_out_vrr,
1245 				in_out_vrr->btr.inserted_duration_in_us);
1246 			in_out_vrr->adjust.v_total_max =
1247 				in_out_vrr->adjust.v_total_min;
1248 		}
1249 
1250 		if (in_out_vrr->btr.frame_counter > 0)
1251 			in_out_vrr->btr.frame_counter--;
1252 
1253 		/* Restore FreeSync */
1254 		if (in_out_vrr->btr.frame_counter == 0) {
1255 			in_out_vrr->adjust.v_total_min =
1256 				mod_freesync_calc_v_total_from_refresh(stream,
1257 				in_out_vrr->max_refresh_in_uhz);
1258 			in_out_vrr->adjust.v_total_max =
1259 				mod_freesync_calc_v_total_from_refresh(stream,
1260 				in_out_vrr->min_refresh_in_uhz);
1261 		}
1262 	}
1263 
1264 	/* If in fullscreen freesync mode or in video, do not program
1265 	 * static screen ramp values
1266 	 */
1267 	if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE)
1268 		in_out_vrr->fixed.ramping_active = false;
1269 
1270 	/* Gradual Static Screen Ramping Logic
1271 	 * Execute if ramp is active and user enabled freesync static screen
1272 	 */
1273 	if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED &&
1274 				in_out_vrr->fixed.ramping_active) {
1275 		update_v_total_for_static_ramp(
1276 				core_freesync, stream, in_out_vrr);
1277 	}
1278 }
1279 
1280 void mod_freesync_get_settings(struct mod_freesync *mod_freesync,
1281 		const struct mod_vrr_params *vrr,
1282 		unsigned int *v_total_min, unsigned int *v_total_max,
1283 		unsigned int *event_triggers,
1284 		unsigned int *window_min, unsigned int *window_max,
1285 		unsigned int *lfc_mid_point_in_us,
1286 		unsigned int *inserted_frames,
1287 		unsigned int *inserted_duration_in_us)
1288 {
1289 	if (mod_freesync == NULL)
1290 		return;
1291 
1292 	if (vrr->supported) {
1293 		*v_total_min = vrr->adjust.v_total_min;
1294 		*v_total_max = vrr->adjust.v_total_max;
1295 		*event_triggers = 0;
1296 		*lfc_mid_point_in_us = vrr->btr.mid_point_in_us;
1297 		*inserted_frames = vrr->btr.frames_to_insert;
1298 		*inserted_duration_in_us = vrr->btr.inserted_duration_in_us;
1299 	}
1300 }
1301 
1302 unsigned long long mod_freesync_calc_nominal_field_rate(
1303 			const struct dc_stream_state *stream)
1304 {
1305 	unsigned long long nominal_field_rate_in_uhz = 0;
1306 	unsigned int total = stream->timing.h_total * stream->timing.v_total;
1307 
1308 	/* Calculate nominal field rate for stream, rounded up to nearest integer */
1309 	nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz;
1310 	nominal_field_rate_in_uhz *= 100000000ULL;
1311 
1312 	nominal_field_rate_in_uhz =	div_u64(nominal_field_rate_in_uhz, total);
1313 
1314 	return nominal_field_rate_in_uhz;
1315 }
1316 
1317 unsigned long long mod_freesync_calc_field_rate_from_timing(
1318 		unsigned int vtotal, unsigned int htotal, unsigned int pix_clk)
1319 {
1320 	unsigned long long field_rate_in_uhz = 0;
1321 	unsigned int total = htotal * vtotal;
1322 
1323 	/* Calculate nominal field rate for stream, rounded up to nearest integer */
1324 	field_rate_in_uhz = pix_clk;
1325 	field_rate_in_uhz *= 1000000ULL;
1326 
1327 	field_rate_in_uhz =	div_u64(field_rate_in_uhz, total);
1328 
1329 	return field_rate_in_uhz;
1330 }
1331 
1332 bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr)
1333 {
1334 	return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED);
1335 }
1336 
1337 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz,
1338 		uint32_t max_refresh_cap_in_uhz,
1339 		uint32_t nominal_field_rate_in_uhz)
1340 {
1341 
1342 	/* Typically nominal refresh calculated can have some fractional part.
1343 	 * Allow for some rounding error of actual video timing by taking floor
1344 	 * of caps and request. Round the nominal refresh rate.
1345 	 *
1346 	 * Dividing will convert everything to units in Hz although input
1347 	 * variable name is in uHz!
1348 	 *
1349 	 * Also note, this takes care of rounding error on the nominal refresh
1350 	 * so by rounding error we only expect it to be off by a small amount,
1351 	 * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx.
1352 	 *
1353 	 * Example 1. Caps    Min = 40 Hz, Max = 144 Hz
1354 	 *            Request Min = 40 Hz, Max = 144 Hz
1355 	 *                    Nominal = 143.5x Hz rounded to 144 Hz
1356 	 *            This function should allow this as valid request
1357 	 *
1358 	 * Example 2. Caps    Min = 40 Hz, Max = 144 Hz
1359 	 *            Request Min = 40 Hz, Max = 144 Hz
1360 	 *                    Nominal = 144.4x Hz rounded to 144 Hz
1361 	 *            This function should allow this as valid request
1362 	 *
1363 	 * Example 3. Caps    Min = 40 Hz, Max = 144 Hz
1364 	 *            Request Min = 40 Hz, Max = 144 Hz
1365 	 *                    Nominal = 120.xx Hz rounded to 120 Hz
1366 	 *            This function should return NOT valid since the requested
1367 	 *            max is greater than current timing's nominal
1368 	 *
1369 	 * Example 4. Caps    Min = 40 Hz, Max = 120 Hz
1370 	 *            Request Min = 40 Hz, Max = 120 Hz
1371 	 *                    Nominal = 144.xx Hz rounded to 144 Hz
1372 	 *            This function should return NOT valid since the nominal
1373 	 *            is greater than the capability's max refresh
1374 	 */
1375 	nominal_field_rate_in_uhz =
1376 			div_u64(nominal_field_rate_in_uhz + 500000, 1000000);
1377 	min_refresh_cap_in_uhz /= 1000000;
1378 	max_refresh_cap_in_uhz /= 1000000;
1379 
1380 	/* Check nominal is within range */
1381 	if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz ||
1382 		nominal_field_rate_in_uhz < min_refresh_cap_in_uhz)
1383 		return false;
1384 
1385 	/* If nominal is less than max, limit the max allowed refresh rate */
1386 	if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz)
1387 		max_refresh_cap_in_uhz = nominal_field_rate_in_uhz;
1388 
1389 	/* Check min is within range */
1390 	if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz)
1391 		return false;
1392 
1393 	/* For variable range, check for at least 10 Hz range */
1394 	if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10)
1395 		return false;
1396 
1397 	return true;
1398 }
1399