1 /* 2 * Copyright 2016-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "mod_freesync.h" 29 #include "core_types.h" 30 31 #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 32 33 #define MIN_REFRESH_RANGE 10 34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */ 35 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65) 36 /* Number of elements in the render times cache array */ 37 #define RENDER_TIMES_MAX_COUNT 10 38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */ 39 #define BTR_MAX_MARGIN 2500 40 /* Threshold to change BTR multiplier (to avoid frequent changes) */ 41 #define BTR_DRIFT_MARGIN 2000 42 /* Threshold to exit fixed refresh rate */ 43 #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1 44 /* Number of consecutive frames to check before entering/exiting fixed refresh */ 45 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5 46 #define FIXED_REFRESH_EXIT_FRAME_COUNT 10 47 /* Flip interval workaround constants */ 48 #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2 49 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5 50 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500 51 #define MICRO_HZ_TO_HZ(x) (x / 1000000) 52 53 struct core_freesync { 54 struct mod_freesync public; 55 struct dc *dc; 56 }; 57 58 #define MOD_FREESYNC_TO_CORE(mod_freesync)\ 59 container_of(mod_freesync, struct core_freesync, public) 60 61 struct mod_freesync *mod_freesync_create(struct dc *dc) 62 { 63 struct core_freesync *core_freesync = 64 kzalloc(sizeof(struct core_freesync), GFP_KERNEL); 65 66 if (core_freesync == NULL) 67 goto fail_alloc_context; 68 69 if (dc == NULL) 70 goto fail_construct; 71 72 core_freesync->dc = dc; 73 return &core_freesync->public; 74 75 fail_construct: 76 kfree(core_freesync); 77 78 fail_alloc_context: 79 return NULL; 80 } 81 82 void mod_freesync_destroy(struct mod_freesync *mod_freesync) 83 { 84 struct core_freesync *core_freesync = NULL; 85 86 if (mod_freesync == NULL) 87 return; 88 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 89 kfree(core_freesync); 90 } 91 92 #if 0 /* Unused currently */ 93 static unsigned int calc_refresh_in_uhz_from_duration( 94 unsigned int duration_in_ns) 95 { 96 unsigned int refresh_in_uhz = 97 ((unsigned int)(div64_u64((1000000000ULL * 1000000), 98 duration_in_ns))); 99 return refresh_in_uhz; 100 } 101 #endif 102 103 static unsigned int calc_duration_in_us_from_refresh_in_uhz( 104 unsigned int refresh_in_uhz) 105 { 106 unsigned int duration_in_us = 107 ((unsigned int)(div64_u64((1000000000ULL * 1000), 108 refresh_in_uhz))); 109 return duration_in_us; 110 } 111 112 static unsigned int calc_duration_in_us_from_v_total( 113 const struct dc_stream_state *stream, 114 const struct mod_vrr_params *in_vrr, 115 unsigned int v_total) 116 { 117 unsigned int duration_in_us = 118 (unsigned int)(div64_u64(((unsigned long long)(v_total) 119 * 10000) * stream->timing.h_total, 120 stream->timing.pix_clk_100hz)); 121 122 return duration_in_us; 123 } 124 125 static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream) 126 { 127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; 128 129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { 130 max_hw_v_total -= stream->timing.v_front_porch + 1; 131 } 132 133 return max_hw_v_total; 134 } 135 136 unsigned int mod_freesync_calc_v_total_from_refresh( 137 const struct dc_stream_state *stream, 138 unsigned int refresh_in_uhz) 139 { 140 unsigned int v_total; 141 unsigned int frame_duration_in_ns; 142 143 if (refresh_in_uhz == 0) 144 return stream->timing.v_total; 145 146 frame_duration_in_ns = 147 ((unsigned int)(div64_u64((1000000000ULL * 1000000), 148 refresh_in_uhz))); 149 150 if (MICRO_HZ_TO_HZ(refresh_in_uhz) <= stream->timing.min_refresh_in_uhz) { 151 /* When the target refresh rate is the minimum panel refresh rate, 152 * round down the vtotal value to avoid stretching vblank over 153 * panel's vtotal boundary. 154 */ 155 v_total = div64_u64(div64_u64(((unsigned long long)( 156 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 157 stream->timing.h_total), 1000000); 158 } else { 159 v_total = div64_u64(div64_u64(((unsigned long long)( 160 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 161 stream->timing.h_total) + 500000, 1000000); 162 } 163 164 /* v_total cannot be less than nominal */ 165 if (v_total < stream->timing.v_total) { 166 ASSERT(v_total < stream->timing.v_total); 167 v_total = stream->timing.v_total; 168 } 169 170 return v_total; 171 } 172 173 static unsigned int calc_v_total_from_duration( 174 const struct dc_stream_state *stream, 175 const struct mod_vrr_params *vrr, 176 unsigned int duration_in_us) 177 { 178 unsigned int v_total = 0; 179 180 if (duration_in_us < vrr->min_duration_in_us) 181 duration_in_us = vrr->min_duration_in_us; 182 183 if (duration_in_us > vrr->max_duration_in_us) 184 duration_in_us = vrr->max_duration_in_us; 185 186 if (dc_is_hdmi_signal(stream->signal)) { // change for HDMI to comply with spec 187 uint32_t h_total_up_scaled; 188 189 h_total_up_scaled = stream->timing.h_total * 10000; 190 v_total = div_u64((unsigned long long)duration_in_us 191 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1), 192 h_total_up_scaled); //ceiling for MMax and MMin for MVRR 193 } else { 194 v_total = div64_u64(div64_u64(((unsigned long long)( 195 duration_in_us) * (stream->timing.pix_clk_100hz / 10)), 196 stream->timing.h_total), 1000); 197 } 198 199 /* v_total cannot be less than nominal */ 200 if (v_total < stream->timing.v_total) { 201 ASSERT(v_total < stream->timing.v_total); 202 v_total = stream->timing.v_total; 203 } 204 205 return v_total; 206 } 207 208 static void update_v_total_for_static_ramp( 209 struct core_freesync *core_freesync, 210 const struct dc_stream_state *stream, 211 struct mod_vrr_params *in_out_vrr) 212 { 213 unsigned int v_total = 0; 214 unsigned int current_duration_in_us = 215 calc_duration_in_us_from_v_total( 216 stream, in_out_vrr, 217 in_out_vrr->adjust.v_total_max); 218 unsigned int target_duration_in_us = 219 calc_duration_in_us_from_refresh_in_uhz( 220 in_out_vrr->fixed.target_refresh_in_uhz); 221 bool ramp_direction_is_up = (current_duration_in_us > 222 target_duration_in_us) ? true : false; 223 224 /* Calculate ratio between new and current frame duration with 3 digit */ 225 unsigned int frame_duration_ratio = div64_u64(1000000, 226 (1000 + div64_u64(((unsigned long long)( 227 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) * 228 current_duration_in_us), 229 1000000))); 230 231 /* Calculate delta between new and current frame duration in us */ 232 unsigned int frame_duration_delta = div64_u64(((unsigned long long)( 233 current_duration_in_us) * 234 (1000 - frame_duration_ratio)), 1000); 235 236 /* Adjust frame duration delta based on ratio between current and 237 * standard frame duration (frame duration at 60 Hz refresh rate). 238 */ 239 unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)( 240 frame_duration_delta) * current_duration_in_us), 16666); 241 242 /* Going to a higher refresh rate (lower frame duration) */ 243 if (ramp_direction_is_up) { 244 /* Reduce frame duration */ 245 current_duration_in_us -= ramp_rate_interpolated; 246 247 /* Adjust for frame duration below min */ 248 if (current_duration_in_us <= target_duration_in_us) { 249 in_out_vrr->fixed.ramping_active = false; 250 in_out_vrr->fixed.ramping_done = true; 251 current_duration_in_us = 252 calc_duration_in_us_from_refresh_in_uhz( 253 in_out_vrr->fixed.target_refresh_in_uhz); 254 } 255 /* Going to a lower refresh rate (larger frame duration) */ 256 } else { 257 /* Increase frame duration */ 258 current_duration_in_us += ramp_rate_interpolated; 259 260 /* Adjust for frame duration above max */ 261 if (current_duration_in_us >= target_duration_in_us) { 262 in_out_vrr->fixed.ramping_active = false; 263 in_out_vrr->fixed.ramping_done = true; 264 current_duration_in_us = 265 calc_duration_in_us_from_refresh_in_uhz( 266 in_out_vrr->fixed.target_refresh_in_uhz); 267 } 268 } 269 270 v_total = div64_u64(div64_u64(((unsigned long long)( 271 current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)), 272 stream->timing.h_total), 1000); 273 274 /* v_total cannot be less than nominal */ 275 if (v_total < stream->timing.v_total) 276 v_total = stream->timing.v_total; 277 278 in_out_vrr->adjust.v_total_min = v_total; 279 in_out_vrr->adjust.v_total_max = v_total; 280 } 281 282 static void apply_below_the_range(struct core_freesync *core_freesync, 283 const struct dc_stream_state *stream, 284 unsigned int last_render_time_in_us, 285 struct mod_vrr_params *in_out_vrr) 286 { 287 unsigned int inserted_frame_duration_in_us = 0; 288 unsigned int mid_point_frames_ceil = 0; 289 unsigned int mid_point_frames_floor = 0; 290 unsigned int frame_time_in_us = 0; 291 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF; 292 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF; 293 unsigned int frames_to_insert = 0; 294 unsigned int delta_from_mid_point_delta_in_us; 295 unsigned int max_render_time_in_us = 296 in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us; 297 298 /* Program BTR */ 299 if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) { 300 /* Exit Below the Range */ 301 if (in_out_vrr->btr.btr_active) { 302 in_out_vrr->btr.frame_counter = 0; 303 in_out_vrr->btr.btr_active = false; 304 } 305 } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) { 306 /* Enter Below the Range */ 307 if (!in_out_vrr->btr.btr_active) 308 in_out_vrr->btr.btr_active = true; 309 } 310 311 /* BTR set to "not active" so disengage */ 312 if (!in_out_vrr->btr.btr_active) { 313 in_out_vrr->btr.inserted_duration_in_us = 0; 314 in_out_vrr->btr.frames_to_insert = 0; 315 in_out_vrr->btr.frame_counter = 0; 316 317 /* Restore FreeSync */ 318 in_out_vrr->adjust.v_total_min = 319 mod_freesync_calc_v_total_from_refresh(stream, 320 in_out_vrr->max_refresh_in_uhz); 321 in_out_vrr->adjust.v_total_max = 322 mod_freesync_calc_v_total_from_refresh(stream, 323 in_out_vrr->min_refresh_in_uhz); 324 /* BTR set to "active" so engage */ 325 } else { 326 327 /* Calculate number of midPoint frames that could fit within 328 * the render time interval - take ceil of this value 329 */ 330 mid_point_frames_ceil = (last_render_time_in_us + 331 in_out_vrr->btr.mid_point_in_us - 1) / 332 in_out_vrr->btr.mid_point_in_us; 333 334 if (mid_point_frames_ceil > 0) { 335 frame_time_in_us = last_render_time_in_us / 336 mid_point_frames_ceil; 337 delta_from_mid_point_in_us_1 = 338 (in_out_vrr->btr.mid_point_in_us > 339 frame_time_in_us) ? 340 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) : 341 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us); 342 } 343 344 /* Calculate number of midPoint frames that could fit within 345 * the render time interval - take floor of this value 346 */ 347 mid_point_frames_floor = last_render_time_in_us / 348 in_out_vrr->btr.mid_point_in_us; 349 350 if (mid_point_frames_floor > 0) { 351 352 frame_time_in_us = last_render_time_in_us / 353 mid_point_frames_floor; 354 delta_from_mid_point_in_us_2 = 355 (in_out_vrr->btr.mid_point_in_us > 356 frame_time_in_us) ? 357 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) : 358 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us); 359 } 360 361 /* Choose number of frames to insert based on how close it 362 * can get to the mid point of the variable range. 363 * - Delta for CEIL: delta_from_mid_point_in_us_1 364 * - Delta for FLOOR: delta_from_mid_point_in_us_2 365 */ 366 if (mid_point_frames_ceil && 367 (last_render_time_in_us / mid_point_frames_ceil) < 368 in_out_vrr->min_duration_in_us) { 369 /* Check for out of range. 370 * If using CEIL produces a value that is out of range, 371 * then we are forced to use FLOOR. 372 */ 373 frames_to_insert = mid_point_frames_floor; 374 } else if (mid_point_frames_floor < 2) { 375 /* Check if FLOOR would result in non-LFC. In this case 376 * choose to use CEIL 377 */ 378 frames_to_insert = mid_point_frames_ceil; 379 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) { 380 /* If choosing CEIL results in a frame duration that is 381 * closer to the mid point of the range. 382 * Choose CEIL 383 */ 384 frames_to_insert = mid_point_frames_ceil; 385 } else { 386 /* If choosing FLOOR results in a frame duration that is 387 * closer to the mid point of the range. 388 * Choose FLOOR 389 */ 390 frames_to_insert = mid_point_frames_floor; 391 } 392 393 /* Prefer current frame multiplier when BTR is enabled unless it drifts 394 * too far from the midpoint 395 */ 396 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) { 397 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 - 398 delta_from_mid_point_in_us_1; 399 } else { 400 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 - 401 delta_from_mid_point_in_us_2; 402 } 403 if (in_out_vrr->btr.frames_to_insert != 0 && 404 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) { 405 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) < 406 max_render_time_in_us) && 407 ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) > 408 in_out_vrr->min_duration_in_us)) 409 frames_to_insert = in_out_vrr->btr.frames_to_insert; 410 } 411 412 /* Either we've calculated the number of frames to insert, 413 * or we need to insert min duration frames 414 */ 415 if (frames_to_insert && 416 (last_render_time_in_us / frames_to_insert) < 417 in_out_vrr->min_duration_in_us){ 418 frames_to_insert -= (frames_to_insert > 1) ? 419 1 : 0; 420 } 421 422 if (frames_to_insert > 0) 423 inserted_frame_duration_in_us = last_render_time_in_us / 424 frames_to_insert; 425 426 if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us) 427 inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us; 428 429 /* Cache the calculated variables */ 430 in_out_vrr->btr.inserted_duration_in_us = 431 inserted_frame_duration_in_us; 432 in_out_vrr->btr.frames_to_insert = frames_to_insert; 433 in_out_vrr->btr.frame_counter = frames_to_insert; 434 } 435 } 436 437 static void apply_fixed_refresh(struct core_freesync *core_freesync, 438 const struct dc_stream_state *stream, 439 unsigned int last_render_time_in_us, 440 struct mod_vrr_params *in_out_vrr) 441 { 442 bool update = false; 443 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us; 444 445 /* Compute the exit refresh rate and exit frame duration */ 446 unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us) 447 + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ)); 448 unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz; 449 450 if (last_render_time_in_us < exit_frame_duration_in_us) { 451 /* Exit Fixed Refresh mode */ 452 if (in_out_vrr->fixed.fixed_active) { 453 in_out_vrr->fixed.frame_counter++; 454 455 if (in_out_vrr->fixed.frame_counter > 456 FIXED_REFRESH_EXIT_FRAME_COUNT) { 457 in_out_vrr->fixed.frame_counter = 0; 458 in_out_vrr->fixed.fixed_active = false; 459 in_out_vrr->fixed.target_refresh_in_uhz = 0; 460 update = true; 461 } 462 } else 463 in_out_vrr->fixed.frame_counter = 0; 464 } else if (last_render_time_in_us > max_render_time_in_us) { 465 /* Enter Fixed Refresh mode */ 466 if (!in_out_vrr->fixed.fixed_active) { 467 in_out_vrr->fixed.frame_counter++; 468 469 if (in_out_vrr->fixed.frame_counter > 470 FIXED_REFRESH_ENTER_FRAME_COUNT) { 471 in_out_vrr->fixed.frame_counter = 0; 472 in_out_vrr->fixed.fixed_active = true; 473 in_out_vrr->fixed.target_refresh_in_uhz = 474 in_out_vrr->max_refresh_in_uhz; 475 update = true; 476 } 477 } else 478 in_out_vrr->fixed.frame_counter = 0; 479 } 480 481 if (update) { 482 if (in_out_vrr->fixed.fixed_active) { 483 in_out_vrr->adjust.v_total_min = 484 mod_freesync_calc_v_total_from_refresh( 485 stream, in_out_vrr->max_refresh_in_uhz); 486 in_out_vrr->adjust.v_total_max = 487 in_out_vrr->adjust.v_total_min; 488 } else { 489 in_out_vrr->adjust.v_total_min = 490 mod_freesync_calc_v_total_from_refresh(stream, 491 in_out_vrr->max_refresh_in_uhz); 492 in_out_vrr->adjust.v_total_max = 493 mod_freesync_calc_v_total_from_refresh(stream, 494 in_out_vrr->min_refresh_in_uhz); 495 } 496 } 497 } 498 499 static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr, 500 unsigned int curr_time_stamp_in_us) 501 { 502 in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us - 503 in_vrr->flip_interval.v_update_timestamp_in_us; 504 505 /* Determine conditions for stopping workaround */ 506 if (in_vrr->flip_interval.flip_interval_workaround_active && 507 in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD && 508 in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) { 509 in_vrr->flip_interval.flip_interval_detect_counter = 0; 510 in_vrr->flip_interval.program_flip_interval_workaround = true; 511 in_vrr->flip_interval.flip_interval_workaround_active = false; 512 } else { 513 /* Determine conditions for starting workaround */ 514 if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD && 515 in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) { 516 /* Increase flip interval counter we have 2 vsyncs between flips and 517 * vsync to flip interval is less than 500us 518 */ 519 in_vrr->flip_interval.flip_interval_detect_counter++; 520 if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) { 521 /* Start workaround if we detect 5 consecutive instances of the above case */ 522 in_vrr->flip_interval.program_flip_interval_workaround = true; 523 in_vrr->flip_interval.flip_interval_workaround_active = true; 524 } 525 } else { 526 /* Reset the flip interval counter if we condition is no longer met */ 527 in_vrr->flip_interval.flip_interval_detect_counter = 0; 528 } 529 } 530 531 in_vrr->flip_interval.vsyncs_between_flip = 0; 532 } 533 534 static bool vrr_settings_require_update(struct core_freesync *core_freesync, 535 struct mod_freesync_config *in_config, 536 unsigned int min_refresh_in_uhz, 537 unsigned int max_refresh_in_uhz, 538 struct mod_vrr_params *in_vrr) 539 { 540 if (in_vrr->state != in_config->state) { 541 return true; 542 } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED && 543 in_vrr->fixed.target_refresh_in_uhz != 544 in_config->fixed_refresh_in_uhz) { 545 return true; 546 } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) { 547 return true; 548 } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) { 549 return true; 550 } 551 552 return false; 553 } 554 555 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, 556 const struct dc_stream_state *stream, 557 unsigned int *vmin, 558 unsigned int *vmax) 559 { 560 *vmin = stream->adjust.v_total_min; 561 *vmax = stream->adjust.v_total_max; 562 563 return true; 564 } 565 566 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, 567 struct dc_stream_state *stream, 568 unsigned int *nom_v_pos, 569 unsigned int *v_pos) 570 { 571 struct core_freesync *core_freesync = NULL; 572 struct crtc_position position; 573 574 if (mod_freesync == NULL) 575 return false; 576 577 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 578 579 if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, 580 &position.vertical_count, 581 &position.nominal_vcount)) { 582 583 *nom_v_pos = position.nominal_vcount; 584 *v_pos = position.vertical_count; 585 586 return true; 587 } 588 589 return false; 590 } 591 592 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr, 593 struct dc_info_packet *infopacket, 594 bool freesync_on_desktop) 595 { 596 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 597 infopacket->sb[1] = 0x1A; 598 599 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 600 infopacket->sb[2] = 0x00; 601 602 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 603 infopacket->sb[3] = 0x00; 604 605 /* PB4 = Reserved */ 606 607 /* PB5 = Reserved */ 608 609 /* PB6 = [Bits 7:3 = Reserved] */ 610 611 /* PB6 = [Bit 0 = FreeSync Supported] */ 612 if (vrr->state != VRR_STATE_UNSUPPORTED) 613 infopacket->sb[6] |= 0x01; 614 615 /* PB6 = [Bit 1 = FreeSync Enabled] */ 616 if (vrr->state != VRR_STATE_DISABLED && 617 vrr->state != VRR_STATE_UNSUPPORTED) 618 infopacket->sb[6] |= 0x02; 619 620 if (freesync_on_desktop) { 621 /* PB6 = [Bit 2 = FreeSync Active] */ 622 if (vrr->state != VRR_STATE_DISABLED && 623 vrr->state != VRR_STATE_UNSUPPORTED) 624 infopacket->sb[6] |= 0x04; 625 } else { 626 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 627 vrr->state == VRR_STATE_ACTIVE_FIXED) 628 infopacket->sb[6] |= 0x04; 629 } 630 631 // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range 632 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 633 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 634 vrr->state == VRR_STATE_ACTIVE_FIXED) { 635 infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000); 636 } else { 637 infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000); 638 } 639 640 /* PB8 = FreeSync Maximum refresh rate (Hz) 641 * Note: We should never go above the field rate of the mode timing set. 642 */ 643 infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000); 644 } 645 646 static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, 647 struct dc_info_packet *infopacket, 648 bool freesync_on_desktop) 649 { 650 unsigned int min_refresh; 651 unsigned int max_refresh; 652 unsigned int fixed_refresh; 653 unsigned int min_programmed; 654 655 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 656 infopacket->sb[1] = 0x1A; 657 658 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 659 infopacket->sb[2] = 0x00; 660 661 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 662 infopacket->sb[3] = 0x00; 663 664 /* PB4 = Reserved */ 665 666 /* PB5 = Reserved */ 667 668 /* PB6 = [Bits 7:3 = Reserved] */ 669 670 /* PB6 = [Bit 0 = FreeSync Supported] */ 671 if (vrr->state != VRR_STATE_UNSUPPORTED) 672 infopacket->sb[6] |= 0x01; 673 674 /* PB6 = [Bit 1 = FreeSync Enabled] */ 675 if (vrr->state != VRR_STATE_DISABLED && 676 vrr->state != VRR_STATE_UNSUPPORTED) 677 infopacket->sb[6] |= 0x02; 678 679 /* PB6 = [Bit 2 = FreeSync Active] */ 680 if (freesync_on_desktop) { 681 if (vrr->state != VRR_STATE_DISABLED && 682 vrr->state != VRR_STATE_UNSUPPORTED) 683 infopacket->sb[6] |= 0x04; 684 } else { 685 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 686 vrr->state == VRR_STATE_ACTIVE_FIXED) 687 infopacket->sb[6] |= 0x04; 688 } 689 690 min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000; 691 max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000; 692 fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000; 693 694 min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh : 695 (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh : 696 (vrr->state == VRR_STATE_INACTIVE) ? min_refresh : 697 max_refresh; // Non-fs case, program nominal range 698 699 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 700 infopacket->sb[7] = min_programmed & 0xFF; 701 702 /* PB8 = FreeSync Maximum refresh rate (Hz) */ 703 infopacket->sb[8] = max_refresh & 0xFF; 704 705 /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */ 706 infopacket->sb[11] = (min_programmed >> 8) & 0x03; 707 708 /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */ 709 infopacket->sb[12] = (max_refresh >> 8) & 0x03; 710 711 /* PB16 : Reserved bits 7:1, FixedRate bit 0 */ 712 infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0; 713 } 714 715 static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf, 716 struct dc_info_packet *infopacket) 717 { 718 if (app_tf != TRANSFER_FUNC_UNKNOWN) { 719 infopacket->valid = true; 720 721 if (app_tf == TRANSFER_FUNC_PQ2084) 722 infopacket->sb[9] |= 0x20; // PB9 = [Bit 5 = PQ EOTF Active] 723 else { 724 infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active] 725 if (app_tf == TRANSFER_FUNC_GAMMA_22) 726 infopacket->sb[9] |= 0x04; // PB9 = [Bit 2 = Gamma 2.2 EOTF Active] 727 } 728 } 729 } 730 731 static void build_vrr_infopacket_header_v1(enum signal_type signal, 732 struct dc_info_packet *infopacket, 733 unsigned int *payload_size) 734 { 735 if (dc_is_hdmi_signal(signal)) { 736 737 /* HEADER */ 738 739 /* HB0 = Packet Type = 0x83 (Source Product 740 * Descriptor InfoFrame) 741 */ 742 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 743 744 /* HB1 = Version = 0x01 */ 745 infopacket->hb1 = 0x01; 746 747 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */ 748 infopacket->hb2 = 0x08; 749 750 *payload_size = 0x08; 751 752 } else if (dc_is_dp_signal(signal)) { 753 754 /* HEADER */ 755 756 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 757 * when used to associate audio related info packets 758 */ 759 infopacket->hb0 = 0x00; 760 761 /* HB1 = Packet Type = 0x83 (Source Product 762 * Descriptor InfoFrame) 763 */ 764 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 765 766 /* HB2 = [Bits 7:0 = Least significant eight bits - 767 * For INFOFRAME, the value must be 1Bh] 768 */ 769 infopacket->hb2 = 0x1B; 770 771 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1] 772 * [Bits 1:0 = Most significant two bits = 0x00] 773 */ 774 infopacket->hb3 = 0x04; 775 776 *payload_size = 0x1B; 777 } 778 } 779 780 static void build_vrr_infopacket_header_v2(enum signal_type signal, 781 struct dc_info_packet *infopacket, 782 unsigned int *payload_size) 783 { 784 if (dc_is_hdmi_signal(signal)) { 785 786 /* HEADER */ 787 788 /* HB0 = Packet Type = 0x83 (Source Product 789 * Descriptor InfoFrame) 790 */ 791 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 792 793 /* HB1 = Version = 0x02 */ 794 infopacket->hb1 = 0x02; 795 796 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */ 797 infopacket->hb2 = 0x09; 798 799 *payload_size = 0x09; 800 } else if (dc_is_dp_signal(signal)) { 801 802 /* HEADER */ 803 804 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 805 * when used to associate audio related info packets 806 */ 807 infopacket->hb0 = 0x00; 808 809 /* HB1 = Packet Type = 0x83 (Source Product 810 * Descriptor InfoFrame) 811 */ 812 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 813 814 /* HB2 = [Bits 7:0 = Least significant eight bits - 815 * For INFOFRAME, the value must be 1Bh] 816 */ 817 infopacket->hb2 = 0x1B; 818 819 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2] 820 * [Bits 1:0 = Most significant two bits = 0x00] 821 */ 822 infopacket->hb3 = 0x08; 823 824 *payload_size = 0x1B; 825 } 826 } 827 828 static void build_vrr_infopacket_header_v3(enum signal_type signal, 829 struct dc_info_packet *infopacket, 830 unsigned int *payload_size) 831 { 832 unsigned char version; 833 834 version = 3; 835 if (dc_is_hdmi_signal(signal)) { 836 837 /* HEADER */ 838 839 /* HB0 = Packet Type = 0x83 (Source Product 840 * Descriptor InfoFrame) 841 */ 842 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 843 844 /* HB1 = Version = 0x03 */ 845 infopacket->hb1 = version; 846 847 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */ 848 infopacket->hb2 = 0x10; 849 850 *payload_size = 0x10; 851 } else if (dc_is_dp_signal(signal)) { 852 853 /* HEADER */ 854 855 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 856 * when used to associate audio related info packets 857 */ 858 infopacket->hb0 = 0x00; 859 860 /* HB1 = Packet Type = 0x83 (Source Product 861 * Descriptor InfoFrame) 862 */ 863 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 864 865 /* HB2 = [Bits 7:0 = Least significant eight bits - 866 * For INFOFRAME, the value must be 1Bh] 867 */ 868 infopacket->hb2 = 0x1B; 869 870 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2] 871 * [Bits 1:0 = Most significant two bits = 0x00] 872 */ 873 874 infopacket->hb3 = (version & 0x3F) << 2; 875 876 *payload_size = 0x1B; 877 } 878 } 879 880 static void build_vrr_infopacket_checksum(unsigned int *payload_size, 881 struct dc_info_packet *infopacket) 882 { 883 /* Calculate checksum */ 884 unsigned int idx = 0; 885 unsigned char checksum = 0; 886 887 checksum += infopacket->hb0; 888 checksum += infopacket->hb1; 889 checksum += infopacket->hb2; 890 checksum += infopacket->hb3; 891 892 for (idx = 1; idx <= *payload_size; idx++) 893 checksum += infopacket->sb[idx]; 894 895 /* PB0 = Checksum (one byte complement) */ 896 infopacket->sb[0] = (unsigned char)(0x100 - checksum); 897 898 infopacket->valid = true; 899 } 900 901 static void build_vrr_infopacket_v1(enum signal_type signal, 902 const struct mod_vrr_params *vrr, 903 struct dc_info_packet *infopacket, 904 bool freesync_on_desktop) 905 { 906 /* SPD info packet for FreeSync */ 907 unsigned int payload_size = 0; 908 909 build_vrr_infopacket_header_v1(signal, infopacket, &payload_size); 910 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); 911 build_vrr_infopacket_checksum(&payload_size, infopacket); 912 913 infopacket->valid = true; 914 } 915 916 static void build_vrr_infopacket_v2(enum signal_type signal, 917 const struct mod_vrr_params *vrr, 918 enum color_transfer_func app_tf, 919 struct dc_info_packet *infopacket, 920 bool freesync_on_desktop) 921 { 922 unsigned int payload_size = 0; 923 924 build_vrr_infopacket_header_v2(signal, infopacket, &payload_size); 925 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); 926 927 build_vrr_infopacket_fs2_data(app_tf, infopacket); 928 929 build_vrr_infopacket_checksum(&payload_size, infopacket); 930 931 infopacket->valid = true; 932 } 933 934 static void build_vrr_infopacket_v3(enum signal_type signal, 935 const struct mod_vrr_params *vrr, 936 enum color_transfer_func app_tf, 937 struct dc_info_packet *infopacket, 938 bool freesync_on_desktop) 939 { 940 unsigned int payload_size = 0; 941 942 build_vrr_infopacket_header_v3(signal, infopacket, &payload_size); 943 build_vrr_infopacket_data_v3(vrr, infopacket, freesync_on_desktop); 944 945 build_vrr_infopacket_fs2_data(app_tf, infopacket); 946 947 build_vrr_infopacket_checksum(&payload_size, infopacket); 948 949 infopacket->valid = true; 950 } 951 952 static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type, 953 struct dc_info_packet *infopacket) 954 { 955 uint8_t idx = 0, size = 0; 956 957 size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 : 958 (packet_type == PACKET_TYPE_FS_V3) ? 0x10 : 959 0x09); 960 961 for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B 962 infopacket->sb[idx] = infopacket->sb[idx-1]; 963 964 infopacket->sb[1] = size; // Length 965 infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version 966 infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3 967 infopacket->hb2 = 0x1D; 968 } 969 970 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, 971 const struct dc_stream_state *stream, 972 const struct mod_vrr_params *vrr, 973 enum vrr_packet_type packet_type, 974 enum color_transfer_func app_tf, 975 struct dc_info_packet *infopacket, 976 bool pack_sdp_v1_3) 977 { 978 /* SPD info packet for FreeSync 979 * VTEM info packet for HdmiVRR 980 * Check if Freesync is supported. Return if false. If true, 981 * set the corresponding bit in the info packet 982 */ 983 if (!vrr->send_info_frame) 984 return; 985 986 switch (packet_type) { 987 case PACKET_TYPE_FS_V3: 988 build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop); 989 break; 990 case PACKET_TYPE_FS_V2: 991 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop); 992 break; 993 case PACKET_TYPE_VRR: 994 case PACKET_TYPE_FS_V1: 995 default: 996 build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop); 997 } 998 999 if (true == pack_sdp_v1_3 && 1000 true == dc_is_dp_signal(stream->signal) && 1001 packet_type != PACKET_TYPE_VRR && 1002 packet_type != PACKET_TYPE_VTEM) 1003 build_vrr_infopacket_sdp_v1_3(packet_type, infopacket); 1004 } 1005 1006 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, 1007 const struct dc_stream_state *stream, 1008 struct mod_freesync_config *in_config, 1009 struct mod_vrr_params *in_out_vrr) 1010 { 1011 struct core_freesync *core_freesync = NULL; 1012 unsigned long long nominal_field_rate_in_uhz = 0; 1013 unsigned long long rounded_nominal_in_uhz = 0; 1014 unsigned int refresh_range = 0; 1015 unsigned long long min_refresh_in_uhz = 0; 1016 unsigned long long max_refresh_in_uhz = 0; 1017 unsigned long long min_hardware_refresh_in_uhz = 0; 1018 1019 if (mod_freesync == NULL) 1020 return; 1021 1022 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1023 1024 /* Calculate nominal field rate for stream */ 1025 nominal_field_rate_in_uhz = 1026 mod_freesync_calc_nominal_field_rate(stream); 1027 1028 if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) { 1029 min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL), 1030 (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream))); 1031 } 1032 /* Limit minimum refresh rate to what can be supported by hardware */ 1033 min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ? 1034 min_hardware_refresh_in_uhz : in_config->min_refresh_in_uhz; 1035 max_refresh_in_uhz = in_config->max_refresh_in_uhz; 1036 1037 /* Full range may be larger than current video timing, so cap at nominal */ 1038 if (max_refresh_in_uhz > nominal_field_rate_in_uhz) 1039 max_refresh_in_uhz = nominal_field_rate_in_uhz; 1040 1041 /* Full range may be larger than current video timing, so cap at nominal */ 1042 if (min_refresh_in_uhz > max_refresh_in_uhz) 1043 min_refresh_in_uhz = max_refresh_in_uhz; 1044 1045 /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */ 1046 rounded_nominal_in_uhz = 1047 div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000; 1048 if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) && 1049 in_config->max_refresh_in_uhz == rounded_nominal_in_uhz) 1050 min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2); 1051 1052 if (!vrr_settings_require_update(core_freesync, 1053 in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz, 1054 in_out_vrr)) 1055 return; 1056 1057 in_out_vrr->state = in_config->state; 1058 in_out_vrr->send_info_frame = in_config->vsif_supported; 1059 1060 if (in_config->state == VRR_STATE_UNSUPPORTED) { 1061 in_out_vrr->state = VRR_STATE_UNSUPPORTED; 1062 in_out_vrr->supported = false; 1063 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1064 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1065 1066 return; 1067 1068 } else { 1069 in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz; 1070 in_out_vrr->max_duration_in_us = 1071 calc_duration_in_us_from_refresh_in_uhz( 1072 (unsigned int)min_refresh_in_uhz); 1073 1074 in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz; 1075 in_out_vrr->min_duration_in_us = 1076 calc_duration_in_us_from_refresh_in_uhz( 1077 (unsigned int)max_refresh_in_uhz); 1078 1079 if (in_config->state == VRR_STATE_ACTIVE_FIXED) 1080 in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz; 1081 else 1082 in_out_vrr->fixed_refresh_in_uhz = 0; 1083 1084 refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) - 1085 div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000); 1086 1087 in_out_vrr->supported = true; 1088 } 1089 1090 in_out_vrr->fixed.ramping_active = in_config->ramping; 1091 1092 in_out_vrr->btr.btr_enabled = in_config->btr; 1093 1094 if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz)) 1095 in_out_vrr->btr.btr_enabled = false; 1096 else { 1097 in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us - 1098 2 * in_out_vrr->min_duration_in_us; 1099 if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN) 1100 in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN; 1101 } 1102 1103 in_out_vrr->btr.btr_active = false; 1104 in_out_vrr->btr.inserted_duration_in_us = 0; 1105 in_out_vrr->btr.frames_to_insert = 0; 1106 in_out_vrr->btr.frame_counter = 0; 1107 in_out_vrr->fixed.fixed_active = false; 1108 in_out_vrr->fixed.target_refresh_in_uhz = 0; 1109 1110 in_out_vrr->btr.mid_point_in_us = 1111 (in_out_vrr->min_duration_in_us + 1112 in_out_vrr->max_duration_in_us) / 2; 1113 1114 if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) { 1115 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1116 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1117 } else if (in_out_vrr->state == VRR_STATE_DISABLED) { 1118 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1119 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1120 } else if (in_out_vrr->state == VRR_STATE_INACTIVE) { 1121 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1122 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1123 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1124 refresh_range >= MIN_REFRESH_RANGE) { 1125 1126 in_out_vrr->adjust.v_total_min = 1127 mod_freesync_calc_v_total_from_refresh(stream, 1128 in_out_vrr->max_refresh_in_uhz); 1129 in_out_vrr->adjust.v_total_max = 1130 mod_freesync_calc_v_total_from_refresh(stream, 1131 in_out_vrr->min_refresh_in_uhz); 1132 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) { 1133 in_out_vrr->fixed.target_refresh_in_uhz = 1134 in_out_vrr->fixed_refresh_in_uhz; 1135 if (in_out_vrr->fixed.ramping_active && 1136 in_out_vrr->fixed.fixed_active) { 1137 /* Do not update vtotals if ramping is already active 1138 * in order to continue ramp from current refresh. 1139 */ 1140 in_out_vrr->fixed.fixed_active = true; 1141 } else { 1142 in_out_vrr->fixed.fixed_active = true; 1143 in_out_vrr->adjust.v_total_min = 1144 mod_freesync_calc_v_total_from_refresh(stream, 1145 in_out_vrr->fixed.target_refresh_in_uhz); 1146 in_out_vrr->adjust.v_total_max = 1147 in_out_vrr->adjust.v_total_min; 1148 } 1149 } else { 1150 in_out_vrr->state = VRR_STATE_INACTIVE; 1151 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1152 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1153 } 1154 1155 in_out_vrr->adjust.allow_otg_v_count_halt = (in_config->state == VRR_STATE_ACTIVE_FIXED) ? true : false; 1156 } 1157 1158 void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync, 1159 const struct dc_plane_state *plane, 1160 const struct dc_stream_state *stream, 1161 unsigned int curr_time_stamp_in_us, 1162 struct mod_vrr_params *in_out_vrr) 1163 { 1164 struct core_freesync *core_freesync = NULL; 1165 unsigned int last_render_time_in_us = 0; 1166 1167 if (mod_freesync == NULL) 1168 return; 1169 1170 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1171 1172 if (in_out_vrr->supported && 1173 in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) { 1174 1175 last_render_time_in_us = curr_time_stamp_in_us - 1176 plane->time.prev_update_time_in_us; 1177 1178 if (in_out_vrr->btr.btr_enabled) { 1179 apply_below_the_range(core_freesync, 1180 stream, 1181 last_render_time_in_us, 1182 in_out_vrr); 1183 } else { 1184 apply_fixed_refresh(core_freesync, 1185 stream, 1186 last_render_time_in_us, 1187 in_out_vrr); 1188 } 1189 1190 determine_flip_interval_workaround_req(in_out_vrr, 1191 curr_time_stamp_in_us); 1192 1193 } 1194 } 1195 1196 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, 1197 const struct dc_stream_state *stream, 1198 struct mod_vrr_params *in_out_vrr) 1199 { 1200 struct core_freesync *core_freesync = NULL; 1201 unsigned int cur_timestamp_in_us; 1202 unsigned long long cur_tick; 1203 1204 if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL)) 1205 return; 1206 1207 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1208 1209 if (in_out_vrr->supported == false) 1210 return; 1211 1212 cur_tick = dm_get_timestamp(core_freesync->dc->ctx); 1213 cur_timestamp_in_us = (unsigned int) 1214 div_u64(dm_get_elapse_time_in_ns(core_freesync->dc->ctx, cur_tick, 0), 1000); 1215 1216 in_out_vrr->flip_interval.vsyncs_between_flip++; 1217 in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us; 1218 1219 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1220 (in_out_vrr->flip_interval.flip_interval_workaround_active || 1221 (!in_out_vrr->flip_interval.flip_interval_workaround_active && 1222 in_out_vrr->flip_interval.program_flip_interval_workaround))) { 1223 // set freesync vmin vmax to nominal for workaround 1224 in_out_vrr->adjust.v_total_min = 1225 mod_freesync_calc_v_total_from_refresh( 1226 stream, in_out_vrr->max_refresh_in_uhz); 1227 in_out_vrr->adjust.v_total_max = 1228 in_out_vrr->adjust.v_total_min; 1229 in_out_vrr->flip_interval.program_flip_interval_workaround = false; 1230 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true; 1231 return; 1232 } 1233 1234 if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE && 1235 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) { 1236 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false; 1237 in_out_vrr->flip_interval.flip_interval_detect_counter = 0; 1238 in_out_vrr->flip_interval.vsyncs_between_flip = 0; 1239 in_out_vrr->flip_interval.vsync_to_flip_in_us = 0; 1240 } 1241 1242 /* Below the Range Logic */ 1243 1244 /* Only execute if in fullscreen mode */ 1245 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1246 in_out_vrr->btr.btr_active) { 1247 /* TODO: pass in flag for Pre-DCE12 ASIC 1248 * in order for frame variable duration to take affect, 1249 * it needs to be done one VSYNC early, which is at 1250 * frameCounter == 1. 1251 * For DCE12 and newer updates to V_TOTAL_MIN/MAX 1252 * will take affect on current frame 1253 */ 1254 if (in_out_vrr->btr.frames_to_insert == 1255 in_out_vrr->btr.frame_counter) { 1256 in_out_vrr->adjust.v_total_min = 1257 calc_v_total_from_duration(stream, 1258 in_out_vrr, 1259 in_out_vrr->btr.inserted_duration_in_us); 1260 in_out_vrr->adjust.v_total_max = 1261 in_out_vrr->adjust.v_total_min; 1262 } 1263 1264 if (in_out_vrr->btr.frame_counter > 0) 1265 in_out_vrr->btr.frame_counter--; 1266 1267 /* Restore FreeSync */ 1268 if (in_out_vrr->btr.frame_counter == 0) { 1269 in_out_vrr->adjust.v_total_min = 1270 mod_freesync_calc_v_total_from_refresh(stream, 1271 in_out_vrr->max_refresh_in_uhz); 1272 in_out_vrr->adjust.v_total_max = 1273 mod_freesync_calc_v_total_from_refresh(stream, 1274 in_out_vrr->min_refresh_in_uhz); 1275 } 1276 } 1277 1278 /* If in fullscreen freesync mode or in video, do not program 1279 * static screen ramp values 1280 */ 1281 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) 1282 in_out_vrr->fixed.ramping_active = false; 1283 1284 /* Gradual Static Screen Ramping Logic 1285 * Execute if ramp is active and user enabled freesync static screen 1286 */ 1287 if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED && 1288 in_out_vrr->fixed.ramping_active) { 1289 update_v_total_for_static_ramp( 1290 core_freesync, stream, in_out_vrr); 1291 } 1292 } 1293 1294 void mod_freesync_get_settings(struct mod_freesync *mod_freesync, 1295 const struct mod_vrr_params *vrr, 1296 unsigned int *v_total_min, unsigned int *v_total_max, 1297 unsigned int *event_triggers, 1298 unsigned int *window_min, unsigned int *window_max, 1299 unsigned int *lfc_mid_point_in_us, 1300 unsigned int *inserted_frames, 1301 unsigned int *inserted_duration_in_us) 1302 { 1303 if (mod_freesync == NULL) 1304 return; 1305 1306 if (vrr->supported) { 1307 *v_total_min = vrr->adjust.v_total_min; 1308 *v_total_max = vrr->adjust.v_total_max; 1309 *event_triggers = 0; 1310 *lfc_mid_point_in_us = vrr->btr.mid_point_in_us; 1311 *inserted_frames = vrr->btr.frames_to_insert; 1312 *inserted_duration_in_us = vrr->btr.inserted_duration_in_us; 1313 } 1314 } 1315 1316 unsigned long long mod_freesync_calc_nominal_field_rate( 1317 const struct dc_stream_state *stream) 1318 { 1319 unsigned long long nominal_field_rate_in_uhz = 0; 1320 unsigned int total = stream->timing.h_total * stream->timing.v_total; 1321 1322 /* Calculate nominal field rate for stream, rounded up to nearest integer */ 1323 nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz; 1324 nominal_field_rate_in_uhz *= 100000000ULL; 1325 1326 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total); 1327 1328 return nominal_field_rate_in_uhz; 1329 } 1330 1331 unsigned long long mod_freesync_calc_field_rate_from_timing( 1332 unsigned int vtotal, unsigned int htotal, unsigned int pix_clk) 1333 { 1334 unsigned long long field_rate_in_uhz = 0; 1335 unsigned int total = htotal * vtotal; 1336 1337 /* Calculate nominal field rate for stream, rounded up to nearest integer */ 1338 field_rate_in_uhz = pix_clk; 1339 field_rate_in_uhz *= 1000000ULL; 1340 1341 field_rate_in_uhz = div_u64(field_rate_in_uhz, total); 1342 1343 return field_rate_in_uhz; 1344 } 1345 1346 bool mod_freesync_get_freesync_enabled(struct mod_vrr_params *pVrr) 1347 { 1348 return (pVrr->state != VRR_STATE_UNSUPPORTED) && (pVrr->state != VRR_STATE_DISABLED); 1349 } 1350 1351 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, 1352 uint32_t max_refresh_cap_in_uhz, 1353 uint32_t nominal_field_rate_in_uhz) 1354 { 1355 1356 /* Typically nominal refresh calculated can have some fractional part. 1357 * Allow for some rounding error of actual video timing by taking floor 1358 * of caps and request. Round the nominal refresh rate. 1359 * 1360 * Dividing will convert everything to units in Hz although input 1361 * variable name is in uHz! 1362 * 1363 * Also note, this takes care of rounding error on the nominal refresh 1364 * so by rounding error we only expect it to be off by a small amount, 1365 * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx. 1366 * 1367 * Example 1. Caps Min = 40 Hz, Max = 144 Hz 1368 * Request Min = 40 Hz, Max = 144 Hz 1369 * Nominal = 143.5x Hz rounded to 144 Hz 1370 * This function should allow this as valid request 1371 * 1372 * Example 2. Caps Min = 40 Hz, Max = 144 Hz 1373 * Request Min = 40 Hz, Max = 144 Hz 1374 * Nominal = 144.4x Hz rounded to 144 Hz 1375 * This function should allow this as valid request 1376 * 1377 * Example 3. Caps Min = 40 Hz, Max = 144 Hz 1378 * Request Min = 40 Hz, Max = 144 Hz 1379 * Nominal = 120.xx Hz rounded to 120 Hz 1380 * This function should return NOT valid since the requested 1381 * max is greater than current timing's nominal 1382 * 1383 * Example 4. Caps Min = 40 Hz, Max = 120 Hz 1384 * Request Min = 40 Hz, Max = 120 Hz 1385 * Nominal = 144.xx Hz rounded to 144 Hz 1386 * This function should return NOT valid since the nominal 1387 * is greater than the capability's max refresh 1388 */ 1389 nominal_field_rate_in_uhz = 1390 div_u64(nominal_field_rate_in_uhz + 500000, 1000000); 1391 min_refresh_cap_in_uhz /= 1000000; 1392 max_refresh_cap_in_uhz /= 1000000; 1393 1394 /* Check nominal is within range */ 1395 if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz || 1396 nominal_field_rate_in_uhz < min_refresh_cap_in_uhz) 1397 return false; 1398 1399 /* If nominal is less than max, limit the max allowed refresh rate */ 1400 if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz) 1401 max_refresh_cap_in_uhz = nominal_field_rate_in_uhz; 1402 1403 /* Check min is within range */ 1404 if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz) 1405 return false; 1406 1407 /* For variable range, check for at least 10 Hz range */ 1408 if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10) 1409 return false; 1410 1411 return true; 1412 } 1413