1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/slab.h> 27 28 #include "dm_services.h" 29 #include "dc.h" 30 #include "mod_freesync.h" 31 #include "core_types.h" 32 #include "dm_services.h" 33 34 #define MOD_FREESYNC_MAX_CONCURRENT_STREAMS 32 35 36 #define MIN_REFRESH_RANGE 10 37 /* Refresh rate ramp at a fixed rate of 65 Hz/second */ 38 #define STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME ((1000 / 60) * 65) 39 /* Number of elements in the render times cache array */ 40 #define RENDER_TIMES_MAX_COUNT 10 41 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */ 42 #define BTR_MAX_MARGIN 2500 43 /* Threshold to change BTR multiplier (to avoid frequent changes) */ 44 #define BTR_DRIFT_MARGIN 2000 45 /* Threshold to exit fixed refresh rate */ 46 #define FIXED_REFRESH_EXIT_MARGIN_IN_HZ 1 47 /* Number of consecutive frames to check before entering/exiting fixed refresh */ 48 #define FIXED_REFRESH_ENTER_FRAME_COUNT 5 49 #define FIXED_REFRESH_EXIT_FRAME_COUNT 10 50 /* Flip interval workaround constants */ 51 #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2 52 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5 53 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500 54 55 struct core_freesync { 56 struct mod_freesync public; 57 struct dc *dc; 58 }; 59 60 #define MOD_FREESYNC_TO_CORE(mod_freesync)\ 61 container_of(mod_freesync, struct core_freesync, public) 62 63 struct mod_freesync *mod_freesync_create(struct dc *dc) 64 { 65 struct core_freesync *core_freesync = 66 kzalloc(sizeof(struct core_freesync), GFP_KERNEL); 67 68 if (core_freesync == NULL) 69 goto fail_alloc_context; 70 71 if (dc == NULL) 72 goto fail_construct; 73 74 core_freesync->dc = dc; 75 return &core_freesync->public; 76 77 fail_construct: 78 kfree(core_freesync); 79 80 fail_alloc_context: 81 return NULL; 82 } 83 84 void mod_freesync_destroy(struct mod_freesync *mod_freesync) 85 { 86 struct core_freesync *core_freesync = NULL; 87 if (mod_freesync == NULL) 88 return; 89 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 90 kfree(core_freesync); 91 } 92 93 #if 0 /* Unused currently */ 94 static unsigned int calc_refresh_in_uhz_from_duration( 95 unsigned int duration_in_ns) 96 { 97 unsigned int refresh_in_uhz = 98 ((unsigned int)(div64_u64((1000000000ULL * 1000000), 99 duration_in_ns))); 100 return refresh_in_uhz; 101 } 102 #endif 103 104 static unsigned int calc_duration_in_us_from_refresh_in_uhz( 105 unsigned int refresh_in_uhz) 106 { 107 unsigned int duration_in_us = 108 ((unsigned int)(div64_u64((1000000000ULL * 1000), 109 refresh_in_uhz))); 110 return duration_in_us; 111 } 112 113 static unsigned int calc_duration_in_us_from_v_total( 114 const struct dc_stream_state *stream, 115 const struct mod_vrr_params *in_vrr, 116 unsigned int v_total) 117 { 118 unsigned int duration_in_us = 119 (unsigned int)(div64_u64(((unsigned long long)(v_total) 120 * 10000) * stream->timing.h_total, 121 stream->timing.pix_clk_100hz)); 122 123 return duration_in_us; 124 } 125 126 unsigned int mod_freesync_calc_v_total_from_refresh( 127 const struct dc_stream_state *stream, 128 unsigned int refresh_in_uhz) 129 { 130 unsigned int v_total; 131 unsigned int frame_duration_in_ns; 132 133 frame_duration_in_ns = 134 ((unsigned int)(div64_u64((1000000000ULL * 1000000), 135 refresh_in_uhz))); 136 137 v_total = div64_u64(div64_u64(((unsigned long long)( 138 frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), 139 stream->timing.h_total), 1000000); 140 141 /* v_total cannot be less than nominal */ 142 if (v_total < stream->timing.v_total) { 143 ASSERT(v_total < stream->timing.v_total); 144 v_total = stream->timing.v_total; 145 } 146 147 return v_total; 148 } 149 150 static unsigned int calc_v_total_from_duration( 151 const struct dc_stream_state *stream, 152 const struct mod_vrr_params *vrr, 153 unsigned int duration_in_us) 154 { 155 unsigned int v_total = 0; 156 157 if (duration_in_us < vrr->min_duration_in_us) 158 duration_in_us = vrr->min_duration_in_us; 159 160 if (duration_in_us > vrr->max_duration_in_us) 161 duration_in_us = vrr->max_duration_in_us; 162 163 if (dc_is_hdmi_signal(stream->signal)) { 164 uint32_t h_total_up_scaled; 165 166 h_total_up_scaled = stream->timing.h_total * 10000; 167 v_total = div_u64((unsigned long long)duration_in_us 168 * stream->timing.pix_clk_100hz + (h_total_up_scaled - 1), 169 h_total_up_scaled); 170 } else { 171 v_total = div64_u64(div64_u64(((unsigned long long)( 172 duration_in_us) * (stream->timing.pix_clk_100hz / 10)), 173 stream->timing.h_total), 1000); 174 } 175 176 /* v_total cannot be less than nominal */ 177 if (v_total < stream->timing.v_total) { 178 ASSERT(v_total < stream->timing.v_total); 179 v_total = stream->timing.v_total; 180 } 181 182 return v_total; 183 } 184 185 static void update_v_total_for_static_ramp( 186 struct core_freesync *core_freesync, 187 const struct dc_stream_state *stream, 188 struct mod_vrr_params *in_out_vrr) 189 { 190 unsigned int v_total = 0; 191 unsigned int current_duration_in_us = 192 calc_duration_in_us_from_v_total( 193 stream, in_out_vrr, 194 in_out_vrr->adjust.v_total_max); 195 unsigned int target_duration_in_us = 196 calc_duration_in_us_from_refresh_in_uhz( 197 in_out_vrr->fixed.target_refresh_in_uhz); 198 bool ramp_direction_is_up = (current_duration_in_us > 199 target_duration_in_us) ? true : false; 200 201 /* Calculate ratio between new and current frame duration with 3 digit */ 202 unsigned int frame_duration_ratio = div64_u64(1000000, 203 (1000 + div64_u64(((unsigned long long)( 204 STATIC_SCREEN_RAMP_DELTA_REFRESH_RATE_PER_FRAME) * 205 current_duration_in_us), 206 1000000))); 207 208 /* Calculate delta between new and current frame duration in us */ 209 unsigned int frame_duration_delta = div64_u64(((unsigned long long)( 210 current_duration_in_us) * 211 (1000 - frame_duration_ratio)), 1000); 212 213 /* Adjust frame duration delta based on ratio between current and 214 * standard frame duration (frame duration at 60 Hz refresh rate). 215 */ 216 unsigned int ramp_rate_interpolated = div64_u64(((unsigned long long)( 217 frame_duration_delta) * current_duration_in_us), 16666); 218 219 /* Going to a higher refresh rate (lower frame duration) */ 220 if (ramp_direction_is_up) { 221 /* Reduce frame duration */ 222 current_duration_in_us -= ramp_rate_interpolated; 223 224 /* Adjust for frame duration below min */ 225 if (current_duration_in_us <= target_duration_in_us) { 226 in_out_vrr->fixed.ramping_active = false; 227 in_out_vrr->fixed.ramping_done = true; 228 current_duration_in_us = 229 calc_duration_in_us_from_refresh_in_uhz( 230 in_out_vrr->fixed.target_refresh_in_uhz); 231 } 232 /* Going to a lower refresh rate (larger frame duration) */ 233 } else { 234 /* Increase frame duration */ 235 current_duration_in_us += ramp_rate_interpolated; 236 237 /* Adjust for frame duration above max */ 238 if (current_duration_in_us >= target_duration_in_us) { 239 in_out_vrr->fixed.ramping_active = false; 240 in_out_vrr->fixed.ramping_done = true; 241 current_duration_in_us = 242 calc_duration_in_us_from_refresh_in_uhz( 243 in_out_vrr->fixed.target_refresh_in_uhz); 244 } 245 } 246 247 v_total = div64_u64(div64_u64(((unsigned long long)( 248 current_duration_in_us) * (stream->timing.pix_clk_100hz / 10)), 249 stream->timing.h_total), 1000); 250 251 /* v_total cannot be less than nominal */ 252 if (v_total < stream->timing.v_total) 253 v_total = stream->timing.v_total; 254 255 in_out_vrr->adjust.v_total_min = v_total; 256 in_out_vrr->adjust.v_total_max = v_total; 257 } 258 259 static void apply_below_the_range(struct core_freesync *core_freesync, 260 const struct dc_stream_state *stream, 261 unsigned int last_render_time_in_us, 262 struct mod_vrr_params *in_out_vrr) 263 { 264 unsigned int inserted_frame_duration_in_us = 0; 265 unsigned int mid_point_frames_ceil = 0; 266 unsigned int mid_point_frames_floor = 0; 267 unsigned int frame_time_in_us = 0; 268 unsigned int delta_from_mid_point_in_us_1 = 0xFFFFFFFF; 269 unsigned int delta_from_mid_point_in_us_2 = 0xFFFFFFFF; 270 unsigned int frames_to_insert = 0; 271 unsigned int delta_from_mid_point_delta_in_us; 272 unsigned int max_render_time_in_us = 273 in_out_vrr->max_duration_in_us - in_out_vrr->btr.margin_in_us; 274 275 /* Program BTR */ 276 if ((last_render_time_in_us + in_out_vrr->btr.margin_in_us / 2) < max_render_time_in_us) { 277 /* Exit Below the Range */ 278 if (in_out_vrr->btr.btr_active) { 279 in_out_vrr->btr.frame_counter = 0; 280 in_out_vrr->btr.btr_active = false; 281 } 282 } else if (last_render_time_in_us > (max_render_time_in_us + in_out_vrr->btr.margin_in_us / 2)) { 283 /* Enter Below the Range */ 284 if (!in_out_vrr->btr.btr_active) { 285 in_out_vrr->btr.btr_active = true; 286 } 287 } 288 289 /* BTR set to "not active" so disengage */ 290 if (!in_out_vrr->btr.btr_active) { 291 in_out_vrr->btr.inserted_duration_in_us = 0; 292 in_out_vrr->btr.frames_to_insert = 0; 293 in_out_vrr->btr.frame_counter = 0; 294 295 /* Restore FreeSync */ 296 in_out_vrr->adjust.v_total_min = 297 mod_freesync_calc_v_total_from_refresh(stream, 298 in_out_vrr->max_refresh_in_uhz); 299 in_out_vrr->adjust.v_total_max = 300 mod_freesync_calc_v_total_from_refresh(stream, 301 in_out_vrr->min_refresh_in_uhz); 302 /* BTR set to "active" so engage */ 303 } else { 304 305 /* Calculate number of midPoint frames that could fit within 306 * the render time interval - take ceil of this value 307 */ 308 mid_point_frames_ceil = (last_render_time_in_us + 309 in_out_vrr->btr.mid_point_in_us - 1) / 310 in_out_vrr->btr.mid_point_in_us; 311 312 if (mid_point_frames_ceil > 0) { 313 frame_time_in_us = last_render_time_in_us / 314 mid_point_frames_ceil; 315 delta_from_mid_point_in_us_1 = 316 (in_out_vrr->btr.mid_point_in_us > 317 frame_time_in_us) ? 318 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) : 319 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us); 320 } 321 322 /* Calculate number of midPoint frames that could fit within 323 * the render time interval - take floor of this value 324 */ 325 mid_point_frames_floor = last_render_time_in_us / 326 in_out_vrr->btr.mid_point_in_us; 327 328 if (mid_point_frames_floor > 0) { 329 330 frame_time_in_us = last_render_time_in_us / 331 mid_point_frames_floor; 332 delta_from_mid_point_in_us_2 = 333 (in_out_vrr->btr.mid_point_in_us > 334 frame_time_in_us) ? 335 (in_out_vrr->btr.mid_point_in_us - frame_time_in_us) : 336 (frame_time_in_us - in_out_vrr->btr.mid_point_in_us); 337 } 338 339 /* Choose number of frames to insert based on how close it 340 * can get to the mid point of the variable range. 341 * - Delta for CEIL: delta_from_mid_point_in_us_1 342 * - Delta for FLOOR: delta_from_mid_point_in_us_2 343 */ 344 if ((last_render_time_in_us / mid_point_frames_ceil) < in_out_vrr->min_duration_in_us) { 345 /* Check for out of range. 346 * If using CEIL produces a value that is out of range, 347 * then we are forced to use FLOOR. 348 */ 349 frames_to_insert = mid_point_frames_floor; 350 } else if (mid_point_frames_floor < 2) { 351 /* Check if FLOOR would result in non-LFC. In this case 352 * choose to use CEIL 353 */ 354 frames_to_insert = mid_point_frames_ceil; 355 } else if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) { 356 /* If choosing CEIL results in a frame duration that is 357 * closer to the mid point of the range. 358 * Choose CEIL 359 */ 360 frames_to_insert = mid_point_frames_ceil; 361 } else { 362 /* If choosing FLOOR results in a frame duration that is 363 * closer to the mid point of the range. 364 * Choose FLOOR 365 */ 366 frames_to_insert = mid_point_frames_floor; 367 } 368 369 /* Prefer current frame multiplier when BTR is enabled unless it drifts 370 * too far from the midpoint 371 */ 372 if (delta_from_mid_point_in_us_1 < delta_from_mid_point_in_us_2) { 373 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_2 - 374 delta_from_mid_point_in_us_1; 375 } else { 376 delta_from_mid_point_delta_in_us = delta_from_mid_point_in_us_1 - 377 delta_from_mid_point_in_us_2; 378 } 379 if (in_out_vrr->btr.frames_to_insert != 0 && 380 delta_from_mid_point_delta_in_us < BTR_DRIFT_MARGIN) { 381 if (((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) < 382 max_render_time_in_us) && 383 ((last_render_time_in_us / in_out_vrr->btr.frames_to_insert) > 384 in_out_vrr->min_duration_in_us)) 385 frames_to_insert = in_out_vrr->btr.frames_to_insert; 386 } 387 388 /* Either we've calculated the number of frames to insert, 389 * or we need to insert min duration frames 390 */ 391 if (last_render_time_in_us / frames_to_insert < 392 in_out_vrr->min_duration_in_us){ 393 frames_to_insert -= (frames_to_insert > 1) ? 394 1 : 0; 395 } 396 397 if (frames_to_insert > 0) 398 inserted_frame_duration_in_us = last_render_time_in_us / 399 frames_to_insert; 400 401 if (inserted_frame_duration_in_us < in_out_vrr->min_duration_in_us) 402 inserted_frame_duration_in_us = in_out_vrr->min_duration_in_us; 403 404 /* Cache the calculated variables */ 405 in_out_vrr->btr.inserted_duration_in_us = 406 inserted_frame_duration_in_us; 407 in_out_vrr->btr.frames_to_insert = frames_to_insert; 408 in_out_vrr->btr.frame_counter = frames_to_insert; 409 } 410 } 411 412 static void apply_fixed_refresh(struct core_freesync *core_freesync, 413 const struct dc_stream_state *stream, 414 unsigned int last_render_time_in_us, 415 struct mod_vrr_params *in_out_vrr) 416 { 417 bool update = false; 418 unsigned int max_render_time_in_us = in_out_vrr->max_duration_in_us; 419 420 /* Compute the exit refresh rate and exit frame duration */ 421 unsigned int exit_refresh_rate_in_milli_hz = ((1000000000/max_render_time_in_us) 422 + (1000*FIXED_REFRESH_EXIT_MARGIN_IN_HZ)); 423 unsigned int exit_frame_duration_in_us = 1000000000/exit_refresh_rate_in_milli_hz; 424 425 if (last_render_time_in_us < exit_frame_duration_in_us) { 426 /* Exit Fixed Refresh mode */ 427 if (in_out_vrr->fixed.fixed_active) { 428 in_out_vrr->fixed.frame_counter++; 429 430 if (in_out_vrr->fixed.frame_counter > 431 FIXED_REFRESH_EXIT_FRAME_COUNT) { 432 in_out_vrr->fixed.frame_counter = 0; 433 in_out_vrr->fixed.fixed_active = false; 434 in_out_vrr->fixed.target_refresh_in_uhz = 0; 435 update = true; 436 } 437 } else 438 in_out_vrr->fixed.frame_counter = 0; 439 } else if (last_render_time_in_us > max_render_time_in_us) { 440 /* Enter Fixed Refresh mode */ 441 if (!in_out_vrr->fixed.fixed_active) { 442 in_out_vrr->fixed.frame_counter++; 443 444 if (in_out_vrr->fixed.frame_counter > 445 FIXED_REFRESH_ENTER_FRAME_COUNT) { 446 in_out_vrr->fixed.frame_counter = 0; 447 in_out_vrr->fixed.fixed_active = true; 448 in_out_vrr->fixed.target_refresh_in_uhz = 449 in_out_vrr->max_refresh_in_uhz; 450 update = true; 451 } 452 } else 453 in_out_vrr->fixed.frame_counter = 0; 454 } 455 456 if (update) { 457 if (in_out_vrr->fixed.fixed_active) { 458 in_out_vrr->adjust.v_total_min = 459 mod_freesync_calc_v_total_from_refresh( 460 stream, in_out_vrr->max_refresh_in_uhz); 461 in_out_vrr->adjust.v_total_max = 462 in_out_vrr->adjust.v_total_min; 463 } else { 464 in_out_vrr->adjust.v_total_min = 465 mod_freesync_calc_v_total_from_refresh(stream, 466 in_out_vrr->max_refresh_in_uhz); 467 in_out_vrr->adjust.v_total_max = 468 mod_freesync_calc_v_total_from_refresh(stream, 469 in_out_vrr->min_refresh_in_uhz); 470 } 471 } 472 } 473 474 static void determine_flip_interval_workaround_req(struct mod_vrr_params *in_vrr, 475 unsigned int curr_time_stamp_in_us) 476 { 477 in_vrr->flip_interval.vsync_to_flip_in_us = curr_time_stamp_in_us - 478 in_vrr->flip_interval.v_update_timestamp_in_us; 479 480 /* Determine conditions for stopping workaround */ 481 if (in_vrr->flip_interval.flip_interval_workaround_active && 482 in_vrr->flip_interval.vsyncs_between_flip < VSYNCS_BETWEEN_FLIP_THRESHOLD && 483 in_vrr->flip_interval.vsync_to_flip_in_us > FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) { 484 in_vrr->flip_interval.flip_interval_detect_counter = 0; 485 in_vrr->flip_interval.program_flip_interval_workaround = true; 486 in_vrr->flip_interval.flip_interval_workaround_active = false; 487 } else { 488 /* Determine conditions for starting workaround */ 489 if (in_vrr->flip_interval.vsyncs_between_flip >= VSYNCS_BETWEEN_FLIP_THRESHOLD && 490 in_vrr->flip_interval.vsync_to_flip_in_us < FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US) { 491 /* Increase flip interval counter we have 2 vsyncs between flips and 492 * vsync to flip interval is less than 500us 493 */ 494 in_vrr->flip_interval.flip_interval_detect_counter++; 495 if (in_vrr->flip_interval.flip_interval_detect_counter > FREESYNC_CONSEC_FLIP_AFTER_VSYNC) { 496 /* Start workaround if we detect 5 consecutive instances of the above case */ 497 in_vrr->flip_interval.program_flip_interval_workaround = true; 498 in_vrr->flip_interval.flip_interval_workaround_active = true; 499 } 500 } else { 501 /* Reset the flip interval counter if we condition is no longer met */ 502 in_vrr->flip_interval.flip_interval_detect_counter = 0; 503 } 504 } 505 506 in_vrr->flip_interval.vsyncs_between_flip = 0; 507 } 508 509 static bool vrr_settings_require_update(struct core_freesync *core_freesync, 510 struct mod_freesync_config *in_config, 511 unsigned int min_refresh_in_uhz, 512 unsigned int max_refresh_in_uhz, 513 struct mod_vrr_params *in_vrr) 514 { 515 if (in_vrr->state != in_config->state) { 516 return true; 517 } else if (in_vrr->state == VRR_STATE_ACTIVE_FIXED && 518 in_vrr->fixed.target_refresh_in_uhz != 519 in_config->fixed_refresh_in_uhz) { 520 return true; 521 } else if (in_vrr->min_refresh_in_uhz != min_refresh_in_uhz) { 522 return true; 523 } else if (in_vrr->max_refresh_in_uhz != max_refresh_in_uhz) { 524 return true; 525 } 526 527 return false; 528 } 529 530 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, 531 const struct dc_stream_state *stream, 532 unsigned int *vmin, 533 unsigned int *vmax) 534 { 535 *vmin = stream->adjust.v_total_min; 536 *vmax = stream->adjust.v_total_max; 537 538 return true; 539 } 540 541 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, 542 struct dc_stream_state *stream, 543 unsigned int *nom_v_pos, 544 unsigned int *v_pos) 545 { 546 struct core_freesync *core_freesync = NULL; 547 struct crtc_position position; 548 549 if (mod_freesync == NULL) 550 return false; 551 552 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 553 554 if (dc_stream_get_crtc_position(core_freesync->dc, &stream, 1, 555 &position.vertical_count, 556 &position.nominal_vcount)) { 557 558 *nom_v_pos = position.nominal_vcount; 559 *v_pos = position.vertical_count; 560 561 return true; 562 } 563 564 return false; 565 } 566 567 static void build_vrr_infopacket_data_v1(const struct mod_vrr_params *vrr, 568 struct dc_info_packet *infopacket, 569 bool freesync_on_desktop) 570 { 571 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 572 infopacket->sb[1] = 0x1A; 573 574 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 575 infopacket->sb[2] = 0x00; 576 577 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 578 infopacket->sb[3] = 0x00; 579 580 /* PB4 = Reserved */ 581 582 /* PB5 = Reserved */ 583 584 /* PB6 = [Bits 7:3 = Reserved] */ 585 586 /* PB6 = [Bit 0 = FreeSync Supported] */ 587 if (vrr->state != VRR_STATE_UNSUPPORTED) 588 infopacket->sb[6] |= 0x01; 589 590 /* PB6 = [Bit 1 = FreeSync Enabled] */ 591 if (vrr->state != VRR_STATE_DISABLED && 592 vrr->state != VRR_STATE_UNSUPPORTED) 593 infopacket->sb[6] |= 0x02; 594 595 if (freesync_on_desktop) { 596 /* PB6 = [Bit 2 = FreeSync Active] */ 597 if (vrr->state != VRR_STATE_DISABLED && 598 vrr->state != VRR_STATE_UNSUPPORTED) 599 infopacket->sb[6] |= 0x04; 600 } else { 601 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 602 vrr->state == VRR_STATE_ACTIVE_FIXED) 603 infopacket->sb[6] |= 0x04; 604 } 605 606 // For v1 & 2 infoframes program nominal if non-fs mode, otherwise full range 607 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 608 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 609 vrr->state == VRR_STATE_ACTIVE_FIXED) { 610 infopacket->sb[7] = (unsigned char)((vrr->min_refresh_in_uhz + 500000) / 1000000); 611 } else { 612 infopacket->sb[7] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000); 613 } 614 615 /* PB8 = FreeSync Maximum refresh rate (Hz) 616 * Note: We should never go above the field rate of the mode timing set. 617 */ 618 infopacket->sb[8] = (unsigned char)((vrr->max_refresh_in_uhz + 500000) / 1000000); 619 620 /* FreeSync HDR */ 621 infopacket->sb[9] = 0; 622 infopacket->sb[10] = 0; 623 } 624 625 static void build_vrr_infopacket_data_v3(const struct mod_vrr_params *vrr, 626 struct dc_info_packet *infopacket) 627 { 628 unsigned int min_refresh; 629 unsigned int max_refresh; 630 unsigned int fixed_refresh; 631 unsigned int min_programmed; 632 unsigned int max_programmed; 633 634 /* PB1 = 0x1A (24bit AMD IEEE OUI (0x00001A) - Byte 0) */ 635 infopacket->sb[1] = 0x1A; 636 637 /* PB2 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 1) */ 638 infopacket->sb[2] = 0x00; 639 640 /* PB3 = 0x00 (24bit AMD IEEE OUI (0x00001A) - Byte 2) */ 641 infopacket->sb[3] = 0x00; 642 643 /* PB4 = Reserved */ 644 645 /* PB5 = Reserved */ 646 647 /* PB6 = [Bits 7:3 = Reserved] */ 648 649 /* PB6 = [Bit 0 = FreeSync Supported] */ 650 if (vrr->state != VRR_STATE_UNSUPPORTED) 651 infopacket->sb[6] |= 0x01; 652 653 /* PB6 = [Bit 1 = FreeSync Enabled] */ 654 if (vrr->state != VRR_STATE_DISABLED && 655 vrr->state != VRR_STATE_UNSUPPORTED) 656 infopacket->sb[6] |= 0x02; 657 658 /* PB6 = [Bit 2 = FreeSync Active] */ 659 if (vrr->state == VRR_STATE_ACTIVE_VARIABLE || 660 vrr->state == VRR_STATE_ACTIVE_FIXED) 661 infopacket->sb[6] |= 0x04; 662 663 min_refresh = (vrr->min_refresh_in_uhz + 500000) / 1000000; 664 max_refresh = (vrr->max_refresh_in_uhz + 500000) / 1000000; 665 fixed_refresh = (vrr->fixed_refresh_in_uhz + 500000) / 1000000; 666 667 min_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh : 668 (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? min_refresh : 669 (vrr->state == VRR_STATE_INACTIVE) ? min_refresh : 670 max_refresh; // Non-fs case, program nominal range 671 672 max_programmed = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? fixed_refresh : 673 (vrr->state == VRR_STATE_ACTIVE_VARIABLE) ? max_refresh : 674 max_refresh;// Non-fs case, program nominal range 675 676 /* PB7 = FreeSync Minimum refresh rate (Hz) */ 677 infopacket->sb[7] = min_programmed & 0xFF; 678 679 /* PB8 = FreeSync Maximum refresh rate (Hz) */ 680 infopacket->sb[8] = max_programmed & 0xFF; 681 682 /* PB11 : MSB FreeSync Minimum refresh rate [Hz] - bits 9:8 */ 683 infopacket->sb[11] = (min_programmed >> 8) & 0x03; 684 685 /* PB12 : MSB FreeSync Maximum refresh rate [Hz] - bits 9:8 */ 686 infopacket->sb[12] = (max_programmed >> 8) & 0x03; 687 688 /* PB16 : Reserved bits 7:1, FixedRate bit 0 */ 689 infopacket->sb[16] = (vrr->state == VRR_STATE_ACTIVE_FIXED) ? 1 : 0; 690 691 //FreeSync HDR 692 infopacket->sb[9] = 0; 693 infopacket->sb[10] = 0; 694 } 695 696 static void build_vrr_infopacket_fs2_data(enum color_transfer_func app_tf, 697 struct dc_info_packet *infopacket) 698 { 699 if (app_tf != TRANSFER_FUNC_UNKNOWN) { 700 infopacket->valid = true; 701 702 infopacket->sb[6] |= 0x08; // PB6 = [Bit 3 = Native Color Active] 703 704 if (app_tf == TRANSFER_FUNC_GAMMA_22) { 705 infopacket->sb[9] |= 0x04; // PB6 = [Bit 2 = Gamma 2.2 EOTF Active] 706 } 707 } 708 } 709 710 static void build_vrr_infopacket_header_v1(enum signal_type signal, 711 struct dc_info_packet *infopacket, 712 unsigned int *payload_size) 713 { 714 if (dc_is_hdmi_signal(signal)) { 715 716 /* HEADER */ 717 718 /* HB0 = Packet Type = 0x83 (Source Product 719 * Descriptor InfoFrame) 720 */ 721 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 722 723 /* HB1 = Version = 0x01 */ 724 infopacket->hb1 = 0x01; 725 726 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x08] */ 727 infopacket->hb2 = 0x08; 728 729 *payload_size = 0x08; 730 731 } else if (dc_is_dp_signal(signal)) { 732 733 /* HEADER */ 734 735 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 736 * when used to associate audio related info packets 737 */ 738 infopacket->hb0 = 0x00; 739 740 /* HB1 = Packet Type = 0x83 (Source Product 741 * Descriptor InfoFrame) 742 */ 743 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 744 745 /* HB2 = [Bits 7:0 = Least significant eight bits - 746 * For INFOFRAME, the value must be 1Bh] 747 */ 748 infopacket->hb2 = 0x1B; 749 750 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x1] 751 * [Bits 1:0 = Most significant two bits = 0x00] 752 */ 753 infopacket->hb3 = 0x04; 754 755 *payload_size = 0x1B; 756 } 757 } 758 759 static void build_vrr_infopacket_header_v2(enum signal_type signal, 760 struct dc_info_packet *infopacket, 761 unsigned int *payload_size) 762 { 763 if (dc_is_hdmi_signal(signal)) { 764 765 /* HEADER */ 766 767 /* HB0 = Packet Type = 0x83 (Source Product 768 * Descriptor InfoFrame) 769 */ 770 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 771 772 /* HB1 = Version = 0x02 */ 773 infopacket->hb1 = 0x02; 774 775 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length = 0x09] */ 776 infopacket->hb2 = 0x09; 777 778 *payload_size = 0x0A; 779 780 } else if (dc_is_dp_signal(signal)) { 781 782 /* HEADER */ 783 784 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 785 * when used to associate audio related info packets 786 */ 787 infopacket->hb0 = 0x00; 788 789 /* HB1 = Packet Type = 0x83 (Source Product 790 * Descriptor InfoFrame) 791 */ 792 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 793 794 /* HB2 = [Bits 7:0 = Least significant eight bits - 795 * For INFOFRAME, the value must be 1Bh] 796 */ 797 infopacket->hb2 = 0x1B; 798 799 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2] 800 * [Bits 1:0 = Most significant two bits = 0x00] 801 */ 802 infopacket->hb3 = 0x08; 803 804 *payload_size = 0x1B; 805 } 806 } 807 808 static void build_vrr_infopacket_header_v3(enum signal_type signal, 809 struct dc_info_packet *infopacket, 810 unsigned int *payload_size) 811 { 812 unsigned char version; 813 814 version = 3; 815 if (dc_is_hdmi_signal(signal)) { 816 817 /* HEADER */ 818 819 /* HB0 = Packet Type = 0x83 (Source Product 820 * Descriptor InfoFrame) 821 */ 822 infopacket->hb0 = DC_HDMI_INFOFRAME_TYPE_SPD; 823 824 /* HB1 = Version = 0x03 */ 825 infopacket->hb1 = version; 826 827 /* HB2 = [Bits 7:5 = 0] [Bits 4:0 = Length] */ 828 *payload_size = 0x10; 829 infopacket->hb2 = *payload_size - 1; //-1 for checksum 830 831 } else if (dc_is_dp_signal(signal)) { 832 833 /* HEADER */ 834 835 /* HB0 = Secondary-data Packet ID = 0 - Only non-zero 836 * when used to associate audio related info packets 837 */ 838 infopacket->hb0 = 0x00; 839 840 /* HB1 = Packet Type = 0x83 (Source Product 841 * Descriptor InfoFrame) 842 */ 843 infopacket->hb1 = DC_HDMI_INFOFRAME_TYPE_SPD; 844 845 /* HB2 = [Bits 7:0 = Least significant eight bits - 846 * For INFOFRAME, the value must be 1Bh] 847 */ 848 infopacket->hb2 = 0x1B; 849 850 /* HB3 = [Bits 7:2 = INFOFRAME SDP Version Number = 0x2] 851 * [Bits 1:0 = Most significant two bits = 0x00] 852 */ 853 854 infopacket->hb3 = (version & 0x3F) << 2; 855 856 *payload_size = 0x1B; 857 } 858 } 859 860 static void build_vrr_infopacket_checksum(unsigned int *payload_size, 861 struct dc_info_packet *infopacket) 862 { 863 /* Calculate checksum */ 864 unsigned int idx = 0; 865 unsigned char checksum = 0; 866 867 checksum += infopacket->hb0; 868 checksum += infopacket->hb1; 869 checksum += infopacket->hb2; 870 checksum += infopacket->hb3; 871 872 for (idx = 1; idx <= *payload_size; idx++) 873 checksum += infopacket->sb[idx]; 874 875 /* PB0 = Checksum (one byte complement) */ 876 infopacket->sb[0] = (unsigned char)(0x100 - checksum); 877 878 infopacket->valid = true; 879 } 880 881 static void build_vrr_infopacket_v1(enum signal_type signal, 882 const struct mod_vrr_params *vrr, 883 struct dc_info_packet *infopacket, 884 bool freesync_on_desktop) 885 { 886 /* SPD info packet for FreeSync */ 887 unsigned int payload_size = 0; 888 889 build_vrr_infopacket_header_v1(signal, infopacket, &payload_size); 890 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); 891 build_vrr_infopacket_checksum(&payload_size, infopacket); 892 893 infopacket->valid = true; 894 } 895 896 static void build_vrr_infopacket_v2(enum signal_type signal, 897 const struct mod_vrr_params *vrr, 898 enum color_transfer_func app_tf, 899 struct dc_info_packet *infopacket, 900 bool freesync_on_desktop) 901 { 902 unsigned int payload_size = 0; 903 904 build_vrr_infopacket_header_v2(signal, infopacket, &payload_size); 905 build_vrr_infopacket_data_v1(vrr, infopacket, freesync_on_desktop); 906 907 build_vrr_infopacket_fs2_data(app_tf, infopacket); 908 909 build_vrr_infopacket_checksum(&payload_size, infopacket); 910 911 infopacket->valid = true; 912 } 913 #ifndef TRIM_FSFT 914 static void build_vrr_infopacket_fast_transport_data( 915 bool ftActive, 916 unsigned int ftOutputRate, 917 struct dc_info_packet *infopacket) 918 { 919 /* PB9 : bit7 - fast transport Active*/ 920 unsigned char activeBit = (ftActive) ? 1 << 7 : 0; 921 922 infopacket->sb[1] &= ~activeBit; //clear bit 923 infopacket->sb[1] |= activeBit; //set bit 924 925 /* PB13 : Target Output Pixel Rate [kHz] - bits 7:0 */ 926 infopacket->sb[13] = ftOutputRate & 0xFF; 927 928 /* PB14 : Target Output Pixel Rate [kHz] - bits 15:8 */ 929 infopacket->sb[14] = (ftOutputRate >> 8) & 0xFF; 930 931 /* PB15 : Target Output Pixel Rate [kHz] - bits 23:16 */ 932 infopacket->sb[15] = (ftOutputRate >> 16) & 0xFF; 933 934 } 935 #endif 936 937 static void build_vrr_infopacket_v3(enum signal_type signal, 938 const struct mod_vrr_params *vrr, 939 #ifndef TRIM_FSFT 940 bool ftActive, unsigned int ftOutputRate, 941 #endif 942 enum color_transfer_func app_tf, 943 struct dc_info_packet *infopacket) 944 { 945 unsigned int payload_size = 0; 946 947 build_vrr_infopacket_header_v3(signal, infopacket, &payload_size); 948 build_vrr_infopacket_data_v3(vrr, infopacket); 949 950 build_vrr_infopacket_fs2_data(app_tf, infopacket); 951 952 #ifndef TRIM_FSFT 953 build_vrr_infopacket_fast_transport_data( 954 ftActive, 955 ftOutputRate, 956 infopacket); 957 #endif 958 959 build_vrr_infopacket_checksum(&payload_size, infopacket); 960 961 infopacket->valid = true; 962 } 963 964 static void build_vrr_infopacket_sdp_v1_3(enum vrr_packet_type packet_type, 965 struct dc_info_packet *infopacket) 966 { 967 uint8_t idx = 0, size = 0; 968 969 size = ((packet_type == PACKET_TYPE_FS_V1) ? 0x08 : 970 (packet_type == PACKET_TYPE_FS_V3) ? 0x10 : 971 0x09); 972 973 for (idx = infopacket->hb2; idx > 1; idx--) // Data Byte Count: 0x1B 974 infopacket->sb[idx] = infopacket->sb[idx-1]; 975 976 infopacket->sb[1] = size; // Length 977 infopacket->sb[0] = (infopacket->hb3 >> 2) & 0x3F;//Version 978 infopacket->hb3 = (0x13 << 2); // Header,SDP 1.3 979 infopacket->hb2 = 0x1D; 980 } 981 982 void mod_freesync_build_vrr_infopacket(struct mod_freesync *mod_freesync, 983 const struct dc_stream_state *stream, 984 const struct mod_vrr_params *vrr, 985 enum vrr_packet_type packet_type, 986 enum color_transfer_func app_tf, 987 struct dc_info_packet *infopacket, 988 bool pack_sdp_v1_3) 989 { 990 /* SPD info packet for FreeSync 991 * VTEM info packet for HdmiVRR 992 * Check if Freesync is supported. Return if false. If true, 993 * set the corresponding bit in the info packet 994 */ 995 if (!vrr->send_info_frame) 996 return; 997 998 switch (packet_type) { 999 case PACKET_TYPE_FS_V3: 1000 #ifndef TRIM_FSFT 1001 // always populate with pixel rate. 1002 build_vrr_infopacket_v3( 1003 stream->signal, vrr, 1004 stream->timing.flags.FAST_TRANSPORT, 1005 (stream->timing.flags.FAST_TRANSPORT) ? 1006 stream->timing.fast_transport_output_rate_100hz : 1007 stream->timing.pix_clk_100hz, 1008 app_tf, infopacket); 1009 #else 1010 build_vrr_infopacket_v3(stream->signal, vrr, app_tf, infopacket); 1011 #endif 1012 break; 1013 case PACKET_TYPE_FS_V2: 1014 build_vrr_infopacket_v2(stream->signal, vrr, app_tf, infopacket, stream->freesync_on_desktop); 1015 break; 1016 case PACKET_TYPE_VRR: 1017 case PACKET_TYPE_FS_V1: 1018 default: 1019 build_vrr_infopacket_v1(stream->signal, vrr, infopacket, stream->freesync_on_desktop); 1020 } 1021 1022 if (true == pack_sdp_v1_3 && 1023 true == dc_is_dp_signal(stream->signal) && 1024 packet_type != PACKET_TYPE_VRR && 1025 packet_type != PACKET_TYPE_VTEM) 1026 build_vrr_infopacket_sdp_v1_3(packet_type, infopacket); 1027 } 1028 1029 void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, 1030 const struct dc_stream_state *stream, 1031 struct mod_freesync_config *in_config, 1032 struct mod_vrr_params *in_out_vrr) 1033 { 1034 struct core_freesync *core_freesync = NULL; 1035 unsigned long long nominal_field_rate_in_uhz = 0; 1036 unsigned long long rounded_nominal_in_uhz = 0; 1037 unsigned int refresh_range = 0; 1038 unsigned long long min_refresh_in_uhz = 0; 1039 unsigned long long max_refresh_in_uhz = 0; 1040 1041 if (mod_freesync == NULL) 1042 return; 1043 1044 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1045 1046 /* Calculate nominal field rate for stream */ 1047 nominal_field_rate_in_uhz = 1048 mod_freesync_calc_nominal_field_rate(stream); 1049 1050 min_refresh_in_uhz = in_config->min_refresh_in_uhz; 1051 max_refresh_in_uhz = in_config->max_refresh_in_uhz; 1052 1053 /* Full range may be larger than current video timing, so cap at nominal */ 1054 if (max_refresh_in_uhz > nominal_field_rate_in_uhz) 1055 max_refresh_in_uhz = nominal_field_rate_in_uhz; 1056 1057 /* Full range may be larger than current video timing, so cap at nominal */ 1058 if (min_refresh_in_uhz > max_refresh_in_uhz) 1059 min_refresh_in_uhz = max_refresh_in_uhz; 1060 1061 /* If a monitor reports exactly max refresh of 2x of min, enforce it on nominal */ 1062 rounded_nominal_in_uhz = 1063 div_u64(nominal_field_rate_in_uhz + 50000, 100000) * 100000; 1064 if (in_config->max_refresh_in_uhz == (2 * in_config->min_refresh_in_uhz) && 1065 in_config->max_refresh_in_uhz == rounded_nominal_in_uhz) 1066 min_refresh_in_uhz = div_u64(nominal_field_rate_in_uhz, 2); 1067 1068 if (!vrr_settings_require_update(core_freesync, 1069 in_config, (unsigned int)min_refresh_in_uhz, (unsigned int)max_refresh_in_uhz, 1070 in_out_vrr)) 1071 return; 1072 1073 in_out_vrr->state = in_config->state; 1074 in_out_vrr->send_info_frame = in_config->vsif_supported; 1075 1076 if (in_config->state == VRR_STATE_UNSUPPORTED) { 1077 in_out_vrr->state = VRR_STATE_UNSUPPORTED; 1078 in_out_vrr->supported = false; 1079 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1080 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1081 1082 return; 1083 1084 } else { 1085 in_out_vrr->min_refresh_in_uhz = (unsigned int)min_refresh_in_uhz; 1086 in_out_vrr->max_duration_in_us = 1087 calc_duration_in_us_from_refresh_in_uhz( 1088 (unsigned int)min_refresh_in_uhz); 1089 1090 in_out_vrr->max_refresh_in_uhz = (unsigned int)max_refresh_in_uhz; 1091 in_out_vrr->min_duration_in_us = 1092 calc_duration_in_us_from_refresh_in_uhz( 1093 (unsigned int)max_refresh_in_uhz); 1094 1095 if (in_config->state == VRR_STATE_ACTIVE_FIXED) 1096 in_out_vrr->fixed_refresh_in_uhz = in_config->fixed_refresh_in_uhz; 1097 else 1098 in_out_vrr->fixed_refresh_in_uhz = 0; 1099 1100 refresh_range = div_u64(in_out_vrr->max_refresh_in_uhz + 500000, 1000000) - 1101 + div_u64(in_out_vrr->min_refresh_in_uhz + 500000, 1000000); 1102 1103 in_out_vrr->supported = true; 1104 } 1105 1106 in_out_vrr->fixed.ramping_active = in_config->ramping; 1107 1108 in_out_vrr->btr.btr_enabled = in_config->btr; 1109 1110 if (in_out_vrr->max_refresh_in_uhz < (2 * in_out_vrr->min_refresh_in_uhz)) 1111 in_out_vrr->btr.btr_enabled = false; 1112 else { 1113 in_out_vrr->btr.margin_in_us = in_out_vrr->max_duration_in_us - 1114 2 * in_out_vrr->min_duration_in_us; 1115 if (in_out_vrr->btr.margin_in_us > BTR_MAX_MARGIN) 1116 in_out_vrr->btr.margin_in_us = BTR_MAX_MARGIN; 1117 } 1118 1119 in_out_vrr->btr.btr_active = false; 1120 in_out_vrr->btr.inserted_duration_in_us = 0; 1121 in_out_vrr->btr.frames_to_insert = 0; 1122 in_out_vrr->btr.frame_counter = 0; 1123 in_out_vrr->fixed.fixed_active = false; 1124 in_out_vrr->fixed.target_refresh_in_uhz = 0; 1125 1126 in_out_vrr->btr.mid_point_in_us = 1127 (in_out_vrr->min_duration_in_us + 1128 in_out_vrr->max_duration_in_us) / 2; 1129 1130 if (in_out_vrr->state == VRR_STATE_UNSUPPORTED) { 1131 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1132 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1133 } else if (in_out_vrr->state == VRR_STATE_DISABLED) { 1134 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1135 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1136 } else if (in_out_vrr->state == VRR_STATE_INACTIVE) { 1137 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1138 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1139 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1140 refresh_range >= MIN_REFRESH_RANGE) { 1141 1142 in_out_vrr->adjust.v_total_min = 1143 mod_freesync_calc_v_total_from_refresh(stream, 1144 in_out_vrr->max_refresh_in_uhz); 1145 in_out_vrr->adjust.v_total_max = 1146 mod_freesync_calc_v_total_from_refresh(stream, 1147 in_out_vrr->min_refresh_in_uhz); 1148 } else if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED) { 1149 in_out_vrr->fixed.target_refresh_in_uhz = 1150 in_out_vrr->fixed_refresh_in_uhz; 1151 if (in_out_vrr->fixed.ramping_active && 1152 in_out_vrr->fixed.fixed_active) { 1153 /* Do not update vtotals if ramping is already active 1154 * in order to continue ramp from current refresh. 1155 */ 1156 in_out_vrr->fixed.fixed_active = true; 1157 } else { 1158 in_out_vrr->fixed.fixed_active = true; 1159 in_out_vrr->adjust.v_total_min = 1160 mod_freesync_calc_v_total_from_refresh(stream, 1161 in_out_vrr->fixed.target_refresh_in_uhz); 1162 in_out_vrr->adjust.v_total_max = 1163 in_out_vrr->adjust.v_total_min; 1164 } 1165 } else { 1166 in_out_vrr->state = VRR_STATE_INACTIVE; 1167 in_out_vrr->adjust.v_total_min = stream->timing.v_total; 1168 in_out_vrr->adjust.v_total_max = stream->timing.v_total; 1169 } 1170 } 1171 1172 void mod_freesync_handle_preflip(struct mod_freesync *mod_freesync, 1173 const struct dc_plane_state *plane, 1174 const struct dc_stream_state *stream, 1175 unsigned int curr_time_stamp_in_us, 1176 struct mod_vrr_params *in_out_vrr) 1177 { 1178 struct core_freesync *core_freesync = NULL; 1179 unsigned int last_render_time_in_us = 0; 1180 unsigned int average_render_time_in_us = 0; 1181 1182 if (mod_freesync == NULL) 1183 return; 1184 1185 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1186 1187 if (in_out_vrr->supported && 1188 in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) { 1189 unsigned int i = 0; 1190 unsigned int oldest_index = plane->time.index + 1; 1191 1192 if (oldest_index >= DC_PLANE_UPDATE_TIMES_MAX) 1193 oldest_index = 0; 1194 1195 last_render_time_in_us = curr_time_stamp_in_us - 1196 plane->time.prev_update_time_in_us; 1197 1198 /* Sum off all entries except oldest one */ 1199 for (i = 0; i < DC_PLANE_UPDATE_TIMES_MAX; i++) { 1200 average_render_time_in_us += 1201 plane->time.time_elapsed_in_us[i]; 1202 } 1203 average_render_time_in_us -= 1204 plane->time.time_elapsed_in_us[oldest_index]; 1205 1206 /* Add render time for current flip */ 1207 average_render_time_in_us += last_render_time_in_us; 1208 average_render_time_in_us /= DC_PLANE_UPDATE_TIMES_MAX; 1209 1210 if (in_out_vrr->btr.btr_enabled) { 1211 apply_below_the_range(core_freesync, 1212 stream, 1213 last_render_time_in_us, 1214 in_out_vrr); 1215 } else { 1216 apply_fixed_refresh(core_freesync, 1217 stream, 1218 last_render_time_in_us, 1219 in_out_vrr); 1220 } 1221 1222 determine_flip_interval_workaround_req(in_out_vrr, 1223 curr_time_stamp_in_us); 1224 1225 } 1226 } 1227 1228 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, 1229 const struct dc_stream_state *stream, 1230 struct mod_vrr_params *in_out_vrr) 1231 { 1232 struct core_freesync *core_freesync = NULL; 1233 unsigned int cur_timestamp_in_us; 1234 1235 if ((mod_freesync == NULL) || (stream == NULL) || (in_out_vrr == NULL)) 1236 return; 1237 1238 core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); 1239 1240 if (in_out_vrr->supported == false) 1241 return; 1242 1243 cur_timestamp_in_us = dm_get_timestamp(core_freesync->dc->ctx)/10; 1244 1245 in_out_vrr->flip_interval.vsyncs_between_flip++; 1246 in_out_vrr->flip_interval.v_update_timestamp_in_us = cur_timestamp_in_us; 1247 1248 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1249 (in_out_vrr->flip_interval.flip_interval_workaround_active || 1250 (!in_out_vrr->flip_interval.flip_interval_workaround_active && 1251 in_out_vrr->flip_interval.program_flip_interval_workaround))) { 1252 // set freesync vmin vmax to nominal for workaround 1253 in_out_vrr->adjust.v_total_min = 1254 mod_freesync_calc_v_total_from_refresh( 1255 stream, in_out_vrr->max_refresh_in_uhz); 1256 in_out_vrr->adjust.v_total_max = 1257 in_out_vrr->adjust.v_total_min; 1258 in_out_vrr->flip_interval.program_flip_interval_workaround = false; 1259 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = true; 1260 return; 1261 } 1262 1263 if (in_out_vrr->state != VRR_STATE_ACTIVE_VARIABLE && 1264 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup) { 1265 in_out_vrr->flip_interval.do_flip_interval_workaround_cleanup = false; 1266 in_out_vrr->flip_interval.flip_interval_detect_counter = 0; 1267 in_out_vrr->flip_interval.vsyncs_between_flip = 0; 1268 in_out_vrr->flip_interval.vsync_to_flip_in_us = 0; 1269 } 1270 1271 /* Below the Range Logic */ 1272 1273 /* Only execute if in fullscreen mode */ 1274 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE && 1275 in_out_vrr->btr.btr_active) { 1276 /* TODO: pass in flag for Pre-DCE12 ASIC 1277 * in order for frame variable duration to take affect, 1278 * it needs to be done one VSYNC early, which is at 1279 * frameCounter == 1. 1280 * For DCE12 and newer updates to V_TOTAL_MIN/MAX 1281 * will take affect on current frame 1282 */ 1283 if (in_out_vrr->btr.frames_to_insert == 1284 in_out_vrr->btr.frame_counter) { 1285 in_out_vrr->adjust.v_total_min = 1286 calc_v_total_from_duration(stream, 1287 in_out_vrr, 1288 in_out_vrr->btr.inserted_duration_in_us); 1289 in_out_vrr->adjust.v_total_max = 1290 in_out_vrr->adjust.v_total_min; 1291 } 1292 1293 if (in_out_vrr->btr.frame_counter > 0) 1294 in_out_vrr->btr.frame_counter--; 1295 1296 /* Restore FreeSync */ 1297 if (in_out_vrr->btr.frame_counter == 0) { 1298 in_out_vrr->adjust.v_total_min = 1299 mod_freesync_calc_v_total_from_refresh(stream, 1300 in_out_vrr->max_refresh_in_uhz); 1301 in_out_vrr->adjust.v_total_max = 1302 mod_freesync_calc_v_total_from_refresh(stream, 1303 in_out_vrr->min_refresh_in_uhz); 1304 } 1305 } 1306 1307 /* If in fullscreen freesync mode or in video, do not program 1308 * static screen ramp values 1309 */ 1310 if (in_out_vrr->state == VRR_STATE_ACTIVE_VARIABLE) 1311 in_out_vrr->fixed.ramping_active = false; 1312 1313 /* Gradual Static Screen Ramping Logic 1314 * Execute if ramp is active and user enabled freesync static screen 1315 */ 1316 if (in_out_vrr->state == VRR_STATE_ACTIVE_FIXED && 1317 in_out_vrr->fixed.ramping_active) { 1318 update_v_total_for_static_ramp( 1319 core_freesync, stream, in_out_vrr); 1320 } 1321 } 1322 1323 void mod_freesync_get_settings(struct mod_freesync *mod_freesync, 1324 const struct mod_vrr_params *vrr, 1325 unsigned int *v_total_min, unsigned int *v_total_max, 1326 unsigned int *event_triggers, 1327 unsigned int *window_min, unsigned int *window_max, 1328 unsigned int *lfc_mid_point_in_us, 1329 unsigned int *inserted_frames, 1330 unsigned int *inserted_duration_in_us) 1331 { 1332 if (mod_freesync == NULL) 1333 return; 1334 1335 if (vrr->supported) { 1336 *v_total_min = vrr->adjust.v_total_min; 1337 *v_total_max = vrr->adjust.v_total_max; 1338 *event_triggers = 0; 1339 *lfc_mid_point_in_us = vrr->btr.mid_point_in_us; 1340 *inserted_frames = vrr->btr.frames_to_insert; 1341 *inserted_duration_in_us = vrr->btr.inserted_duration_in_us; 1342 } 1343 } 1344 1345 unsigned long long mod_freesync_calc_nominal_field_rate( 1346 const struct dc_stream_state *stream) 1347 { 1348 unsigned long long nominal_field_rate_in_uhz = 0; 1349 unsigned int total = stream->timing.h_total * stream->timing.v_total; 1350 1351 /* Calculate nominal field rate for stream, rounded up to nearest integer */ 1352 nominal_field_rate_in_uhz = stream->timing.pix_clk_100hz; 1353 nominal_field_rate_in_uhz *= 100000000ULL; 1354 1355 nominal_field_rate_in_uhz = div_u64(nominal_field_rate_in_uhz, total); 1356 1357 return nominal_field_rate_in_uhz; 1358 } 1359 1360 unsigned long long mod_freesync_calc_field_rate_from_timing( 1361 unsigned int vtotal, unsigned int htotal, unsigned int pix_clk) 1362 { 1363 unsigned long long field_rate_in_uhz = 0; 1364 unsigned int total = htotal * vtotal; 1365 1366 /* Calculate nominal field rate for stream, rounded up to nearest integer */ 1367 field_rate_in_uhz = pix_clk; 1368 field_rate_in_uhz *= 1000000ULL; 1369 1370 field_rate_in_uhz = div_u64(field_rate_in_uhz, total); 1371 1372 return field_rate_in_uhz; 1373 } 1374 1375 bool mod_freesync_is_valid_range(uint32_t min_refresh_cap_in_uhz, 1376 uint32_t max_refresh_cap_in_uhz, 1377 uint32_t nominal_field_rate_in_uhz) 1378 { 1379 1380 /* Typically nominal refresh calculated can have some fractional part. 1381 * Allow for some rounding error of actual video timing by taking floor 1382 * of caps and request. Round the nominal refresh rate. 1383 * 1384 * Dividing will convert everything to units in Hz although input 1385 * variable name is in uHz! 1386 * 1387 * Also note, this takes care of rounding error on the nominal refresh 1388 * so by rounding error we only expect it to be off by a small amount, 1389 * such as < 0.1 Hz. i.e. 143.9xxx or 144.1xxx. 1390 * 1391 * Example 1. Caps Min = 40 Hz, Max = 144 Hz 1392 * Request Min = 40 Hz, Max = 144 Hz 1393 * Nominal = 143.5x Hz rounded to 144 Hz 1394 * This function should allow this as valid request 1395 * 1396 * Example 2. Caps Min = 40 Hz, Max = 144 Hz 1397 * Request Min = 40 Hz, Max = 144 Hz 1398 * Nominal = 144.4x Hz rounded to 144 Hz 1399 * This function should allow this as valid request 1400 * 1401 * Example 3. Caps Min = 40 Hz, Max = 144 Hz 1402 * Request Min = 40 Hz, Max = 144 Hz 1403 * Nominal = 120.xx Hz rounded to 120 Hz 1404 * This function should return NOT valid since the requested 1405 * max is greater than current timing's nominal 1406 * 1407 * Example 4. Caps Min = 40 Hz, Max = 120 Hz 1408 * Request Min = 40 Hz, Max = 120 Hz 1409 * Nominal = 144.xx Hz rounded to 144 Hz 1410 * This function should return NOT valid since the nominal 1411 * is greater than the capability's max refresh 1412 */ 1413 nominal_field_rate_in_uhz = 1414 div_u64(nominal_field_rate_in_uhz + 500000, 1000000); 1415 min_refresh_cap_in_uhz /= 1000000; 1416 max_refresh_cap_in_uhz /= 1000000; 1417 1418 /* Check nominal is within range */ 1419 if (nominal_field_rate_in_uhz > max_refresh_cap_in_uhz || 1420 nominal_field_rate_in_uhz < min_refresh_cap_in_uhz) 1421 return false; 1422 1423 /* If nominal is less than max, limit the max allowed refresh rate */ 1424 if (nominal_field_rate_in_uhz < max_refresh_cap_in_uhz) 1425 max_refresh_cap_in_uhz = nominal_field_rate_in_uhz; 1426 1427 /* Check min is within range */ 1428 if (min_refresh_cap_in_uhz > max_refresh_cap_in_uhz) 1429 return false; 1430 1431 /* For variable range, check for at least 10 Hz range */ 1432 if (nominal_field_rate_in_uhz - min_refresh_cap_in_uhz < 10) 1433 return false; 1434 1435 return true; 1436 } 1437