xref: /linux/drivers/gpu/drm/amd/display/include/dpcd_defs.h (revision e2683c8868d03382da7e1ce8453b543a043066d1)
1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef __DAL_DPCD_DEFS_H__
27 #define __DAL_DPCD_DEFS_H__
28 
29 #include <drm/display/drm_dp_helper.h>
30 #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
31 #define DP_SINK_HW_REVISION_START 0x409
32 #endif
33 /* Panel Replay*/
34 #ifndef DP_PANEL_REPLAY_CAPABILITY_SUPPORT // can remove this once the define gets into linux drm_dp_helper.h
35 #define DP_PANEL_REPLAY_CAPABILITY_SUPPORT 0x0b0
36 #endif /* DP_PANEL_REPLAY_CAPABILITY_SUPPORT */
37 #ifndef DP_PANEL_REPLAY_CAPABILITY // can remove this once the define gets into linux drm_dp_helper.h
38 #define DP_PANEL_REPLAY_CAPABILITY 0x0b1
39 #endif /* DP_PANEL_REPLAY_CAPABILITY */
40 #ifndef DP_PR_SU_X_GRANULARITY_LOW         // can remove this once the define gets into linux drm_dp_helper.h
41 #define DP_PR_SU_X_GRANULARITY_LOW			0x0b2
42 #endif /* DP_PR_SU_X_GRANULARITY_LOW */
43 #ifndef DP_PR_SU_X_GRANULARITY_HIGH        // can remove this once the define gets into linux drm_dp_helper.h
44 #define DP_PR_SU_X_GRANULARITY_HIGH			0x0b3
45 #endif /* DP_PR_SU_X_GRANULARITY_HIGH */
46 #ifndef DP_PR_SU_Y_GRANULARITY             // can remove this once the define gets into linux drm_dp_helper.h
47 #define DP_PR_SU_Y_GRANULARITY				0x0b4
48 #endif /* DP_PR_SU_Y_GRANULARITY */
49 #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW // can remove this once the define gets into linux drm_dp_helper.h
50 #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW		0x0b5
51 #endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_LOW */
52 #ifndef DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH // can remove this once the define gets into linux drm_dp_helper.h
53 #define DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH	0x0b6
54 #endif /* DP_PR_SU_Y_GRANULARITY_EXTENDED_CAP_HIGH */
55 #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  // can remove this once the define gets into linux drm_dp_helper.h
56 #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1  0x1b0
57 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_1 */
58 #ifndef DP_PANEL_REPLAY_ENABLE // can remove this once the define gets into linux drm_dp_helper.h
59 #define DP_PANEL_REPLAY_ENABLE (1 << 0)
60 #endif /* DP_PANEL_REPLAY_ENABLE */
61 #ifndef DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 // can remove this once the define gets into linux drm_dp_helper.h
62 #define DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 0x1b1
63 #endif /* DP_PANEL_REPLAY_ENABLE_AND_CONFIGURATION_2 */
64 #ifndef DP_PR_ERROR_STATUS                  // can remove this once the define gets into linux drm_dp_helper.h
65 #define DP_PR_ERROR_STATUS                  0x2020  /* DP 2.0 */
66 #endif /* DP_PR_ERROR_STATUS */
67 #ifndef DP_PR_REPLAY_SINK_STATUS            // can remove this once the define gets into linux drm_dp_helper.h
68 #define DP_PR_REPLAY_SINK_STATUS            0x2022
69 #endif /* DP_PR_REPLAY_SINK_STATUS */
70 #ifndef DP_PR_LINK_CRC_ERROR               // can remove this once the define gets into linux drm_dp_helper.h
71 #define DP_PR_LINK_CRC_ERROR               (1 << 0)
72 #endif /* DP_PR_LINK_CRC_ERROR */
73 #ifndef DP_PR_RFB_STORAGE_ERROR            // can remove this once the define gets into linux drm_dp_helper.h
74 #define DP_PR_RFB_STORAGE_ERROR            (1 << 1)
75 #endif /* DP_PR_RFB_STORAGE_ERROR */
76 #ifndef DP_PR_VSC_SDP_UNCORRECTABLE_ERROR // can remove this once the define gets into linux drm_dp_helper.h
77 #define DP_PR_VSC_SDP_UNCORRECTABLE_ERROR  (1 << 2) /* eDP 1.4 */
78 #endif /* DP_PR_VSC_SDP_UNCORRECTABLE_ERROR */
79 #ifndef DP_PR_ASSDP_MISSING_ERROR          // can remove this once the define gets into linux drm_dp_helper.h
80 #define DP_PR_ASSDP_MISSING_ERROR          (1 << 3) /* eDP 1.5 */
81 #endif /* DP_PR_ASSDP_MISSING_ERROR */
82 
83 enum dpcd_revision {
84 	DPCD_REV_10 = 0x10,
85 	DPCD_REV_11 = 0x11,
86 	DPCD_REV_12 = 0x12,
87 	DPCD_REV_13 = 0x13,
88 	DPCD_REV_14 = 0x14
89 };
90 
91 /* these are the types stored at DOWNSTREAMPORT_PRESENT */
92 enum dpcd_downstream_port_type {
93 	DOWNSTREAM_DP = 0,
94 	DOWNSTREAM_VGA,
95 	DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
96 	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
97 };
98 
99 enum dpcd_link_test_patterns {
100 	LINK_TEST_PATTERN_NONE = 0,
101 	LINK_TEST_PATTERN_COLOR_RAMP,
102 	LINK_TEST_PATTERN_VERTICAL_BARS,
103 	LINK_TEST_PATTERN_COLOR_SQUARES
104 };
105 
106 enum dpcd_test_color_format {
107 	TEST_COLOR_FORMAT_RGB = 0,
108 	TEST_COLOR_FORMAT_YCBCR422,
109 	TEST_COLOR_FORMAT_YCBCR444
110 };
111 
112 enum dpcd_test_bit_depth {
113 	TEST_BIT_DEPTH_6 = 0,
114 	TEST_BIT_DEPTH_8,
115 	TEST_BIT_DEPTH_10,
116 	TEST_BIT_DEPTH_12,
117 	TEST_BIT_DEPTH_16
118 };
119 
120 /* PHY (encoder) test patterns
121 The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
122 */
123 enum dpcd_phy_test_patterns {
124 	PHY_TEST_PATTERN_NONE = 0,
125 	PHY_TEST_PATTERN_D10_2,
126 	PHY_TEST_PATTERN_SYMBOL_ERROR,
127 	PHY_TEST_PATTERN_PRBS7,
128 	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
129 	PHY_TEST_PATTERN_CP2520_1,
130 	PHY_TEST_PATTERN_CP2520_2,
131 	PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
132 	PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8,
133 	PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10,
134 	PHY_TEST_PATTERN_PRBS9 = 0x18,
135 	PHY_TEST_PATTERN_PRBS11 = 0x20,
136 	PHY_TEST_PATTERN_PRBS15 = 0x28,
137 	PHY_TEST_PATTERN_PRBS23 = 0x30,
138 	PHY_TEST_PATTERN_PRBS31 = 0x38,
139 	PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
140 	PHY_TEST_PATTERN_SQUARE = 0x48,
141 	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
142 	PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
143 	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
144 };
145 
146 enum dpcd_test_dyn_range {
147 	TEST_DYN_RANGE_VESA = 0,
148 	TEST_DYN_RANGE_CEA
149 };
150 
151 enum dpcd_audio_test_pattern {
152 	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
153 	AUDIO_TEST_PATTERN_SAWTOOTH
154 };
155 
156 enum dpcd_audio_sampling_rate {
157 	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
158 	AUDIO_SAMPLING_RATE_44_1KHZ,
159 	AUDIO_SAMPLING_RATE_48KHZ,
160 	AUDIO_SAMPLING_RATE_88_2KHZ,
161 	AUDIO_SAMPLING_RATE_96KHZ,
162 	AUDIO_SAMPLING_RATE_176_4KHZ,
163 	AUDIO_SAMPLING_RATE_192KHZ
164 };
165 
166 enum dpcd_audio_channels {
167 	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
168 	AUDIO_CHANNELS_2,
169 	AUDIO_CHANNELS_3,
170 	AUDIO_CHANNELS_4,
171 	AUDIO_CHANNELS_5,
172 	AUDIO_CHANNELS_6,
173 	AUDIO_CHANNELS_7,
174 	AUDIO_CHANNELS_8,
175 
176 	AUDIO_CHANNELS_COUNT
177 };
178 
179 enum dpcd_audio_test_pattern_periods {
180 	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
181 	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
182 	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
183 	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
184 	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
185 	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
186 	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
187 	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
188 	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
189 	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
190 	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
191 };
192 
193 /* This enum is for programming DPCD TRAINING_PATTERN_SET */
194 enum dpcd_training_patterns {
195 	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
196 	DPCD_TRAINING_PATTERN_1,
197 	DPCD_TRAINING_PATTERN_2,
198 	DPCD_TRAINING_PATTERN_3,
199 	DPCD_TRAINING_PATTERN_4 = 7,
200 	DPCD_128b_132b_TPS1 = 1,
201 	DPCD_128b_132b_TPS2 = 2,
202 	DPCD_128b_132b_TPS2_CDS = 3,
203 };
204 
205 /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
206 It defines the possible PSR states. */
207 enum dpcd_psr_sink_states {
208 	PSR_SINK_STATE_INACTIVE = 0,
209 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
210 	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
211 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
212 	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
213 	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
214 };
215 
216 #define DP_SOURCE_SEQUENCE                      0x30C
217 #define DP_SOURCE_TABLE_REVISION                0x310
218 #define DP_SOURCE_PAYLOAD_SIZE                  0x311
219 #define DP_SOURCE_SINK_CAP                      0x317
220 #define DP_SOURCE_BACKLIGHT_LEVEL               0x320
221 #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK        0x326
222 #define DP_SOURCE_BACKLIGHT_CONTROL             0x32E
223 #define DP_SOURCE_BACKLIGHT_ENABLE              0x32F
224 #define DP_SINK_DRR_GRANULARITY                 0x33B
225 #define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED      0x340
226 #define DP_SINK_PR_REPLAY_STATUS                0x378
227 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE     0x379
228 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
229 #define DP_SINK_EMISSION_RATE                   0x37E
230 #define DP_SINK_PR_FRAME_SKIP_COUNT             0x337
231 
232 /* Remove once drm_dp_helper.h is updated upstream */
233 #ifndef DP_TOTAL_LTTPR_CNT
234 #define DP_TOTAL_LTTPR_CNT                                  0xF000A /* 2.1 */
235 #endif
236 
237 #endif /* __DAL_DPCD_DEFS_H__ */
238