xref: /linux/drivers/gpu/drm/amd/display/include/dpcd_defs.h (revision c34e9ab9a612ee8b18273398ef75c207b01f516d)
14562236bSHarry Wentland /*
24562236bSHarry Wentland  * Copyright 2012-15 Advanced Micro Devices, Inc.
34562236bSHarry Wentland  *
44562236bSHarry Wentland  * Permission is hereby granted, free of charge, to any person obtaining a
54562236bSHarry Wentland  * copy of this software and associated documentation files (the "Software"),
64562236bSHarry Wentland  * to deal in the Software without restriction, including without limitation
74562236bSHarry Wentland  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
84562236bSHarry Wentland  * and/or sell copies of the Software, and to permit persons to whom the
94562236bSHarry Wentland  * Software is furnished to do so, subject to the following conditions:
104562236bSHarry Wentland  *
114562236bSHarry Wentland  * The above copyright notice and this permission notice shall be included in
124562236bSHarry Wentland  * all copies or substantial portions of the Software.
134562236bSHarry Wentland  *
144562236bSHarry Wentland  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
154562236bSHarry Wentland  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
164562236bSHarry Wentland  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
174562236bSHarry Wentland  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
184562236bSHarry Wentland  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
194562236bSHarry Wentland  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
204562236bSHarry Wentland  * OTHER DEALINGS IN THE SOFTWARE.
214562236bSHarry Wentland  *
224562236bSHarry Wentland  * Authors: AMD
234562236bSHarry Wentland  *
244562236bSHarry Wentland  */
254562236bSHarry Wentland 
264562236bSHarry Wentland #ifndef __DAL_DPCD_DEFS_H__
274562236bSHarry Wentland #define __DAL_DPCD_DEFS_H__
284562236bSHarry Wentland 
29da68386dSThomas Zimmermann #include <drm/display/drm_dp_helper.h>
304b99affbSAlvin lee #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h
314b99affbSAlvin lee #define DP_SINK_HW_REVISION_START 0x409
324b99affbSAlvin lee #endif
334562236bSHarry Wentland 
344562236bSHarry Wentland enum dpcd_revision {
354562236bSHarry Wentland 	DPCD_REV_10 = 0x10,
364562236bSHarry Wentland 	DPCD_REV_11 = 0x11,
374562236bSHarry Wentland 	DPCD_REV_12 = 0x12,
384562236bSHarry Wentland 	DPCD_REV_13 = 0x13,
394562236bSHarry Wentland 	DPCD_REV_14 = 0x14
404562236bSHarry Wentland };
414562236bSHarry Wentland 
424562236bSHarry Wentland /* these are the types stored at DOWNSTREAMPORT_PRESENT */
434562236bSHarry Wentland enum dpcd_downstream_port_type {
444562236bSHarry Wentland 	DOWNSTREAM_DP = 0,
454562236bSHarry Wentland 	DOWNSTREAM_VGA,
46b7066693SDale Zhao 	DOWNSTREAM_DVI_HDMI_DP_PLUS_PLUS,/* DVI, HDMI, DP++ */
474562236bSHarry Wentland 	DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */
484562236bSHarry Wentland };
494562236bSHarry Wentland 
504562236bSHarry Wentland enum dpcd_link_test_patterns {
514562236bSHarry Wentland 	LINK_TEST_PATTERN_NONE = 0,
524562236bSHarry Wentland 	LINK_TEST_PATTERN_COLOR_RAMP,
534562236bSHarry Wentland 	LINK_TEST_PATTERN_VERTICAL_BARS,
544562236bSHarry Wentland 	LINK_TEST_PATTERN_COLOR_SQUARES
554562236bSHarry Wentland };
564562236bSHarry Wentland 
574562236bSHarry Wentland enum dpcd_test_color_format {
584562236bSHarry Wentland 	TEST_COLOR_FORMAT_RGB = 0,
594562236bSHarry Wentland 	TEST_COLOR_FORMAT_YCBCR422,
604562236bSHarry Wentland 	TEST_COLOR_FORMAT_YCBCR444
614562236bSHarry Wentland };
624562236bSHarry Wentland 
634562236bSHarry Wentland enum dpcd_test_bit_depth {
644562236bSHarry Wentland 	TEST_BIT_DEPTH_6 = 0,
654562236bSHarry Wentland 	TEST_BIT_DEPTH_8,
664562236bSHarry Wentland 	TEST_BIT_DEPTH_10,
674562236bSHarry Wentland 	TEST_BIT_DEPTH_12,
684562236bSHarry Wentland 	TEST_BIT_DEPTH_16
694562236bSHarry Wentland };
704562236bSHarry Wentland 
714562236bSHarry Wentland /* PHY (encoder) test patterns
724562236bSHarry Wentland The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248)
734562236bSHarry Wentland */
744562236bSHarry Wentland enum dpcd_phy_test_patterns {
754562236bSHarry Wentland 	PHY_TEST_PATTERN_NONE = 0,
764562236bSHarry Wentland 	PHY_TEST_PATTERN_D10_2,
774562236bSHarry Wentland 	PHY_TEST_PATTERN_SYMBOL_ERROR,
784562236bSHarry Wentland 	PHY_TEST_PATTERN_PRBS7,
794562236bSHarry Wentland 	PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */
800e19401fSTony Cheng 	PHY_TEST_PATTERN_CP2520_1,
810e19401fSTony Cheng 	PHY_TEST_PATTERN_CP2520_2,
820e19401fSTony Cheng 	PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */
83f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_128b_132b_TPS1 = 0x8,
84f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_128b_132b_TPS2 = 0x10,
85f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_PRBS9 = 0x18,
86f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_PRBS11 = 0x20,
87f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_PRBS15 = 0x28,
88f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_PRBS23 = 0x30,
89f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_PRBS31 = 0x38,
90f01ee019SFangzhi Zuo 	PHY_TEST_PATTERN_264BIT_CUSTOM = 0x40,
91345ce3fcSWenjing Liu 	PHY_TEST_PATTERN_SQUARE = 0x48,
92345ce3fcSWenjing Liu 	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DISABLED = 0x49,
93345ce3fcSWenjing Liu 	PHY_TEST_PATTERN_SQUARE_DEEMPHASIS_DISABLED = 0x4A,
94345ce3fcSWenjing Liu 	PHY_TEST_PATTERN_SQUARE_PRESHOOT_DEEMPHASIS_DISABLED = 0x4B,
954562236bSHarry Wentland };
964562236bSHarry Wentland 
974562236bSHarry Wentland enum dpcd_test_dyn_range {
984562236bSHarry Wentland 	TEST_DYN_RANGE_VESA = 0,
994562236bSHarry Wentland 	TEST_DYN_RANGE_CEA
1004562236bSHarry Wentland };
1014562236bSHarry Wentland 
1024562236bSHarry Wentland enum dpcd_audio_test_pattern {
1034562236bSHarry Wentland 	AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */
1044562236bSHarry Wentland 	AUDIO_TEST_PATTERN_SAWTOOTH
1054562236bSHarry Wentland };
1064562236bSHarry Wentland 
1074562236bSHarry Wentland enum dpcd_audio_sampling_rate {
1084562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */
1094562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_44_1KHZ,
1104562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_48KHZ,
1114562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_88_2KHZ,
1124562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_96KHZ,
1134562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_176_4KHZ,
1144562236bSHarry Wentland 	AUDIO_SAMPLING_RATE_192KHZ
1154562236bSHarry Wentland };
1164562236bSHarry Wentland 
1174562236bSHarry Wentland enum dpcd_audio_channels {
1184562236bSHarry Wentland 	AUDIO_CHANNELS_1 = 0,/* direct HW translation */
1194562236bSHarry Wentland 	AUDIO_CHANNELS_2,
1204562236bSHarry Wentland 	AUDIO_CHANNELS_3,
1214562236bSHarry Wentland 	AUDIO_CHANNELS_4,
1224562236bSHarry Wentland 	AUDIO_CHANNELS_5,
1234562236bSHarry Wentland 	AUDIO_CHANNELS_6,
1244562236bSHarry Wentland 	AUDIO_CHANNELS_7,
1254562236bSHarry Wentland 	AUDIO_CHANNELS_8,
1264562236bSHarry Wentland 
1274562236bSHarry Wentland 	AUDIO_CHANNELS_COUNT
1284562236bSHarry Wentland };
1294562236bSHarry Wentland 
1304562236bSHarry Wentland enum dpcd_audio_test_pattern_periods {
1314562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */
1324562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_3,
1334562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_6,
1344562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_12,
1354562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_24,
1364562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_48,
1374562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_96,
1384562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_192,
1394562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_384,
1404562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_768,
1414562236bSHarry Wentland 	DPCD_AUDIO_TEST_PATTERN_PERIOD_1536
1424562236bSHarry Wentland };
1434562236bSHarry Wentland 
1444562236bSHarry Wentland /* This enum is for programming DPCD TRAINING_PATTERN_SET */
1454562236bSHarry Wentland enum dpcd_training_patterns {
1464562236bSHarry Wentland 	DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */
1474562236bSHarry Wentland 	DPCD_TRAINING_PATTERN_1,
1484562236bSHarry Wentland 	DPCD_TRAINING_PATTERN_2,
1494562236bSHarry Wentland 	DPCD_TRAINING_PATTERN_3,
150f01ee019SFangzhi Zuo 	DPCD_TRAINING_PATTERN_4 = 7,
151f01ee019SFangzhi Zuo 	DPCD_128b_132b_TPS1 = 1,
152f01ee019SFangzhi Zuo 	DPCD_128b_132b_TPS2 = 2,
153f01ee019SFangzhi Zuo 	DPCD_128b_132b_TPS2_CDS = 3,
1544562236bSHarry Wentland };
1554562236bSHarry Wentland 
1564562236bSHarry Wentland /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus
1574562236bSHarry Wentland It defines the possible PSR states. */
1584562236bSHarry Wentland enum dpcd_psr_sink_states {
1594562236bSHarry Wentland 	PSR_SINK_STATE_INACTIVE = 0,
1604562236bSHarry Wentland 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1,
1614562236bSHarry Wentland 	PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2,
1624562236bSHarry Wentland 	PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3,
1634562236bSHarry Wentland 	PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4,
1644562236bSHarry Wentland 	PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
1654562236bSHarry Wentland };
1664562236bSHarry Wentland 
167*668d6808SRobin Chen #define DP_SOURCE_SEQUENCE                      0x30C
1688a683eb6SRodrigo Siqueira #define DP_SOURCE_TABLE_REVISION                0x310
1698a683eb6SRodrigo Siqueira #define DP_SOURCE_PAYLOAD_SIZE                  0x311
1708a683eb6SRodrigo Siqueira #define DP_SOURCE_SINK_CAP                      0x317
1718a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_LEVEL               0x320
1728a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_CURRENT_PEAK        0x326
1738a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_CONTROL             0x32E
1748a683eb6SRodrigo Siqueira #define DP_SOURCE_BACKLIGHT_ENABLE              0x32F
1759248681fSAshley Thomas #define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED      0x340
176e0138644SBhawanpreet Lakha #define DP_SINK_PR_REPLAY_STATUS                0x378
17776bd3478SBhawanpreet Lakha #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE     0x379
17876bd3478SBhawanpreet Lakha #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
179*668d6808SRobin Chen #define DP_SINK_EMISSION_RATE                   0x37E
1808a683eb6SRodrigo Siqueira 
1812ec6c7f8SMichael Strauss /* Remove once drm_dp_helper.h is updated upstream */
1822ec6c7f8SMichael Strauss #ifndef DP_TOTAL_LTTPR_CNT
1832ec6c7f8SMichael Strauss #define DP_TOTAL_LTTPR_CNT                                  0xF000A /* 2.1 */
1842ec6c7f8SMichael Strauss #endif
1852ec6c7f8SMichael Strauss 
1864562236bSHarry Wentland #endif /* __DAL_DPCD_DEFS_H__ */
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