1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn36.h" 42 #include "dmub_dcn401.h" 43 #include "os_types.h" 44 /* 45 * Note: the DMUB service is standalone. No additional headers should be 46 * added below or above this line unless they reside within the DMUB 47 * folder. 48 */ 49 50 /* Alignment for framebuffer memory. */ 51 #define DMUB_FB_ALIGNMENT (1024 * 1024) 52 53 /* Stack size. */ 54 #define DMUB_STACK_SIZE (128 * 1024) 55 56 /* Context size. */ 57 #define DMUB_CONTEXT_SIZE (512 * 1024) 58 59 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 60 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 61 62 /* Default state size if meta is absent. */ 63 #define DMUB_FW_STATE_SIZE (64 * 1024) 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (1024) 67 68 /* Default indirect buffer size. */ 69 #define DMUB_IB_MEM_SIZE (1280) 70 71 /* Default LSDMA ring buffer size. */ 72 #define DMUB_LSDMA_RB_SIZE (64 * 1024) 73 74 /* Number of windows in use. */ 75 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 76 /* Base addresses. */ 77 78 #define DMUB_CW0_BASE (0x60000000) 79 #define DMUB_CW1_BASE (0x61000000) 80 #define DMUB_CW3_BASE (0x63000000) 81 #define DMUB_CW4_BASE (0x64000000) 82 #define DMUB_CW5_BASE (0x65000000) 83 #define DMUB_CW6_BASE (0x66000000) 84 85 #define DMUB_REGION5_BASE (0xA0000000) 86 #define DMUB_REGION6_BASE (0xC0000000) 87 88 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 89 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 90 91 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 92 { 93 return (val + factor - 1) / factor * factor; 94 } 95 96 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 97 { 98 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 99 uint8_t buf[64]; 100 uint32_t pos, end; 101 102 /** 103 * Read 64-byte chunks since we don't want to store a 104 * large temporary buffer for this purpose. 105 */ 106 end = fb->size / sizeof(buf) * sizeof(buf); 107 108 for (pos = 0; pos < end; pos += sizeof(buf)) 109 dmub_memcpy(buf, base + pos, sizeof(buf)); 110 111 /* Read anything leftover into the buffer. */ 112 if (end < fb->size) 113 dmub_memcpy(buf, base + pos, fb->size - end); 114 } 115 116 static const struct dmub_fw_meta_info * 117 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 118 { 119 const union dmub_fw_meta *meta; 120 121 if (!blob || !blob_size) 122 return NULL; 123 124 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 125 return NULL; 126 127 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 128 sizeof(union dmub_fw_meta)); 129 130 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 131 return NULL; 132 133 return &meta->info; 134 } 135 136 static const struct dmub_fw_meta_info * 137 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 138 { 139 const struct dmub_fw_meta_info *info = NULL; 140 141 if (params->fw_bss_data && params->bss_data_size) { 142 /* Legacy metadata region. */ 143 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 144 params->bss_data_size, 145 DMUB_FW_META_OFFSET); 146 } else if (params->fw_inst_const && params->inst_const_size) { 147 /* Combined metadata region - can be aligned to 16-bytes. */ 148 uint32_t i; 149 150 for (i = 0; i < 16; ++i) { 151 info = dmub_get_fw_meta_info_from_blob( 152 params->fw_inst_const, params->inst_const_size, i); 153 154 if (info) 155 break; 156 } 157 } 158 159 return info; 160 } 161 162 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 163 { 164 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 165 166 /* default to specifying now inbox type */ 167 enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 168 169 switch (asic) { 170 case DMUB_ASIC_DCN20: 171 case DMUB_ASIC_DCN21: 172 case DMUB_ASIC_DCN30: 173 case DMUB_ASIC_DCN301: 174 case DMUB_ASIC_DCN302: 175 case DMUB_ASIC_DCN303: 176 dmub->regs = &dmub_srv_dcn20_regs; 177 178 funcs->reset = dmub_dcn20_reset; 179 funcs->reset_release = dmub_dcn20_reset_release; 180 funcs->backdoor_load = dmub_dcn20_backdoor_load; 181 funcs->setup_windows = dmub_dcn20_setup_windows; 182 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 183 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 184 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 185 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 186 funcs->is_supported = dmub_dcn20_is_supported; 187 funcs->is_hw_init = dmub_dcn20_is_hw_init; 188 funcs->set_gpint = dmub_dcn20_set_gpint; 189 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 190 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 191 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 192 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 193 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 194 funcs->get_current_time = dmub_dcn20_get_current_time; 195 196 // Out mailbox register access functions for RN and above 197 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 198 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 199 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 200 201 //outbox0 call stacks 202 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 203 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 204 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 205 206 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 207 208 if (asic == DMUB_ASIC_DCN21) 209 dmub->regs = &dmub_srv_dcn21_regs; 210 211 if (asic == DMUB_ASIC_DCN30) { 212 dmub->regs = &dmub_srv_dcn30_regs; 213 214 funcs->backdoor_load = dmub_dcn30_backdoor_load; 215 funcs->setup_windows = dmub_dcn30_setup_windows; 216 } 217 if (asic == DMUB_ASIC_DCN301) { 218 dmub->regs = &dmub_srv_dcn301_regs; 219 220 funcs->backdoor_load = dmub_dcn30_backdoor_load; 221 funcs->setup_windows = dmub_dcn30_setup_windows; 222 } 223 if (asic == DMUB_ASIC_DCN302) { 224 dmub->regs = &dmub_srv_dcn302_regs; 225 226 funcs->backdoor_load = dmub_dcn30_backdoor_load; 227 funcs->setup_windows = dmub_dcn30_setup_windows; 228 } 229 if (asic == DMUB_ASIC_DCN303) { 230 dmub->regs = &dmub_srv_dcn303_regs; 231 232 funcs->backdoor_load = dmub_dcn30_backdoor_load; 233 funcs->setup_windows = dmub_dcn30_setup_windows; 234 } 235 break; 236 237 case DMUB_ASIC_DCN31: 238 case DMUB_ASIC_DCN31B: 239 case DMUB_ASIC_DCN314: 240 case DMUB_ASIC_DCN315: 241 case DMUB_ASIC_DCN316: 242 if (asic == DMUB_ASIC_DCN314) { 243 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 244 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 245 } else if (asic == DMUB_ASIC_DCN315) { 246 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 247 } else if (asic == DMUB_ASIC_DCN316) { 248 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 249 } else { 250 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 251 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 252 } 253 funcs->reset = dmub_dcn31_reset; 254 funcs->reset_release = dmub_dcn31_reset_release; 255 funcs->backdoor_load = dmub_dcn31_backdoor_load; 256 funcs->setup_windows = dmub_dcn31_setup_windows; 257 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 258 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 259 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 260 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 261 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 262 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 263 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 264 funcs->is_supported = dmub_dcn31_is_supported; 265 funcs->is_hw_init = dmub_dcn31_is_hw_init; 266 funcs->set_gpint = dmub_dcn31_set_gpint; 267 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 268 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 269 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 270 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 271 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 272 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 273 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 274 //outbox0 call stacks 275 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 276 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 277 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 278 279 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 280 funcs->should_detect = dmub_dcn31_should_detect; 281 funcs->get_current_time = dmub_dcn31_get_current_time; 282 283 break; 284 285 case DMUB_ASIC_DCN32: 286 case DMUB_ASIC_DCN321: 287 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 288 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 289 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 290 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 291 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 292 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 293 funcs->reset = dmub_dcn32_reset; 294 funcs->reset_release = dmub_dcn32_reset_release; 295 funcs->backdoor_load = dmub_dcn32_backdoor_load; 296 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 297 funcs->setup_windows = dmub_dcn32_setup_windows; 298 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 299 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 300 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 301 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 302 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 303 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 304 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 305 funcs->is_supported = dmub_dcn32_is_supported; 306 funcs->is_hw_init = dmub_dcn32_is_hw_init; 307 funcs->set_gpint = dmub_dcn32_set_gpint; 308 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 309 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 310 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 311 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 312 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 313 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 314 315 /* outbox0 call stacks */ 316 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 317 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 318 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 319 funcs->get_current_time = dmub_dcn32_get_current_time; 320 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 321 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 322 323 break; 324 325 case DMUB_ASIC_DCN35: 326 case DMUB_ASIC_DCN351: 327 case DMUB_ASIC_DCN36: 328 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 329 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 330 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 331 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 332 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 333 funcs->reset = dmub_dcn35_reset; 334 funcs->reset_release = dmub_dcn35_reset_release; 335 funcs->backdoor_load = dmub_dcn35_backdoor_load; 336 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 337 funcs->setup_windows = dmub_dcn35_setup_windows; 338 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 339 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 340 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 341 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 342 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 343 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 344 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 345 funcs->is_supported = dmub_dcn35_is_supported; 346 funcs->is_hw_init = dmub_dcn35_is_hw_init; 347 funcs->set_gpint = dmub_dcn35_set_gpint; 348 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 349 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 350 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 351 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 352 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 353 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 354 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 355 //outbox0 call stacks 356 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 357 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 358 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 359 360 funcs->get_current_time = dmub_dcn35_get_current_time; 361 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 362 funcs->get_preos_fw_info = dmub_dcn35_get_preos_fw_info; 363 364 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 365 if (asic == DMUB_ASIC_DCN351) 366 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 367 if (asic == DMUB_ASIC_DCN36) 368 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 369 370 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 371 funcs->should_detect = dmub_dcn35_should_detect; 372 break; 373 374 case DMUB_ASIC_DCN401: 375 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 376 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 377 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 378 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 379 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 380 funcs->reset = dmub_dcn401_reset; 381 funcs->reset_release = dmub_dcn401_reset_release; 382 funcs->backdoor_load = dmub_dcn401_backdoor_load; 383 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 384 funcs->setup_windows = dmub_dcn401_setup_windows; 385 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 386 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 387 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 388 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 389 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 390 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 391 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 392 funcs->is_supported = dmub_dcn401_is_supported; 393 funcs->is_hw_init = dmub_dcn401_is_hw_init; 394 funcs->set_gpint = dmub_dcn401_set_gpint; 395 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 396 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 397 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 398 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 399 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 400 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 401 //outbox0 call stacks 402 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 403 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 404 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 405 406 funcs->get_current_time = dmub_dcn401_get_current_time; 407 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 408 409 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 410 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 411 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 412 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 413 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 414 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 415 default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 416 417 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 418 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 419 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 420 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 421 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 422 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 423 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 424 break; 425 default: 426 return false; 427 } 428 429 /* set default inbox type if not overriden */ 430 if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 431 if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 432 /* use default inbox type as specified by DCN rev */ 433 dmub->inbox_type = default_inbox_type; 434 } else if (funcs->send_reg_inbox0_cmd_msg) { 435 /* prefer reg as default inbox type if present */ 436 dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 437 } else { 438 /* use fb as fallback */ 439 dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 440 } 441 } 442 443 return true; 444 } 445 446 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 447 const struct dmub_srv_create_params *params) 448 { 449 enum dmub_status status = DMUB_STATUS_OK; 450 451 dmub_memset(dmub, 0, sizeof(*dmub)); 452 453 dmub->funcs = params->funcs; 454 dmub->user_ctx = params->user_ctx; 455 dmub->asic = params->asic; 456 dmub->fw_version = params->fw_version; 457 dmub->is_virtual = params->is_virtual; 458 dmub->inbox_type = params->inbox_type; 459 460 /* Setup asic dependent hardware funcs. */ 461 if (!dmub_srv_hw_setup(dmub, params->asic)) { 462 status = DMUB_STATUS_INVALID; 463 goto cleanup; 464 } 465 466 /* Override (some) hardware funcs based on user params. */ 467 if (params->hw_funcs) { 468 if (params->hw_funcs->emul_get_inbox1_rptr) 469 dmub->hw_funcs.emul_get_inbox1_rptr = 470 params->hw_funcs->emul_get_inbox1_rptr; 471 472 if (params->hw_funcs->emul_set_inbox1_wptr) 473 dmub->hw_funcs.emul_set_inbox1_wptr = 474 params->hw_funcs->emul_set_inbox1_wptr; 475 476 if (params->hw_funcs->is_supported) 477 dmub->hw_funcs.is_supported = 478 params->hw_funcs->is_supported; 479 } 480 481 /* Sanity checks for required hw func pointers. */ 482 if (!dmub->hw_funcs.get_inbox1_rptr || 483 !dmub->hw_funcs.set_inbox1_wptr) { 484 status = DMUB_STATUS_INVALID; 485 goto cleanup; 486 } 487 488 cleanup: 489 if (status == DMUB_STATUS_OK) 490 dmub->sw_init = true; 491 else 492 dmub_srv_destroy(dmub); 493 494 return status; 495 } 496 497 void dmub_srv_destroy(struct dmub_srv *dmub) 498 { 499 dmub_memset(dmub, 0, sizeof(*dmub)); 500 } 501 502 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 503 struct dmub_srv_region_info *out, 504 const uint32_t *window_sizes, 505 enum dmub_window_memory_type memory_type) 506 { 507 uint32_t i, top = 0; 508 509 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 510 if (params->window_memory_type[i] == memory_type) { 511 struct dmub_region *region = &out->regions[i]; 512 513 region->base = dmub_align(top, 256); 514 region->top = region->base + dmub_align(window_sizes[i], 64); 515 top = region->top; 516 } 517 } 518 519 return dmub_align(top, 4096); 520 } 521 522 enum dmub_status 523 dmub_srv_calc_region_info(struct dmub_srv *dmub, 524 const struct dmub_srv_region_params *params, 525 struct dmub_srv_region_info *out) 526 { 527 const struct dmub_fw_meta_info *fw_info; 528 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 529 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 530 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 531 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 532 533 if (!dmub->sw_init) 534 return DMUB_STATUS_INVALID; 535 536 memset(out, 0, sizeof(*out)); 537 memset(window_sizes, 0, sizeof(window_sizes)); 538 539 out->num_regions = DMUB_NUM_WINDOWS; 540 541 fw_info = dmub_get_fw_meta_info(params); 542 543 if (fw_info) { 544 memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); 545 546 fw_state_size = fw_info->fw_region_size; 547 trace_buffer_size = fw_info->trace_buffer_size; 548 shared_state_size = fw_info->shared_state_size; 549 550 /** 551 * If DM didn't fill in a version, then fill it in based on 552 * the firmware meta now that we have it. 553 * 554 * TODO: Make it easier for driver to extract this out to 555 * pass during creation. 556 */ 557 if (dmub->fw_version == 0) 558 dmub->fw_version = fw_info->fw_version; 559 } 560 561 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 562 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 563 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 564 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 565 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 566 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 567 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 568 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64); 569 window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE; 570 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 571 window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE; 572 window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64); 573 574 out->fb_size = 575 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 576 577 out->gart_size = 578 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 579 580 return DMUB_STATUS_OK; 581 } 582 583 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 584 const struct dmub_srv_memory_params *params, 585 struct dmub_srv_fb_info *out) 586 { 587 uint32_t i; 588 589 if (!dmub->sw_init) 590 return DMUB_STATUS_INVALID; 591 592 memset(out, 0, sizeof(*out)); 593 594 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 595 return DMUB_STATUS_INVALID; 596 597 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 598 const struct dmub_region *reg = 599 ¶ms->region_info->regions[i]; 600 601 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 602 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 603 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 604 } else { 605 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 606 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 607 } 608 609 out->fb[i].size = reg->top - reg->base; 610 } 611 612 out->num_fb = DMUB_NUM_WINDOWS; 613 614 return DMUB_STATUS_OK; 615 } 616 617 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 618 bool *is_supported) 619 { 620 *is_supported = false; 621 622 if (!dmub->sw_init) 623 return DMUB_STATUS_INVALID; 624 625 if (dmub->hw_funcs.is_supported) 626 *is_supported = dmub->hw_funcs.is_supported(dmub); 627 628 return DMUB_STATUS_OK; 629 } 630 631 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 632 { 633 *is_hw_init = false; 634 635 if (!dmub->sw_init) 636 return DMUB_STATUS_INVALID; 637 638 if (!dmub->hw_init) 639 return DMUB_STATUS_OK; 640 641 if (dmub->hw_funcs.is_hw_init) 642 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 643 644 return DMUB_STATUS_OK; 645 } 646 647 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 648 const struct dmub_srv_hw_params *params) 649 { 650 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 651 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 652 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 653 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 654 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 655 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 656 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 657 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 658 659 struct dmub_rb_init_params rb_params, outbox0_rb_params; 660 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 661 struct dmub_region inbox1, outbox1, outbox0; 662 663 uint32_t i; 664 665 if (!dmub->sw_init) 666 return DMUB_STATUS_INVALID; 667 668 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 669 if (!params->fb[i]) { 670 ASSERT(0); 671 return DMUB_STATUS_INVALID; 672 } 673 } 674 675 dmub->fb_base = params->fb_base; 676 dmub->fb_offset = params->fb_offset; 677 dmub->psp_version = params->psp_version; 678 679 if (dmub->hw_funcs.reset) 680 dmub->hw_funcs.reset(dmub); 681 682 /* reset the cache of the last wptr as well now that hw is reset */ 683 dmub->inbox1_last_wptr = 0; 684 685 cw0.offset.quad_part = inst_fb->gpu_addr; 686 cw0.region.base = DMUB_CW0_BASE; 687 cw0.region.top = cw0.region.base + inst_fb->size - 1; 688 689 cw1.offset.quad_part = stack_fb->gpu_addr; 690 cw1.region.base = DMUB_CW1_BASE; 691 cw1.region.top = cw1.region.base + stack_fb->size - 1; 692 693 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 694 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 695 696 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 697 /** 698 * Read back all the instruction memory so we don't hang the 699 * DMCUB when backdoor loading if the write from x86 hasn't been 700 * flushed yet. This only occurs in backdoor loading. 701 */ 702 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 703 dmub_flush_buffer_mem(inst_fb); 704 705 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 706 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 707 else 708 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 709 } 710 711 cw2.offset.quad_part = data_fb->gpu_addr; 712 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 713 cw2.region.top = cw2.region.base + data_fb->size; 714 715 cw3.offset.quad_part = bios_fb->gpu_addr; 716 cw3.region.base = DMUB_CW3_BASE; 717 cw3.region.top = cw3.region.base + bios_fb->size; 718 719 cw4.offset.quad_part = mail_fb->gpu_addr; 720 cw4.region.base = DMUB_CW4_BASE; 721 cw4.region.top = cw4.region.base + mail_fb->size; 722 723 /** 724 * Doubled the mailbox region to accomodate inbox and outbox. 725 * Note: Currently, currently total mailbox size is 16KB. It is split 726 * equally into 8KB between inbox and outbox. If this config is 727 * changed, then uncached base address configuration of outbox1 728 * has to be updated in funcs->setup_out_mailbox. 729 */ 730 inbox1.base = cw4.region.base; 731 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 732 outbox1.base = inbox1.top; 733 outbox1.top = inbox1.top + DMUB_RB_SIZE; 734 735 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 736 cw5.region.base = DMUB_CW5_BASE; 737 cw5.region.top = cw5.region.base + tracebuff_fb->size; 738 739 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 740 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 741 742 cw6.offset.quad_part = fw_state_fb->gpu_addr; 743 cw6.region.base = DMUB_CW6_BASE; 744 cw6.region.top = cw6.region.base + fw_state_fb->size; 745 746 dmub->fw_state = (void *)((uintptr_t)(fw_state_fb->cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET); 747 748 region6.offset.quad_part = shared_state_fb->gpu_addr; 749 region6.region.base = DMUB_CW6_BASE; 750 region6.region.top = region6.region.base + shared_state_fb->size; 751 752 dmub->shared_state = shared_state_fb->cpu_addr; 753 754 dmub->scratch_mem_fb = *params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 755 dmub->ib_mem_gart = *params->fb[DMUB_WINDOW_IB_MEM]; 756 757 dmub->cursor_offload_fb = *params->fb[DMUB_WINDOW_CURSOR_OFFLOAD]; 758 dmub->cursor_offload_v1 = (struct dmub_cursor_offload_v1 *)dmub->cursor_offload_fb.cpu_addr; 759 760 if (dmub->hw_funcs.setup_windows) 761 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 762 763 if (dmub->hw_funcs.setup_outbox0) 764 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 765 766 if (dmub->hw_funcs.setup_mailbox) 767 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 768 if (dmub->hw_funcs.setup_out_mailbox) 769 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 770 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 771 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 772 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 773 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 774 775 dmub_memset(&rb_params, 0, sizeof(rb_params)); 776 rb_params.ctx = dmub; 777 rb_params.base_address = mail_fb->cpu_addr; 778 rb_params.capacity = DMUB_RB_SIZE; 779 dmub_rb_init(&dmub->inbox1.rb, &rb_params); 780 781 // Initialize outbox1 ring buffer 782 rb_params.ctx = dmub; 783 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 784 rb_params.capacity = DMUB_RB_SIZE; 785 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 786 787 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 788 outbox0_rb_params.ctx = dmub; 789 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 790 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 791 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 792 793 /* Report to DMUB what features are supported by current driver */ 794 if (dmub->hw_funcs.enable_dmub_boot_options) 795 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 796 797 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 798 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 799 params->skip_panel_power_sequence); 800 801 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 802 dmub->hw_funcs.reset_release(dmub); 803 804 dmub->hw_init = true; 805 dmub->power_state = DMUB_POWER_STATE_D0; 806 807 return DMUB_STATUS_OK; 808 } 809 810 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 811 { 812 if (!dmub->sw_init) 813 return DMUB_STATUS_INVALID; 814 815 if (dmub->hw_funcs.reset) 816 dmub->hw_funcs.reset(dmub); 817 818 /* mailboxes have been reset in hw, so reset the sw state as well */ 819 dmub->inbox1_last_wptr = 0; 820 dmub->inbox1.rb.wrpt = 0; 821 dmub->inbox1.rb.rptr = 0; 822 dmub->inbox1.num_reported = 0; 823 dmub->inbox1.num_submitted = 0; 824 dmub->reg_inbox0.num_reported = 0; 825 dmub->reg_inbox0.num_submitted = 0; 826 dmub->reg_inbox0.is_pending = 0; 827 dmub->outbox0_rb.wrpt = 0; 828 dmub->outbox0_rb.rptr = 0; 829 dmub->outbox1_rb.wrpt = 0; 830 dmub->outbox1_rb.rptr = 0; 831 832 dmub->hw_init = false; 833 834 return DMUB_STATUS_OK; 835 } 836 837 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 838 const union dmub_rb_cmd *cmd) 839 { 840 if (!dmub->hw_init) 841 return DMUB_STATUS_INVALID; 842 843 if (dmub->power_state != DMUB_POWER_STATE_D0) 844 return DMUB_STATUS_POWER_STATE_D3; 845 846 if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 847 dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 848 return DMUB_STATUS_HW_FAILURE; 849 } 850 851 if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 852 dmub->inbox1.num_submitted++; 853 return DMUB_STATUS_OK; 854 } 855 856 return DMUB_STATUS_QUEUE_FULL; 857 } 858 859 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 860 { 861 struct dmub_rb flush_rb; 862 863 if (!dmub->hw_init) 864 return DMUB_STATUS_INVALID; 865 866 if (dmub->power_state != DMUB_POWER_STATE_D0) 867 return DMUB_STATUS_POWER_STATE_D3; 868 869 /** 870 * Read back all the queued commands to ensure that they've 871 * been flushed to framebuffer memory. Otherwise DMCUB might 872 * read back stale, fully invalid or partially invalid data. 873 */ 874 flush_rb = dmub->inbox1.rb; 875 flush_rb.rptr = dmub->inbox1_last_wptr; 876 dmub_rb_flush_pending(&flush_rb); 877 878 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 879 880 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 881 882 return DMUB_STATUS_OK; 883 } 884 885 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 886 { 887 if (!dmub->hw_funcs.is_hw_powered_up) 888 return true; 889 890 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 891 return false; 892 893 return true; 894 } 895 896 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 897 uint32_t timeout_us) 898 { 899 uint32_t i; 900 901 if (!dmub->hw_init) 902 return DMUB_STATUS_INVALID; 903 904 for (i = 0; i <= timeout_us; i += 100) { 905 if (dmub_srv_is_hw_pwr_up(dmub)) 906 return DMUB_STATUS_OK; 907 908 udelay(100); 909 } 910 911 return DMUB_STATUS_TIMEOUT; 912 } 913 914 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 915 uint32_t timeout_us) 916 { 917 uint32_t i; 918 bool hw_on = true; 919 920 if (!dmub->hw_init) 921 return DMUB_STATUS_INVALID; 922 923 for (i = 0; i <= timeout_us; i += 100) { 924 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 925 926 if (dmub->hw_funcs.is_hw_powered_up) 927 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 928 929 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 930 return DMUB_STATUS_OK; 931 932 udelay(100); 933 } 934 935 return DMUB_STATUS_TIMEOUT; 936 } 937 938 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 939 { 940 if (dmub->reg_inbox0.is_pending) { 941 dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 942 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 943 944 if (!dmub->reg_inbox0.is_pending) { 945 /* ack the rsp interrupt */ 946 if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 947 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 948 949 /* only update the reported count if commands aren't being batched */ 950 if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 951 dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 952 } 953 } 954 } 955 } 956 957 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 958 uint32_t timeout_us) 959 { 960 uint32_t i; 961 const uint32_t polling_interval_us = 1; 962 struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 963 struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 964 const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 965 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 966 967 if (!dmub->hw_init || 968 !dmub->hw_funcs.get_inbox1_wptr) 969 return DMUB_STATUS_INVALID; 970 971 for (i = 0; i <= timeout_us; i += polling_interval_us) { 972 scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 973 scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 974 975 scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 976 dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 977 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 978 979 if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 980 return DMUB_STATUS_HW_FAILURE; 981 982 /* check current HW state first, but use command submission vs reported as a fallback */ 983 if ((dmub_rb_empty(&scratch_inbox1.rb) || 984 inbox1->num_reported >= scratch_inbox1.num_submitted) && 985 (!scratch_reg_inbox0.is_pending || 986 reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 987 return DMUB_STATUS_OK; 988 989 udelay(polling_interval_us); 990 } 991 992 return DMUB_STATUS_TIMEOUT; 993 } 994 995 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 996 uint32_t timeout_us) 997 { 998 enum dmub_status status; 999 uint32_t i; 1000 const uint32_t polling_interval_us = 1; 1001 1002 if (!dmub->hw_init) 1003 return DMUB_STATUS_INVALID; 1004 1005 for (i = 0; i < timeout_us; i += polling_interval_us) { 1006 status = dmub_srv_update_inbox_status(dmub); 1007 1008 if (status != DMUB_STATUS_OK) 1009 return status; 1010 1011 /* check for idle */ 1012 if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 1013 return DMUB_STATUS_OK; 1014 1015 udelay(polling_interval_us); 1016 } 1017 1018 return DMUB_STATUS_TIMEOUT; 1019 } 1020 1021 enum dmub_status 1022 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 1023 enum dmub_gpint_command command_code, 1024 uint16_t param, uint32_t timeout_us) 1025 { 1026 union dmub_gpint_data_register reg; 1027 uint32_t i; 1028 1029 if (!dmub->sw_init) 1030 return DMUB_STATUS_INVALID; 1031 1032 if (!dmub->hw_funcs.set_gpint) 1033 return DMUB_STATUS_INVALID; 1034 1035 if (!dmub->hw_funcs.is_gpint_acked) 1036 return DMUB_STATUS_INVALID; 1037 1038 reg.bits.status = 1; 1039 reg.bits.command_code = command_code; 1040 reg.bits.param = param; 1041 1042 dmub->hw_funcs.set_gpint(dmub, reg); 1043 1044 for (i = 0; i < timeout_us; ++i) { 1045 udelay(1); 1046 1047 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 1048 return DMUB_STATUS_OK; 1049 } 1050 1051 return DMUB_STATUS_TIMEOUT; 1052 } 1053 1054 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 1055 uint32_t *response) 1056 { 1057 *response = 0; 1058 1059 if (!dmub->sw_init) 1060 return DMUB_STATUS_INVALID; 1061 1062 if (!dmub->hw_funcs.get_gpint_response) 1063 return DMUB_STATUS_INVALID; 1064 1065 *response = dmub->hw_funcs.get_gpint_response(dmub); 1066 1067 return DMUB_STATUS_OK; 1068 } 1069 1070 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 1071 uint32_t *dataout) 1072 { 1073 *dataout = 0; 1074 1075 if (!dmub->sw_init) 1076 return DMUB_STATUS_INVALID; 1077 1078 if (!dmub->hw_funcs.get_gpint_dataout) 1079 return DMUB_STATUS_INVALID; 1080 1081 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 1082 1083 return DMUB_STATUS_OK; 1084 } 1085 1086 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1087 union dmub_fw_boot_status *status) 1088 { 1089 status->all = 0; 1090 1091 if (!dmub->sw_init) 1092 return DMUB_STATUS_INVALID; 1093 1094 if (dmub->hw_funcs.get_fw_status) 1095 *status = dmub->hw_funcs.get_fw_status(dmub); 1096 1097 return DMUB_STATUS_OK; 1098 } 1099 1100 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1101 union dmub_fw_boot_options *option) 1102 { 1103 option->all = 0; 1104 1105 if (!dmub->sw_init) 1106 return DMUB_STATUS_INVALID; 1107 1108 if (dmub->hw_funcs.get_fw_boot_option) 1109 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1110 1111 return DMUB_STATUS_OK; 1112 } 1113 1114 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1115 bool skip) 1116 { 1117 if (!dmub->sw_init) 1118 return DMUB_STATUS_INVALID; 1119 1120 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1121 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1122 1123 return DMUB_STATUS_OK; 1124 } 1125 1126 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1127 void *entry) 1128 { 1129 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1130 uint64_t *dst = (uint64_t *)entry; 1131 uint8_t i; 1132 uint8_t loop_count; 1133 1134 if (rb->rptr == rb->wrpt) 1135 return false; 1136 1137 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1138 // copying data 1139 for (i = 0; i < loop_count; i++) 1140 *dst++ = *src++; 1141 1142 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1143 1144 rb->rptr %= rb->capacity; 1145 1146 return true; 1147 } 1148 1149 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1150 { 1151 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1152 1153 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1154 } 1155 1156 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1157 { 1158 if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1159 return false; 1160 dmub->hw_funcs.get_diagnostic_data(dmub); 1161 return true; 1162 } 1163 1164 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1165 { 1166 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1167 return false; 1168 1169 return dmub->hw_funcs.should_detect(dmub); 1170 } 1171 1172 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1173 { 1174 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1175 return DMUB_STATUS_INVALID; 1176 1177 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1178 return DMUB_STATUS_OK; 1179 } 1180 1181 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1182 { 1183 uint32_t i = 0; 1184 uint32_t ack = 0; 1185 1186 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1187 return DMUB_STATUS_INVALID; 1188 1189 for (i = 0; i <= timeout_us; i++) { 1190 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1191 if (ack) 1192 return DMUB_STATUS_OK; 1193 udelay(1); 1194 } 1195 return DMUB_STATUS_TIMEOUT; 1196 } 1197 1198 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1199 union dmub_inbox0_data_register data) 1200 { 1201 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1202 return DMUB_STATUS_INVALID; 1203 1204 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1205 return DMUB_STATUS_OK; 1206 } 1207 1208 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1209 { 1210 if (dmub->hw_funcs.subvp_save_surf_addr) { 1211 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1212 addr, 1213 subvp_index); 1214 } 1215 } 1216 1217 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1218 { 1219 if (!dmub || !dmub->hw_init) 1220 return; 1221 1222 dmub->power_state = dmub_srv_power_state; 1223 } 1224 1225 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1226 { 1227 uint32_t num_pending = 0; 1228 1229 if (!dmub->hw_init) 1230 return DMUB_STATUS_INVALID; 1231 1232 if (dmub->power_state != DMUB_POWER_STATE_D0) 1233 return DMUB_STATUS_POWER_STATE_D3; 1234 1235 if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1236 !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1237 return DMUB_STATUS_INVALID; 1238 1239 if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1240 num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1241 else 1242 /* num_submitted wrapped */ 1243 num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1244 (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1245 1246 if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1247 return DMUB_STATUS_QUEUE_FULL; 1248 1249 /* clear last rsp ack and send message */ 1250 dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1251 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1252 1253 dmub->reg_inbox0.num_submitted++; 1254 dmub->reg_inbox0.is_pending = true; 1255 dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1256 1257 return DMUB_STATUS_OK; 1258 } 1259 1260 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1261 union dmub_rb_cmd *cmd_rsp) 1262 { 1263 if (dmub) { 1264 if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1265 dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1266 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1267 } else { 1268 dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1269 } 1270 } 1271 } 1272 1273 static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1274 { 1275 if (!dmub || !dmub->sw_init) 1276 return DMUB_STATUS_INVALID; 1277 1278 dmub->reg_inbox0.is_pending = 0; 1279 dmub->reg_inbox0.is_multi_pending = 0; 1280 1281 return DMUB_STATUS_OK; 1282 } 1283 1284 static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1285 { 1286 if (!dmub->sw_init) 1287 return DMUB_STATUS_INVALID; 1288 1289 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1290 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1291 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1292 1293 if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1294 return DMUB_STATUS_HW_FAILURE; 1295 } else { 1296 dmub->inbox1.rb.rptr = rptr; 1297 dmub->inbox1.rb.wrpt = wptr; 1298 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1299 } 1300 } 1301 1302 return DMUB_STATUS_OK; 1303 } 1304 1305 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1306 { 1307 enum dmub_status status; 1308 1309 status = dmub_srv_sync_reg_inbox0(dmub); 1310 if (status != DMUB_STATUS_OK) 1311 return status; 1312 1313 status = dmub_srv_sync_inbox1(dmub); 1314 if (status != DMUB_STATUS_OK) 1315 return status; 1316 1317 return DMUB_STATUS_OK; 1318 } 1319 1320 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1321 uint32_t timeout_us, 1322 uint32_t num_free_required) 1323 { 1324 enum dmub_status status; 1325 uint32_t i; 1326 const uint32_t polling_interval_us = 1; 1327 1328 if (!dmub->hw_init) 1329 return DMUB_STATUS_INVALID; 1330 1331 for (i = 0; i < timeout_us; i += polling_interval_us) { 1332 status = dmub_srv_update_inbox_status(dmub); 1333 1334 if (status != DMUB_STATUS_OK) 1335 return status; 1336 1337 /* check for space in inbox1 */ 1338 if (dmub_rb_num_free(&dmub->inbox1.rb) >= num_free_required) 1339 return DMUB_STATUS_OK; 1340 1341 udelay(polling_interval_us); 1342 } 1343 1344 return DMUB_STATUS_TIMEOUT; 1345 } 1346 1347 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) 1348 { 1349 uint32_t rptr; 1350 1351 if (!dmub->hw_init) 1352 return DMUB_STATUS_INVALID; 1353 1354 if (dmub->power_state != DMUB_POWER_STATE_D0) 1355 return DMUB_STATUS_POWER_STATE_D3; 1356 1357 /* update inbox1 state */ 1358 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1359 1360 if (rptr > dmub->inbox1.rb.capacity) 1361 return DMUB_STATUS_HW_FAILURE; 1362 1363 if (dmub->inbox1.rb.rptr > rptr) { 1364 /* rb wrapped */ 1365 dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1366 } else { 1367 dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1368 } 1369 dmub->inbox1.rb.rptr = rptr; 1370 1371 /* update reg_inbox0 */ 1372 dmub_srv_update_reg_inbox0_status(dmub); 1373 1374 return DMUB_STATUS_OK; 1375 } 1376 1377 bool dmub_srv_get_preos_info(struct dmub_srv *dmub) 1378 { 1379 if (!dmub || !dmub->hw_funcs.get_preos_fw_info) 1380 return false; 1381 1382 return dmub->hw_funcs.get_preos_fw_info(dmub); 1383 } 1384