1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "os_types.h" 40 /* 41 * Note: the DMUB service is standalone. No additional headers should be 42 * added below or above this line unless they reside within the DMUB 43 * folder. 44 */ 45 46 /* Alignment for framebuffer memory. */ 47 #define DMUB_FB_ALIGNMENT (1024 * 1024) 48 49 /* Stack size. */ 50 #define DMUB_STACK_SIZE (128 * 1024) 51 52 /* Context size. */ 53 #define DMUB_CONTEXT_SIZE (512 * 1024) 54 55 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 56 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 57 58 /* Default state size if meta is absent. */ 59 #define DMUB_FW_STATE_SIZE (64 * 1024) 60 61 /* Default tracebuffer size if meta is absent. */ 62 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 63 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (256) 67 68 /* Number of windows in use. */ 69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 70 /* Base addresses. */ 71 72 #define DMUB_CW0_BASE (0x60000000) 73 #define DMUB_CW1_BASE (0x61000000) 74 #define DMUB_CW3_BASE (0x63000000) 75 #define DMUB_CW4_BASE (0x64000000) 76 #define DMUB_CW5_BASE (0x65000000) 77 #define DMUB_CW6_BASE (0x66000000) 78 79 #define DMUB_REGION5_BASE (0xA0000000) 80 81 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 82 83 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 84 { 85 return (val + factor - 1) / factor * factor; 86 } 87 88 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 89 { 90 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 91 uint8_t buf[64]; 92 uint32_t pos, end; 93 94 /** 95 * Read 64-byte chunks since we don't want to store a 96 * large temporary buffer for this purpose. 97 */ 98 end = fb->size / sizeof(buf) * sizeof(buf); 99 100 for (pos = 0; pos < end; pos += sizeof(buf)) 101 dmub_memcpy(buf, base + pos, sizeof(buf)); 102 103 /* Read anything leftover into the buffer. */ 104 if (end < fb->size) 105 dmub_memcpy(buf, base + pos, fb->size - end); 106 } 107 108 static const struct dmub_fw_meta_info * 109 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 110 { 111 const union dmub_fw_meta *meta; 112 113 if (!blob || !blob_size) 114 return NULL; 115 116 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 117 return NULL; 118 119 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 120 sizeof(union dmub_fw_meta)); 121 122 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 123 return NULL; 124 125 return &meta->info; 126 } 127 128 static const struct dmub_fw_meta_info * 129 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 130 { 131 const struct dmub_fw_meta_info *info = NULL; 132 133 if (params->fw_bss_data && params->bss_data_size) { 134 /* Legacy metadata region. */ 135 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 136 params->bss_data_size, 137 DMUB_FW_META_OFFSET); 138 } else if (params->fw_inst_const && params->inst_const_size) { 139 /* Combined metadata region - can be aligned to 16-bytes. */ 140 uint32_t i; 141 142 for (i = 0; i < 16; ++i) { 143 info = dmub_get_fw_meta_info_from_blob( 144 params->fw_inst_const, params->inst_const_size, i); 145 146 if (info) 147 break; 148 } 149 } 150 151 return info; 152 } 153 154 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 155 { 156 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 157 158 switch (asic) { 159 case DMUB_ASIC_DCN20: 160 case DMUB_ASIC_DCN21: 161 case DMUB_ASIC_DCN30: 162 case DMUB_ASIC_DCN301: 163 case DMUB_ASIC_DCN302: 164 case DMUB_ASIC_DCN303: 165 dmub->regs = &dmub_srv_dcn20_regs; 166 167 funcs->reset = dmub_dcn20_reset; 168 funcs->reset_release = dmub_dcn20_reset_release; 169 funcs->backdoor_load = dmub_dcn20_backdoor_load; 170 funcs->setup_windows = dmub_dcn20_setup_windows; 171 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 172 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 173 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 174 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 175 funcs->is_supported = dmub_dcn20_is_supported; 176 funcs->is_hw_init = dmub_dcn20_is_hw_init; 177 funcs->set_gpint = dmub_dcn20_set_gpint; 178 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 179 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 180 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 181 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 182 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 183 funcs->get_current_time = dmub_dcn20_get_current_time; 184 185 // Out mailbox register access functions for RN and above 186 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 187 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 188 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 189 190 //outbox0 call stacks 191 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 192 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 193 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 194 195 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 196 197 if (asic == DMUB_ASIC_DCN21) 198 dmub->regs = &dmub_srv_dcn21_regs; 199 200 if (asic == DMUB_ASIC_DCN30) { 201 dmub->regs = &dmub_srv_dcn30_regs; 202 203 funcs->backdoor_load = dmub_dcn30_backdoor_load; 204 funcs->setup_windows = dmub_dcn30_setup_windows; 205 } 206 if (asic == DMUB_ASIC_DCN301) { 207 dmub->regs = &dmub_srv_dcn301_regs; 208 209 funcs->backdoor_load = dmub_dcn30_backdoor_load; 210 funcs->setup_windows = dmub_dcn30_setup_windows; 211 } 212 if (asic == DMUB_ASIC_DCN302) { 213 dmub->regs = &dmub_srv_dcn302_regs; 214 215 funcs->backdoor_load = dmub_dcn30_backdoor_load; 216 funcs->setup_windows = dmub_dcn30_setup_windows; 217 } 218 if (asic == DMUB_ASIC_DCN303) { 219 dmub->regs = &dmub_srv_dcn303_regs; 220 221 funcs->backdoor_load = dmub_dcn30_backdoor_load; 222 funcs->setup_windows = dmub_dcn30_setup_windows; 223 } 224 break; 225 226 case DMUB_ASIC_DCN31: 227 case DMUB_ASIC_DCN31B: 228 case DMUB_ASIC_DCN314: 229 case DMUB_ASIC_DCN315: 230 case DMUB_ASIC_DCN316: 231 if (asic == DMUB_ASIC_DCN314) { 232 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 233 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 234 } else if (asic == DMUB_ASIC_DCN315) { 235 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 236 } else if (asic == DMUB_ASIC_DCN316) { 237 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 238 } else { 239 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 240 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 241 } 242 funcs->reset = dmub_dcn31_reset; 243 funcs->reset_release = dmub_dcn31_reset_release; 244 funcs->backdoor_load = dmub_dcn31_backdoor_load; 245 funcs->setup_windows = dmub_dcn31_setup_windows; 246 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 247 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 248 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 249 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 250 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 251 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 252 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 253 funcs->is_supported = dmub_dcn31_is_supported; 254 funcs->is_hw_init = dmub_dcn31_is_hw_init; 255 funcs->set_gpint = dmub_dcn31_set_gpint; 256 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 257 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 258 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 259 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 260 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 261 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 262 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 263 //outbox0 call stacks 264 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 265 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 266 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 267 268 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 269 funcs->should_detect = dmub_dcn31_should_detect; 270 funcs->get_current_time = dmub_dcn31_get_current_time; 271 272 break; 273 274 case DMUB_ASIC_DCN32: 275 case DMUB_ASIC_DCN321: 276 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 277 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 278 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 279 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 280 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 281 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 282 funcs->reset = dmub_dcn32_reset; 283 funcs->reset_release = dmub_dcn32_reset_release; 284 funcs->backdoor_load = dmub_dcn32_backdoor_load; 285 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 286 funcs->setup_windows = dmub_dcn32_setup_windows; 287 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 288 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 289 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 290 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 291 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 292 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 293 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 294 funcs->is_supported = dmub_dcn32_is_supported; 295 funcs->is_hw_init = dmub_dcn32_is_hw_init; 296 funcs->set_gpint = dmub_dcn32_set_gpint; 297 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 298 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 299 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 300 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 301 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 302 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 303 304 /* outbox0 call stacks */ 305 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 306 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 307 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 308 funcs->get_current_time = dmub_dcn32_get_current_time; 309 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 310 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 311 312 break; 313 314 default: 315 return false; 316 } 317 318 return true; 319 } 320 321 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 322 const struct dmub_srv_create_params *params) 323 { 324 enum dmub_status status = DMUB_STATUS_OK; 325 326 dmub_memset(dmub, 0, sizeof(*dmub)); 327 328 dmub->funcs = params->funcs; 329 dmub->user_ctx = params->user_ctx; 330 dmub->asic = params->asic; 331 dmub->fw_version = params->fw_version; 332 dmub->is_virtual = params->is_virtual; 333 334 /* Setup asic dependent hardware funcs. */ 335 if (!dmub_srv_hw_setup(dmub, params->asic)) { 336 status = DMUB_STATUS_INVALID; 337 goto cleanup; 338 } 339 340 /* Override (some) hardware funcs based on user params. */ 341 if (params->hw_funcs) { 342 if (params->hw_funcs->emul_get_inbox1_rptr) 343 dmub->hw_funcs.emul_get_inbox1_rptr = 344 params->hw_funcs->emul_get_inbox1_rptr; 345 346 if (params->hw_funcs->emul_set_inbox1_wptr) 347 dmub->hw_funcs.emul_set_inbox1_wptr = 348 params->hw_funcs->emul_set_inbox1_wptr; 349 350 if (params->hw_funcs->is_supported) 351 dmub->hw_funcs.is_supported = 352 params->hw_funcs->is_supported; 353 } 354 355 /* Sanity checks for required hw func pointers. */ 356 if (!dmub->hw_funcs.get_inbox1_rptr || 357 !dmub->hw_funcs.set_inbox1_wptr) { 358 status = DMUB_STATUS_INVALID; 359 goto cleanup; 360 } 361 362 cleanup: 363 if (status == DMUB_STATUS_OK) 364 dmub->sw_init = true; 365 else 366 dmub_srv_destroy(dmub); 367 368 return status; 369 } 370 371 void dmub_srv_destroy(struct dmub_srv *dmub) 372 { 373 dmub_memset(dmub, 0, sizeof(*dmub)); 374 } 375 376 enum dmub_status 377 dmub_srv_calc_region_info(struct dmub_srv *dmub, 378 const struct dmub_srv_region_params *params, 379 struct dmub_srv_region_info *out) 380 { 381 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 382 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 383 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 384 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 385 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 386 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 387 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 388 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 389 const struct dmub_fw_meta_info *fw_info; 390 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 391 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 392 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 393 394 if (!dmub->sw_init) 395 return DMUB_STATUS_INVALID; 396 397 memset(out, 0, sizeof(*out)); 398 399 out->num_regions = DMUB_NUM_WINDOWS; 400 401 inst->base = 0x0; 402 inst->top = inst->base + params->inst_const_size; 403 404 data->base = dmub_align(inst->top, 256); 405 data->top = data->base + params->bss_data_size; 406 407 /* 408 * All cache windows below should be aligned to the size 409 * of the DMCUB cache line, 64 bytes. 410 */ 411 412 stack->base = dmub_align(data->top, 256); 413 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 414 415 bios->base = dmub_align(stack->top, 256); 416 bios->top = bios->base + params->vbios_size; 417 418 mail->base = dmub_align(bios->top, 256); 419 mail->top = mail->base + DMUB_MAILBOX_SIZE; 420 421 fw_info = dmub_get_fw_meta_info(params); 422 423 if (fw_info) { 424 fw_state_size = fw_info->fw_region_size; 425 trace_buffer_size = fw_info->trace_buffer_size; 426 427 /** 428 * If DM didn't fill in a version, then fill it in based on 429 * the firmware meta now that we have it. 430 * 431 * TODO: Make it easier for driver to extract this out to 432 * pass during creation. 433 */ 434 if (dmub->fw_version == 0) 435 dmub->fw_version = fw_info->fw_version; 436 } 437 438 trace_buff->base = dmub_align(mail->top, 256); 439 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 440 441 fw_state->base = dmub_align(trace_buff->top, 256); 442 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 443 444 scratch_mem->base = dmub_align(fw_state->top, 256); 445 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 446 447 out->fb_size = dmub_align(scratch_mem->top, 4096); 448 449 return DMUB_STATUS_OK; 450 } 451 452 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 453 const struct dmub_srv_fb_params *params, 454 struct dmub_srv_fb_info *out) 455 { 456 uint8_t *cpu_base; 457 uint64_t gpu_base; 458 uint32_t i; 459 460 if (!dmub->sw_init) 461 return DMUB_STATUS_INVALID; 462 463 memset(out, 0, sizeof(*out)); 464 465 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 466 return DMUB_STATUS_INVALID; 467 468 cpu_base = (uint8_t *)params->cpu_addr; 469 gpu_base = params->gpu_addr; 470 471 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 472 const struct dmub_region *reg = 473 ¶ms->region_info->regions[i]; 474 475 out->fb[i].cpu_addr = cpu_base + reg->base; 476 out->fb[i].gpu_addr = gpu_base + reg->base; 477 out->fb[i].size = reg->top - reg->base; 478 } 479 480 out->num_fb = DMUB_NUM_WINDOWS; 481 482 return DMUB_STATUS_OK; 483 } 484 485 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 486 bool *is_supported) 487 { 488 *is_supported = false; 489 490 if (!dmub->sw_init) 491 return DMUB_STATUS_INVALID; 492 493 if (dmub->hw_funcs.is_supported) 494 *is_supported = dmub->hw_funcs.is_supported(dmub); 495 496 return DMUB_STATUS_OK; 497 } 498 499 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 500 { 501 *is_hw_init = false; 502 503 if (!dmub->sw_init) 504 return DMUB_STATUS_INVALID; 505 506 if (!dmub->hw_init) 507 return DMUB_STATUS_OK; 508 509 if (dmub->hw_funcs.is_hw_init) 510 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 511 512 return DMUB_STATUS_OK; 513 } 514 515 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 516 const struct dmub_srv_hw_params *params) 517 { 518 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 519 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 520 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 521 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 522 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 523 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 524 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 525 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 526 527 struct dmub_rb_init_params rb_params, outbox0_rb_params; 528 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 529 struct dmub_region inbox1, outbox1, outbox0; 530 531 if (!dmub->sw_init) 532 return DMUB_STATUS_INVALID; 533 534 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 535 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 536 ASSERT(0); 537 return DMUB_STATUS_INVALID; 538 } 539 540 dmub->fb_base = params->fb_base; 541 dmub->fb_offset = params->fb_offset; 542 dmub->psp_version = params->psp_version; 543 544 if (dmub->hw_funcs.reset) 545 dmub->hw_funcs.reset(dmub); 546 547 /* reset the cache of the last wptr as well now that hw is reset */ 548 dmub->inbox1_last_wptr = 0; 549 550 cw0.offset.quad_part = inst_fb->gpu_addr; 551 cw0.region.base = DMUB_CW0_BASE; 552 cw0.region.top = cw0.region.base + inst_fb->size - 1; 553 554 cw1.offset.quad_part = stack_fb->gpu_addr; 555 cw1.region.base = DMUB_CW1_BASE; 556 cw1.region.top = cw1.region.base + stack_fb->size - 1; 557 558 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 559 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 560 561 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 562 /** 563 * Read back all the instruction memory so we don't hang the 564 * DMCUB when backdoor loading if the write from x86 hasn't been 565 * flushed yet. This only occurs in backdoor loading. 566 */ 567 dmub_flush_buffer_mem(inst_fb); 568 569 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 570 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 571 else 572 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 573 } 574 575 cw2.offset.quad_part = data_fb->gpu_addr; 576 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 577 cw2.region.top = cw2.region.base + data_fb->size; 578 579 cw3.offset.quad_part = bios_fb->gpu_addr; 580 cw3.region.base = DMUB_CW3_BASE; 581 cw3.region.top = cw3.region.base + bios_fb->size; 582 583 cw4.offset.quad_part = mail_fb->gpu_addr; 584 cw4.region.base = DMUB_CW4_BASE; 585 cw4.region.top = cw4.region.base + mail_fb->size; 586 587 /** 588 * Doubled the mailbox region to accomodate inbox and outbox. 589 * Note: Currently, currently total mailbox size is 16KB. It is split 590 * equally into 8KB between inbox and outbox. If this config is 591 * changed, then uncached base address configuration of outbox1 592 * has to be updated in funcs->setup_out_mailbox. 593 */ 594 inbox1.base = cw4.region.base; 595 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 596 outbox1.base = inbox1.top; 597 outbox1.top = cw4.region.top; 598 599 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 600 cw5.region.base = DMUB_CW5_BASE; 601 cw5.region.top = cw5.region.base + tracebuff_fb->size; 602 603 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 604 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 605 606 cw6.offset.quad_part = fw_state_fb->gpu_addr; 607 cw6.region.base = DMUB_CW6_BASE; 608 cw6.region.top = cw6.region.base + fw_state_fb->size; 609 610 dmub->fw_state = fw_state_fb->cpu_addr; 611 612 dmub->scratch_mem_fb = *scratch_mem_fb; 613 614 if (dmub->hw_funcs.setup_windows) 615 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 616 617 if (dmub->hw_funcs.setup_outbox0) 618 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 619 620 if (dmub->hw_funcs.setup_mailbox) 621 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 622 if (dmub->hw_funcs.setup_out_mailbox) 623 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 624 625 dmub_memset(&rb_params, 0, sizeof(rb_params)); 626 rb_params.ctx = dmub; 627 rb_params.base_address = mail_fb->cpu_addr; 628 rb_params.capacity = DMUB_RB_SIZE; 629 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 630 631 // Initialize outbox1 ring buffer 632 rb_params.ctx = dmub; 633 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 634 rb_params.capacity = DMUB_RB_SIZE; 635 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 636 637 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 638 outbox0_rb_params.ctx = dmub; 639 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 640 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 641 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 642 643 /* Report to DMUB what features are supported by current driver */ 644 if (dmub->hw_funcs.enable_dmub_boot_options) 645 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 646 647 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 648 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 649 params->skip_panel_power_sequence); 650 651 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 652 dmub->hw_funcs.reset_release(dmub); 653 654 dmub->hw_init = true; 655 656 return DMUB_STATUS_OK; 657 } 658 659 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 660 { 661 if (!dmub->sw_init) 662 return DMUB_STATUS_INVALID; 663 664 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 665 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 666 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 667 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 668 } 669 670 return DMUB_STATUS_OK; 671 } 672 673 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 674 { 675 if (!dmub->sw_init) 676 return DMUB_STATUS_INVALID; 677 678 if (dmub->hw_funcs.reset) 679 dmub->hw_funcs.reset(dmub); 680 681 /* mailboxes have been reset in hw, so reset the sw state as well */ 682 dmub->inbox1_last_wptr = 0; 683 dmub->inbox1_rb.wrpt = 0; 684 dmub->inbox1_rb.rptr = 0; 685 dmub->outbox0_rb.wrpt = 0; 686 dmub->outbox0_rb.rptr = 0; 687 dmub->outbox1_rb.wrpt = 0; 688 dmub->outbox1_rb.rptr = 0; 689 690 dmub->hw_init = false; 691 692 return DMUB_STATUS_OK; 693 } 694 695 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 696 const union dmub_rb_cmd *cmd) 697 { 698 if (!dmub->hw_init) 699 return DMUB_STATUS_INVALID; 700 701 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 702 return DMUB_STATUS_OK; 703 704 return DMUB_STATUS_QUEUE_FULL; 705 } 706 707 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 708 { 709 struct dmub_rb flush_rb; 710 711 if (!dmub->hw_init) 712 return DMUB_STATUS_INVALID; 713 714 /** 715 * Read back all the queued commands to ensure that they've 716 * been flushed to framebuffer memory. Otherwise DMCUB might 717 * read back stale, fully invalid or partially invalid data. 718 */ 719 flush_rb = dmub->inbox1_rb; 720 flush_rb.rptr = dmub->inbox1_last_wptr; 721 dmub_rb_flush_pending(&flush_rb); 722 723 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 724 725 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 726 727 return DMUB_STATUS_OK; 728 } 729 730 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 731 uint32_t timeout_us) 732 { 733 uint32_t i; 734 735 if (!dmub->hw_init) 736 return DMUB_STATUS_INVALID; 737 738 for (i = 0; i <= timeout_us; i += 100) { 739 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 740 741 if (status.bits.dal_fw && status.bits.mailbox_rdy) 742 return DMUB_STATUS_OK; 743 744 udelay(100); 745 } 746 747 return DMUB_STATUS_TIMEOUT; 748 } 749 750 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 751 uint32_t timeout_us) 752 { 753 uint32_t i, rptr; 754 755 if (!dmub->hw_init) 756 return DMUB_STATUS_INVALID; 757 758 for (i = 0; i <= timeout_us; ++i) { 759 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 760 761 if (rptr > dmub->inbox1_rb.capacity) 762 return DMUB_STATUS_HW_FAILURE; 763 764 dmub->inbox1_rb.rptr = rptr; 765 766 if (dmub_rb_empty(&dmub->inbox1_rb)) 767 return DMUB_STATUS_OK; 768 769 udelay(1); 770 } 771 772 return DMUB_STATUS_TIMEOUT; 773 } 774 775 enum dmub_status 776 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 777 enum dmub_gpint_command command_code, 778 uint16_t param, uint32_t timeout_us) 779 { 780 union dmub_gpint_data_register reg; 781 uint32_t i; 782 783 if (!dmub->sw_init) 784 return DMUB_STATUS_INVALID; 785 786 if (!dmub->hw_funcs.set_gpint) 787 return DMUB_STATUS_INVALID; 788 789 if (!dmub->hw_funcs.is_gpint_acked) 790 return DMUB_STATUS_INVALID; 791 792 reg.bits.status = 1; 793 reg.bits.command_code = command_code; 794 reg.bits.param = param; 795 796 dmub->hw_funcs.set_gpint(dmub, reg); 797 798 for (i = 0; i < timeout_us; ++i) { 799 udelay(1); 800 801 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 802 return DMUB_STATUS_OK; 803 } 804 805 return DMUB_STATUS_TIMEOUT; 806 } 807 808 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 809 uint32_t *response) 810 { 811 *response = 0; 812 813 if (!dmub->sw_init) 814 return DMUB_STATUS_INVALID; 815 816 if (!dmub->hw_funcs.get_gpint_response) 817 return DMUB_STATUS_INVALID; 818 819 *response = dmub->hw_funcs.get_gpint_response(dmub); 820 821 return DMUB_STATUS_OK; 822 } 823 824 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 825 uint32_t *dataout) 826 { 827 *dataout = 0; 828 829 if (!dmub->sw_init) 830 return DMUB_STATUS_INVALID; 831 832 if (!dmub->hw_funcs.get_gpint_dataout) 833 return DMUB_STATUS_INVALID; 834 835 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 836 837 return DMUB_STATUS_OK; 838 } 839 840 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 841 union dmub_fw_boot_status *status) 842 { 843 status->all = 0; 844 845 if (!dmub->sw_init) 846 return DMUB_STATUS_INVALID; 847 848 if (dmub->hw_funcs.get_fw_status) 849 *status = dmub->hw_funcs.get_fw_status(dmub); 850 851 return DMUB_STATUS_OK; 852 } 853 854 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 855 union dmub_fw_boot_options *option) 856 { 857 option->all = 0; 858 859 if (!dmub->sw_init) 860 return DMUB_STATUS_INVALID; 861 862 if (dmub->hw_funcs.get_fw_boot_option) 863 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 864 865 return DMUB_STATUS_OK; 866 } 867 868 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 869 bool skip) 870 { 871 if (!dmub->sw_init) 872 return DMUB_STATUS_INVALID; 873 874 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 875 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 876 877 return DMUB_STATUS_OK; 878 } 879 880 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 881 union dmub_rb_cmd *cmd) 882 { 883 enum dmub_status status = DMUB_STATUS_OK; 884 885 // Queue command 886 status = dmub_srv_cmd_queue(dmub, cmd); 887 888 if (status != DMUB_STATUS_OK) 889 return status; 890 891 // Execute command 892 status = dmub_srv_cmd_execute(dmub); 893 894 if (status != DMUB_STATUS_OK) 895 return status; 896 897 // Wait for DMUB to process command 898 status = dmub_srv_wait_for_idle(dmub, 100000); 899 900 if (status != DMUB_STATUS_OK) 901 return status; 902 903 // Copy data back from ring buffer into command 904 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 905 906 return status; 907 } 908 909 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 910 void *entry) 911 { 912 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 913 uint64_t *dst = (uint64_t *)entry; 914 uint8_t i; 915 uint8_t loop_count; 916 917 if (rb->rptr == rb->wrpt) 918 return false; 919 920 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 921 // copying data 922 for (i = 0; i < loop_count; i++) 923 *dst++ = *src++; 924 925 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 926 927 rb->rptr %= rb->capacity; 928 929 return true; 930 } 931 932 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 933 { 934 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 935 936 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 937 } 938 939 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 940 { 941 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 942 return false; 943 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 944 return true; 945 } 946 947 bool dmub_srv_should_detect(struct dmub_srv *dmub) 948 { 949 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 950 return false; 951 952 return dmub->hw_funcs.should_detect(dmub); 953 } 954 955 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 956 { 957 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 958 return DMUB_STATUS_INVALID; 959 960 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 961 return DMUB_STATUS_OK; 962 } 963 964 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 965 { 966 uint32_t i = 0; 967 uint32_t ack = 0; 968 969 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 970 return DMUB_STATUS_INVALID; 971 972 for (i = 0; i <= timeout_us; i++) { 973 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 974 if (ack) 975 return DMUB_STATUS_OK; 976 } 977 return DMUB_STATUS_TIMEOUT; 978 } 979 980 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 981 union dmub_inbox0_data_register data) 982 { 983 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 984 return DMUB_STATUS_INVALID; 985 986 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 987 return DMUB_STATUS_OK; 988 } 989 990 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 991 { 992 if (dmub->hw_funcs.subvp_save_surf_addr) { 993 dmub->hw_funcs.subvp_save_surf_addr(dmub, 994 addr, 995 subvp_index); 996 } 997 } 998