1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn36.h" 42 #include "dmub_dcn401.h" 43 #include "os_types.h" 44 /* 45 * Note: the DMUB service is standalone. No additional headers should be 46 * added below or above this line unless they reside within the DMUB 47 * folder. 48 */ 49 50 /* Alignment for framebuffer memory. */ 51 #define DMUB_FB_ALIGNMENT (1024 * 1024) 52 53 /* Stack size. */ 54 #define DMUB_STACK_SIZE (128 * 1024) 55 56 /* Context size. */ 57 #define DMUB_CONTEXT_SIZE (512 * 1024) 58 59 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 60 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 61 62 /* Default state size if meta is absent. */ 63 #define DMUB_FW_STATE_SIZE (64 * 1024) 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (1024) 67 68 /* Default indirect buffer size. */ 69 #define DMUB_IB_MEM_SIZE (1280) 70 71 /* Number of windows in use. */ 72 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 73 /* Base addresses. */ 74 75 #define DMUB_CW0_BASE (0x60000000) 76 #define DMUB_CW1_BASE (0x61000000) 77 #define DMUB_CW3_BASE (0x63000000) 78 #define DMUB_CW4_BASE (0x64000000) 79 #define DMUB_CW5_BASE (0x65000000) 80 #define DMUB_CW6_BASE (0x66000000) 81 82 #define DMUB_REGION5_BASE (0xA0000000) 83 #define DMUB_REGION6_BASE (0xC0000000) 84 85 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 86 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 87 88 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 89 { 90 return (val + factor - 1) / factor * factor; 91 } 92 93 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 94 { 95 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 96 uint8_t buf[64]; 97 uint32_t pos, end; 98 99 /** 100 * Read 64-byte chunks since we don't want to store a 101 * large temporary buffer for this purpose. 102 */ 103 end = fb->size / sizeof(buf) * sizeof(buf); 104 105 for (pos = 0; pos < end; pos += sizeof(buf)) 106 dmub_memcpy(buf, base + pos, sizeof(buf)); 107 108 /* Read anything leftover into the buffer. */ 109 if (end < fb->size) 110 dmub_memcpy(buf, base + pos, fb->size - end); 111 } 112 113 static const struct dmub_fw_meta_info * 114 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 115 { 116 const union dmub_fw_meta *meta; 117 118 if (!blob || !blob_size) 119 return NULL; 120 121 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 122 return NULL; 123 124 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 125 sizeof(union dmub_fw_meta)); 126 127 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 128 return NULL; 129 130 return &meta->info; 131 } 132 133 static const struct dmub_fw_meta_info * 134 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 135 { 136 const struct dmub_fw_meta_info *info = NULL; 137 138 if (params->fw_bss_data && params->bss_data_size) { 139 /* Legacy metadata region. */ 140 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 141 params->bss_data_size, 142 DMUB_FW_META_OFFSET); 143 } else if (params->fw_inst_const && params->inst_const_size) { 144 /* Combined metadata region - can be aligned to 16-bytes. */ 145 uint32_t i; 146 147 for (i = 0; i < 16; ++i) { 148 info = dmub_get_fw_meta_info_from_blob( 149 params->fw_inst_const, params->inst_const_size, i); 150 151 if (info) 152 break; 153 } 154 } 155 156 return info; 157 } 158 159 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 160 { 161 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 162 163 /* default to specifying now inbox type */ 164 enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 165 166 switch (asic) { 167 case DMUB_ASIC_DCN20: 168 case DMUB_ASIC_DCN21: 169 case DMUB_ASIC_DCN30: 170 case DMUB_ASIC_DCN301: 171 case DMUB_ASIC_DCN302: 172 case DMUB_ASIC_DCN303: 173 dmub->regs = &dmub_srv_dcn20_regs; 174 175 funcs->reset = dmub_dcn20_reset; 176 funcs->reset_release = dmub_dcn20_reset_release; 177 funcs->backdoor_load = dmub_dcn20_backdoor_load; 178 funcs->setup_windows = dmub_dcn20_setup_windows; 179 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 180 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 181 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 182 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 183 funcs->is_supported = dmub_dcn20_is_supported; 184 funcs->is_hw_init = dmub_dcn20_is_hw_init; 185 funcs->set_gpint = dmub_dcn20_set_gpint; 186 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 187 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 188 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 189 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 190 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 191 funcs->get_current_time = dmub_dcn20_get_current_time; 192 193 // Out mailbox register access functions for RN and above 194 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 195 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 196 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 197 198 //outbox0 call stacks 199 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 200 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 201 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 202 203 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 204 205 if (asic == DMUB_ASIC_DCN21) 206 dmub->regs = &dmub_srv_dcn21_regs; 207 208 if (asic == DMUB_ASIC_DCN30) { 209 dmub->regs = &dmub_srv_dcn30_regs; 210 211 funcs->backdoor_load = dmub_dcn30_backdoor_load; 212 funcs->setup_windows = dmub_dcn30_setup_windows; 213 } 214 if (asic == DMUB_ASIC_DCN301) { 215 dmub->regs = &dmub_srv_dcn301_regs; 216 217 funcs->backdoor_load = dmub_dcn30_backdoor_load; 218 funcs->setup_windows = dmub_dcn30_setup_windows; 219 } 220 if (asic == DMUB_ASIC_DCN302) { 221 dmub->regs = &dmub_srv_dcn302_regs; 222 223 funcs->backdoor_load = dmub_dcn30_backdoor_load; 224 funcs->setup_windows = dmub_dcn30_setup_windows; 225 } 226 if (asic == DMUB_ASIC_DCN303) { 227 dmub->regs = &dmub_srv_dcn303_regs; 228 229 funcs->backdoor_load = dmub_dcn30_backdoor_load; 230 funcs->setup_windows = dmub_dcn30_setup_windows; 231 } 232 break; 233 234 case DMUB_ASIC_DCN31: 235 case DMUB_ASIC_DCN31B: 236 case DMUB_ASIC_DCN314: 237 case DMUB_ASIC_DCN315: 238 case DMUB_ASIC_DCN316: 239 if (asic == DMUB_ASIC_DCN314) { 240 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 241 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 242 } else if (asic == DMUB_ASIC_DCN315) { 243 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 244 } else if (asic == DMUB_ASIC_DCN316) { 245 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 246 } else { 247 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 248 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 249 } 250 funcs->reset = dmub_dcn31_reset; 251 funcs->reset_release = dmub_dcn31_reset_release; 252 funcs->backdoor_load = dmub_dcn31_backdoor_load; 253 funcs->setup_windows = dmub_dcn31_setup_windows; 254 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 255 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 256 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 257 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 258 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 259 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 260 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 261 funcs->is_supported = dmub_dcn31_is_supported; 262 funcs->is_hw_init = dmub_dcn31_is_hw_init; 263 funcs->set_gpint = dmub_dcn31_set_gpint; 264 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 265 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 266 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 267 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 268 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 269 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 270 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 271 //outbox0 call stacks 272 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 273 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 274 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 275 276 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 277 funcs->should_detect = dmub_dcn31_should_detect; 278 funcs->get_current_time = dmub_dcn31_get_current_time; 279 280 break; 281 282 case DMUB_ASIC_DCN32: 283 case DMUB_ASIC_DCN321: 284 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 285 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 286 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 287 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 288 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 289 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 290 funcs->reset = dmub_dcn32_reset; 291 funcs->reset_release = dmub_dcn32_reset_release; 292 funcs->backdoor_load = dmub_dcn32_backdoor_load; 293 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 294 funcs->setup_windows = dmub_dcn32_setup_windows; 295 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 296 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 297 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 298 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 299 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 300 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 301 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 302 funcs->is_supported = dmub_dcn32_is_supported; 303 funcs->is_hw_init = dmub_dcn32_is_hw_init; 304 funcs->set_gpint = dmub_dcn32_set_gpint; 305 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 306 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 307 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 308 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 309 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 310 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 311 312 /* outbox0 call stacks */ 313 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 314 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 315 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 316 funcs->get_current_time = dmub_dcn32_get_current_time; 317 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 318 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 319 320 break; 321 322 case DMUB_ASIC_DCN35: 323 case DMUB_ASIC_DCN351: 324 case DMUB_ASIC_DCN36: 325 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 326 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 327 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 328 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 329 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 330 funcs->reset = dmub_dcn35_reset; 331 funcs->reset_release = dmub_dcn35_reset_release; 332 funcs->backdoor_load = dmub_dcn35_backdoor_load; 333 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 334 funcs->setup_windows = dmub_dcn35_setup_windows; 335 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 336 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 337 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 338 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 339 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 340 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 341 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 342 funcs->is_supported = dmub_dcn35_is_supported; 343 funcs->is_hw_init = dmub_dcn35_is_hw_init; 344 funcs->set_gpint = dmub_dcn35_set_gpint; 345 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 346 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 347 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 348 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 349 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 350 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 351 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 352 //outbox0 call stacks 353 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 354 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 355 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 356 357 funcs->get_current_time = dmub_dcn35_get_current_time; 358 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 359 360 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 361 if (asic == DMUB_ASIC_DCN351) 362 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 363 if (asic == DMUB_ASIC_DCN36) 364 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 365 366 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 367 funcs->should_detect = dmub_dcn35_should_detect; 368 break; 369 370 case DMUB_ASIC_DCN401: 371 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 372 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 373 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 374 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 375 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 376 funcs->reset = dmub_dcn401_reset; 377 funcs->reset_release = dmub_dcn401_reset_release; 378 funcs->backdoor_load = dmub_dcn401_backdoor_load; 379 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 380 funcs->setup_windows = dmub_dcn401_setup_windows; 381 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 382 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 383 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 384 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 385 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 386 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 387 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 388 funcs->is_supported = dmub_dcn401_is_supported; 389 funcs->is_hw_init = dmub_dcn401_is_hw_init; 390 funcs->set_gpint = dmub_dcn401_set_gpint; 391 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 392 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 393 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 394 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 395 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 396 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 397 //outbox0 call stacks 398 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 399 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 400 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 401 402 funcs->get_current_time = dmub_dcn401_get_current_time; 403 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 404 405 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 406 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 407 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 408 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 409 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 410 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 411 default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 412 413 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 414 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 415 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 416 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 417 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 418 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 419 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 420 break; 421 default: 422 return false; 423 } 424 425 /* set default inbox type if not overriden */ 426 if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 427 if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 428 /* use default inbox type as specified by DCN rev */ 429 dmub->inbox_type = default_inbox_type; 430 } else if (funcs->send_reg_inbox0_cmd_msg) { 431 /* prefer reg as default inbox type if present */ 432 dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 433 } else { 434 /* use fb as fallback */ 435 dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 436 } 437 } 438 439 return true; 440 } 441 442 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 443 const struct dmub_srv_create_params *params) 444 { 445 enum dmub_status status = DMUB_STATUS_OK; 446 447 dmub_memset(dmub, 0, sizeof(*dmub)); 448 449 dmub->funcs = params->funcs; 450 dmub->user_ctx = params->user_ctx; 451 dmub->asic = params->asic; 452 dmub->fw_version = params->fw_version; 453 dmub->is_virtual = params->is_virtual; 454 dmub->inbox_type = params->inbox_type; 455 456 /* Setup asic dependent hardware funcs. */ 457 if (!dmub_srv_hw_setup(dmub, params->asic)) { 458 status = DMUB_STATUS_INVALID; 459 goto cleanup; 460 } 461 462 /* Override (some) hardware funcs based on user params. */ 463 if (params->hw_funcs) { 464 if (params->hw_funcs->emul_get_inbox1_rptr) 465 dmub->hw_funcs.emul_get_inbox1_rptr = 466 params->hw_funcs->emul_get_inbox1_rptr; 467 468 if (params->hw_funcs->emul_set_inbox1_wptr) 469 dmub->hw_funcs.emul_set_inbox1_wptr = 470 params->hw_funcs->emul_set_inbox1_wptr; 471 472 if (params->hw_funcs->is_supported) 473 dmub->hw_funcs.is_supported = 474 params->hw_funcs->is_supported; 475 } 476 477 /* Sanity checks for required hw func pointers. */ 478 if (!dmub->hw_funcs.get_inbox1_rptr || 479 !dmub->hw_funcs.set_inbox1_wptr) { 480 status = DMUB_STATUS_INVALID; 481 goto cleanup; 482 } 483 484 cleanup: 485 if (status == DMUB_STATUS_OK) 486 dmub->sw_init = true; 487 else 488 dmub_srv_destroy(dmub); 489 490 return status; 491 } 492 493 void dmub_srv_destroy(struct dmub_srv *dmub) 494 { 495 dmub_memset(dmub, 0, sizeof(*dmub)); 496 } 497 498 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 499 struct dmub_srv_region_info *out, 500 const uint32_t *window_sizes, 501 enum dmub_window_memory_type memory_type) 502 { 503 uint32_t i, top = 0; 504 505 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 506 if (params->window_memory_type[i] == memory_type) { 507 struct dmub_region *region = &out->regions[i]; 508 509 region->base = dmub_align(top, 256); 510 region->top = region->base + dmub_align(window_sizes[i], 64); 511 top = region->top; 512 } 513 } 514 515 return dmub_align(top, 4096); 516 } 517 518 enum dmub_status 519 dmub_srv_calc_region_info(struct dmub_srv *dmub, 520 const struct dmub_srv_region_params *params, 521 struct dmub_srv_region_info *out) 522 { 523 const struct dmub_fw_meta_info *fw_info; 524 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 525 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 526 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 527 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 528 529 if (!dmub->sw_init) 530 return DMUB_STATUS_INVALID; 531 532 memset(out, 0, sizeof(*out)); 533 memset(window_sizes, 0, sizeof(window_sizes)); 534 535 out->num_regions = DMUB_NUM_WINDOWS; 536 537 fw_info = dmub_get_fw_meta_info(params); 538 539 if (fw_info) { 540 memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); 541 542 fw_state_size = fw_info->fw_region_size; 543 trace_buffer_size = fw_info->trace_buffer_size; 544 shared_state_size = fw_info->shared_state_size; 545 546 /** 547 * If DM didn't fill in a version, then fill it in based on 548 * the firmware meta now that we have it. 549 * 550 * TODO: Make it easier for driver to extract this out to 551 * pass during creation. 552 */ 553 if (dmub->fw_version == 0) 554 dmub->fw_version = fw_info->fw_version; 555 } 556 557 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 558 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 559 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 560 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 561 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 562 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 563 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 564 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE; 565 window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE; 566 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 567 568 out->fb_size = 569 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 570 571 out->gart_size = 572 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 573 574 return DMUB_STATUS_OK; 575 } 576 577 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 578 const struct dmub_srv_memory_params *params, 579 struct dmub_srv_fb_info *out) 580 { 581 uint32_t i; 582 583 if (!dmub->sw_init) 584 return DMUB_STATUS_INVALID; 585 586 memset(out, 0, sizeof(*out)); 587 588 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 589 return DMUB_STATUS_INVALID; 590 591 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 592 const struct dmub_region *reg = 593 ¶ms->region_info->regions[i]; 594 595 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 596 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 597 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 598 } else { 599 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 600 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 601 } 602 603 out->fb[i].size = reg->top - reg->base; 604 } 605 606 out->num_fb = DMUB_NUM_WINDOWS; 607 608 return DMUB_STATUS_OK; 609 } 610 611 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 612 bool *is_supported) 613 { 614 *is_supported = false; 615 616 if (!dmub->sw_init) 617 return DMUB_STATUS_INVALID; 618 619 if (dmub->hw_funcs.is_supported) 620 *is_supported = dmub->hw_funcs.is_supported(dmub); 621 622 return DMUB_STATUS_OK; 623 } 624 625 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 626 { 627 *is_hw_init = false; 628 629 if (!dmub->sw_init) 630 return DMUB_STATUS_INVALID; 631 632 if (!dmub->hw_init) 633 return DMUB_STATUS_OK; 634 635 if (dmub->hw_funcs.is_hw_init) 636 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 637 638 return DMUB_STATUS_OK; 639 } 640 641 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 642 const struct dmub_srv_hw_params *params) 643 { 644 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 645 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 646 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 647 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 648 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 649 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 650 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 651 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 652 struct dmub_fb *ib_mem_gart = params->fb[DMUB_WINDOW_IB_MEM]; 653 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 654 655 struct dmub_rb_init_params rb_params, outbox0_rb_params; 656 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 657 struct dmub_region inbox1, outbox1, outbox0; 658 659 if (!dmub->sw_init) 660 return DMUB_STATUS_INVALID; 661 662 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 663 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb || !ib_mem_gart) { 664 ASSERT(0); 665 return DMUB_STATUS_INVALID; 666 } 667 668 dmub->fb_base = params->fb_base; 669 dmub->fb_offset = params->fb_offset; 670 dmub->psp_version = params->psp_version; 671 672 if (dmub->hw_funcs.reset) 673 dmub->hw_funcs.reset(dmub); 674 675 /* reset the cache of the last wptr as well now that hw is reset */ 676 dmub->inbox1_last_wptr = 0; 677 678 cw0.offset.quad_part = inst_fb->gpu_addr; 679 cw0.region.base = DMUB_CW0_BASE; 680 cw0.region.top = cw0.region.base + inst_fb->size - 1; 681 682 cw1.offset.quad_part = stack_fb->gpu_addr; 683 cw1.region.base = DMUB_CW1_BASE; 684 cw1.region.top = cw1.region.base + stack_fb->size - 1; 685 686 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 687 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 688 689 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 690 /** 691 * Read back all the instruction memory so we don't hang the 692 * DMCUB when backdoor loading if the write from x86 hasn't been 693 * flushed yet. This only occurs in backdoor loading. 694 */ 695 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 696 dmub_flush_buffer_mem(inst_fb); 697 698 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 699 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 700 else 701 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 702 } 703 704 cw2.offset.quad_part = data_fb->gpu_addr; 705 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 706 cw2.region.top = cw2.region.base + data_fb->size; 707 708 cw3.offset.quad_part = bios_fb->gpu_addr; 709 cw3.region.base = DMUB_CW3_BASE; 710 cw3.region.top = cw3.region.base + bios_fb->size; 711 712 cw4.offset.quad_part = mail_fb->gpu_addr; 713 cw4.region.base = DMUB_CW4_BASE; 714 cw4.region.top = cw4.region.base + mail_fb->size; 715 716 /** 717 * Doubled the mailbox region to accomodate inbox and outbox. 718 * Note: Currently, currently total mailbox size is 16KB. It is split 719 * equally into 8KB between inbox and outbox. If this config is 720 * changed, then uncached base address configuration of outbox1 721 * has to be updated in funcs->setup_out_mailbox. 722 */ 723 inbox1.base = cw4.region.base; 724 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 725 outbox1.base = inbox1.top; 726 outbox1.top = inbox1.top + DMUB_RB_SIZE; 727 728 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 729 cw5.region.base = DMUB_CW5_BASE; 730 cw5.region.top = cw5.region.base + tracebuff_fb->size; 731 732 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 733 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 734 735 cw6.offset.quad_part = fw_state_fb->gpu_addr; 736 cw6.region.base = DMUB_CW6_BASE; 737 cw6.region.top = cw6.region.base + fw_state_fb->size; 738 739 dmub->fw_state = (void *)((uintptr_t)(fw_state_fb->cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET); 740 741 region6.offset.quad_part = shared_state_fb->gpu_addr; 742 region6.region.base = DMUB_CW6_BASE; 743 region6.region.top = region6.region.base + shared_state_fb->size; 744 745 dmub->shared_state = shared_state_fb->cpu_addr; 746 747 dmub->scratch_mem_fb = *scratch_mem_fb; 748 749 dmub->ib_mem_gart = *ib_mem_gart; 750 751 if (dmub->hw_funcs.setup_windows) 752 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 753 754 if (dmub->hw_funcs.setup_outbox0) 755 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 756 757 if (dmub->hw_funcs.setup_mailbox) 758 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 759 if (dmub->hw_funcs.setup_out_mailbox) 760 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 761 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 762 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 763 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 764 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 765 766 dmub_memset(&rb_params, 0, sizeof(rb_params)); 767 rb_params.ctx = dmub; 768 rb_params.base_address = mail_fb->cpu_addr; 769 rb_params.capacity = DMUB_RB_SIZE; 770 dmub_rb_init(&dmub->inbox1.rb, &rb_params); 771 772 // Initialize outbox1 ring buffer 773 rb_params.ctx = dmub; 774 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 775 rb_params.capacity = DMUB_RB_SIZE; 776 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 777 778 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 779 outbox0_rb_params.ctx = dmub; 780 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 781 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 782 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 783 784 /* Report to DMUB what features are supported by current driver */ 785 if (dmub->hw_funcs.enable_dmub_boot_options) 786 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 787 788 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 789 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 790 params->skip_panel_power_sequence); 791 792 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 793 dmub->hw_funcs.reset_release(dmub); 794 795 dmub->hw_init = true; 796 dmub->power_state = DMUB_POWER_STATE_D0; 797 798 return DMUB_STATUS_OK; 799 } 800 801 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 802 { 803 if (!dmub->sw_init) 804 return DMUB_STATUS_INVALID; 805 806 if (dmub->hw_funcs.reset) 807 dmub->hw_funcs.reset(dmub); 808 809 /* mailboxes have been reset in hw, so reset the sw state as well */ 810 dmub->inbox1_last_wptr = 0; 811 dmub->inbox1.rb.wrpt = 0; 812 dmub->inbox1.rb.rptr = 0; 813 dmub->inbox1.num_reported = 0; 814 dmub->inbox1.num_submitted = 0; 815 dmub->reg_inbox0.num_reported = 0; 816 dmub->reg_inbox0.num_submitted = 0; 817 dmub->reg_inbox0.is_pending = 0; 818 dmub->outbox0_rb.wrpt = 0; 819 dmub->outbox0_rb.rptr = 0; 820 dmub->outbox1_rb.wrpt = 0; 821 dmub->outbox1_rb.rptr = 0; 822 823 dmub->hw_init = false; 824 825 return DMUB_STATUS_OK; 826 } 827 828 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 829 const union dmub_rb_cmd *cmd) 830 { 831 if (!dmub->hw_init) 832 return DMUB_STATUS_INVALID; 833 834 if (dmub->power_state != DMUB_POWER_STATE_D0) 835 return DMUB_STATUS_POWER_STATE_D3; 836 837 if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 838 dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 839 return DMUB_STATUS_HW_FAILURE; 840 } 841 842 if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 843 dmub->inbox1.num_submitted++; 844 return DMUB_STATUS_OK; 845 } 846 847 return DMUB_STATUS_QUEUE_FULL; 848 } 849 850 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 851 { 852 struct dmub_rb flush_rb; 853 854 if (!dmub->hw_init) 855 return DMUB_STATUS_INVALID; 856 857 if (dmub->power_state != DMUB_POWER_STATE_D0) 858 return DMUB_STATUS_POWER_STATE_D3; 859 860 /** 861 * Read back all the queued commands to ensure that they've 862 * been flushed to framebuffer memory. Otherwise DMCUB might 863 * read back stale, fully invalid or partially invalid data. 864 */ 865 flush_rb = dmub->inbox1.rb; 866 flush_rb.rptr = dmub->inbox1_last_wptr; 867 dmub_rb_flush_pending(&flush_rb); 868 869 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 870 871 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 872 873 return DMUB_STATUS_OK; 874 } 875 876 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 877 { 878 if (!dmub->hw_funcs.is_hw_powered_up) 879 return true; 880 881 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 882 return false; 883 884 return true; 885 } 886 887 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 888 uint32_t timeout_us) 889 { 890 uint32_t i; 891 892 if (!dmub->hw_init) 893 return DMUB_STATUS_INVALID; 894 895 for (i = 0; i <= timeout_us; i += 100) { 896 if (dmub_srv_is_hw_pwr_up(dmub)) 897 return DMUB_STATUS_OK; 898 899 udelay(100); 900 } 901 902 return DMUB_STATUS_TIMEOUT; 903 } 904 905 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 906 uint32_t timeout_us) 907 { 908 uint32_t i; 909 bool hw_on = true; 910 911 if (!dmub->hw_init) 912 return DMUB_STATUS_INVALID; 913 914 for (i = 0; i <= timeout_us; i += 100) { 915 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 916 917 if (dmub->hw_funcs.is_hw_powered_up) 918 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 919 920 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 921 return DMUB_STATUS_OK; 922 923 udelay(100); 924 } 925 926 return DMUB_STATUS_TIMEOUT; 927 } 928 929 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 930 { 931 if (dmub->reg_inbox0.is_pending) { 932 dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 933 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 934 935 if (!dmub->reg_inbox0.is_pending) { 936 /* ack the rsp interrupt */ 937 if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 938 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 939 940 /* only update the reported count if commands aren't being batched */ 941 if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 942 dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 943 } 944 } 945 } 946 } 947 948 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 949 uint32_t timeout_us) 950 { 951 uint32_t i; 952 const uint32_t polling_interval_us = 1; 953 struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 954 struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 955 const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 956 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 957 958 if (!dmub->hw_init || 959 !dmub->hw_funcs.get_inbox1_wptr) 960 return DMUB_STATUS_INVALID; 961 962 for (i = 0; i <= timeout_us; i += polling_interval_us) { 963 scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 964 scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 965 966 scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 967 dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 968 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 969 970 if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 971 return DMUB_STATUS_HW_FAILURE; 972 973 /* check current HW state first, but use command submission vs reported as a fallback */ 974 if ((dmub_rb_empty(&scratch_inbox1.rb) || 975 inbox1->num_reported >= scratch_inbox1.num_submitted) && 976 (!scratch_reg_inbox0.is_pending || 977 reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 978 return DMUB_STATUS_OK; 979 980 udelay(polling_interval_us); 981 } 982 983 return DMUB_STATUS_TIMEOUT; 984 } 985 986 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 987 uint32_t timeout_us) 988 { 989 enum dmub_status status; 990 uint32_t i; 991 const uint32_t polling_interval_us = 1; 992 993 if (!dmub->hw_init) 994 return DMUB_STATUS_INVALID; 995 996 for (i = 0; i < timeout_us; i += polling_interval_us) { 997 status = dmub_srv_update_inbox_status(dmub); 998 999 if (status != DMUB_STATUS_OK) 1000 return status; 1001 1002 /* check for idle */ 1003 if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 1004 return DMUB_STATUS_OK; 1005 1006 udelay(polling_interval_us); 1007 } 1008 1009 return DMUB_STATUS_TIMEOUT; 1010 } 1011 1012 enum dmub_status 1013 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 1014 enum dmub_gpint_command command_code, 1015 uint16_t param, uint32_t timeout_us) 1016 { 1017 union dmub_gpint_data_register reg; 1018 uint32_t i; 1019 1020 if (!dmub->sw_init) 1021 return DMUB_STATUS_INVALID; 1022 1023 if (!dmub->hw_funcs.set_gpint) 1024 return DMUB_STATUS_INVALID; 1025 1026 if (!dmub->hw_funcs.is_gpint_acked) 1027 return DMUB_STATUS_INVALID; 1028 1029 reg.bits.status = 1; 1030 reg.bits.command_code = command_code; 1031 reg.bits.param = param; 1032 1033 dmub->hw_funcs.set_gpint(dmub, reg); 1034 1035 for (i = 0; i < timeout_us; ++i) { 1036 udelay(1); 1037 1038 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 1039 return DMUB_STATUS_OK; 1040 } 1041 1042 return DMUB_STATUS_TIMEOUT; 1043 } 1044 1045 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 1046 uint32_t *response) 1047 { 1048 *response = 0; 1049 1050 if (!dmub->sw_init) 1051 return DMUB_STATUS_INVALID; 1052 1053 if (!dmub->hw_funcs.get_gpint_response) 1054 return DMUB_STATUS_INVALID; 1055 1056 *response = dmub->hw_funcs.get_gpint_response(dmub); 1057 1058 return DMUB_STATUS_OK; 1059 } 1060 1061 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 1062 uint32_t *dataout) 1063 { 1064 *dataout = 0; 1065 1066 if (!dmub->sw_init) 1067 return DMUB_STATUS_INVALID; 1068 1069 if (!dmub->hw_funcs.get_gpint_dataout) 1070 return DMUB_STATUS_INVALID; 1071 1072 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 1073 1074 return DMUB_STATUS_OK; 1075 } 1076 1077 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1078 union dmub_fw_boot_status *status) 1079 { 1080 status->all = 0; 1081 1082 if (!dmub->sw_init) 1083 return DMUB_STATUS_INVALID; 1084 1085 if (dmub->hw_funcs.get_fw_status) 1086 *status = dmub->hw_funcs.get_fw_status(dmub); 1087 1088 return DMUB_STATUS_OK; 1089 } 1090 1091 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1092 union dmub_fw_boot_options *option) 1093 { 1094 option->all = 0; 1095 1096 if (!dmub->sw_init) 1097 return DMUB_STATUS_INVALID; 1098 1099 if (dmub->hw_funcs.get_fw_boot_option) 1100 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1101 1102 return DMUB_STATUS_OK; 1103 } 1104 1105 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1106 bool skip) 1107 { 1108 if (!dmub->sw_init) 1109 return DMUB_STATUS_INVALID; 1110 1111 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1112 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1113 1114 return DMUB_STATUS_OK; 1115 } 1116 1117 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1118 void *entry) 1119 { 1120 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1121 uint64_t *dst = (uint64_t *)entry; 1122 uint8_t i; 1123 uint8_t loop_count; 1124 1125 if (rb->rptr == rb->wrpt) 1126 return false; 1127 1128 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1129 // copying data 1130 for (i = 0; i < loop_count; i++) 1131 *dst++ = *src++; 1132 1133 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1134 1135 rb->rptr %= rb->capacity; 1136 1137 return true; 1138 } 1139 1140 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1141 { 1142 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1143 1144 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1145 } 1146 1147 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1148 { 1149 if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1150 return false; 1151 dmub->hw_funcs.get_diagnostic_data(dmub); 1152 return true; 1153 } 1154 1155 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1156 { 1157 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1158 return false; 1159 1160 return dmub->hw_funcs.should_detect(dmub); 1161 } 1162 1163 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1164 { 1165 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1166 return DMUB_STATUS_INVALID; 1167 1168 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1169 return DMUB_STATUS_OK; 1170 } 1171 1172 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1173 { 1174 uint32_t i = 0; 1175 uint32_t ack = 0; 1176 1177 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1178 return DMUB_STATUS_INVALID; 1179 1180 for (i = 0; i <= timeout_us; i++) { 1181 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1182 if (ack) 1183 return DMUB_STATUS_OK; 1184 udelay(1); 1185 } 1186 return DMUB_STATUS_TIMEOUT; 1187 } 1188 1189 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1190 union dmub_inbox0_data_register data) 1191 { 1192 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1193 return DMUB_STATUS_INVALID; 1194 1195 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1196 return DMUB_STATUS_OK; 1197 } 1198 1199 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1200 { 1201 if (dmub->hw_funcs.subvp_save_surf_addr) { 1202 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1203 addr, 1204 subvp_index); 1205 } 1206 } 1207 1208 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1209 { 1210 if (!dmub || !dmub->hw_init) 1211 return; 1212 1213 dmub->power_state = dmub_srv_power_state; 1214 } 1215 1216 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1217 { 1218 uint32_t num_pending = 0; 1219 1220 if (!dmub->hw_init) 1221 return DMUB_STATUS_INVALID; 1222 1223 if (dmub->power_state != DMUB_POWER_STATE_D0) 1224 return DMUB_STATUS_POWER_STATE_D3; 1225 1226 if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1227 !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1228 return DMUB_STATUS_INVALID; 1229 1230 if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1231 num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1232 else 1233 /* num_submitted wrapped */ 1234 num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1235 (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1236 1237 if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1238 return DMUB_STATUS_QUEUE_FULL; 1239 1240 /* clear last rsp ack and send message */ 1241 dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1242 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1243 1244 dmub->reg_inbox0.num_submitted++; 1245 dmub->reg_inbox0.is_pending = true; 1246 dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1247 1248 return DMUB_STATUS_OK; 1249 } 1250 1251 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1252 union dmub_rb_cmd *cmd_rsp) 1253 { 1254 if (dmub) { 1255 if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1256 dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1257 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1258 } else { 1259 dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1260 } 1261 } 1262 } 1263 1264 static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1265 { 1266 if (!dmub || !dmub->sw_init) 1267 return DMUB_STATUS_INVALID; 1268 1269 dmub->reg_inbox0.is_pending = 0; 1270 dmub->reg_inbox0.is_multi_pending = 0; 1271 1272 return DMUB_STATUS_OK; 1273 } 1274 1275 static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1276 { 1277 if (!dmub->sw_init) 1278 return DMUB_STATUS_INVALID; 1279 1280 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1281 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1282 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1283 1284 if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1285 return DMUB_STATUS_HW_FAILURE; 1286 } else { 1287 dmub->inbox1.rb.rptr = rptr; 1288 dmub->inbox1.rb.wrpt = wptr; 1289 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1290 } 1291 } 1292 1293 return DMUB_STATUS_OK; 1294 } 1295 1296 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1297 { 1298 enum dmub_status status; 1299 1300 status = dmub_srv_sync_reg_inbox0(dmub); 1301 if (status != DMUB_STATUS_OK) 1302 return status; 1303 1304 status = dmub_srv_sync_inbox1(dmub); 1305 if (status != DMUB_STATUS_OK) 1306 return status; 1307 1308 return DMUB_STATUS_OK; 1309 } 1310 1311 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1312 uint32_t timeout_us, 1313 uint32_t num_free_required) 1314 { 1315 enum dmub_status status; 1316 uint32_t i; 1317 const uint32_t polling_interval_us = 1; 1318 1319 if (!dmub->hw_init) 1320 return DMUB_STATUS_INVALID; 1321 1322 for (i = 0; i < timeout_us; i += polling_interval_us) { 1323 status = dmub_srv_update_inbox_status(dmub); 1324 1325 if (status != DMUB_STATUS_OK) 1326 return status; 1327 1328 /* check for space in inbox1 */ 1329 if (dmub_rb_num_free(&dmub->inbox1.rb) >= num_free_required) 1330 return DMUB_STATUS_OK; 1331 1332 udelay(polling_interval_us); 1333 } 1334 1335 return DMUB_STATUS_TIMEOUT; 1336 } 1337 1338 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) 1339 { 1340 uint32_t rptr; 1341 1342 if (!dmub->hw_init) 1343 return DMUB_STATUS_INVALID; 1344 1345 if (dmub->power_state != DMUB_POWER_STATE_D0) 1346 return DMUB_STATUS_POWER_STATE_D3; 1347 1348 /* update inbox1 state */ 1349 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1350 1351 if (rptr > dmub->inbox1.rb.capacity) 1352 return DMUB_STATUS_HW_FAILURE; 1353 1354 if (dmub->inbox1.rb.rptr > rptr) { 1355 /* rb wrapped */ 1356 dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1357 } else { 1358 dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1359 } 1360 dmub->inbox1.rb.rptr = rptr; 1361 1362 /* update reg_inbox0 */ 1363 dmub_srv_update_reg_inbox0_status(dmub); 1364 1365 return DMUB_STATUS_OK; 1366 } 1367