1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn401.h" 42 #include "os_types.h" 43 /* 44 * Note: the DMUB service is standalone. No additional headers should be 45 * added below or above this line unless they reside within the DMUB 46 * folder. 47 */ 48 49 /* Alignment for framebuffer memory. */ 50 #define DMUB_FB_ALIGNMENT (1024 * 1024) 51 52 /* Stack size. */ 53 #define DMUB_STACK_SIZE (128 * 1024) 54 55 /* Context size. */ 56 #define DMUB_CONTEXT_SIZE (512 * 1024) 57 58 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 59 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 60 61 /* Default state size if meta is absent. */ 62 #define DMUB_FW_STATE_SIZE (64 * 1024) 63 64 /* Default scratch mem size. */ 65 #define DMUB_SCRATCH_MEM_SIZE (1024) 66 67 /* Number of windows in use. */ 68 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 69 /* Base addresses. */ 70 71 #define DMUB_CW0_BASE (0x60000000) 72 #define DMUB_CW1_BASE (0x61000000) 73 #define DMUB_CW3_BASE (0x63000000) 74 #define DMUB_CW4_BASE (0x64000000) 75 #define DMUB_CW5_BASE (0x65000000) 76 #define DMUB_CW6_BASE (0x66000000) 77 78 #define DMUB_REGION5_BASE (0xA0000000) 79 #define DMUB_REGION6_BASE (0xC0000000) 80 81 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 82 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 83 84 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 85 { 86 return (val + factor - 1) / factor * factor; 87 } 88 89 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 90 { 91 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 92 uint8_t buf[64]; 93 uint32_t pos, end; 94 95 /** 96 * Read 64-byte chunks since we don't want to store a 97 * large temporary buffer for this purpose. 98 */ 99 end = fb->size / sizeof(buf) * sizeof(buf); 100 101 for (pos = 0; pos < end; pos += sizeof(buf)) 102 dmub_memcpy(buf, base + pos, sizeof(buf)); 103 104 /* Read anything leftover into the buffer. */ 105 if (end < fb->size) 106 dmub_memcpy(buf, base + pos, fb->size - end); 107 } 108 109 static const struct dmub_fw_meta_info * 110 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 111 { 112 const union dmub_fw_meta *meta; 113 114 if (!blob || !blob_size) 115 return NULL; 116 117 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 118 return NULL; 119 120 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 121 sizeof(union dmub_fw_meta)); 122 123 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 124 return NULL; 125 126 return &meta->info; 127 } 128 129 static const struct dmub_fw_meta_info * 130 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 131 { 132 const struct dmub_fw_meta_info *info = NULL; 133 134 if (params->fw_bss_data && params->bss_data_size) { 135 /* Legacy metadata region. */ 136 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 137 params->bss_data_size, 138 DMUB_FW_META_OFFSET); 139 } else if (params->fw_inst_const && params->inst_const_size) { 140 /* Combined metadata region - can be aligned to 16-bytes. */ 141 uint32_t i; 142 143 for (i = 0; i < 16; ++i) { 144 info = dmub_get_fw_meta_info_from_blob( 145 params->fw_inst_const, params->inst_const_size, i); 146 147 if (info) 148 break; 149 } 150 } 151 152 return info; 153 } 154 155 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 156 { 157 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 158 159 switch (asic) { 160 case DMUB_ASIC_DCN20: 161 case DMUB_ASIC_DCN21: 162 case DMUB_ASIC_DCN30: 163 case DMUB_ASIC_DCN301: 164 case DMUB_ASIC_DCN302: 165 case DMUB_ASIC_DCN303: 166 dmub->regs = &dmub_srv_dcn20_regs; 167 168 funcs->reset = dmub_dcn20_reset; 169 funcs->reset_release = dmub_dcn20_reset_release; 170 funcs->backdoor_load = dmub_dcn20_backdoor_load; 171 funcs->setup_windows = dmub_dcn20_setup_windows; 172 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 173 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 174 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 175 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 176 funcs->is_supported = dmub_dcn20_is_supported; 177 funcs->is_hw_init = dmub_dcn20_is_hw_init; 178 funcs->set_gpint = dmub_dcn20_set_gpint; 179 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 180 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 181 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 182 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 183 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 184 funcs->get_current_time = dmub_dcn20_get_current_time; 185 186 // Out mailbox register access functions for RN and above 187 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 188 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 189 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 190 191 //outbox0 call stacks 192 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 193 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 194 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 195 196 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 197 198 if (asic == DMUB_ASIC_DCN21) 199 dmub->regs = &dmub_srv_dcn21_regs; 200 201 if (asic == DMUB_ASIC_DCN30) { 202 dmub->regs = &dmub_srv_dcn30_regs; 203 204 funcs->backdoor_load = dmub_dcn30_backdoor_load; 205 funcs->setup_windows = dmub_dcn30_setup_windows; 206 } 207 if (asic == DMUB_ASIC_DCN301) { 208 dmub->regs = &dmub_srv_dcn301_regs; 209 210 funcs->backdoor_load = dmub_dcn30_backdoor_load; 211 funcs->setup_windows = dmub_dcn30_setup_windows; 212 } 213 if (asic == DMUB_ASIC_DCN302) { 214 dmub->regs = &dmub_srv_dcn302_regs; 215 216 funcs->backdoor_load = dmub_dcn30_backdoor_load; 217 funcs->setup_windows = dmub_dcn30_setup_windows; 218 } 219 if (asic == DMUB_ASIC_DCN303) { 220 dmub->regs = &dmub_srv_dcn303_regs; 221 222 funcs->backdoor_load = dmub_dcn30_backdoor_load; 223 funcs->setup_windows = dmub_dcn30_setup_windows; 224 } 225 break; 226 227 case DMUB_ASIC_DCN31: 228 case DMUB_ASIC_DCN31B: 229 case DMUB_ASIC_DCN314: 230 case DMUB_ASIC_DCN315: 231 case DMUB_ASIC_DCN316: 232 if (asic == DMUB_ASIC_DCN314) { 233 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 234 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 235 } else if (asic == DMUB_ASIC_DCN315) { 236 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 237 } else if (asic == DMUB_ASIC_DCN316) { 238 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 239 } else { 240 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 241 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 242 } 243 funcs->reset = dmub_dcn31_reset; 244 funcs->reset_release = dmub_dcn31_reset_release; 245 funcs->backdoor_load = dmub_dcn31_backdoor_load; 246 funcs->setup_windows = dmub_dcn31_setup_windows; 247 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 248 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 249 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 250 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 251 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 252 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 253 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 254 funcs->is_supported = dmub_dcn31_is_supported; 255 funcs->is_hw_init = dmub_dcn31_is_hw_init; 256 funcs->set_gpint = dmub_dcn31_set_gpint; 257 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 258 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 259 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 260 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 261 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 262 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 263 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 264 //outbox0 call stacks 265 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 266 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 267 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 268 269 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 270 funcs->should_detect = dmub_dcn31_should_detect; 271 funcs->get_current_time = dmub_dcn31_get_current_time; 272 273 break; 274 275 case DMUB_ASIC_DCN32: 276 case DMUB_ASIC_DCN321: 277 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 278 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 279 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 280 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 281 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 282 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 283 funcs->reset = dmub_dcn32_reset; 284 funcs->reset_release = dmub_dcn32_reset_release; 285 funcs->backdoor_load = dmub_dcn32_backdoor_load; 286 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 287 funcs->setup_windows = dmub_dcn32_setup_windows; 288 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 289 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 290 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 291 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 292 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 293 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 294 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 295 funcs->is_supported = dmub_dcn32_is_supported; 296 funcs->is_hw_init = dmub_dcn32_is_hw_init; 297 funcs->set_gpint = dmub_dcn32_set_gpint; 298 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 299 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 300 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 301 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 302 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 303 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 304 305 /* outbox0 call stacks */ 306 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 307 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 308 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 309 funcs->get_current_time = dmub_dcn32_get_current_time; 310 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 311 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 312 313 break; 314 315 case DMUB_ASIC_DCN35: 316 case DMUB_ASIC_DCN351: 317 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 318 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 319 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 320 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 321 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 322 funcs->reset = dmub_dcn35_reset; 323 funcs->reset_release = dmub_dcn35_reset_release; 324 funcs->backdoor_load = dmub_dcn35_backdoor_load; 325 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 326 funcs->setup_windows = dmub_dcn35_setup_windows; 327 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 328 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 329 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 330 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 331 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 332 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 333 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 334 funcs->is_supported = dmub_dcn35_is_supported; 335 funcs->is_hw_init = dmub_dcn35_is_hw_init; 336 funcs->set_gpint = dmub_dcn35_set_gpint; 337 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 338 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 339 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 340 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 341 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 342 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 343 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 344 //outbox0 call stacks 345 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 346 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 347 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 348 349 funcs->get_current_time = dmub_dcn35_get_current_time; 350 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 351 352 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 353 if (asic == DMUB_ASIC_DCN351) 354 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 355 356 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 357 funcs->should_detect = dmub_dcn35_should_detect; 358 break; 359 360 case DMUB_ASIC_DCN401: 361 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 362 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 363 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 364 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 365 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 366 funcs->reset = dmub_dcn401_reset; 367 funcs->reset_release = dmub_dcn401_reset_release; 368 funcs->backdoor_load = dmub_dcn401_backdoor_load; 369 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 370 funcs->setup_windows = dmub_dcn401_setup_windows; 371 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 372 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 373 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 374 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 375 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 376 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 377 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 378 funcs->is_supported = dmub_dcn401_is_supported; 379 funcs->is_hw_init = dmub_dcn401_is_hw_init; 380 funcs->set_gpint = dmub_dcn401_set_gpint; 381 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 382 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 383 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 384 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 385 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 386 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 387 //outbox0 call stacks 388 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 389 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 390 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 391 392 funcs->get_current_time = dmub_dcn401_get_current_time; 393 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 394 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 395 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 396 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 397 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 398 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 399 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 400 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 401 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 402 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 403 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 404 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 405 break; 406 default: 407 return false; 408 } 409 410 return true; 411 } 412 413 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 414 const struct dmub_srv_create_params *params) 415 { 416 enum dmub_status status = DMUB_STATUS_OK; 417 418 dmub_memset(dmub, 0, sizeof(*dmub)); 419 420 dmub->funcs = params->funcs; 421 dmub->user_ctx = params->user_ctx; 422 dmub->asic = params->asic; 423 dmub->fw_version = params->fw_version; 424 dmub->is_virtual = params->is_virtual; 425 426 /* Setup asic dependent hardware funcs. */ 427 if (!dmub_srv_hw_setup(dmub, params->asic)) { 428 status = DMUB_STATUS_INVALID; 429 goto cleanup; 430 } 431 432 /* Override (some) hardware funcs based on user params. */ 433 if (params->hw_funcs) { 434 if (params->hw_funcs->emul_get_inbox1_rptr) 435 dmub->hw_funcs.emul_get_inbox1_rptr = 436 params->hw_funcs->emul_get_inbox1_rptr; 437 438 if (params->hw_funcs->emul_set_inbox1_wptr) 439 dmub->hw_funcs.emul_set_inbox1_wptr = 440 params->hw_funcs->emul_set_inbox1_wptr; 441 442 if (params->hw_funcs->is_supported) 443 dmub->hw_funcs.is_supported = 444 params->hw_funcs->is_supported; 445 } 446 447 /* Sanity checks for required hw func pointers. */ 448 if (!dmub->hw_funcs.get_inbox1_rptr || 449 !dmub->hw_funcs.set_inbox1_wptr) { 450 status = DMUB_STATUS_INVALID; 451 goto cleanup; 452 } 453 454 cleanup: 455 if (status == DMUB_STATUS_OK) 456 dmub->sw_init = true; 457 else 458 dmub_srv_destroy(dmub); 459 460 return status; 461 } 462 463 void dmub_srv_destroy(struct dmub_srv *dmub) 464 { 465 dmub_memset(dmub, 0, sizeof(*dmub)); 466 } 467 468 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 469 struct dmub_srv_region_info *out, 470 const uint32_t *window_sizes, 471 enum dmub_window_memory_type memory_type) 472 { 473 uint32_t i, top = 0; 474 475 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 476 if (params->window_memory_type[i] == memory_type) { 477 struct dmub_region *region = &out->regions[i]; 478 479 region->base = dmub_align(top, 256); 480 region->top = region->base + dmub_align(window_sizes[i], 64); 481 top = region->top; 482 } 483 } 484 485 return dmub_align(top, 4096); 486 } 487 488 enum dmub_status 489 dmub_srv_calc_region_info(struct dmub_srv *dmub, 490 const struct dmub_srv_region_params *params, 491 struct dmub_srv_region_info *out) 492 { 493 const struct dmub_fw_meta_info *fw_info; 494 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 495 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 496 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 497 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 498 499 if (!dmub->sw_init) 500 return DMUB_STATUS_INVALID; 501 502 memset(out, 0, sizeof(*out)); 503 memset(window_sizes, 0, sizeof(window_sizes)); 504 505 out->num_regions = DMUB_NUM_WINDOWS; 506 507 fw_info = dmub_get_fw_meta_info(params); 508 509 if (fw_info) { 510 memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); 511 512 fw_state_size = fw_info->fw_region_size; 513 trace_buffer_size = fw_info->trace_buffer_size; 514 shared_state_size = fw_info->shared_state_size; 515 516 /** 517 * If DM didn't fill in a version, then fill it in based on 518 * the firmware meta now that we have it. 519 * 520 * TODO: Make it easier for driver to extract this out to 521 * pass during creation. 522 */ 523 if (dmub->fw_version == 0) 524 dmub->fw_version = fw_info->fw_version; 525 } 526 527 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 528 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 529 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 530 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 531 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 532 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 533 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 534 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE; 535 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 536 537 out->fb_size = 538 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 539 540 out->gart_size = 541 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 542 543 return DMUB_STATUS_OK; 544 } 545 546 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 547 const struct dmub_srv_memory_params *params, 548 struct dmub_srv_fb_info *out) 549 { 550 uint32_t i; 551 552 if (!dmub->sw_init) 553 return DMUB_STATUS_INVALID; 554 555 memset(out, 0, sizeof(*out)); 556 557 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 558 return DMUB_STATUS_INVALID; 559 560 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 561 const struct dmub_region *reg = 562 ¶ms->region_info->regions[i]; 563 564 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 565 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 566 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 567 } else { 568 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 569 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 570 } 571 572 out->fb[i].size = reg->top - reg->base; 573 } 574 575 out->num_fb = DMUB_NUM_WINDOWS; 576 577 return DMUB_STATUS_OK; 578 } 579 580 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 581 bool *is_supported) 582 { 583 *is_supported = false; 584 585 if (!dmub->sw_init) 586 return DMUB_STATUS_INVALID; 587 588 if (dmub->hw_funcs.is_supported) 589 *is_supported = dmub->hw_funcs.is_supported(dmub); 590 591 return DMUB_STATUS_OK; 592 } 593 594 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 595 { 596 *is_hw_init = false; 597 598 if (!dmub->sw_init) 599 return DMUB_STATUS_INVALID; 600 601 if (!dmub->hw_init) 602 return DMUB_STATUS_OK; 603 604 if (dmub->hw_funcs.is_hw_init) 605 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 606 607 return DMUB_STATUS_OK; 608 } 609 610 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 611 const struct dmub_srv_hw_params *params) 612 { 613 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 614 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 615 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 616 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 617 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 618 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 619 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 620 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 621 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 622 623 struct dmub_rb_init_params rb_params, outbox0_rb_params; 624 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 625 struct dmub_region inbox1, outbox1, outbox0; 626 627 if (!dmub->sw_init) 628 return DMUB_STATUS_INVALID; 629 630 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 631 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 632 ASSERT(0); 633 return DMUB_STATUS_INVALID; 634 } 635 636 dmub->fb_base = params->fb_base; 637 dmub->fb_offset = params->fb_offset; 638 dmub->psp_version = params->psp_version; 639 640 if (dmub->hw_funcs.reset) 641 dmub->hw_funcs.reset(dmub); 642 643 /* reset the cache of the last wptr as well now that hw is reset */ 644 dmub->inbox1_last_wptr = 0; 645 646 cw0.offset.quad_part = inst_fb->gpu_addr; 647 cw0.region.base = DMUB_CW0_BASE; 648 cw0.region.top = cw0.region.base + inst_fb->size - 1; 649 650 cw1.offset.quad_part = stack_fb->gpu_addr; 651 cw1.region.base = DMUB_CW1_BASE; 652 cw1.region.top = cw1.region.base + stack_fb->size - 1; 653 654 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 655 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 656 657 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 658 /** 659 * Read back all the instruction memory so we don't hang the 660 * DMCUB when backdoor loading if the write from x86 hasn't been 661 * flushed yet. This only occurs in backdoor loading. 662 */ 663 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 664 dmub_flush_buffer_mem(inst_fb); 665 666 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 667 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 668 else 669 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 670 } 671 672 cw2.offset.quad_part = data_fb->gpu_addr; 673 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 674 cw2.region.top = cw2.region.base + data_fb->size; 675 676 cw3.offset.quad_part = bios_fb->gpu_addr; 677 cw3.region.base = DMUB_CW3_BASE; 678 cw3.region.top = cw3.region.base + bios_fb->size; 679 680 cw4.offset.quad_part = mail_fb->gpu_addr; 681 cw4.region.base = DMUB_CW4_BASE; 682 cw4.region.top = cw4.region.base + mail_fb->size; 683 684 /** 685 * Doubled the mailbox region to accomodate inbox and outbox. 686 * Note: Currently, currently total mailbox size is 16KB. It is split 687 * equally into 8KB between inbox and outbox. If this config is 688 * changed, then uncached base address configuration of outbox1 689 * has to be updated in funcs->setup_out_mailbox. 690 */ 691 inbox1.base = cw4.region.base; 692 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 693 outbox1.base = inbox1.top; 694 outbox1.top = cw4.region.top; 695 696 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 697 cw5.region.base = DMUB_CW5_BASE; 698 cw5.region.top = cw5.region.base + tracebuff_fb->size; 699 700 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 701 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 702 703 cw6.offset.quad_part = fw_state_fb->gpu_addr; 704 cw6.region.base = DMUB_CW6_BASE; 705 cw6.region.top = cw6.region.base + fw_state_fb->size; 706 707 dmub->fw_state = fw_state_fb->cpu_addr; 708 709 region6.offset.quad_part = shared_state_fb->gpu_addr; 710 region6.region.base = DMUB_CW6_BASE; 711 region6.region.top = region6.region.base + shared_state_fb->size; 712 713 dmub->shared_state = shared_state_fb->cpu_addr; 714 715 dmub->scratch_mem_fb = *scratch_mem_fb; 716 717 if (dmub->hw_funcs.setup_windows) 718 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 719 720 if (dmub->hw_funcs.setup_outbox0) 721 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 722 723 if (dmub->hw_funcs.setup_mailbox) 724 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 725 if (dmub->hw_funcs.setup_out_mailbox) 726 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 727 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 728 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 729 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 730 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 731 732 dmub_memset(&rb_params, 0, sizeof(rb_params)); 733 rb_params.ctx = dmub; 734 rb_params.base_address = mail_fb->cpu_addr; 735 rb_params.capacity = DMUB_RB_SIZE; 736 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 737 738 // Initialize outbox1 ring buffer 739 rb_params.ctx = dmub; 740 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 741 rb_params.capacity = DMUB_RB_SIZE; 742 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 743 744 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 745 outbox0_rb_params.ctx = dmub; 746 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 747 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 748 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 749 750 /* Report to DMUB what features are supported by current driver */ 751 if (dmub->hw_funcs.enable_dmub_boot_options) 752 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 753 754 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 755 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 756 params->skip_panel_power_sequence); 757 758 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 759 dmub->hw_funcs.reset_release(dmub); 760 761 dmub->hw_init = true; 762 dmub->power_state = DMUB_POWER_STATE_D0; 763 764 return DMUB_STATUS_OK; 765 } 766 767 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 768 { 769 if (!dmub->sw_init) 770 return DMUB_STATUS_INVALID; 771 772 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 773 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 774 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 775 776 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { 777 return DMUB_STATUS_HW_FAILURE; 778 } else { 779 dmub->inbox1_rb.rptr = rptr; 780 dmub->inbox1_rb.wrpt = wptr; 781 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 782 } 783 } 784 785 return DMUB_STATUS_OK; 786 } 787 788 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 789 { 790 if (!dmub->sw_init) 791 return DMUB_STATUS_INVALID; 792 793 if (dmub->hw_funcs.reset) 794 dmub->hw_funcs.reset(dmub); 795 796 /* mailboxes have been reset in hw, so reset the sw state as well */ 797 dmub->inbox1_last_wptr = 0; 798 dmub->inbox1_rb.wrpt = 0; 799 dmub->inbox1_rb.rptr = 0; 800 dmub->outbox0_rb.wrpt = 0; 801 dmub->outbox0_rb.rptr = 0; 802 dmub->outbox1_rb.wrpt = 0; 803 dmub->outbox1_rb.rptr = 0; 804 805 dmub->hw_init = false; 806 807 return DMUB_STATUS_OK; 808 } 809 810 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 811 const union dmub_rb_cmd *cmd) 812 { 813 if (!dmub->hw_init) 814 return DMUB_STATUS_INVALID; 815 816 if (dmub->power_state != DMUB_POWER_STATE_D0) 817 return DMUB_STATUS_POWER_STATE_D3; 818 819 if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || 820 dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) { 821 return DMUB_STATUS_HW_FAILURE; 822 } 823 824 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 825 return DMUB_STATUS_OK; 826 827 return DMUB_STATUS_QUEUE_FULL; 828 } 829 830 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 831 { 832 struct dmub_rb flush_rb; 833 834 if (!dmub->hw_init) 835 return DMUB_STATUS_INVALID; 836 837 if (dmub->power_state != DMUB_POWER_STATE_D0) 838 return DMUB_STATUS_POWER_STATE_D3; 839 840 /** 841 * Read back all the queued commands to ensure that they've 842 * been flushed to framebuffer memory. Otherwise DMCUB might 843 * read back stale, fully invalid or partially invalid data. 844 */ 845 flush_rb = dmub->inbox1_rb; 846 flush_rb.rptr = dmub->inbox1_last_wptr; 847 dmub_rb_flush_pending(&flush_rb); 848 849 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 850 851 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 852 853 return DMUB_STATUS_OK; 854 } 855 856 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 857 { 858 if (!dmub->hw_funcs.is_hw_powered_up) 859 return true; 860 861 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 862 return false; 863 864 return true; 865 } 866 867 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 868 uint32_t timeout_us) 869 { 870 uint32_t i; 871 872 if (!dmub->hw_init) 873 return DMUB_STATUS_INVALID; 874 875 for (i = 0; i <= timeout_us; i += 100) { 876 if (dmub_srv_is_hw_pwr_up(dmub)) 877 return DMUB_STATUS_OK; 878 879 udelay(100); 880 } 881 882 return DMUB_STATUS_TIMEOUT; 883 } 884 885 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 886 uint32_t timeout_us) 887 { 888 uint32_t i; 889 bool hw_on = true; 890 891 if (!dmub->hw_init) 892 return DMUB_STATUS_INVALID; 893 894 for (i = 0; i <= timeout_us; i += 100) { 895 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 896 897 if (dmub->hw_funcs.is_hw_powered_up) 898 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 899 900 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 901 return DMUB_STATUS_OK; 902 903 udelay(100); 904 } 905 906 return DMUB_STATUS_TIMEOUT; 907 } 908 909 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 910 uint32_t timeout_us) 911 { 912 uint32_t i, rptr; 913 914 if (!dmub->hw_init) 915 return DMUB_STATUS_INVALID; 916 917 for (i = 0; i <= timeout_us; ++i) { 918 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 919 920 if (rptr > dmub->inbox1_rb.capacity) 921 return DMUB_STATUS_HW_FAILURE; 922 923 dmub->inbox1_rb.rptr = rptr; 924 925 if (dmub_rb_empty(&dmub->inbox1_rb)) 926 return DMUB_STATUS_OK; 927 928 udelay(1); 929 } 930 931 return DMUB_STATUS_TIMEOUT; 932 } 933 934 enum dmub_status 935 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 936 enum dmub_gpint_command command_code, 937 uint16_t param, uint32_t timeout_us) 938 { 939 union dmub_gpint_data_register reg; 940 uint32_t i; 941 942 if (!dmub->sw_init) 943 return DMUB_STATUS_INVALID; 944 945 if (!dmub->hw_funcs.set_gpint) 946 return DMUB_STATUS_INVALID; 947 948 if (!dmub->hw_funcs.is_gpint_acked) 949 return DMUB_STATUS_INVALID; 950 951 reg.bits.status = 1; 952 reg.bits.command_code = command_code; 953 reg.bits.param = param; 954 955 dmub->hw_funcs.set_gpint(dmub, reg); 956 957 for (i = 0; i < timeout_us; ++i) { 958 udelay(1); 959 960 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 961 return DMUB_STATUS_OK; 962 } 963 964 return DMUB_STATUS_TIMEOUT; 965 } 966 967 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 968 uint32_t *response) 969 { 970 *response = 0; 971 972 if (!dmub->sw_init) 973 return DMUB_STATUS_INVALID; 974 975 if (!dmub->hw_funcs.get_gpint_response) 976 return DMUB_STATUS_INVALID; 977 978 *response = dmub->hw_funcs.get_gpint_response(dmub); 979 980 return DMUB_STATUS_OK; 981 } 982 983 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 984 uint32_t *dataout) 985 { 986 *dataout = 0; 987 988 if (!dmub->sw_init) 989 return DMUB_STATUS_INVALID; 990 991 if (!dmub->hw_funcs.get_gpint_dataout) 992 return DMUB_STATUS_INVALID; 993 994 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 995 996 return DMUB_STATUS_OK; 997 } 998 999 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1000 union dmub_fw_boot_status *status) 1001 { 1002 status->all = 0; 1003 1004 if (!dmub->sw_init) 1005 return DMUB_STATUS_INVALID; 1006 1007 if (dmub->hw_funcs.get_fw_status) 1008 *status = dmub->hw_funcs.get_fw_status(dmub); 1009 1010 return DMUB_STATUS_OK; 1011 } 1012 1013 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1014 union dmub_fw_boot_options *option) 1015 { 1016 option->all = 0; 1017 1018 if (!dmub->sw_init) 1019 return DMUB_STATUS_INVALID; 1020 1021 if (dmub->hw_funcs.get_fw_boot_option) 1022 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1023 1024 return DMUB_STATUS_OK; 1025 } 1026 1027 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1028 bool skip) 1029 { 1030 if (!dmub->sw_init) 1031 return DMUB_STATUS_INVALID; 1032 1033 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1034 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1035 1036 return DMUB_STATUS_OK; 1037 } 1038 1039 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 1040 union dmub_rb_cmd *cmd) 1041 { 1042 enum dmub_status status = DMUB_STATUS_OK; 1043 1044 // Queue command 1045 status = dmub_srv_cmd_queue(dmub, cmd); 1046 1047 if (status != DMUB_STATUS_OK) 1048 return status; 1049 1050 // Execute command 1051 status = dmub_srv_cmd_execute(dmub); 1052 1053 if (status != DMUB_STATUS_OK) 1054 return status; 1055 1056 // Wait for DMUB to process command 1057 status = dmub_srv_wait_for_idle(dmub, 100000); 1058 1059 if (status != DMUB_STATUS_OK) 1060 return status; 1061 1062 // Copy data back from ring buffer into command 1063 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 1064 1065 return status; 1066 } 1067 1068 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1069 void *entry) 1070 { 1071 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1072 uint64_t *dst = (uint64_t *)entry; 1073 uint8_t i; 1074 uint8_t loop_count; 1075 1076 if (rb->rptr == rb->wrpt) 1077 return false; 1078 1079 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1080 // copying data 1081 for (i = 0; i < loop_count; i++) 1082 *dst++ = *src++; 1083 1084 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1085 1086 rb->rptr %= rb->capacity; 1087 1088 return true; 1089 } 1090 1091 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1092 { 1093 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1094 1095 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1096 } 1097 1098 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 1099 { 1100 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 1101 return false; 1102 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 1103 return true; 1104 } 1105 1106 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1107 { 1108 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1109 return false; 1110 1111 return dmub->hw_funcs.should_detect(dmub); 1112 } 1113 1114 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1115 { 1116 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1117 return DMUB_STATUS_INVALID; 1118 1119 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1120 return DMUB_STATUS_OK; 1121 } 1122 1123 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1124 { 1125 uint32_t i = 0; 1126 uint32_t ack = 0; 1127 1128 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1129 return DMUB_STATUS_INVALID; 1130 1131 for (i = 0; i <= timeout_us; i++) { 1132 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1133 if (ack) 1134 return DMUB_STATUS_OK; 1135 udelay(1); 1136 } 1137 return DMUB_STATUS_TIMEOUT; 1138 } 1139 1140 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1141 union dmub_inbox0_data_register data) 1142 { 1143 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1144 return DMUB_STATUS_INVALID; 1145 1146 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1147 return DMUB_STATUS_OK; 1148 } 1149 1150 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1151 { 1152 if (dmub->hw_funcs.subvp_save_surf_addr) { 1153 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1154 addr, 1155 subvp_index); 1156 } 1157 } 1158 1159 enum dmub_status dmub_srv_send_reg_inbox0_cmd( 1160 struct dmub_srv *dmub, 1161 union dmub_rb_cmd *cmd, 1162 bool with_reply, uint32_t timeout_us) 1163 { 1164 uint32_t rsp_ready = 0; 1165 uint32_t i; 1166 1167 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1168 1169 for (i = 0; i < timeout_us; i++) { 1170 rsp_ready = dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1171 if (rsp_ready) 1172 break; 1173 udelay(1); 1174 } 1175 if (rsp_ready == 0) 1176 return DMUB_STATUS_TIMEOUT; 1177 1178 if (with_reply) 1179 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd); 1180 1181 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 1182 1183 /* wait for rsp int status is cleared to initial state before exit */ 1184 for (; i <= timeout_us; i++) { 1185 rsp_ready = dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1186 if (rsp_ready == 0) 1187 break; 1188 udelay(1); 1189 } 1190 ASSERT(rsp_ready == 0); 1191 1192 return DMUB_STATUS_OK; 1193 } 1194 1195 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1196 { 1197 if (!dmub || !dmub->hw_init) 1198 return; 1199 1200 dmub->power_state = dmub_srv_power_state; 1201 } 1202