1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "os_types.h" 41 /* 42 * Note: the DMUB service is standalone. No additional headers should be 43 * added below or above this line unless they reside within the DMUB 44 * folder. 45 */ 46 47 /* Alignment for framebuffer memory. */ 48 #define DMUB_FB_ALIGNMENT (1024 * 1024) 49 50 /* Stack size. */ 51 #define DMUB_STACK_SIZE (128 * 1024) 52 53 /* Context size. */ 54 #define DMUB_CONTEXT_SIZE (512 * 1024) 55 56 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 57 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 58 59 /* Default state size if meta is absent. */ 60 #define DMUB_FW_STATE_SIZE (64 * 1024) 61 62 /* Default tracebuffer size if meta is absent. */ 63 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 64 65 66 /* Default scratch mem size. */ 67 #define DMUB_SCRATCH_MEM_SIZE (256) 68 69 /* Number of windows in use. */ 70 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 71 /* Base addresses. */ 72 73 #define DMUB_CW0_BASE (0x60000000) 74 #define DMUB_CW1_BASE (0x61000000) 75 #define DMUB_CW3_BASE (0x63000000) 76 #define DMUB_CW4_BASE (0x64000000) 77 #define DMUB_CW5_BASE (0x65000000) 78 #define DMUB_CW6_BASE (0x66000000) 79 80 #define DMUB_REGION5_BASE (0xA0000000) 81 82 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 83 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 84 85 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 86 { 87 return (val + factor - 1) / factor * factor; 88 } 89 90 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 91 { 92 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 93 uint8_t buf[64]; 94 uint32_t pos, end; 95 96 /** 97 * Read 64-byte chunks since we don't want to store a 98 * large temporary buffer for this purpose. 99 */ 100 end = fb->size / sizeof(buf) * sizeof(buf); 101 102 for (pos = 0; pos < end; pos += sizeof(buf)) 103 dmub_memcpy(buf, base + pos, sizeof(buf)); 104 105 /* Read anything leftover into the buffer. */ 106 if (end < fb->size) 107 dmub_memcpy(buf, base + pos, fb->size - end); 108 } 109 110 static const struct dmub_fw_meta_info * 111 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 112 { 113 const union dmub_fw_meta *meta; 114 115 if (!blob || !blob_size) 116 return NULL; 117 118 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 119 return NULL; 120 121 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 122 sizeof(union dmub_fw_meta)); 123 124 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 125 return NULL; 126 127 return &meta->info; 128 } 129 130 static const struct dmub_fw_meta_info * 131 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 132 { 133 const struct dmub_fw_meta_info *info = NULL; 134 135 if (params->fw_bss_data && params->bss_data_size) { 136 /* Legacy metadata region. */ 137 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 138 params->bss_data_size, 139 DMUB_FW_META_OFFSET); 140 } else if (params->fw_inst_const && params->inst_const_size) { 141 /* Combined metadata region - can be aligned to 16-bytes. */ 142 uint32_t i; 143 144 for (i = 0; i < 16; ++i) { 145 info = dmub_get_fw_meta_info_from_blob( 146 params->fw_inst_const, params->inst_const_size, i); 147 148 if (info) 149 break; 150 } 151 } 152 153 return info; 154 } 155 156 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 157 { 158 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 159 160 switch (asic) { 161 case DMUB_ASIC_DCN20: 162 case DMUB_ASIC_DCN21: 163 case DMUB_ASIC_DCN30: 164 case DMUB_ASIC_DCN301: 165 case DMUB_ASIC_DCN302: 166 case DMUB_ASIC_DCN303: 167 dmub->regs = &dmub_srv_dcn20_regs; 168 169 funcs->reset = dmub_dcn20_reset; 170 funcs->reset_release = dmub_dcn20_reset_release; 171 funcs->backdoor_load = dmub_dcn20_backdoor_load; 172 funcs->setup_windows = dmub_dcn20_setup_windows; 173 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 174 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 175 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 176 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 177 funcs->is_supported = dmub_dcn20_is_supported; 178 funcs->is_hw_init = dmub_dcn20_is_hw_init; 179 funcs->set_gpint = dmub_dcn20_set_gpint; 180 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 181 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 182 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 183 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 184 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 185 funcs->get_current_time = dmub_dcn20_get_current_time; 186 187 // Out mailbox register access functions for RN and above 188 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 189 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 190 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 191 192 //outbox0 call stacks 193 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 194 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 195 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 196 197 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 198 199 if (asic == DMUB_ASIC_DCN21) 200 dmub->regs = &dmub_srv_dcn21_regs; 201 202 if (asic == DMUB_ASIC_DCN30) { 203 dmub->regs = &dmub_srv_dcn30_regs; 204 205 funcs->backdoor_load = dmub_dcn30_backdoor_load; 206 funcs->setup_windows = dmub_dcn30_setup_windows; 207 } 208 if (asic == DMUB_ASIC_DCN301) { 209 dmub->regs = &dmub_srv_dcn301_regs; 210 211 funcs->backdoor_load = dmub_dcn30_backdoor_load; 212 funcs->setup_windows = dmub_dcn30_setup_windows; 213 } 214 if (asic == DMUB_ASIC_DCN302) { 215 dmub->regs = &dmub_srv_dcn302_regs; 216 217 funcs->backdoor_load = dmub_dcn30_backdoor_load; 218 funcs->setup_windows = dmub_dcn30_setup_windows; 219 } 220 if (asic == DMUB_ASIC_DCN303) { 221 dmub->regs = &dmub_srv_dcn303_regs; 222 223 funcs->backdoor_load = dmub_dcn30_backdoor_load; 224 funcs->setup_windows = dmub_dcn30_setup_windows; 225 } 226 break; 227 228 case DMUB_ASIC_DCN31: 229 case DMUB_ASIC_DCN31B: 230 case DMUB_ASIC_DCN314: 231 case DMUB_ASIC_DCN315: 232 case DMUB_ASIC_DCN316: 233 if (asic == DMUB_ASIC_DCN314) { 234 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 235 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 236 } else if (asic == DMUB_ASIC_DCN315) { 237 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 238 } else if (asic == DMUB_ASIC_DCN316) { 239 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 240 } else { 241 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 242 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 243 } 244 funcs->reset = dmub_dcn31_reset; 245 funcs->reset_release = dmub_dcn31_reset_release; 246 funcs->backdoor_load = dmub_dcn31_backdoor_load; 247 funcs->setup_windows = dmub_dcn31_setup_windows; 248 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 249 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 250 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 251 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 252 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 253 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 254 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 255 funcs->is_supported = dmub_dcn31_is_supported; 256 funcs->is_hw_init = dmub_dcn31_is_hw_init; 257 funcs->set_gpint = dmub_dcn31_set_gpint; 258 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 259 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 260 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 261 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 262 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 263 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 264 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 265 //outbox0 call stacks 266 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 267 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 268 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 269 270 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 271 funcs->should_detect = dmub_dcn31_should_detect; 272 funcs->get_current_time = dmub_dcn31_get_current_time; 273 274 break; 275 276 case DMUB_ASIC_DCN32: 277 case DMUB_ASIC_DCN321: 278 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 279 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 280 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 281 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 282 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 283 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 284 funcs->reset = dmub_dcn32_reset; 285 funcs->reset_release = dmub_dcn32_reset_release; 286 funcs->backdoor_load = dmub_dcn32_backdoor_load; 287 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 288 funcs->setup_windows = dmub_dcn32_setup_windows; 289 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 290 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 291 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 292 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 293 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 294 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 295 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 296 funcs->is_supported = dmub_dcn32_is_supported; 297 funcs->is_hw_init = dmub_dcn32_is_hw_init; 298 funcs->set_gpint = dmub_dcn32_set_gpint; 299 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 300 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 301 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 302 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 303 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 304 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 305 306 /* outbox0 call stacks */ 307 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 308 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 309 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 310 funcs->get_current_time = dmub_dcn32_get_current_time; 311 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 312 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 313 314 break; 315 316 case DMUB_ASIC_DCN35: 317 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 318 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 319 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 320 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 321 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 322 funcs->reset = dmub_dcn35_reset; 323 funcs->reset_release = dmub_dcn35_reset_release; 324 funcs->backdoor_load = dmub_dcn35_backdoor_load; 325 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 326 funcs->setup_windows = dmub_dcn35_setup_windows; 327 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 328 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 329 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 330 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 331 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 332 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 333 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 334 funcs->is_supported = dmub_dcn35_is_supported; 335 funcs->is_hw_init = dmub_dcn35_is_hw_init; 336 funcs->set_gpint = dmub_dcn35_set_gpint; 337 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 338 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 339 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 340 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 341 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 342 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 343 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 344 //outbox0 call stacks 345 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 346 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 347 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 348 349 funcs->get_current_time = dmub_dcn35_get_current_time; 350 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 351 352 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 353 354 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 355 funcs->should_detect = dmub_dcn35_should_detect; 356 break; 357 358 default: 359 return false; 360 } 361 362 return true; 363 } 364 365 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 366 const struct dmub_srv_create_params *params) 367 { 368 enum dmub_status status = DMUB_STATUS_OK; 369 370 dmub_memset(dmub, 0, sizeof(*dmub)); 371 372 dmub->funcs = params->funcs; 373 dmub->user_ctx = params->user_ctx; 374 dmub->asic = params->asic; 375 dmub->fw_version = params->fw_version; 376 dmub->is_virtual = params->is_virtual; 377 378 /* Setup asic dependent hardware funcs. */ 379 if (!dmub_srv_hw_setup(dmub, params->asic)) { 380 status = DMUB_STATUS_INVALID; 381 goto cleanup; 382 } 383 384 /* Override (some) hardware funcs based on user params. */ 385 if (params->hw_funcs) { 386 if (params->hw_funcs->emul_get_inbox1_rptr) 387 dmub->hw_funcs.emul_get_inbox1_rptr = 388 params->hw_funcs->emul_get_inbox1_rptr; 389 390 if (params->hw_funcs->emul_set_inbox1_wptr) 391 dmub->hw_funcs.emul_set_inbox1_wptr = 392 params->hw_funcs->emul_set_inbox1_wptr; 393 394 if (params->hw_funcs->is_supported) 395 dmub->hw_funcs.is_supported = 396 params->hw_funcs->is_supported; 397 } 398 399 /* Sanity checks for required hw func pointers. */ 400 if (!dmub->hw_funcs.get_inbox1_rptr || 401 !dmub->hw_funcs.set_inbox1_wptr) { 402 status = DMUB_STATUS_INVALID; 403 goto cleanup; 404 } 405 406 cleanup: 407 if (status == DMUB_STATUS_OK) 408 dmub->sw_init = true; 409 else 410 dmub_srv_destroy(dmub); 411 412 return status; 413 } 414 415 void dmub_srv_destroy(struct dmub_srv *dmub) 416 { 417 dmub_memset(dmub, 0, sizeof(*dmub)); 418 } 419 420 enum dmub_status 421 dmub_srv_calc_region_info(struct dmub_srv *dmub, 422 const struct dmub_srv_region_params *params, 423 struct dmub_srv_region_info *out) 424 { 425 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 426 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 427 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 428 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 429 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 430 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 431 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 432 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 433 const struct dmub_fw_meta_info *fw_info; 434 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 435 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 436 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 437 438 if (!dmub->sw_init) 439 return DMUB_STATUS_INVALID; 440 441 memset(out, 0, sizeof(*out)); 442 443 out->num_regions = DMUB_NUM_WINDOWS; 444 445 inst->base = 0x0; 446 inst->top = inst->base + params->inst_const_size; 447 448 data->base = dmub_align(inst->top, 256); 449 data->top = data->base + params->bss_data_size; 450 451 /* 452 * All cache windows below should be aligned to the size 453 * of the DMCUB cache line, 64 bytes. 454 */ 455 456 stack->base = dmub_align(data->top, 256); 457 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 458 459 bios->base = dmub_align(stack->top, 256); 460 bios->top = bios->base + params->vbios_size; 461 462 mail->base = dmub_align(bios->top, 256); 463 mail->top = mail->base + DMUB_MAILBOX_SIZE; 464 465 fw_info = dmub_get_fw_meta_info(params); 466 467 if (fw_info) { 468 fw_state_size = fw_info->fw_region_size; 469 trace_buffer_size = fw_info->trace_buffer_size; 470 471 /** 472 * If DM didn't fill in a version, then fill it in based on 473 * the firmware meta now that we have it. 474 * 475 * TODO: Make it easier for driver to extract this out to 476 * pass during creation. 477 */ 478 if (dmub->fw_version == 0) 479 dmub->fw_version = fw_info->fw_version; 480 } 481 482 trace_buff->base = dmub_align(mail->top, 256); 483 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 484 485 fw_state->base = dmub_align(trace_buff->top, 256); 486 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 487 488 scratch_mem->base = dmub_align(fw_state->top, 256); 489 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 490 491 out->fb_size = dmub_align(scratch_mem->top, 4096); 492 493 return DMUB_STATUS_OK; 494 } 495 496 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 497 const struct dmub_srv_fb_params *params, 498 struct dmub_srv_fb_info *out) 499 { 500 uint8_t *cpu_base; 501 uint64_t gpu_base; 502 uint32_t i; 503 504 if (!dmub->sw_init) 505 return DMUB_STATUS_INVALID; 506 507 memset(out, 0, sizeof(*out)); 508 509 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 510 return DMUB_STATUS_INVALID; 511 512 cpu_base = (uint8_t *)params->cpu_addr; 513 gpu_base = params->gpu_addr; 514 515 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 516 const struct dmub_region *reg = 517 ¶ms->region_info->regions[i]; 518 519 out->fb[i].cpu_addr = cpu_base + reg->base; 520 out->fb[i].gpu_addr = gpu_base + reg->base; 521 out->fb[i].size = reg->top - reg->base; 522 } 523 524 out->num_fb = DMUB_NUM_WINDOWS; 525 526 return DMUB_STATUS_OK; 527 } 528 529 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 530 bool *is_supported) 531 { 532 *is_supported = false; 533 534 if (!dmub->sw_init) 535 return DMUB_STATUS_INVALID; 536 537 if (dmub->hw_funcs.is_supported) 538 *is_supported = dmub->hw_funcs.is_supported(dmub); 539 540 return DMUB_STATUS_OK; 541 } 542 543 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 544 { 545 *is_hw_init = false; 546 547 if (!dmub->sw_init) 548 return DMUB_STATUS_INVALID; 549 550 if (!dmub->hw_init) 551 return DMUB_STATUS_OK; 552 553 if (dmub->hw_funcs.is_hw_init) 554 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 555 556 return DMUB_STATUS_OK; 557 } 558 559 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 560 const struct dmub_srv_hw_params *params) 561 { 562 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 563 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 564 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 565 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 566 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 567 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 568 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 569 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 570 571 struct dmub_rb_init_params rb_params, outbox0_rb_params; 572 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 573 struct dmub_region inbox1, outbox1, outbox0; 574 575 if (!dmub->sw_init) 576 return DMUB_STATUS_INVALID; 577 578 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 579 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 580 ASSERT(0); 581 return DMUB_STATUS_INVALID; 582 } 583 584 dmub->fb_base = params->fb_base; 585 dmub->fb_offset = params->fb_offset; 586 dmub->psp_version = params->psp_version; 587 588 if (dmub->hw_funcs.reset) 589 dmub->hw_funcs.reset(dmub); 590 591 /* reset the cache of the last wptr as well now that hw is reset */ 592 dmub->inbox1_last_wptr = 0; 593 594 cw0.offset.quad_part = inst_fb->gpu_addr; 595 cw0.region.base = DMUB_CW0_BASE; 596 cw0.region.top = cw0.region.base + inst_fb->size - 1; 597 598 cw1.offset.quad_part = stack_fb->gpu_addr; 599 cw1.region.base = DMUB_CW1_BASE; 600 cw1.region.top = cw1.region.base + stack_fb->size - 1; 601 602 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 603 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 604 605 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 606 /** 607 * Read back all the instruction memory so we don't hang the 608 * DMCUB when backdoor loading if the write from x86 hasn't been 609 * flushed yet. This only occurs in backdoor loading. 610 */ 611 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 612 dmub_flush_buffer_mem(inst_fb); 613 614 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 615 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 616 else 617 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 618 } 619 620 cw2.offset.quad_part = data_fb->gpu_addr; 621 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 622 cw2.region.top = cw2.region.base + data_fb->size; 623 624 cw3.offset.quad_part = bios_fb->gpu_addr; 625 cw3.region.base = DMUB_CW3_BASE; 626 cw3.region.top = cw3.region.base + bios_fb->size; 627 628 cw4.offset.quad_part = mail_fb->gpu_addr; 629 cw4.region.base = DMUB_CW4_BASE; 630 cw4.region.top = cw4.region.base + mail_fb->size; 631 632 /** 633 * Doubled the mailbox region to accomodate inbox and outbox. 634 * Note: Currently, currently total mailbox size is 16KB. It is split 635 * equally into 8KB between inbox and outbox. If this config is 636 * changed, then uncached base address configuration of outbox1 637 * has to be updated in funcs->setup_out_mailbox. 638 */ 639 inbox1.base = cw4.region.base; 640 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 641 outbox1.base = inbox1.top; 642 outbox1.top = cw4.region.top; 643 644 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 645 cw5.region.base = DMUB_CW5_BASE; 646 cw5.region.top = cw5.region.base + tracebuff_fb->size; 647 648 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 649 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 650 651 cw6.offset.quad_part = fw_state_fb->gpu_addr; 652 cw6.region.base = DMUB_CW6_BASE; 653 cw6.region.top = cw6.region.base + fw_state_fb->size; 654 655 dmub->fw_state = fw_state_fb->cpu_addr; 656 657 dmub->scratch_mem_fb = *scratch_mem_fb; 658 659 if (dmub->hw_funcs.setup_windows) 660 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 661 662 if (dmub->hw_funcs.setup_outbox0) 663 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 664 665 if (dmub->hw_funcs.setup_mailbox) 666 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 667 if (dmub->hw_funcs.setup_out_mailbox) 668 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 669 670 dmub_memset(&rb_params, 0, sizeof(rb_params)); 671 rb_params.ctx = dmub; 672 rb_params.base_address = mail_fb->cpu_addr; 673 rb_params.capacity = DMUB_RB_SIZE; 674 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 675 676 // Initialize outbox1 ring buffer 677 rb_params.ctx = dmub; 678 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 679 rb_params.capacity = DMUB_RB_SIZE; 680 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 681 682 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 683 outbox0_rb_params.ctx = dmub; 684 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 685 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 686 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 687 688 /* Report to DMUB what features are supported by current driver */ 689 if (dmub->hw_funcs.enable_dmub_boot_options) 690 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 691 692 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 693 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 694 params->skip_panel_power_sequence); 695 696 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 697 dmub->hw_funcs.reset_release(dmub); 698 699 dmub->hw_init = true; 700 701 return DMUB_STATUS_OK; 702 } 703 704 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 705 { 706 if (!dmub->sw_init) 707 return DMUB_STATUS_INVALID; 708 709 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 710 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 711 dmub->inbox1_rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 712 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 713 } 714 715 return DMUB_STATUS_OK; 716 } 717 718 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 719 { 720 if (!dmub->sw_init) 721 return DMUB_STATUS_INVALID; 722 723 if (dmub->hw_funcs.reset) 724 dmub->hw_funcs.reset(dmub); 725 726 /* mailboxes have been reset in hw, so reset the sw state as well */ 727 dmub->inbox1_last_wptr = 0; 728 dmub->inbox1_rb.wrpt = 0; 729 dmub->inbox1_rb.rptr = 0; 730 dmub->outbox0_rb.wrpt = 0; 731 dmub->outbox0_rb.rptr = 0; 732 dmub->outbox1_rb.wrpt = 0; 733 dmub->outbox1_rb.rptr = 0; 734 735 dmub->hw_init = false; 736 737 return DMUB_STATUS_OK; 738 } 739 740 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 741 const union dmub_rb_cmd *cmd) 742 { 743 if (!dmub->hw_init) 744 return DMUB_STATUS_INVALID; 745 746 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 747 return DMUB_STATUS_OK; 748 749 return DMUB_STATUS_QUEUE_FULL; 750 } 751 752 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 753 { 754 struct dmub_rb flush_rb; 755 756 if (!dmub->hw_init) 757 return DMUB_STATUS_INVALID; 758 759 /** 760 * Read back all the queued commands to ensure that they've 761 * been flushed to framebuffer memory. Otherwise DMCUB might 762 * read back stale, fully invalid or partially invalid data. 763 */ 764 flush_rb = dmub->inbox1_rb; 765 flush_rb.rptr = dmub->inbox1_last_wptr; 766 dmub_rb_flush_pending(&flush_rb); 767 768 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 769 770 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 771 772 return DMUB_STATUS_OK; 773 } 774 775 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 776 { 777 if (!dmub->hw_funcs.is_hw_powered_up) 778 return true; 779 780 return dmub->hw_funcs.is_hw_powered_up(dmub) && 781 dmub->hw_funcs.is_hw_init(dmub); 782 } 783 784 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 785 uint32_t timeout_us) 786 { 787 uint32_t i; 788 789 if (!dmub->hw_init) 790 return DMUB_STATUS_INVALID; 791 792 for (i = 0; i <= timeout_us; i += 100) { 793 if (dmub_srv_is_hw_pwr_up(dmub)) 794 return DMUB_STATUS_OK; 795 796 udelay(100); 797 } 798 799 return DMUB_STATUS_TIMEOUT; 800 } 801 802 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 803 uint32_t timeout_us) 804 { 805 uint32_t i; 806 bool hw_on = true; 807 808 if (!dmub->hw_init) 809 return DMUB_STATUS_INVALID; 810 811 for (i = 0; i <= timeout_us; i += 100) { 812 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 813 814 if (dmub->hw_funcs.is_hw_powered_up) 815 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 816 817 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 818 return DMUB_STATUS_OK; 819 820 udelay(100); 821 } 822 823 return DMUB_STATUS_TIMEOUT; 824 } 825 826 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 827 uint32_t timeout_us) 828 { 829 uint32_t i, rptr; 830 831 if (!dmub->hw_init) 832 return DMUB_STATUS_INVALID; 833 834 for (i = 0; i <= timeout_us; ++i) { 835 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 836 837 if (rptr > dmub->inbox1_rb.capacity) 838 return DMUB_STATUS_HW_FAILURE; 839 840 dmub->inbox1_rb.rptr = rptr; 841 842 if (dmub_rb_empty(&dmub->inbox1_rb)) 843 return DMUB_STATUS_OK; 844 845 udelay(1); 846 } 847 848 return DMUB_STATUS_TIMEOUT; 849 } 850 851 enum dmub_status 852 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 853 enum dmub_gpint_command command_code, 854 uint16_t param, uint32_t timeout_us) 855 { 856 union dmub_gpint_data_register reg; 857 uint32_t i; 858 859 if (!dmub->sw_init) 860 return DMUB_STATUS_INVALID; 861 862 if (!dmub->hw_funcs.set_gpint) 863 return DMUB_STATUS_INVALID; 864 865 if (!dmub->hw_funcs.is_gpint_acked) 866 return DMUB_STATUS_INVALID; 867 868 reg.bits.status = 1; 869 reg.bits.command_code = command_code; 870 reg.bits.param = param; 871 872 dmub->hw_funcs.set_gpint(dmub, reg); 873 874 for (i = 0; i < timeout_us; ++i) { 875 udelay(1); 876 877 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 878 return DMUB_STATUS_OK; 879 } 880 881 return DMUB_STATUS_TIMEOUT; 882 } 883 884 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 885 uint32_t *response) 886 { 887 *response = 0; 888 889 if (!dmub->sw_init) 890 return DMUB_STATUS_INVALID; 891 892 if (!dmub->hw_funcs.get_gpint_response) 893 return DMUB_STATUS_INVALID; 894 895 *response = dmub->hw_funcs.get_gpint_response(dmub); 896 897 return DMUB_STATUS_OK; 898 } 899 900 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 901 uint32_t *dataout) 902 { 903 *dataout = 0; 904 905 if (!dmub->sw_init) 906 return DMUB_STATUS_INVALID; 907 908 if (!dmub->hw_funcs.get_gpint_dataout) 909 return DMUB_STATUS_INVALID; 910 911 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 912 913 return DMUB_STATUS_OK; 914 } 915 916 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 917 union dmub_fw_boot_status *status) 918 { 919 status->all = 0; 920 921 if (!dmub->sw_init) 922 return DMUB_STATUS_INVALID; 923 924 if (dmub->hw_funcs.get_fw_status) 925 *status = dmub->hw_funcs.get_fw_status(dmub); 926 927 return DMUB_STATUS_OK; 928 } 929 930 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 931 union dmub_fw_boot_options *option) 932 { 933 option->all = 0; 934 935 if (!dmub->sw_init) 936 return DMUB_STATUS_INVALID; 937 938 if (dmub->hw_funcs.get_fw_boot_option) 939 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 940 941 return DMUB_STATUS_OK; 942 } 943 944 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 945 bool skip) 946 { 947 if (!dmub->sw_init) 948 return DMUB_STATUS_INVALID; 949 950 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 951 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 952 953 return DMUB_STATUS_OK; 954 } 955 956 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 957 union dmub_rb_cmd *cmd) 958 { 959 enum dmub_status status = DMUB_STATUS_OK; 960 961 // Queue command 962 status = dmub_srv_cmd_queue(dmub, cmd); 963 964 if (status != DMUB_STATUS_OK) 965 return status; 966 967 // Execute command 968 status = dmub_srv_cmd_execute(dmub); 969 970 if (status != DMUB_STATUS_OK) 971 return status; 972 973 // Wait for DMUB to process command 974 status = dmub_srv_wait_for_idle(dmub, 100000); 975 976 if (status != DMUB_STATUS_OK) 977 return status; 978 979 // Copy data back from ring buffer into command 980 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 981 982 return status; 983 } 984 985 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 986 void *entry) 987 { 988 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 989 uint64_t *dst = (uint64_t *)entry; 990 uint8_t i; 991 uint8_t loop_count; 992 993 if (rb->rptr == rb->wrpt) 994 return false; 995 996 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 997 // copying data 998 for (i = 0; i < loop_count; i++) 999 *dst++ = *src++; 1000 1001 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1002 1003 rb->rptr %= rb->capacity; 1004 1005 return true; 1006 } 1007 1008 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1009 { 1010 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1011 1012 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1013 } 1014 1015 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 1016 { 1017 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 1018 return false; 1019 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 1020 return true; 1021 } 1022 1023 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1024 { 1025 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1026 return false; 1027 1028 return dmub->hw_funcs.should_detect(dmub); 1029 } 1030 1031 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1032 { 1033 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1034 return DMUB_STATUS_INVALID; 1035 1036 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1037 return DMUB_STATUS_OK; 1038 } 1039 1040 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1041 { 1042 uint32_t i = 0; 1043 uint32_t ack = 0; 1044 1045 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1046 return DMUB_STATUS_INVALID; 1047 1048 for (i = 0; i <= timeout_us; i++) { 1049 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1050 if (ack) 1051 return DMUB_STATUS_OK; 1052 } 1053 return DMUB_STATUS_TIMEOUT; 1054 } 1055 1056 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1057 union dmub_inbox0_data_register data) 1058 { 1059 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1060 return DMUB_STATUS_INVALID; 1061 1062 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1063 return DMUB_STATUS_OK; 1064 } 1065 1066 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1067 { 1068 if (dmub->hw_funcs.subvp_save_surf_addr) { 1069 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1070 addr, 1071 subvp_index); 1072 } 1073 } 1074