1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn316.h" 36 #include "os_types.h" 37 /* 38 * Note: the DMUB service is standalone. No additional headers should be 39 * added below or above this line unless they reside within the DMUB 40 * folder. 41 */ 42 43 /* Alignment for framebuffer memory. */ 44 #define DMUB_FB_ALIGNMENT (1024 * 1024) 45 46 /* Stack size. */ 47 #define DMUB_STACK_SIZE (128 * 1024) 48 49 /* Context size. */ 50 #define DMUB_CONTEXT_SIZE (512 * 1024) 51 52 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 53 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 54 55 /* Default state size if meta is absent. */ 56 #define DMUB_FW_STATE_SIZE (64 * 1024) 57 58 /* Default tracebuffer size if meta is absent. */ 59 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 60 61 62 /* Default scratch mem size. */ 63 #define DMUB_SCRATCH_MEM_SIZE (256) 64 65 /* Number of windows in use. */ 66 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 67 /* Base addresses. */ 68 69 #define DMUB_CW0_BASE (0x60000000) 70 #define DMUB_CW1_BASE (0x61000000) 71 #define DMUB_CW3_BASE (0x63000000) 72 #define DMUB_CW4_BASE (0x64000000) 73 #define DMUB_CW5_BASE (0x65000000) 74 #define DMUB_CW6_BASE (0x66000000) 75 76 #define DMUB_REGION5_BASE (0xA0000000) 77 78 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 79 { 80 return (val + factor - 1) / factor * factor; 81 } 82 83 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 84 { 85 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 86 uint8_t buf[64]; 87 uint32_t pos, end; 88 89 /** 90 * Read 64-byte chunks since we don't want to store a 91 * large temporary buffer for this purpose. 92 */ 93 end = fb->size / sizeof(buf) * sizeof(buf); 94 95 for (pos = 0; pos < end; pos += sizeof(buf)) 96 dmub_memcpy(buf, base + pos, sizeof(buf)); 97 98 /* Read anything leftover into the buffer. */ 99 if (end < fb->size) 100 dmub_memcpy(buf, base + pos, fb->size - end); 101 } 102 103 static const struct dmub_fw_meta_info * 104 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 105 { 106 const union dmub_fw_meta *meta; 107 108 if (!blob || !blob_size) 109 return NULL; 110 111 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 112 return NULL; 113 114 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 115 sizeof(union dmub_fw_meta)); 116 117 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 118 return NULL; 119 120 return &meta->info; 121 } 122 123 static const struct dmub_fw_meta_info * 124 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 125 { 126 const struct dmub_fw_meta_info *info = NULL; 127 128 if (params->fw_bss_data && params->bss_data_size) { 129 /* Legacy metadata region. */ 130 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 131 params->bss_data_size, 132 DMUB_FW_META_OFFSET); 133 } else if (params->fw_inst_const && params->inst_const_size) { 134 /* Combined metadata region - can be aligned to 16-bytes. */ 135 uint32_t i; 136 137 for (i = 0; i < 16; ++i) { 138 info = dmub_get_fw_meta_info_from_blob( 139 params->fw_inst_const, params->inst_const_size, i); 140 141 if (info) 142 break; 143 } 144 } 145 146 return info; 147 } 148 149 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 150 { 151 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 152 153 switch (asic) { 154 case DMUB_ASIC_DCN20: 155 case DMUB_ASIC_DCN21: 156 case DMUB_ASIC_DCN30: 157 case DMUB_ASIC_DCN301: 158 case DMUB_ASIC_DCN302: 159 case DMUB_ASIC_DCN303: 160 dmub->regs = &dmub_srv_dcn20_regs; 161 162 funcs->reset = dmub_dcn20_reset; 163 funcs->reset_release = dmub_dcn20_reset_release; 164 funcs->backdoor_load = dmub_dcn20_backdoor_load; 165 funcs->setup_windows = dmub_dcn20_setup_windows; 166 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 167 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 168 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 169 funcs->is_supported = dmub_dcn20_is_supported; 170 funcs->is_hw_init = dmub_dcn20_is_hw_init; 171 funcs->set_gpint = dmub_dcn20_set_gpint; 172 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 173 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 174 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 175 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 176 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 177 funcs->get_current_time = dmub_dcn20_get_current_time; 178 179 // Out mailbox register access functions for RN and above 180 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 181 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 182 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 183 184 //outbox0 call stacks 185 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 186 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 187 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 188 189 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 190 191 if (asic == DMUB_ASIC_DCN21) { 192 dmub->regs = &dmub_srv_dcn21_regs; 193 194 funcs->is_phy_init = dmub_dcn21_is_phy_init; 195 } 196 if (asic == DMUB_ASIC_DCN30) { 197 dmub->regs = &dmub_srv_dcn30_regs; 198 199 funcs->backdoor_load = dmub_dcn30_backdoor_load; 200 funcs->setup_windows = dmub_dcn30_setup_windows; 201 } 202 if (asic == DMUB_ASIC_DCN301) { 203 dmub->regs = &dmub_srv_dcn301_regs; 204 205 funcs->backdoor_load = dmub_dcn30_backdoor_load; 206 funcs->setup_windows = dmub_dcn30_setup_windows; 207 } 208 if (asic == DMUB_ASIC_DCN302) { 209 dmub->regs = &dmub_srv_dcn302_regs; 210 211 funcs->backdoor_load = dmub_dcn30_backdoor_load; 212 funcs->setup_windows = dmub_dcn30_setup_windows; 213 } 214 if (asic == DMUB_ASIC_DCN303) { 215 dmub->regs = &dmub_srv_dcn303_regs; 216 217 funcs->backdoor_load = dmub_dcn30_backdoor_load; 218 funcs->setup_windows = dmub_dcn30_setup_windows; 219 } 220 break; 221 222 case DMUB_ASIC_DCN31: 223 case DMUB_ASIC_DCN31B: 224 case DMUB_ASIC_DCN316: 225 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 226 if (asic == DMUB_ASIC_DCN316) 227 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 228 funcs->reset = dmub_dcn31_reset; 229 funcs->reset_release = dmub_dcn31_reset_release; 230 funcs->backdoor_load = dmub_dcn31_backdoor_load; 231 funcs->setup_windows = dmub_dcn31_setup_windows; 232 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 233 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 234 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 235 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 236 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 237 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 238 funcs->is_supported = dmub_dcn31_is_supported; 239 funcs->is_hw_init = dmub_dcn31_is_hw_init; 240 funcs->set_gpint = dmub_dcn31_set_gpint; 241 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 242 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 243 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 244 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 245 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 246 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 247 //outbox0 call stacks 248 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 249 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 250 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 251 252 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 253 funcs->should_detect = dmub_dcn31_should_detect; 254 funcs->get_current_time = dmub_dcn31_get_current_time; 255 256 break; 257 258 default: 259 return false; 260 } 261 262 return true; 263 } 264 265 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 266 const struct dmub_srv_create_params *params) 267 { 268 enum dmub_status status = DMUB_STATUS_OK; 269 270 dmub_memset(dmub, 0, sizeof(*dmub)); 271 272 dmub->funcs = params->funcs; 273 dmub->user_ctx = params->user_ctx; 274 dmub->asic = params->asic; 275 dmub->fw_version = params->fw_version; 276 dmub->is_virtual = params->is_virtual; 277 278 /* Setup asic dependent hardware funcs. */ 279 if (!dmub_srv_hw_setup(dmub, params->asic)) { 280 status = DMUB_STATUS_INVALID; 281 goto cleanup; 282 } 283 284 /* Override (some) hardware funcs based on user params. */ 285 if (params->hw_funcs) { 286 if (params->hw_funcs->emul_get_inbox1_rptr) 287 dmub->hw_funcs.emul_get_inbox1_rptr = 288 params->hw_funcs->emul_get_inbox1_rptr; 289 290 if (params->hw_funcs->emul_set_inbox1_wptr) 291 dmub->hw_funcs.emul_set_inbox1_wptr = 292 params->hw_funcs->emul_set_inbox1_wptr; 293 294 if (params->hw_funcs->is_supported) 295 dmub->hw_funcs.is_supported = 296 params->hw_funcs->is_supported; 297 } 298 299 /* Sanity checks for required hw func pointers. */ 300 if (!dmub->hw_funcs.get_inbox1_rptr || 301 !dmub->hw_funcs.set_inbox1_wptr) { 302 status = DMUB_STATUS_INVALID; 303 goto cleanup; 304 } 305 306 cleanup: 307 if (status == DMUB_STATUS_OK) 308 dmub->sw_init = true; 309 else 310 dmub_srv_destroy(dmub); 311 312 return status; 313 } 314 315 void dmub_srv_destroy(struct dmub_srv *dmub) 316 { 317 dmub_memset(dmub, 0, sizeof(*dmub)); 318 } 319 320 enum dmub_status 321 dmub_srv_calc_region_info(struct dmub_srv *dmub, 322 const struct dmub_srv_region_params *params, 323 struct dmub_srv_region_info *out) 324 { 325 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 326 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 327 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 328 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 329 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 330 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 331 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 332 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 333 const struct dmub_fw_meta_info *fw_info; 334 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 335 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 336 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 337 338 if (!dmub->sw_init) 339 return DMUB_STATUS_INVALID; 340 341 memset(out, 0, sizeof(*out)); 342 343 out->num_regions = DMUB_NUM_WINDOWS; 344 345 inst->base = 0x0; 346 inst->top = inst->base + params->inst_const_size; 347 348 data->base = dmub_align(inst->top, 256); 349 data->top = data->base + params->bss_data_size; 350 351 /* 352 * All cache windows below should be aligned to the size 353 * of the DMCUB cache line, 64 bytes. 354 */ 355 356 stack->base = dmub_align(data->top, 256); 357 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 358 359 bios->base = dmub_align(stack->top, 256); 360 bios->top = bios->base + params->vbios_size; 361 362 mail->base = dmub_align(bios->top, 256); 363 mail->top = mail->base + DMUB_MAILBOX_SIZE; 364 365 fw_info = dmub_get_fw_meta_info(params); 366 367 if (fw_info) { 368 fw_state_size = fw_info->fw_region_size; 369 trace_buffer_size = fw_info->trace_buffer_size; 370 371 /** 372 * If DM didn't fill in a version, then fill it in based on 373 * the firmware meta now that we have it. 374 * 375 * TODO: Make it easier for driver to extract this out to 376 * pass during creation. 377 */ 378 if (dmub->fw_version == 0) 379 dmub->fw_version = fw_info->fw_version; 380 } 381 382 trace_buff->base = dmub_align(mail->top, 256); 383 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 384 385 fw_state->base = dmub_align(trace_buff->top, 256); 386 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 387 388 scratch_mem->base = dmub_align(fw_state->top, 256); 389 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 390 391 out->fb_size = dmub_align(scratch_mem->top, 4096); 392 393 return DMUB_STATUS_OK; 394 } 395 396 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 397 const struct dmub_srv_fb_params *params, 398 struct dmub_srv_fb_info *out) 399 { 400 uint8_t *cpu_base; 401 uint64_t gpu_base; 402 uint32_t i; 403 404 if (!dmub->sw_init) 405 return DMUB_STATUS_INVALID; 406 407 memset(out, 0, sizeof(*out)); 408 409 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 410 return DMUB_STATUS_INVALID; 411 412 cpu_base = (uint8_t *)params->cpu_addr; 413 gpu_base = params->gpu_addr; 414 415 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 416 const struct dmub_region *reg = 417 ¶ms->region_info->regions[i]; 418 419 out->fb[i].cpu_addr = cpu_base + reg->base; 420 out->fb[i].gpu_addr = gpu_base + reg->base; 421 out->fb[i].size = reg->top - reg->base; 422 } 423 424 out->num_fb = DMUB_NUM_WINDOWS; 425 426 return DMUB_STATUS_OK; 427 } 428 429 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 430 bool *is_supported) 431 { 432 *is_supported = false; 433 434 if (!dmub->sw_init) 435 return DMUB_STATUS_INVALID; 436 437 if (dmub->hw_funcs.is_supported) 438 *is_supported = dmub->hw_funcs.is_supported(dmub); 439 440 return DMUB_STATUS_OK; 441 } 442 443 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 444 { 445 *is_hw_init = false; 446 447 if (!dmub->sw_init) 448 return DMUB_STATUS_INVALID; 449 450 if (!dmub->hw_init) 451 return DMUB_STATUS_OK; 452 453 if (dmub->hw_funcs.is_hw_init) 454 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 455 456 return DMUB_STATUS_OK; 457 } 458 459 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 460 const struct dmub_srv_hw_params *params) 461 { 462 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 463 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 464 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 465 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 466 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 467 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 468 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 469 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 470 471 struct dmub_rb_init_params rb_params, outbox0_rb_params; 472 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 473 struct dmub_region inbox1, outbox1, outbox0; 474 475 if (!dmub->sw_init) 476 return DMUB_STATUS_INVALID; 477 478 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 479 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 480 ASSERT(0); 481 return DMUB_STATUS_INVALID; 482 } 483 484 dmub->fb_base = params->fb_base; 485 dmub->fb_offset = params->fb_offset; 486 dmub->psp_version = params->psp_version; 487 488 if (dmub->hw_funcs.reset) 489 dmub->hw_funcs.reset(dmub); 490 491 cw0.offset.quad_part = inst_fb->gpu_addr; 492 cw0.region.base = DMUB_CW0_BASE; 493 cw0.region.top = cw0.region.base + inst_fb->size - 1; 494 495 cw1.offset.quad_part = stack_fb->gpu_addr; 496 cw1.region.base = DMUB_CW1_BASE; 497 cw1.region.top = cw1.region.base + stack_fb->size - 1; 498 499 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 500 /** 501 * Read back all the instruction memory so we don't hang the 502 * DMCUB when backdoor loading if the write from x86 hasn't been 503 * flushed yet. This only occurs in backdoor loading. 504 */ 505 dmub_flush_buffer_mem(inst_fb); 506 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 507 } 508 509 cw2.offset.quad_part = data_fb->gpu_addr; 510 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 511 cw2.region.top = cw2.region.base + data_fb->size; 512 513 cw3.offset.quad_part = bios_fb->gpu_addr; 514 cw3.region.base = DMUB_CW3_BASE; 515 cw3.region.top = cw3.region.base + bios_fb->size; 516 517 cw4.offset.quad_part = mail_fb->gpu_addr; 518 cw4.region.base = DMUB_CW4_BASE; 519 cw4.region.top = cw4.region.base + mail_fb->size; 520 521 /** 522 * Doubled the mailbox region to accomodate inbox and outbox. 523 * Note: Currently, currently total mailbox size is 16KB. It is split 524 * equally into 8KB between inbox and outbox. If this config is 525 * changed, then uncached base address configuration of outbox1 526 * has to be updated in funcs->setup_out_mailbox. 527 */ 528 inbox1.base = cw4.region.base; 529 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 530 outbox1.base = inbox1.top; 531 outbox1.top = cw4.region.top; 532 533 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 534 cw5.region.base = DMUB_CW5_BASE; 535 cw5.region.top = cw5.region.base + tracebuff_fb->size; 536 537 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 538 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 539 540 cw6.offset.quad_part = fw_state_fb->gpu_addr; 541 cw6.region.base = DMUB_CW6_BASE; 542 cw6.region.top = cw6.region.base + fw_state_fb->size; 543 544 dmub->fw_state = fw_state_fb->cpu_addr; 545 546 dmub->scratch_mem_fb = *scratch_mem_fb; 547 548 if (dmub->hw_funcs.setup_windows) 549 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6); 550 551 if (dmub->hw_funcs.setup_outbox0) 552 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 553 554 if (dmub->hw_funcs.setup_mailbox) 555 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 556 if (dmub->hw_funcs.setup_out_mailbox) 557 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 558 559 dmub_memset(&rb_params, 0, sizeof(rb_params)); 560 rb_params.ctx = dmub; 561 rb_params.base_address = mail_fb->cpu_addr; 562 rb_params.capacity = DMUB_RB_SIZE; 563 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 564 565 // Initialize outbox1 ring buffer 566 rb_params.ctx = dmub; 567 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 568 rb_params.capacity = DMUB_RB_SIZE; 569 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 570 571 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 572 outbox0_rb_params.ctx = dmub; 573 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 574 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 575 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 576 577 /* Report to DMUB what features are supported by current driver */ 578 if (dmub->hw_funcs.enable_dmub_boot_options) 579 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 580 581 if (dmub->hw_funcs.reset_release) 582 dmub->hw_funcs.reset_release(dmub); 583 584 dmub->hw_init = true; 585 586 return DMUB_STATUS_OK; 587 } 588 589 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 590 { 591 if (!dmub->sw_init) 592 return DMUB_STATUS_INVALID; 593 594 if (dmub->hw_funcs.reset) 595 dmub->hw_funcs.reset(dmub); 596 597 dmub->hw_init = false; 598 599 return DMUB_STATUS_OK; 600 } 601 602 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 603 const union dmub_rb_cmd *cmd) 604 { 605 if (!dmub->hw_init) 606 return DMUB_STATUS_INVALID; 607 608 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 609 return DMUB_STATUS_OK; 610 611 return DMUB_STATUS_QUEUE_FULL; 612 } 613 614 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 615 { 616 struct dmub_rb flush_rb; 617 618 if (!dmub->hw_init) 619 return DMUB_STATUS_INVALID; 620 621 /** 622 * Read back all the queued commands to ensure that they've 623 * been flushed to framebuffer memory. Otherwise DMCUB might 624 * read back stale, fully invalid or partially invalid data. 625 */ 626 flush_rb = dmub->inbox1_rb; 627 flush_rb.rptr = dmub->inbox1_last_wptr; 628 dmub_rb_flush_pending(&flush_rb); 629 630 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 631 632 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 633 634 return DMUB_STATUS_OK; 635 } 636 637 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 638 uint32_t timeout_us) 639 { 640 uint32_t i; 641 642 if (!dmub->hw_init) 643 return DMUB_STATUS_INVALID; 644 645 for (i = 0; i <= timeout_us; i += 100) { 646 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 647 648 if (status.bits.dal_fw && status.bits.mailbox_rdy) 649 return DMUB_STATUS_OK; 650 651 udelay(100); 652 } 653 654 return DMUB_STATUS_TIMEOUT; 655 } 656 657 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 658 uint32_t timeout_us) 659 { 660 uint32_t i = 0; 661 662 if (!dmub->hw_init) 663 return DMUB_STATUS_INVALID; 664 665 if (!dmub->hw_funcs.is_phy_init) 666 return DMUB_STATUS_OK; 667 668 for (i = 0; i <= timeout_us; i += 10) { 669 if (dmub->hw_funcs.is_phy_init(dmub)) 670 return DMUB_STATUS_OK; 671 672 udelay(10); 673 } 674 675 return DMUB_STATUS_TIMEOUT; 676 } 677 678 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 679 uint32_t timeout_us) 680 { 681 uint32_t i, rptr; 682 683 if (!dmub->hw_init) 684 return DMUB_STATUS_INVALID; 685 686 for (i = 0; i <= timeout_us; ++i) { 687 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 688 689 if (rptr > dmub->inbox1_rb.capacity) 690 return DMUB_STATUS_HW_FAILURE; 691 692 dmub->inbox1_rb.rptr = rptr; 693 694 if (dmub_rb_empty(&dmub->inbox1_rb)) 695 return DMUB_STATUS_OK; 696 697 udelay(1); 698 } 699 700 return DMUB_STATUS_TIMEOUT; 701 } 702 703 enum dmub_status 704 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 705 enum dmub_gpint_command command_code, 706 uint16_t param, uint32_t timeout_us) 707 { 708 union dmub_gpint_data_register reg; 709 uint32_t i; 710 711 if (!dmub->sw_init) 712 return DMUB_STATUS_INVALID; 713 714 if (!dmub->hw_funcs.set_gpint) 715 return DMUB_STATUS_INVALID; 716 717 if (!dmub->hw_funcs.is_gpint_acked) 718 return DMUB_STATUS_INVALID; 719 720 reg.bits.status = 1; 721 reg.bits.command_code = command_code; 722 reg.bits.param = param; 723 724 dmub->hw_funcs.set_gpint(dmub, reg); 725 726 for (i = 0; i < timeout_us; ++i) { 727 udelay(1); 728 729 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 730 return DMUB_STATUS_OK; 731 } 732 733 return DMUB_STATUS_TIMEOUT; 734 } 735 736 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 737 uint32_t *response) 738 { 739 *response = 0; 740 741 if (!dmub->sw_init) 742 return DMUB_STATUS_INVALID; 743 744 if (!dmub->hw_funcs.get_gpint_response) 745 return DMUB_STATUS_INVALID; 746 747 *response = dmub->hw_funcs.get_gpint_response(dmub); 748 749 return DMUB_STATUS_OK; 750 } 751 752 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 753 uint32_t *dataout) 754 { 755 *dataout = 0; 756 757 if (!dmub->sw_init) 758 return DMUB_STATUS_INVALID; 759 760 if (!dmub->hw_funcs.get_gpint_dataout) 761 return DMUB_STATUS_INVALID; 762 763 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 764 765 return DMUB_STATUS_OK; 766 } 767 768 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 769 union dmub_fw_boot_status *status) 770 { 771 status->all = 0; 772 773 if (!dmub->sw_init) 774 return DMUB_STATUS_INVALID; 775 776 if (dmub->hw_funcs.get_fw_status) 777 *status = dmub->hw_funcs.get_fw_status(dmub); 778 779 return DMUB_STATUS_OK; 780 } 781 782 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 783 union dmub_rb_cmd *cmd) 784 { 785 enum dmub_status status = DMUB_STATUS_OK; 786 787 // Queue command 788 status = dmub_srv_cmd_queue(dmub, cmd); 789 790 if (status != DMUB_STATUS_OK) 791 return status; 792 793 // Execute command 794 status = dmub_srv_cmd_execute(dmub); 795 796 if (status != DMUB_STATUS_OK) 797 return status; 798 799 // Wait for DMUB to process command 800 status = dmub_srv_wait_for_idle(dmub, 100000); 801 802 if (status != DMUB_STATUS_OK) 803 return status; 804 805 // Copy data back from ring buffer into command 806 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 807 808 return status; 809 } 810 811 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 812 void *entry) 813 { 814 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 815 uint64_t *dst = (uint64_t *)entry; 816 uint8_t i; 817 uint8_t loop_count; 818 819 if (rb->rptr == rb->wrpt) 820 return false; 821 822 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 823 // copying data 824 for (i = 0; i < loop_count; i++) 825 *dst++ = *src++; 826 827 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 828 829 rb->rptr %= rb->capacity; 830 831 return true; 832 } 833 834 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 835 { 836 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 837 838 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 839 } 840 841 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 842 { 843 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 844 return false; 845 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 846 return true; 847 } 848 849 bool dmub_srv_should_detect(struct dmub_srv *dmub) 850 { 851 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 852 return false; 853 854 return dmub->hw_funcs.should_detect(dmub); 855 } 856 857 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 858 { 859 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 860 return DMUB_STATUS_INVALID; 861 862 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 863 return DMUB_STATUS_OK; 864 } 865 866 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 867 { 868 uint32_t i = 0; 869 uint32_t ack = 0; 870 871 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 872 return DMUB_STATUS_INVALID; 873 874 for (i = 0; i <= timeout_us; i++) { 875 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 876 if (ack) 877 return DMUB_STATUS_OK; 878 } 879 return DMUB_STATUS_TIMEOUT; 880 } 881 882 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 883 union dmub_inbox0_data_register data) 884 { 885 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 886 return DMUB_STATUS_INVALID; 887 888 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 889 return DMUB_STATUS_OK; 890 } 891