1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2019-2026 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn36.h" 42 #include "dmub_dcn401.h" 43 #include "dmub_dcn42.h" 44 #include "dmub_dcn42b.h" 45 #include "os_types.h" 46 /* 47 * Note: the DMUB service is standalone. No additional headers should be 48 * added below or above this line unless they reside within the DMUB 49 * folder. 50 */ 51 52 /* Alignment for framebuffer memory. */ 53 #define DMUB_FB_ALIGNMENT (1024 * 1024) 54 55 /* Stack size. */ 56 #define DMUB_STACK_SIZE (128 * 1024) 57 58 /* Context size. */ 59 #define DMUB_CONTEXT_SIZE (512 * 1024) 60 61 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 62 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 63 64 /* Default state size if meta is absent. */ 65 #define DMUB_FW_STATE_SIZE (64 * 1024) 66 67 /* Default scratch mem size. */ 68 #define DMUB_SCRATCH_MEM_SIZE (1024) 69 70 /* Default indirect buffer size. */ 71 #define DMUB_IB_MEM_SIZE (sizeof(struct dmub_fams2_config_v2)) 72 73 /* Default LSDMA ring buffer size. */ 74 #define DMUB_LSDMA_RB_SIZE (64 * 1024) 75 76 /* Number of windows in use. */ 77 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 78 /* Base addresses. */ 79 80 #define DMUB_CW0_BASE (0x60000000) 81 #define DMUB_CW1_BASE (0x61000000) 82 #define DMUB_CW3_BASE (0x63000000) 83 #define DMUB_CW4_BASE (0x64000000) 84 #define DMUB_CW5_BASE (0x65000000) 85 #define DMUB_CW6_BASE (0x66000000) 86 87 #define DMUB_REGION5_BASE (0xA0000000) 88 #define DMUB_REGION6_BASE (0xC0000000) 89 90 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 91 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 92 struct dmub_srv_dcn42_regs dmub_srv_dcn42_regs; 93 94 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 95 { 96 return (val + factor - 1) / factor * factor; 97 } 98 99 void dmub_srv_flush_buffer_mem(struct dmub_srv *dmub, const struct dmub_fb *fb) 100 { 101 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 102 uint8_t buf[64]; 103 uint32_t pos, end; 104 105 /** 106 * Read 64-byte chunks since we don't want to store a 107 * large temporary buffer for this purpose. 108 */ 109 end = fb->size / sizeof(buf) * sizeof(buf); 110 111 for (pos = 0; pos < end; pos += sizeof(buf)) 112 dmub_memcpy(buf, base + pos, sizeof(buf)); 113 114 /* Read anything leftover into the buffer. */ 115 if (end < fb->size) 116 dmub_memcpy(buf, base + pos, fb->size - end); 117 118 (void)dmub; 119 } 120 121 static const struct dmub_fw_meta_info * 122 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 123 { 124 const union dmub_fw_meta *meta; 125 126 if (!blob || !blob_size) 127 return NULL; 128 129 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 130 return NULL; 131 132 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 133 sizeof(union dmub_fw_meta)); 134 135 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 136 return NULL; 137 138 return &meta->info; 139 } 140 141 static const struct dmub_fw_meta_info * 142 dmub_get_fw_meta_info(const struct dmub_srv_fw_meta_info_params *params) 143 { 144 const struct dmub_fw_meta_info *info = NULL; 145 146 if (params->fw_bss_data && params->bss_data_size) { 147 /* Legacy metadata region. */ 148 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 149 params->bss_data_size, 150 DMUB_FW_META_OFFSET); 151 } else if (params->fw_inst_const && params->inst_const_size) { 152 /* Combined metadata region - can be aligned to 16-bytes. */ 153 uint32_t i; 154 155 for (i = 0; i < 16; ++i) { 156 info = dmub_get_fw_meta_info_from_blob( 157 params->fw_inst_const, params->inst_const_size, i); 158 159 if (info) 160 break; 161 } 162 } 163 164 return info; 165 } 166 167 enum dmub_status 168 dmub_srv_get_fw_meta_info_from_raw_fw(struct dmub_srv_fw_meta_info_params *params, 169 struct dmub_fw_meta_info *fw_info_out) 170 { 171 const struct dmub_fw_meta_info *fw_info = NULL; 172 uint32_t inst_const_size_temp = params->inst_const_size; 173 174 /* First try custom psp footer size, if present */ 175 if (params->custom_psp_footer_size) { 176 params->inst_const_size -= params->custom_psp_footer_size; 177 fw_info = dmub_get_fw_meta_info(params); 178 if (fw_info) { 179 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 180 return DMUB_STATUS_OK; 181 } 182 params->inst_const_size = inst_const_size_temp; 183 } 184 185 /* Try 256-byte psp footer size */ 186 params->inst_const_size -= PSP_FOOTER_BYTES_256; 187 fw_info = dmub_get_fw_meta_info(params); 188 if (fw_info) { 189 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 190 return DMUB_STATUS_OK; 191 } 192 193 /* Try 512-byte psp footer size - final attempt */ 194 params->inst_const_size -= PSP_FOOTER_BYTES_256; // 256 bytes already subtracted, subtract 256 again 195 fw_info = dmub_get_fw_meta_info(params); 196 if (fw_info) { 197 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 198 return DMUB_STATUS_OK; 199 } 200 201 /* Restore original inst_const_size and subtract default PSP footer size - default behaviour */ 202 params->inst_const_size = inst_const_size_temp - PSP_FOOTER_BYTES_256; 203 204 return DMUB_STATUS_INVALID; 205 } 206 207 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 208 { 209 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 210 211 /* default to specifying now inbox type */ 212 enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 213 214 switch (asic) { 215 case DMUB_ASIC_DCN20: 216 case DMUB_ASIC_DCN21: 217 case DMUB_ASIC_DCN30: 218 case DMUB_ASIC_DCN301: 219 case DMUB_ASIC_DCN302: 220 case DMUB_ASIC_DCN303: 221 dmub->regs = &dmub_srv_dcn20_regs; 222 223 funcs->reset = dmub_dcn20_reset; 224 funcs->reset_release = dmub_dcn20_reset_release; 225 funcs->backdoor_load = dmub_dcn20_backdoor_load; 226 funcs->setup_windows = dmub_dcn20_setup_windows; 227 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 228 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 229 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 230 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 231 funcs->is_supported = dmub_dcn20_is_supported; 232 funcs->is_hw_init = dmub_dcn20_is_hw_init; 233 funcs->set_gpint = dmub_dcn20_set_gpint; 234 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 235 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 236 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 237 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 238 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 239 funcs->get_current_time = dmub_dcn20_get_current_time; 240 241 // Out mailbox register access functions for RN and above 242 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 243 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 244 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 245 246 //outbox0 call stacks 247 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 248 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 249 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 250 251 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 252 253 if (asic == DMUB_ASIC_DCN21) 254 dmub->regs = &dmub_srv_dcn21_regs; 255 256 if (asic == DMUB_ASIC_DCN30) { 257 dmub->regs = &dmub_srv_dcn30_regs; 258 259 funcs->backdoor_load = dmub_dcn30_backdoor_load; 260 funcs->setup_windows = dmub_dcn30_setup_windows; 261 } 262 if (asic == DMUB_ASIC_DCN301) { 263 dmub->regs = &dmub_srv_dcn301_regs; 264 265 funcs->backdoor_load = dmub_dcn30_backdoor_load; 266 funcs->setup_windows = dmub_dcn30_setup_windows; 267 } 268 if (asic == DMUB_ASIC_DCN302) { 269 dmub->regs = &dmub_srv_dcn302_regs; 270 271 funcs->backdoor_load = dmub_dcn30_backdoor_load; 272 funcs->setup_windows = dmub_dcn30_setup_windows; 273 } 274 if (asic == DMUB_ASIC_DCN303) { 275 dmub->regs = &dmub_srv_dcn303_regs; 276 277 funcs->backdoor_load = dmub_dcn30_backdoor_load; 278 funcs->setup_windows = dmub_dcn30_setup_windows; 279 } 280 break; 281 282 case DMUB_ASIC_DCN31: 283 case DMUB_ASIC_DCN31B: 284 case DMUB_ASIC_DCN314: 285 case DMUB_ASIC_DCN315: 286 case DMUB_ASIC_DCN316: 287 if (asic == DMUB_ASIC_DCN314) { 288 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 289 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 290 } else if (asic == DMUB_ASIC_DCN315) { 291 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 292 } else if (asic == DMUB_ASIC_DCN316) { 293 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 294 } else { 295 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 296 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 297 } 298 funcs->reset = dmub_dcn31_reset; 299 funcs->reset_release = dmub_dcn31_reset_release; 300 funcs->backdoor_load = dmub_dcn31_backdoor_load; 301 funcs->setup_windows = dmub_dcn31_setup_windows; 302 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 303 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 304 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 305 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 306 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 307 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 308 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 309 funcs->is_supported = dmub_dcn31_is_supported; 310 funcs->is_hw_init = dmub_dcn31_is_hw_init; 311 funcs->set_gpint = dmub_dcn31_set_gpint; 312 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 313 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 314 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 315 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 316 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 317 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 318 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 319 //outbox0 call stacks 320 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 321 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 322 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 323 324 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 325 funcs->should_detect = dmub_dcn31_should_detect; 326 funcs->get_current_time = dmub_dcn31_get_current_time; 327 328 break; 329 330 case DMUB_ASIC_DCN32: 331 case DMUB_ASIC_DCN321: 332 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 333 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 334 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 335 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 336 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 337 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 338 funcs->reset = dmub_dcn32_reset; 339 funcs->reset_release = dmub_dcn32_reset_release; 340 funcs->backdoor_load = dmub_dcn32_backdoor_load; 341 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 342 funcs->setup_windows = dmub_dcn32_setup_windows; 343 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 344 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 345 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 346 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 347 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 348 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 349 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 350 funcs->is_supported = dmub_dcn32_is_supported; 351 funcs->is_hw_init = dmub_dcn32_is_hw_init; 352 funcs->set_gpint = dmub_dcn32_set_gpint; 353 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 354 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 355 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 356 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 357 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 358 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 359 360 /* outbox0 call stacks */ 361 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 362 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 363 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 364 funcs->get_current_time = dmub_dcn32_get_current_time; 365 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 366 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 367 368 break; 369 370 case DMUB_ASIC_DCN35: 371 case DMUB_ASIC_DCN351: 372 case DMUB_ASIC_DCN36: 373 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 374 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 375 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 376 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 377 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 378 funcs->reset = dmub_dcn35_reset; 379 funcs->reset_release = dmub_dcn35_reset_release; 380 funcs->backdoor_load = dmub_dcn35_backdoor_load; 381 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 382 funcs->setup_windows = dmub_dcn35_setup_windows; 383 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 384 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 385 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 386 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 387 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 388 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 389 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 390 funcs->is_supported = dmub_dcn35_is_supported; 391 funcs->is_hw_init = dmub_dcn35_is_hw_init; 392 funcs->set_gpint = dmub_dcn35_set_gpint; 393 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 394 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 395 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 396 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 397 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 398 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 399 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 400 //outbox0 call stacks 401 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 402 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 403 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 404 405 funcs->get_current_time = dmub_dcn35_get_current_time; 406 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 407 funcs->get_preos_fw_info = dmub_dcn35_get_preos_fw_info; 408 409 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 410 if (asic == DMUB_ASIC_DCN351) 411 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 412 if (asic == DMUB_ASIC_DCN36) 413 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 414 415 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 416 funcs->should_detect = dmub_dcn35_should_detect; 417 break; 418 case DMUB_ASIC_DCN42: 419 case DMUB_ASIC_DCN42B: 420 dmub->regs_dcn42 = &dmub_srv_dcn42_regs; 421 funcs->configure_dmub_in_system_memory = dmub_dcn42_configure_dmub_in_system_memory; 422 funcs->send_inbox0_cmd = dmub_dcn42_send_inbox0_cmd; 423 funcs->clear_inbox0_ack_register = dmub_dcn42_clear_inbox0_ack_register; 424 funcs->read_inbox0_ack_register = dmub_dcn42_read_inbox0_ack_register; 425 funcs->reset = dmub_dcn42_reset; 426 funcs->reset_release = dmub_dcn42_reset_release; 427 funcs->backdoor_load = dmub_dcn42_backdoor_load; 428 funcs->backdoor_load_zfb_mode = dmub_dcn42_backdoor_load_zfb_mode; 429 funcs->setup_windows = dmub_dcn42_setup_windows; 430 funcs->setup_mailbox = dmub_dcn42_setup_mailbox; 431 funcs->get_inbox1_wptr = dmub_dcn42_get_inbox1_wptr; 432 funcs->get_inbox1_rptr = dmub_dcn42_get_inbox1_rptr; 433 funcs->set_inbox1_wptr = dmub_dcn42_set_inbox1_wptr; 434 funcs->setup_out_mailbox = dmub_dcn42_setup_out_mailbox; 435 funcs->get_outbox1_wptr = dmub_dcn42_get_outbox1_wptr; 436 funcs->set_outbox1_rptr = dmub_dcn42_set_outbox1_rptr; 437 funcs->is_supported = dmub_dcn42_is_supported; 438 funcs->is_hw_init = dmub_dcn42_is_hw_init; 439 funcs->set_gpint = dmub_dcn42_set_gpint; 440 funcs->is_gpint_acked = dmub_dcn42_is_gpint_acked; 441 funcs->get_gpint_response = dmub_dcn42_get_gpint_response; 442 funcs->get_gpint_dataout = dmub_dcn42_get_gpint_dataout; 443 funcs->get_fw_status = dmub_dcn42_get_fw_boot_status; 444 funcs->get_fw_boot_option = dmub_dcn42_get_fw_boot_option; 445 funcs->enable_dmub_boot_options = dmub_dcn42_enable_dmub_boot_options; 446 funcs->skip_dmub_panel_power_sequence = dmub_dcn42_skip_dmub_panel_power_sequence; 447 /*outbox0 call stacks*/ 448 funcs->setup_outbox0 = dmub_dcn42_setup_outbox0; 449 funcs->get_outbox0_wptr = dmub_dcn42_get_outbox0_wptr; 450 funcs->set_outbox0_rptr = dmub_dcn42_set_outbox0_rptr; 451 452 funcs->get_current_time = dmub_dcn42_get_current_time; 453 funcs->get_diagnostic_data = dmub_dcn42_get_diagnostic_data; 454 funcs->get_preos_fw_info = dmub_dcn42_get_preos_fw_info; 455 456 /*carried from dcn401*/ 457 funcs->send_reg_inbox0_cmd_msg = dmub_dcn42_send_reg_inbox0_cmd_msg; 458 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn42_read_reg_inbox0_rsp_int_status; 459 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn42_read_reg_inbox0_cmd_rsp; 460 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn42_write_reg_inbox0_rsp_int_ack; 461 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn42_clear_reg_inbox0_rsp_int_ack; 462 funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; 463 default_inbox_type = DMUB_CMD_INTERFACE_FB; /*still default to FB for now*/ 464 465 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn42_write_reg_outbox0_rdy_int_ack; 466 funcs->read_reg_outbox0_msg = dmub_dcn42_read_reg_outbox0_msg; 467 funcs->write_reg_outbox0_rsp = dmub_dcn42_write_reg_outbox0_rsp; 468 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn42_read_reg_outbox0_rdy_int_status; 469 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn42_read_reg_outbox0_rsp_int_status; 470 funcs->enable_reg_inbox0_rsp_int = dmub_dcn42_enable_reg_inbox0_rsp_int; 471 funcs->enable_reg_outbox0_rdy_int = dmub_dcn42_enable_reg_outbox0_rdy_int; 472 funcs->init_reg_offsets = dmub_srv_dcn42_regs_init; 473 if (asic == DMUB_ASIC_DCN42B) 474 funcs->init_reg_offsets = dmub_srv_dcn42b_regs_init; 475 476 funcs->is_hw_powered_up = dmub_dcn42_is_hw_powered_up; 477 funcs->should_detect = dmub_dcn42_should_detect; 478 break; 479 480 case DMUB_ASIC_DCN401: 481 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 482 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 483 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 484 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 485 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 486 funcs->reset = dmub_dcn401_reset; 487 funcs->reset_release = dmub_dcn401_reset_release; 488 funcs->backdoor_load = dmub_dcn401_backdoor_load; 489 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 490 funcs->setup_windows = dmub_dcn401_setup_windows; 491 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 492 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 493 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 494 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 495 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 496 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 497 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 498 funcs->is_supported = dmub_dcn401_is_supported; 499 funcs->is_hw_init = dmub_dcn401_is_hw_init; 500 funcs->set_gpint = dmub_dcn401_set_gpint; 501 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 502 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 503 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 504 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 505 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 506 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 507 //outbox0 call stacks 508 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 509 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 510 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 511 512 funcs->get_current_time = dmub_dcn401_get_current_time; 513 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 514 515 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 516 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 517 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 518 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 519 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 520 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 521 default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 522 523 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 524 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 525 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 526 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 527 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 528 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 529 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 530 break; 531 default: 532 return false; 533 } 534 535 /* set default inbox type if not overriden */ 536 if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 537 if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 538 /* use default inbox type as specified by DCN rev */ 539 dmub->inbox_type = default_inbox_type; 540 } else if (funcs->send_reg_inbox0_cmd_msg) { 541 /* prefer reg as default inbox type if present */ 542 dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 543 } else { 544 /* use fb as fallback */ 545 dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 546 } 547 } 548 549 return true; 550 } 551 552 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 553 const struct dmub_srv_create_params *params) 554 { 555 enum dmub_status status = DMUB_STATUS_OK; 556 557 dmub_memset(dmub, 0, sizeof(*dmub)); 558 559 dmub->funcs = params->funcs; 560 dmub->user_ctx = params->user_ctx; 561 dmub->asic = params->asic; 562 dmub->fw_version = params->fw_version; 563 dmub->is_virtual = params->is_virtual; 564 dmub->inbox_type = params->inbox_type; 565 566 /* Setup asic dependent hardware funcs. */ 567 if (!dmub_srv_hw_setup(dmub, params->asic)) { 568 status = DMUB_STATUS_INVALID; 569 goto cleanup; 570 } 571 572 /* Override (some) hardware funcs based on user params. */ 573 if (params->hw_funcs) { 574 if (params->hw_funcs->emul_get_inbox1_rptr) 575 dmub->hw_funcs.emul_get_inbox1_rptr = 576 params->hw_funcs->emul_get_inbox1_rptr; 577 578 if (params->hw_funcs->emul_set_inbox1_wptr) 579 dmub->hw_funcs.emul_set_inbox1_wptr = 580 params->hw_funcs->emul_set_inbox1_wptr; 581 582 if (params->hw_funcs->is_supported) 583 dmub->hw_funcs.is_supported = 584 params->hw_funcs->is_supported; 585 } 586 587 /* Sanity checks for required hw func pointers. */ 588 if (!dmub->hw_funcs.get_inbox1_rptr || 589 !dmub->hw_funcs.set_inbox1_wptr) { 590 status = DMUB_STATUS_INVALID; 591 goto cleanup; 592 } 593 594 cleanup: 595 if (status == DMUB_STATUS_OK) 596 dmub->sw_init = true; 597 else 598 dmub_srv_destroy(dmub); 599 600 return status; 601 } 602 603 void dmub_srv_destroy(struct dmub_srv *dmub) 604 { 605 dmub_memset(dmub, 0, sizeof(*dmub)); 606 } 607 608 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 609 struct dmub_srv_region_info *out, 610 const uint32_t *window_sizes, 611 enum dmub_window_memory_type memory_type) 612 { 613 uint32_t i, top = 0; 614 615 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 616 if (params->window_memory_type[i] == memory_type) { 617 struct dmub_region *region = &out->regions[i]; 618 619 region->base = dmub_align(top, 256); 620 region->top = region->base + dmub_align(window_sizes[i], 64); 621 top = region->top; 622 } 623 } 624 625 return dmub_align(top, 4096); 626 } 627 628 enum dmub_status 629 dmub_srv_calc_region_info(struct dmub_srv *dmub, 630 const struct dmub_srv_region_params *params, 631 struct dmub_srv_region_info *out) 632 { 633 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 634 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 635 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 636 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 637 638 if (!dmub->sw_init) 639 return DMUB_STATUS_INVALID; 640 641 memset(out, 0, sizeof(*out)); 642 memset(window_sizes, 0, sizeof(window_sizes)); 643 644 out->num_regions = DMUB_NUM_WINDOWS; 645 646 if (params->fw_info) { 647 memcpy(&dmub->meta_info, params->fw_info, sizeof(*params->fw_info)); 648 649 fw_state_size = params->fw_info->fw_region_size; 650 trace_buffer_size = params->fw_info->trace_buffer_size; 651 shared_state_size = params->fw_info->shared_state_size; 652 653 /** 654 * If DM didn't fill in a version, then fill it in based on 655 * the firmware meta now that we have it. 656 * 657 * TODO: Make it easier for driver to extract this out to 658 * pass during creation. 659 */ 660 if (dmub->fw_version == 0) 661 dmub->fw_version = params->fw_info->fw_version; 662 } 663 664 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 665 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 666 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 667 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 668 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 669 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 670 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 671 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64); 672 window_sizes[DMUB_WINDOW_IB_MEM] = dmub_align(DMUB_IB_MEM_SIZE, 64); 673 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 674 window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE; 675 window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64); 676 677 out->fb_size = 678 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 679 680 out->gart_size = 681 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 682 683 return DMUB_STATUS_OK; 684 } 685 686 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 687 const struct dmub_srv_memory_params *params, 688 struct dmub_srv_fb_info *out) 689 { 690 uint32_t i; 691 692 if (!dmub->sw_init) 693 return DMUB_STATUS_INVALID; 694 695 memset(out, 0, sizeof(*out)); 696 697 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 698 return DMUB_STATUS_INVALID; 699 700 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 701 const struct dmub_region *reg = 702 ¶ms->region_info->regions[i]; 703 704 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 705 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 706 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 707 } else { 708 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 709 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 710 } 711 712 out->fb[i].size = reg->top - reg->base; 713 } 714 715 out->num_fb = DMUB_NUM_WINDOWS; 716 717 return DMUB_STATUS_OK; 718 } 719 720 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 721 bool *is_supported) 722 { 723 *is_supported = false; 724 725 if (!dmub->sw_init) 726 return DMUB_STATUS_INVALID; 727 728 if (dmub->hw_funcs.is_supported) 729 *is_supported = dmub->hw_funcs.is_supported(dmub); 730 731 return DMUB_STATUS_OK; 732 } 733 734 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 735 { 736 *is_hw_init = false; 737 738 if (!dmub->sw_init) 739 return DMUB_STATUS_INVALID; 740 741 if (!dmub->hw_init) 742 return DMUB_STATUS_OK; 743 744 if (dmub->hw_funcs.is_hw_init) 745 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 746 747 return DMUB_STATUS_OK; 748 } 749 750 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 751 const struct dmub_srv_hw_params *params) 752 { 753 struct dmub_fb *inst_fb; 754 struct dmub_fb *stack_fb; 755 struct dmub_fb *data_fb; 756 struct dmub_fb *bios_fb; 757 struct dmub_fb *mail_fb; 758 struct dmub_fb *tracebuff_fb; 759 struct dmub_fb *fw_state_fb; 760 struct dmub_fb *shared_state_fb; 761 762 struct dmub_rb_init_params rb_params, outbox0_rb_params; 763 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 764 struct dmub_region inbox1, outbox1, outbox0; 765 766 if (!dmub->sw_init) 767 return DMUB_STATUS_INVALID; 768 769 if (!params->fb_info || params->fb_info->num_fb < DMUB_WINDOW_TOTAL) { 770 ASSERT(0); 771 return DMUB_STATUS_INVALID; 772 } 773 774 inst_fb = ¶ms->fb_info->fb[DMUB_WINDOW_0_INST_CONST]; 775 stack_fb = ¶ms->fb_info->fb[DMUB_WINDOW_1_STACK]; 776 data_fb = ¶ms->fb_info->fb[DMUB_WINDOW_2_BSS_DATA]; 777 bios_fb = ¶ms->fb_info->fb[DMUB_WINDOW_3_VBIOS]; 778 mail_fb = ¶ms->fb_info->fb[DMUB_WINDOW_4_MAILBOX]; 779 tracebuff_fb = ¶ms->fb_info->fb[DMUB_WINDOW_5_TRACEBUFF]; 780 fw_state_fb = ¶ms->fb_info->fb[DMUB_WINDOW_6_FW_STATE]; 781 shared_state_fb = ¶ms->fb_info->fb[DMUB_WINDOW_SHARED_STATE]; 782 783 dmub->fb_info = params->fb_info; 784 785 memcpy(&dmub->soc_fb_info, ¶ms->soc_fb_info, sizeof(params->soc_fb_info)); 786 dmub->psp_version = params->psp_version; 787 788 if (dmub->hw_funcs.reset) 789 dmub->hw_funcs.reset(dmub); 790 791 /* reset the cache of the last wptr as well now that hw is reset */ 792 dmub->inbox1_last_wptr = 0; 793 794 cw0.offset.quad_part = inst_fb->gpu_addr; 795 cw0.region.base = DMUB_CW0_BASE; 796 cw0.region.top = cw0.region.base + inst_fb->size - 1; 797 798 cw1.offset.quad_part = stack_fb->gpu_addr; 799 cw1.region.base = DMUB_CW1_BASE; 800 cw1.region.top = cw1.region.base + stack_fb->size - 1; 801 802 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 803 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 804 805 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 806 /** 807 * Read back all the instruction memory so we don't hang the 808 * DMCUB when backdoor loading if the write from x86 hasn't been 809 * flushed yet. This only occurs in backdoor loading. 810 */ 811 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 812 dmub_srv_flush_buffer_mem(dmub, inst_fb); 813 814 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 815 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 816 else 817 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 818 } 819 820 cw2.offset.quad_part = data_fb->gpu_addr; 821 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 822 cw2.region.top = cw2.region.base + data_fb->size; 823 824 cw3.offset.quad_part = bios_fb->gpu_addr; 825 cw3.region.base = DMUB_CW3_BASE; 826 cw3.region.top = cw3.region.base + bios_fb->size; 827 828 cw4.offset.quad_part = mail_fb->gpu_addr; 829 cw4.region.base = DMUB_CW4_BASE; 830 cw4.region.top = cw4.region.base + mail_fb->size; 831 832 /** 833 * Doubled the mailbox region to accomodate inbox and outbox. 834 * Note: Currently, currently total mailbox size is 16KB. It is split 835 * equally into 8KB between inbox and outbox. If this config is 836 * changed, then uncached base address configuration of outbox1 837 * has to be updated in funcs->setup_out_mailbox. 838 */ 839 inbox1.base = cw4.region.base; 840 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 841 outbox1.base = inbox1.top; 842 outbox1.top = inbox1.top + DMUB_RB_SIZE; 843 844 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 845 cw5.region.base = DMUB_CW5_BASE; 846 cw5.region.top = cw5.region.base + tracebuff_fb->size; 847 848 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 849 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 850 851 cw6.offset.quad_part = fw_state_fb->gpu_addr; 852 cw6.region.base = DMUB_CW6_BASE; 853 cw6.region.top = cw6.region.base + fw_state_fb->size; 854 855 dmub->fw_state = (void *)((uintptr_t)(fw_state_fb->cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET); 856 857 region6.offset.quad_part = shared_state_fb->gpu_addr; 858 region6.region.base = DMUB_CW6_BASE; 859 region6.region.top = region6.region.base + shared_state_fb->size; 860 861 dmub->shared_state = shared_state_fb->cpu_addr; 862 863 dmub->scratch_mem_fb = params->fb_info->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 864 dmub->ib_mem_gart = params->fb_info->fb[DMUB_WINDOW_IB_MEM]; 865 866 dmub->cursor_offload_fb = params->fb_info->fb[DMUB_WINDOW_CURSOR_OFFLOAD]; 867 dmub->cursor_offload_v1 = (struct dmub_cursor_offload_v1 *)dmub->cursor_offload_fb.cpu_addr; 868 869 if (dmub->hw_funcs.setup_windows) 870 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 871 872 if (dmub->hw_funcs.setup_outbox0) 873 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 874 875 if (dmub->hw_funcs.setup_mailbox) 876 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 877 if (dmub->hw_funcs.setup_out_mailbox) 878 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 879 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 880 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 881 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 882 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 883 884 dmub_memset(&rb_params, 0, sizeof(rb_params)); 885 rb_params.ctx = dmub; 886 rb_params.base_address = mail_fb->cpu_addr; 887 rb_params.capacity = DMUB_RB_SIZE; 888 dmub_rb_init(&dmub->inbox1.rb, &rb_params); 889 890 // Initialize outbox1 ring buffer 891 rb_params.ctx = dmub; 892 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 893 rb_params.capacity = DMUB_RB_SIZE; 894 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 895 896 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 897 outbox0_rb_params.ctx = dmub; 898 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 899 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 900 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 901 902 /* Report to DMUB what features are supported by current driver */ 903 if (dmub->hw_funcs.enable_dmub_boot_options) 904 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 905 906 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 907 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 908 params->skip_panel_power_sequence); 909 910 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 911 dmub->hw_funcs.reset_release(dmub); 912 913 dmub->hw_init = true; 914 dmub->power_state = DMUB_POWER_STATE_D0; 915 916 return DMUB_STATUS_OK; 917 } 918 919 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 920 { 921 if (!dmub->sw_init) 922 return DMUB_STATUS_INVALID; 923 924 if (dmub->hw_funcs.reset) 925 dmub->hw_funcs.reset(dmub); 926 927 /* mailboxes have been reset in hw, so reset the sw state as well */ 928 dmub->inbox1_last_wptr = 0; 929 dmub->inbox1.rb.wrpt = 0; 930 dmub->inbox1.rb.rptr = 0; 931 dmub->inbox1.num_reported = 0; 932 dmub->inbox1.num_submitted = 0; 933 dmub->reg_inbox0.num_reported = 0; 934 dmub->reg_inbox0.num_submitted = 0; 935 dmub->reg_inbox0.is_pending = 0; 936 dmub->outbox0_rb.wrpt = 0; 937 dmub->outbox0_rb.rptr = 0; 938 dmub->outbox1_rb.wrpt = 0; 939 dmub->outbox1_rb.rptr = 0; 940 941 dmub->hw_init = false; 942 943 return DMUB_STATUS_OK; 944 } 945 946 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 947 const union dmub_rb_cmd *cmd) 948 { 949 if (!dmub->hw_init) 950 return DMUB_STATUS_INVALID; 951 952 if (dmub->power_state != DMUB_POWER_STATE_D0) 953 return DMUB_STATUS_POWER_STATE_D3; 954 955 if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 956 dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 957 return DMUB_STATUS_HW_FAILURE; 958 } 959 960 if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 961 dmub->inbox1.num_submitted++; 962 return DMUB_STATUS_OK; 963 } 964 965 return DMUB_STATUS_QUEUE_FULL; 966 } 967 968 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 969 { 970 struct dmub_rb flush_rb; 971 972 if (!dmub->hw_init) 973 return DMUB_STATUS_INVALID; 974 975 if (dmub->power_state != DMUB_POWER_STATE_D0) 976 return DMUB_STATUS_POWER_STATE_D3; 977 978 /** 979 * Read back all the queued commands to ensure that they've 980 * been flushed to framebuffer memory. Otherwise DMCUB might 981 * read back stale, fully invalid or partially invalid data. 982 */ 983 flush_rb = dmub->inbox1.rb; 984 flush_rb.rptr = dmub->inbox1_last_wptr; 985 dmub_rb_flush_pending(&flush_rb); 986 987 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 988 989 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 990 991 return DMUB_STATUS_OK; 992 } 993 994 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 995 { 996 if (!dmub->hw_funcs.is_hw_powered_up) 997 return true; 998 999 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 1000 return false; 1001 1002 return true; 1003 } 1004 1005 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 1006 uint32_t timeout_us) 1007 { 1008 uint32_t i; 1009 1010 if (!dmub->hw_init) 1011 return DMUB_STATUS_INVALID; 1012 1013 for (i = 0; i <= timeout_us; i += 100) { 1014 if (dmub_srv_is_hw_pwr_up(dmub)) 1015 return DMUB_STATUS_OK; 1016 1017 udelay(100); 1018 } 1019 1020 return DMUB_STATUS_TIMEOUT; 1021 } 1022 1023 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 1024 uint32_t timeout_us) 1025 { 1026 const uint32_t delay_us = 100; 1027 uint32_t i; 1028 bool hw_on = true; 1029 1030 if (!dmub->hw_init) 1031 return DMUB_STATUS_INVALID; 1032 1033 for (i = 0; i <= timeout_us; i += delay_us) { 1034 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 1035 1036 if (dmub->hw_funcs.is_hw_powered_up) 1037 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 1038 1039 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 1040 return DMUB_STATUS_OK; 1041 1042 udelay(delay_us); 1043 } 1044 1045 return DMUB_STATUS_TIMEOUT; 1046 } 1047 1048 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 1049 { 1050 if (dmub->reg_inbox0.is_pending) { 1051 dmub->reg_inbox0.is_pending = (dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 1052 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub)) != 0; 1053 1054 if (!dmub->reg_inbox0.is_pending) { 1055 /* ack the rsp interrupt */ 1056 if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 1057 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 1058 1059 /* only update the reported count if commands aren't being batched */ 1060 if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 1061 dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 1062 } 1063 } 1064 } 1065 } 1066 1067 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 1068 uint32_t timeout_us) 1069 { 1070 uint32_t i; 1071 const uint32_t polling_interval_us = 1; 1072 struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 1073 struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 1074 const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 1075 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 1076 1077 if (!dmub->hw_init || 1078 !dmub->hw_funcs.get_inbox1_wptr) 1079 return DMUB_STATUS_INVALID; 1080 1081 for (i = 0; i <= timeout_us; i += polling_interval_us) { 1082 scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 1083 scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1084 1085 scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 1086 dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 1087 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1088 1089 if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 1090 return DMUB_STATUS_HW_FAILURE; 1091 1092 /* check current HW state first, but use command submission vs reported as a fallback */ 1093 if ((dmub_rb_empty(&scratch_inbox1.rb) || 1094 inbox1->num_reported >= scratch_inbox1.num_submitted) && 1095 (!scratch_reg_inbox0.is_pending || 1096 reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 1097 return DMUB_STATUS_OK; 1098 1099 udelay(polling_interval_us); 1100 } 1101 1102 return DMUB_STATUS_TIMEOUT; 1103 } 1104 1105 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 1106 uint32_t timeout_us) 1107 { 1108 enum dmub_status status; 1109 uint32_t i; 1110 const uint32_t polling_interval_us = 1; 1111 1112 if (!dmub->hw_init) 1113 return DMUB_STATUS_INVALID; 1114 1115 for (i = 0; i < timeout_us; i += polling_interval_us) { 1116 status = dmub_srv_update_inbox_status(dmub); 1117 1118 if (status != DMUB_STATUS_OK) 1119 return status; 1120 1121 /* check for idle */ 1122 if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 1123 return DMUB_STATUS_OK; 1124 1125 udelay(polling_interval_us); 1126 } 1127 1128 return DMUB_STATUS_TIMEOUT; 1129 } 1130 1131 enum dmub_status 1132 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 1133 enum dmub_gpint_command command_code, 1134 uint16_t param, uint32_t timeout_us) 1135 { 1136 union dmub_gpint_data_register reg; 1137 uint32_t i; 1138 1139 if (!dmub->sw_init) 1140 return DMUB_STATUS_INVALID; 1141 1142 if (!dmub->hw_funcs.set_gpint) 1143 return DMUB_STATUS_INVALID; 1144 1145 if (!dmub->hw_funcs.is_gpint_acked) 1146 return DMUB_STATUS_INVALID; 1147 1148 reg.bits.status = 1; 1149 reg.bits.command_code = command_code; 1150 reg.bits.param = param; 1151 1152 dmub->hw_funcs.set_gpint(dmub, reg); 1153 1154 for (i = 0; i < timeout_us; ++i) { 1155 udelay(1); 1156 1157 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 1158 return DMUB_STATUS_OK; 1159 } 1160 1161 return DMUB_STATUS_TIMEOUT; 1162 } 1163 1164 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 1165 uint32_t *response) 1166 { 1167 *response = 0; 1168 1169 if (!dmub->sw_init) 1170 return DMUB_STATUS_INVALID; 1171 1172 if (!dmub->hw_funcs.get_gpint_response) 1173 return DMUB_STATUS_INVALID; 1174 1175 *response = dmub->hw_funcs.get_gpint_response(dmub); 1176 1177 return DMUB_STATUS_OK; 1178 } 1179 1180 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 1181 uint32_t *dataout) 1182 { 1183 *dataout = 0; 1184 1185 if (!dmub->sw_init) 1186 return DMUB_STATUS_INVALID; 1187 1188 if (!dmub->hw_funcs.get_gpint_dataout) 1189 return DMUB_STATUS_INVALID; 1190 1191 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 1192 1193 return DMUB_STATUS_OK; 1194 } 1195 1196 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1197 union dmub_fw_boot_status *status) 1198 { 1199 status->all = 0; 1200 1201 if (!dmub->sw_init) 1202 return DMUB_STATUS_INVALID; 1203 1204 if (dmub->hw_funcs.get_fw_status) 1205 *status = dmub->hw_funcs.get_fw_status(dmub); 1206 1207 return DMUB_STATUS_OK; 1208 } 1209 1210 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1211 union dmub_fw_boot_options *option) 1212 { 1213 option->all = 0; 1214 1215 if (!dmub->sw_init) 1216 return DMUB_STATUS_INVALID; 1217 1218 if (dmub->hw_funcs.get_fw_boot_option) 1219 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1220 1221 return DMUB_STATUS_OK; 1222 } 1223 1224 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1225 bool skip) 1226 { 1227 if (!dmub->sw_init) 1228 return DMUB_STATUS_INVALID; 1229 1230 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1231 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1232 1233 return DMUB_STATUS_OK; 1234 } 1235 1236 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1237 void *entry) 1238 { 1239 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1240 uint64_t *dst = (uint64_t *)entry; 1241 uint8_t i; 1242 uint8_t loop_count; 1243 1244 if (rb->rptr == rb->wrpt) 1245 return false; 1246 1247 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1248 // copying data 1249 for (i = 0; i < loop_count; i++) 1250 *dst++ = *src++; 1251 1252 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1253 1254 rb->rptr %= rb->capacity; 1255 1256 return true; 1257 } 1258 1259 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1260 { 1261 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1262 1263 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1264 } 1265 1266 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1267 { 1268 if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1269 return false; 1270 dmub->hw_funcs.get_diagnostic_data(dmub); 1271 1272 return true; 1273 } 1274 1275 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1276 { 1277 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1278 return false; 1279 1280 return dmub->hw_funcs.should_detect(dmub); 1281 } 1282 1283 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1284 { 1285 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1286 return DMUB_STATUS_INVALID; 1287 1288 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1289 return DMUB_STATUS_OK; 1290 } 1291 1292 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1293 { 1294 uint32_t i = 0; 1295 uint32_t ack = 0; 1296 1297 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1298 return DMUB_STATUS_INVALID; 1299 1300 for (i = 0; i <= timeout_us; i++) { 1301 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1302 if (ack) 1303 return DMUB_STATUS_OK; 1304 udelay(1); 1305 } 1306 return DMUB_STATUS_TIMEOUT; 1307 } 1308 1309 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1310 union dmub_inbox0_data_register data) 1311 { 1312 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1313 return DMUB_STATUS_INVALID; 1314 1315 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1316 return DMUB_STATUS_OK; 1317 } 1318 1319 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1320 { 1321 if (dmub->hw_funcs.subvp_save_surf_addr) { 1322 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1323 addr, 1324 subvp_index); 1325 } 1326 } 1327 1328 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1329 { 1330 if (!dmub || !dmub->hw_init) 1331 return; 1332 1333 dmub->power_state = dmub_srv_power_state; 1334 } 1335 1336 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1337 { 1338 uint64_t num_pending = 0; 1339 1340 if (!dmub->hw_init) 1341 return DMUB_STATUS_INVALID; 1342 1343 if (dmub->power_state != DMUB_POWER_STATE_D0) 1344 return DMUB_STATUS_POWER_STATE_D3; 1345 1346 if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1347 !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1348 return DMUB_STATUS_INVALID; 1349 1350 if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1351 num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1352 else 1353 /* num_submitted wrapped */ 1354 num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1355 (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1356 1357 if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1358 return DMUB_STATUS_QUEUE_FULL; 1359 1360 /* clear last rsp ack and send message */ 1361 dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1362 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1363 1364 dmub->reg_inbox0.num_submitted++; 1365 dmub->reg_inbox0.is_pending = true; 1366 dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending != 0; 1367 1368 return DMUB_STATUS_OK; 1369 } 1370 1371 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1372 union dmub_rb_cmd *cmd_rsp) 1373 { 1374 if (dmub) { 1375 if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1376 dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1377 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1378 } else { 1379 dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1380 } 1381 } 1382 } 1383 1384 static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1385 { 1386 if (!dmub || !dmub->sw_init) 1387 return DMUB_STATUS_INVALID; 1388 1389 dmub->reg_inbox0.is_pending = 0; 1390 dmub->reg_inbox0.is_multi_pending = 0; 1391 1392 return DMUB_STATUS_OK; 1393 } 1394 1395 static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1396 { 1397 if (!dmub->sw_init) 1398 return DMUB_STATUS_INVALID; 1399 1400 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1401 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1402 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1403 1404 if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1405 return DMUB_STATUS_HW_FAILURE; 1406 } else { 1407 dmub->inbox1.rb.rptr = rptr; 1408 dmub->inbox1.rb.wrpt = wptr; 1409 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1410 } 1411 } 1412 1413 return DMUB_STATUS_OK; 1414 } 1415 1416 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1417 { 1418 enum dmub_status status; 1419 1420 status = dmub_srv_sync_reg_inbox0(dmub); 1421 if (status != DMUB_STATUS_OK) 1422 return status; 1423 1424 status = dmub_srv_sync_inbox1(dmub); 1425 if (status != DMUB_STATUS_OK) 1426 return status; 1427 1428 return DMUB_STATUS_OK; 1429 } 1430 1431 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1432 uint32_t timeout_us, 1433 uint32_t num_free_required) 1434 { 1435 enum dmub_status status; 1436 uint32_t i; 1437 const uint32_t polling_interval_us = 1; 1438 1439 if (!dmub->hw_init) 1440 return DMUB_STATUS_INVALID; 1441 1442 for (i = 0; i < timeout_us; i += polling_interval_us) { 1443 status = dmub_srv_update_inbox_status(dmub); 1444 1445 if (status != DMUB_STATUS_OK) 1446 return status; 1447 1448 /* check for space in inbox1 */ 1449 if (dmub_rb_num_free(&dmub->inbox1.rb) >= num_free_required) 1450 return DMUB_STATUS_OK; 1451 1452 udelay(polling_interval_us); 1453 } 1454 1455 return DMUB_STATUS_TIMEOUT; 1456 } 1457 1458 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) 1459 { 1460 uint32_t rptr; 1461 1462 if (!dmub->hw_init) 1463 return DMUB_STATUS_INVALID; 1464 1465 if (dmub->power_state != DMUB_POWER_STATE_D0) 1466 return DMUB_STATUS_POWER_STATE_D3; 1467 1468 /* update inbox1 state */ 1469 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1470 1471 if (rptr > dmub->inbox1.rb.capacity) 1472 return DMUB_STATUS_HW_FAILURE; 1473 1474 if (dmub->inbox1.rb.rptr > rptr) { 1475 /* rb wrapped */ 1476 dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1477 } else { 1478 dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1479 } 1480 dmub->inbox1.rb.rptr = rptr; 1481 1482 /* update reg_inbox0 */ 1483 dmub_srv_update_reg_inbox0_status(dmub); 1484 1485 return DMUB_STATUS_OK; 1486 } 1487 1488 bool dmub_srv_get_preos_info(struct dmub_srv *dmub) 1489 { 1490 if (!dmub || !dmub->hw_funcs.get_preos_fw_info) 1491 return false; 1492 1493 return dmub->hw_funcs.get_preos_fw_info(dmub); 1494 } 1495