1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "os_types.h" 34 /* 35 * Note: the DMUB service is standalone. No additional headers should be 36 * added below or above this line unless they reside within the DMUB 37 * folder. 38 */ 39 40 /* Alignment for framebuffer memory. */ 41 #define DMUB_FB_ALIGNMENT (1024 * 1024) 42 43 /* Stack size. */ 44 #define DMUB_STACK_SIZE (128 * 1024) 45 46 /* Context size. */ 47 #define DMUB_CONTEXT_SIZE (512 * 1024) 48 49 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 50 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 51 52 /* Default state size if meta is absent. */ 53 #define DMUB_FW_STATE_SIZE (64 * 1024) 54 55 /* Default tracebuffer size if meta is absent. */ 56 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 57 58 /* Default scratch mem size. */ 59 #define DMUB_SCRATCH_MEM_SIZE (256) 60 61 /* Number of windows in use. */ 62 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 63 /* Base addresses. */ 64 65 #define DMUB_CW0_BASE (0x60000000) 66 #define DMUB_CW1_BASE (0x61000000) 67 #define DMUB_CW3_BASE (0x63000000) 68 #define DMUB_CW4_BASE (0x64000000) 69 #define DMUB_CW5_BASE (0x65000000) 70 #define DMUB_CW6_BASE (0x66000000) 71 72 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 73 { 74 return (val + factor - 1) / factor * factor; 75 } 76 77 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 78 { 79 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 80 uint8_t buf[64]; 81 uint32_t pos, end; 82 83 /** 84 * Read 64-byte chunks since we don't want to store a 85 * large temporary buffer for this purpose. 86 */ 87 end = fb->size / sizeof(buf) * sizeof(buf); 88 89 for (pos = 0; pos < end; pos += sizeof(buf)) 90 dmub_memcpy(buf, base + pos, sizeof(buf)); 91 92 /* Read anything leftover into the buffer. */ 93 if (end < fb->size) 94 dmub_memcpy(buf, base + pos, fb->size - end); 95 } 96 97 static const struct dmub_fw_meta_info * 98 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 99 { 100 const union dmub_fw_meta *meta; 101 const uint8_t *blob = NULL; 102 uint32_t blob_size = 0; 103 uint32_t meta_offset = 0; 104 105 if (params->fw_bss_data && params->bss_data_size) { 106 /* Legacy metadata region. */ 107 blob = params->fw_bss_data; 108 blob_size = params->bss_data_size; 109 meta_offset = DMUB_FW_META_OFFSET; 110 } else if (params->fw_inst_const && params->inst_const_size) { 111 /* Combined metadata region. */ 112 blob = params->fw_inst_const; 113 blob_size = params->inst_const_size; 114 meta_offset = 0; 115 } 116 117 if (!blob || !blob_size) 118 return NULL; 119 120 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 121 return NULL; 122 123 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 124 sizeof(union dmub_fw_meta)); 125 126 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 127 return NULL; 128 129 return &meta->info; 130 } 131 132 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 133 { 134 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 135 136 switch (asic) { 137 case DMUB_ASIC_DCN20: 138 case DMUB_ASIC_DCN21: 139 case DMUB_ASIC_DCN30: 140 case DMUB_ASIC_DCN301: 141 case DMUB_ASIC_DCN302: 142 dmub->regs = &dmub_srv_dcn20_regs; 143 144 funcs->reset = dmub_dcn20_reset; 145 funcs->reset_release = dmub_dcn20_reset_release; 146 funcs->backdoor_load = dmub_dcn20_backdoor_load; 147 funcs->setup_windows = dmub_dcn20_setup_windows; 148 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 149 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 150 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 151 funcs->is_supported = dmub_dcn20_is_supported; 152 funcs->is_hw_init = dmub_dcn20_is_hw_init; 153 funcs->set_gpint = dmub_dcn20_set_gpint; 154 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 155 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 156 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 157 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 158 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 159 160 // Out mailbox register access functions for RN and above 161 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 162 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 163 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 164 165 if (asic == DMUB_ASIC_DCN21) { 166 dmub->regs = &dmub_srv_dcn21_regs; 167 168 funcs->is_phy_init = dmub_dcn21_is_phy_init; 169 } 170 if (asic == DMUB_ASIC_DCN30) { 171 dmub->regs = &dmub_srv_dcn30_regs; 172 173 funcs->backdoor_load = dmub_dcn30_backdoor_load; 174 funcs->setup_windows = dmub_dcn30_setup_windows; 175 } 176 if (asic == DMUB_ASIC_DCN301) { 177 dmub->regs = &dmub_srv_dcn301_regs; 178 179 funcs->backdoor_load = dmub_dcn30_backdoor_load; 180 funcs->setup_windows = dmub_dcn30_setup_windows; 181 } 182 if (asic == DMUB_ASIC_DCN302) { 183 dmub->regs = &dmub_srv_dcn302_regs; 184 185 funcs->backdoor_load = dmub_dcn30_backdoor_load; 186 funcs->setup_windows = dmub_dcn30_setup_windows; 187 } 188 break; 189 190 default: 191 return false; 192 } 193 194 return true; 195 } 196 197 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 198 const struct dmub_srv_create_params *params) 199 { 200 enum dmub_status status = DMUB_STATUS_OK; 201 202 dmub_memset(dmub, 0, sizeof(*dmub)); 203 204 dmub->funcs = params->funcs; 205 dmub->user_ctx = params->user_ctx; 206 dmub->asic = params->asic; 207 dmub->fw_version = params->fw_version; 208 dmub->is_virtual = params->is_virtual; 209 210 /* Setup asic dependent hardware funcs. */ 211 if (!dmub_srv_hw_setup(dmub, params->asic)) { 212 status = DMUB_STATUS_INVALID; 213 goto cleanup; 214 } 215 216 /* Override (some) hardware funcs based on user params. */ 217 if (params->hw_funcs) { 218 if (params->hw_funcs->emul_get_inbox1_rptr) 219 dmub->hw_funcs.emul_get_inbox1_rptr = 220 params->hw_funcs->emul_get_inbox1_rptr; 221 222 if (params->hw_funcs->emul_set_inbox1_wptr) 223 dmub->hw_funcs.emul_set_inbox1_wptr = 224 params->hw_funcs->emul_set_inbox1_wptr; 225 226 if (params->hw_funcs->is_supported) 227 dmub->hw_funcs.is_supported = 228 params->hw_funcs->is_supported; 229 } 230 231 /* Sanity checks for required hw func pointers. */ 232 if (!dmub->hw_funcs.get_inbox1_rptr || 233 !dmub->hw_funcs.set_inbox1_wptr) { 234 status = DMUB_STATUS_INVALID; 235 goto cleanup; 236 } 237 238 cleanup: 239 if (status == DMUB_STATUS_OK) 240 dmub->sw_init = true; 241 else 242 dmub_srv_destroy(dmub); 243 244 return status; 245 } 246 247 void dmub_srv_destroy(struct dmub_srv *dmub) 248 { 249 dmub_memset(dmub, 0, sizeof(*dmub)); 250 } 251 252 enum dmub_status 253 dmub_srv_calc_region_info(struct dmub_srv *dmub, 254 const struct dmub_srv_region_params *params, 255 struct dmub_srv_region_info *out) 256 { 257 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 258 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 259 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 260 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 261 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 262 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 263 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 264 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 265 const struct dmub_fw_meta_info *fw_info; 266 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 267 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 268 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 269 270 if (!dmub->sw_init) 271 return DMUB_STATUS_INVALID; 272 273 memset(out, 0, sizeof(*out)); 274 275 out->num_regions = DMUB_NUM_WINDOWS; 276 277 inst->base = 0x0; 278 inst->top = inst->base + params->inst_const_size; 279 280 data->base = dmub_align(inst->top, 256); 281 data->top = data->base + params->bss_data_size; 282 283 /* 284 * All cache windows below should be aligned to the size 285 * of the DMCUB cache line, 64 bytes. 286 */ 287 288 stack->base = dmub_align(data->top, 256); 289 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 290 291 bios->base = dmub_align(stack->top, 256); 292 bios->top = bios->base + params->vbios_size; 293 294 mail->base = dmub_align(bios->top, 256); 295 mail->top = mail->base + DMUB_MAILBOX_SIZE; 296 297 fw_info = dmub_get_fw_meta_info(params); 298 299 if (fw_info) { 300 fw_state_size = fw_info->fw_region_size; 301 trace_buffer_size = fw_info->trace_buffer_size; 302 303 /** 304 * If DM didn't fill in a version, then fill it in based on 305 * the firmware meta now that we have it. 306 * 307 * TODO: Make it easier for driver to extract this out to 308 * pass during creation. 309 */ 310 if (dmub->fw_version == 0) 311 dmub->fw_version = fw_info->fw_version; 312 } 313 314 trace_buff->base = dmub_align(mail->top, 256); 315 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 316 317 fw_state->base = dmub_align(trace_buff->top, 256); 318 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 319 320 scratch_mem->base = dmub_align(fw_state->top, 256); 321 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 322 323 out->fb_size = dmub_align(scratch_mem->top, 4096); 324 325 return DMUB_STATUS_OK; 326 } 327 328 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 329 const struct dmub_srv_fb_params *params, 330 struct dmub_srv_fb_info *out) 331 { 332 uint8_t *cpu_base; 333 uint64_t gpu_base; 334 uint32_t i; 335 336 if (!dmub->sw_init) 337 return DMUB_STATUS_INVALID; 338 339 memset(out, 0, sizeof(*out)); 340 341 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 342 return DMUB_STATUS_INVALID; 343 344 cpu_base = (uint8_t *)params->cpu_addr; 345 gpu_base = params->gpu_addr; 346 347 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 348 const struct dmub_region *reg = 349 ¶ms->region_info->regions[i]; 350 351 out->fb[i].cpu_addr = cpu_base + reg->base; 352 out->fb[i].gpu_addr = gpu_base + reg->base; 353 out->fb[i].size = reg->top - reg->base; 354 } 355 356 out->num_fb = DMUB_NUM_WINDOWS; 357 358 return DMUB_STATUS_OK; 359 } 360 361 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 362 bool *is_supported) 363 { 364 *is_supported = false; 365 366 if (!dmub->sw_init) 367 return DMUB_STATUS_INVALID; 368 369 if (dmub->hw_funcs.is_supported) 370 *is_supported = dmub->hw_funcs.is_supported(dmub); 371 372 return DMUB_STATUS_OK; 373 } 374 375 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 376 { 377 *is_hw_init = false; 378 379 if (!dmub->sw_init) 380 return DMUB_STATUS_INVALID; 381 382 if (!dmub->hw_init) 383 return DMUB_STATUS_OK; 384 385 if (dmub->hw_funcs.is_hw_init) 386 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 387 388 return DMUB_STATUS_OK; 389 } 390 391 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 392 const struct dmub_srv_hw_params *params) 393 { 394 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 395 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 396 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 397 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 398 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 399 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 400 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 401 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 402 403 struct dmub_rb_init_params rb_params; 404 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 405 struct dmub_region inbox1, outbox1; 406 407 if (!dmub->sw_init) 408 return DMUB_STATUS_INVALID; 409 410 dmub->fb_base = params->fb_base; 411 dmub->fb_offset = params->fb_offset; 412 dmub->psp_version = params->psp_version; 413 414 if (dmub->hw_funcs.reset) 415 dmub->hw_funcs.reset(dmub); 416 417 if (inst_fb && data_fb) { 418 cw0.offset.quad_part = inst_fb->gpu_addr; 419 cw0.region.base = DMUB_CW0_BASE; 420 cw0.region.top = cw0.region.base + inst_fb->size - 1; 421 422 cw1.offset.quad_part = stack_fb->gpu_addr; 423 cw1.region.base = DMUB_CW1_BASE; 424 cw1.region.top = cw1.region.base + stack_fb->size - 1; 425 426 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 427 /** 428 * Read back all the instruction memory so we don't hang the 429 * DMCUB when backdoor loading if the write from x86 hasn't been 430 * flushed yet. This only occurs in backdoor loading. 431 */ 432 dmub_flush_buffer_mem(inst_fb); 433 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 434 } 435 436 } 437 438 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 439 fw_state_fb && scratch_mem_fb) { 440 cw2.offset.quad_part = data_fb->gpu_addr; 441 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 442 cw2.region.top = cw2.region.base + data_fb->size; 443 444 cw3.offset.quad_part = bios_fb->gpu_addr; 445 cw3.region.base = DMUB_CW3_BASE; 446 cw3.region.top = cw3.region.base + bios_fb->size; 447 448 cw4.offset.quad_part = mail_fb->gpu_addr; 449 cw4.region.base = DMUB_CW4_BASE; 450 cw4.region.top = cw4.region.base + mail_fb->size; 451 452 /** 453 * Doubled the mailbox region to accomodate inbox and outbox. 454 * Note: Currently, currently total mailbox size is 16KB. It is split 455 * equally into 8KB between inbox and outbox. If this config is 456 * changed, then uncached base address configuration of outbox1 457 * has to be updated in funcs->setup_out_mailbox. 458 */ 459 inbox1.base = cw4.region.base; 460 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 461 outbox1.base = inbox1.top; 462 outbox1.top = cw4.region.top; 463 464 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 465 cw5.region.base = DMUB_CW5_BASE; 466 cw5.region.top = cw5.region.base + tracebuff_fb->size; 467 468 cw6.offset.quad_part = fw_state_fb->gpu_addr; 469 cw6.region.base = DMUB_CW6_BASE; 470 cw6.region.top = cw6.region.base + fw_state_fb->size; 471 472 dmub->fw_state = fw_state_fb->cpu_addr; 473 474 dmub->scratch_mem_fb = *scratch_mem_fb; 475 476 if (dmub->hw_funcs.setup_windows) 477 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 478 &cw5, &cw6); 479 480 if (dmub->hw_funcs.setup_mailbox) 481 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 482 if (dmub->hw_funcs.setup_out_mailbox) 483 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 484 } 485 486 if (mail_fb) { 487 dmub_memset(&rb_params, 0, sizeof(rb_params)); 488 rb_params.ctx = dmub; 489 rb_params.base_address = mail_fb->cpu_addr; 490 rb_params.capacity = DMUB_RB_SIZE; 491 492 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 493 494 // Initialize outbox1 ring buffer 495 rb_params.ctx = dmub; 496 rb_params.base_address = (void *) ((uint64_t) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 497 rb_params.capacity = DMUB_RB_SIZE; 498 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 499 500 } 501 502 if (dmub->hw_funcs.reset_release) 503 dmub->hw_funcs.reset_release(dmub); 504 505 dmub->hw_init = true; 506 507 return DMUB_STATUS_OK; 508 } 509 510 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 511 { 512 if (!dmub->sw_init) 513 return DMUB_STATUS_INVALID; 514 515 if (dmub->hw_funcs.reset) 516 dmub->hw_funcs.reset(dmub); 517 518 dmub->hw_init = false; 519 520 return DMUB_STATUS_OK; 521 } 522 523 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 524 const union dmub_rb_cmd *cmd) 525 { 526 if (!dmub->hw_init) 527 return DMUB_STATUS_INVALID; 528 529 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 530 return DMUB_STATUS_OK; 531 532 return DMUB_STATUS_QUEUE_FULL; 533 } 534 535 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 536 { 537 if (!dmub->hw_init) 538 return DMUB_STATUS_INVALID; 539 540 /** 541 * Read back all the queued commands to ensure that they've 542 * been flushed to framebuffer memory. Otherwise DMCUB might 543 * read back stale, fully invalid or partially invalid data. 544 */ 545 dmub_rb_flush_pending(&dmub->inbox1_rb); 546 547 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 548 return DMUB_STATUS_OK; 549 } 550 551 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 552 uint32_t timeout_us) 553 { 554 uint32_t i; 555 556 if (!dmub->hw_init) 557 return DMUB_STATUS_INVALID; 558 559 for (i = 0; i <= timeout_us; i += 100) { 560 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 561 562 if (status.bits.dal_fw && status.bits.mailbox_rdy) 563 return DMUB_STATUS_OK; 564 565 udelay(100); 566 } 567 568 return DMUB_STATUS_TIMEOUT; 569 } 570 571 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 572 uint32_t timeout_us) 573 { 574 uint32_t i = 0; 575 576 if (!dmub->hw_init) 577 return DMUB_STATUS_INVALID; 578 579 if (!dmub->hw_funcs.is_phy_init) 580 return DMUB_STATUS_OK; 581 582 for (i = 0; i <= timeout_us; i += 10) { 583 if (dmub->hw_funcs.is_phy_init(dmub)) 584 return DMUB_STATUS_OK; 585 586 udelay(10); 587 } 588 589 return DMUB_STATUS_TIMEOUT; 590 } 591 592 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 593 uint32_t timeout_us) 594 { 595 uint32_t i; 596 597 if (!dmub->hw_init) 598 return DMUB_STATUS_INVALID; 599 600 for (i = 0; i <= timeout_us; ++i) { 601 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 602 if (dmub_rb_empty(&dmub->inbox1_rb)) 603 return DMUB_STATUS_OK; 604 605 udelay(1); 606 } 607 608 return DMUB_STATUS_TIMEOUT; 609 } 610 611 enum dmub_status 612 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 613 enum dmub_gpint_command command_code, 614 uint16_t param, uint32_t timeout_us) 615 { 616 union dmub_gpint_data_register reg; 617 uint32_t i; 618 619 if (!dmub->sw_init) 620 return DMUB_STATUS_INVALID; 621 622 if (!dmub->hw_funcs.set_gpint) 623 return DMUB_STATUS_INVALID; 624 625 if (!dmub->hw_funcs.is_gpint_acked) 626 return DMUB_STATUS_INVALID; 627 628 reg.bits.status = 1; 629 reg.bits.command_code = command_code; 630 reg.bits.param = param; 631 632 dmub->hw_funcs.set_gpint(dmub, reg); 633 634 for (i = 0; i < timeout_us; ++i) { 635 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 636 return DMUB_STATUS_OK; 637 } 638 639 return DMUB_STATUS_TIMEOUT; 640 } 641 642 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 643 uint32_t *response) 644 { 645 *response = 0; 646 647 if (!dmub->sw_init) 648 return DMUB_STATUS_INVALID; 649 650 if (!dmub->hw_funcs.get_gpint_response) 651 return DMUB_STATUS_INVALID; 652 653 *response = dmub->hw_funcs.get_gpint_response(dmub); 654 655 return DMUB_STATUS_OK; 656 } 657 658 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 659 union dmub_fw_boot_status *status) 660 { 661 status->all = 0; 662 663 if (!dmub->sw_init) 664 return DMUB_STATUS_INVALID; 665 666 if (dmub->hw_funcs.get_fw_status) 667 *status = dmub->hw_funcs.get_fw_status(dmub); 668 669 return DMUB_STATUS_OK; 670 } 671 672 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 673 union dmub_rb_cmd *cmd) 674 { 675 enum dmub_status status = DMUB_STATUS_OK; 676 677 // Queue command 678 status = dmub_srv_cmd_queue(dmub, cmd); 679 680 if (status != DMUB_STATUS_OK) 681 return status; 682 683 // Execute command 684 status = dmub_srv_cmd_execute(dmub); 685 686 if (status != DMUB_STATUS_OK) 687 return status; 688 689 // Wait for DMUB to process command 690 status = dmub_srv_wait_for_idle(dmub, 100000); 691 692 if (status != DMUB_STATUS_OK) 693 return status; 694 695 // Copy data back from ring buffer into command 696 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 697 698 return status; 699 } 700