1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn36.h" 42 #include "dmub_dcn401.h" 43 #include "os_types.h" 44 /* 45 * Note: the DMUB service is standalone. No additional headers should be 46 * added below or above this line unless they reside within the DMUB 47 * folder. 48 */ 49 50 /* Alignment for framebuffer memory. */ 51 #define DMUB_FB_ALIGNMENT (1024 * 1024) 52 53 /* Stack size. */ 54 #define DMUB_STACK_SIZE (128 * 1024) 55 56 /* Context size. */ 57 #define DMUB_CONTEXT_SIZE (512 * 1024) 58 59 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 60 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 61 62 /* Default state size if meta is absent. */ 63 #define DMUB_FW_STATE_SIZE (64 * 1024) 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (1024) 67 68 /* Number of windows in use. */ 69 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 70 /* Base addresses. */ 71 72 #define DMUB_CW0_BASE (0x60000000) 73 #define DMUB_CW1_BASE (0x61000000) 74 #define DMUB_CW3_BASE (0x63000000) 75 #define DMUB_CW4_BASE (0x64000000) 76 #define DMUB_CW5_BASE (0x65000000) 77 #define DMUB_CW6_BASE (0x66000000) 78 79 #define DMUB_REGION5_BASE (0xA0000000) 80 #define DMUB_REGION6_BASE (0xC0000000) 81 82 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 83 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 84 85 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 86 { 87 return (val + factor - 1) / factor * factor; 88 } 89 90 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 91 { 92 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 93 uint8_t buf[64]; 94 uint32_t pos, end; 95 96 /** 97 * Read 64-byte chunks since we don't want to store a 98 * large temporary buffer for this purpose. 99 */ 100 end = fb->size / sizeof(buf) * sizeof(buf); 101 102 for (pos = 0; pos < end; pos += sizeof(buf)) 103 dmub_memcpy(buf, base + pos, sizeof(buf)); 104 105 /* Read anything leftover into the buffer. */ 106 if (end < fb->size) 107 dmub_memcpy(buf, base + pos, fb->size - end); 108 } 109 110 static const struct dmub_fw_meta_info * 111 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 112 { 113 const union dmub_fw_meta *meta; 114 115 if (!blob || !blob_size) 116 return NULL; 117 118 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 119 return NULL; 120 121 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 122 sizeof(union dmub_fw_meta)); 123 124 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 125 return NULL; 126 127 return &meta->info; 128 } 129 130 static const struct dmub_fw_meta_info * 131 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 132 { 133 const struct dmub_fw_meta_info *info = NULL; 134 135 if (params->fw_bss_data && params->bss_data_size) { 136 /* Legacy metadata region. */ 137 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 138 params->bss_data_size, 139 DMUB_FW_META_OFFSET); 140 } else if (params->fw_inst_const && params->inst_const_size) { 141 /* Combined metadata region - can be aligned to 16-bytes. */ 142 uint32_t i; 143 144 for (i = 0; i < 16; ++i) { 145 info = dmub_get_fw_meta_info_from_blob( 146 params->fw_inst_const, params->inst_const_size, i); 147 148 if (info) 149 break; 150 } 151 } 152 153 return info; 154 } 155 156 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 157 { 158 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 159 160 /* default to specifying now inbox type */ 161 enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 162 163 switch (asic) { 164 case DMUB_ASIC_DCN20: 165 case DMUB_ASIC_DCN21: 166 case DMUB_ASIC_DCN30: 167 case DMUB_ASIC_DCN301: 168 case DMUB_ASIC_DCN302: 169 case DMUB_ASIC_DCN303: 170 dmub->regs = &dmub_srv_dcn20_regs; 171 172 funcs->reset = dmub_dcn20_reset; 173 funcs->reset_release = dmub_dcn20_reset_release; 174 funcs->backdoor_load = dmub_dcn20_backdoor_load; 175 funcs->setup_windows = dmub_dcn20_setup_windows; 176 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 177 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 178 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 179 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 180 funcs->is_supported = dmub_dcn20_is_supported; 181 funcs->is_hw_init = dmub_dcn20_is_hw_init; 182 funcs->set_gpint = dmub_dcn20_set_gpint; 183 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 184 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 185 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 186 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 187 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 188 funcs->get_current_time = dmub_dcn20_get_current_time; 189 190 // Out mailbox register access functions for RN and above 191 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 192 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 193 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 194 195 //outbox0 call stacks 196 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 197 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 198 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 199 200 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 201 202 if (asic == DMUB_ASIC_DCN21) 203 dmub->regs = &dmub_srv_dcn21_regs; 204 205 if (asic == DMUB_ASIC_DCN30) { 206 dmub->regs = &dmub_srv_dcn30_regs; 207 208 funcs->backdoor_load = dmub_dcn30_backdoor_load; 209 funcs->setup_windows = dmub_dcn30_setup_windows; 210 } 211 if (asic == DMUB_ASIC_DCN301) { 212 dmub->regs = &dmub_srv_dcn301_regs; 213 214 funcs->backdoor_load = dmub_dcn30_backdoor_load; 215 funcs->setup_windows = dmub_dcn30_setup_windows; 216 } 217 if (asic == DMUB_ASIC_DCN302) { 218 dmub->regs = &dmub_srv_dcn302_regs; 219 220 funcs->backdoor_load = dmub_dcn30_backdoor_load; 221 funcs->setup_windows = dmub_dcn30_setup_windows; 222 } 223 if (asic == DMUB_ASIC_DCN303) { 224 dmub->regs = &dmub_srv_dcn303_regs; 225 226 funcs->backdoor_load = dmub_dcn30_backdoor_load; 227 funcs->setup_windows = dmub_dcn30_setup_windows; 228 } 229 break; 230 231 case DMUB_ASIC_DCN31: 232 case DMUB_ASIC_DCN31B: 233 case DMUB_ASIC_DCN314: 234 case DMUB_ASIC_DCN315: 235 case DMUB_ASIC_DCN316: 236 if (asic == DMUB_ASIC_DCN314) { 237 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 238 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 239 } else if (asic == DMUB_ASIC_DCN315) { 240 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 241 } else if (asic == DMUB_ASIC_DCN316) { 242 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 243 } else { 244 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 245 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 246 } 247 funcs->reset = dmub_dcn31_reset; 248 funcs->reset_release = dmub_dcn31_reset_release; 249 funcs->backdoor_load = dmub_dcn31_backdoor_load; 250 funcs->setup_windows = dmub_dcn31_setup_windows; 251 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 252 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 253 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 254 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 255 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 256 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 257 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 258 funcs->is_supported = dmub_dcn31_is_supported; 259 funcs->is_hw_init = dmub_dcn31_is_hw_init; 260 funcs->set_gpint = dmub_dcn31_set_gpint; 261 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 262 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 263 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 264 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 265 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 266 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 267 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 268 //outbox0 call stacks 269 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 270 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 271 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 272 273 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 274 funcs->should_detect = dmub_dcn31_should_detect; 275 funcs->get_current_time = dmub_dcn31_get_current_time; 276 277 break; 278 279 case DMUB_ASIC_DCN32: 280 case DMUB_ASIC_DCN321: 281 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 282 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 283 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 284 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 285 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 286 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 287 funcs->reset = dmub_dcn32_reset; 288 funcs->reset_release = dmub_dcn32_reset_release; 289 funcs->backdoor_load = dmub_dcn32_backdoor_load; 290 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 291 funcs->setup_windows = dmub_dcn32_setup_windows; 292 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 293 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 294 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 295 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 296 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 297 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 298 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 299 funcs->is_supported = dmub_dcn32_is_supported; 300 funcs->is_hw_init = dmub_dcn32_is_hw_init; 301 funcs->set_gpint = dmub_dcn32_set_gpint; 302 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 303 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 304 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 305 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 306 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 307 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 308 309 /* outbox0 call stacks */ 310 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 311 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 312 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 313 funcs->get_current_time = dmub_dcn32_get_current_time; 314 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 315 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 316 317 break; 318 319 case DMUB_ASIC_DCN35: 320 case DMUB_ASIC_DCN351: 321 case DMUB_ASIC_DCN36: 322 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 323 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 324 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 325 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 326 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 327 funcs->reset = dmub_dcn35_reset; 328 funcs->reset_release = dmub_dcn35_reset_release; 329 funcs->backdoor_load = dmub_dcn35_backdoor_load; 330 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 331 funcs->setup_windows = dmub_dcn35_setup_windows; 332 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 333 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 334 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 335 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 336 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 337 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 338 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 339 funcs->is_supported = dmub_dcn35_is_supported; 340 funcs->is_hw_init = dmub_dcn35_is_hw_init; 341 funcs->set_gpint = dmub_dcn35_set_gpint; 342 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 343 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 344 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 345 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 346 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 347 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 348 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 349 //outbox0 call stacks 350 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 351 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 352 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 353 354 funcs->get_current_time = dmub_dcn35_get_current_time; 355 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 356 357 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 358 if (asic == DMUB_ASIC_DCN351) 359 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 360 if (asic == DMUB_ASIC_DCN36) 361 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 362 363 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 364 funcs->should_detect = dmub_dcn35_should_detect; 365 break; 366 367 case DMUB_ASIC_DCN401: 368 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 369 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 370 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 371 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 372 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 373 funcs->reset = dmub_dcn401_reset; 374 funcs->reset_release = dmub_dcn401_reset_release; 375 funcs->backdoor_load = dmub_dcn401_backdoor_load; 376 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 377 funcs->setup_windows = dmub_dcn401_setup_windows; 378 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 379 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 380 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 381 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 382 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 383 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 384 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 385 funcs->is_supported = dmub_dcn401_is_supported; 386 funcs->is_hw_init = dmub_dcn401_is_hw_init; 387 funcs->set_gpint = dmub_dcn401_set_gpint; 388 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 389 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 390 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 391 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 392 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 393 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 394 //outbox0 call stacks 395 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 396 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 397 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 398 399 funcs->get_current_time = dmub_dcn401_get_current_time; 400 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 401 402 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 403 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 404 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 405 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 406 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 407 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 408 default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 409 410 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 411 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 412 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 413 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 414 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 415 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 416 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 417 break; 418 default: 419 return false; 420 } 421 422 /* set default inbox type if not overriden */ 423 if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 424 if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 425 /* use default inbox type as specified by DCN rev */ 426 dmub->inbox_type = default_inbox_type; 427 } else if (funcs->send_reg_inbox0_cmd_msg) { 428 /* prefer reg as default inbox type if present */ 429 dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 430 } else { 431 /* use fb as fallback */ 432 dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 433 } 434 } 435 436 return true; 437 } 438 439 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 440 const struct dmub_srv_create_params *params) 441 { 442 enum dmub_status status = DMUB_STATUS_OK; 443 444 dmub_memset(dmub, 0, sizeof(*dmub)); 445 446 dmub->funcs = params->funcs; 447 dmub->user_ctx = params->user_ctx; 448 dmub->asic = params->asic; 449 dmub->fw_version = params->fw_version; 450 dmub->is_virtual = params->is_virtual; 451 dmub->inbox_type = params->inbox_type; 452 453 /* Setup asic dependent hardware funcs. */ 454 if (!dmub_srv_hw_setup(dmub, params->asic)) { 455 status = DMUB_STATUS_INVALID; 456 goto cleanup; 457 } 458 459 /* Override (some) hardware funcs based on user params. */ 460 if (params->hw_funcs) { 461 if (params->hw_funcs->emul_get_inbox1_rptr) 462 dmub->hw_funcs.emul_get_inbox1_rptr = 463 params->hw_funcs->emul_get_inbox1_rptr; 464 465 if (params->hw_funcs->emul_set_inbox1_wptr) 466 dmub->hw_funcs.emul_set_inbox1_wptr = 467 params->hw_funcs->emul_set_inbox1_wptr; 468 469 if (params->hw_funcs->is_supported) 470 dmub->hw_funcs.is_supported = 471 params->hw_funcs->is_supported; 472 } 473 474 /* Sanity checks for required hw func pointers. */ 475 if (!dmub->hw_funcs.get_inbox1_rptr || 476 !dmub->hw_funcs.set_inbox1_wptr) { 477 status = DMUB_STATUS_INVALID; 478 goto cleanup; 479 } 480 481 cleanup: 482 if (status == DMUB_STATUS_OK) 483 dmub->sw_init = true; 484 else 485 dmub_srv_destroy(dmub); 486 487 return status; 488 } 489 490 void dmub_srv_destroy(struct dmub_srv *dmub) 491 { 492 dmub_memset(dmub, 0, sizeof(*dmub)); 493 } 494 495 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 496 struct dmub_srv_region_info *out, 497 const uint32_t *window_sizes, 498 enum dmub_window_memory_type memory_type) 499 { 500 uint32_t i, top = 0; 501 502 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 503 if (params->window_memory_type[i] == memory_type) { 504 struct dmub_region *region = &out->regions[i]; 505 506 region->base = dmub_align(top, 256); 507 region->top = region->base + dmub_align(window_sizes[i], 64); 508 top = region->top; 509 } 510 } 511 512 return dmub_align(top, 4096); 513 } 514 515 enum dmub_status 516 dmub_srv_calc_region_info(struct dmub_srv *dmub, 517 const struct dmub_srv_region_params *params, 518 struct dmub_srv_region_info *out) 519 { 520 const struct dmub_fw_meta_info *fw_info; 521 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 522 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 523 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 524 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 525 526 if (!dmub->sw_init) 527 return DMUB_STATUS_INVALID; 528 529 memset(out, 0, sizeof(*out)); 530 memset(window_sizes, 0, sizeof(window_sizes)); 531 532 out->num_regions = DMUB_NUM_WINDOWS; 533 534 fw_info = dmub_get_fw_meta_info(params); 535 536 if (fw_info) { 537 memcpy(&dmub->meta_info, fw_info, sizeof(*fw_info)); 538 539 fw_state_size = fw_info->fw_region_size; 540 trace_buffer_size = fw_info->trace_buffer_size; 541 shared_state_size = fw_info->shared_state_size; 542 543 /** 544 * If DM didn't fill in a version, then fill it in based on 545 * the firmware meta now that we have it. 546 * 547 * TODO: Make it easier for driver to extract this out to 548 * pass during creation. 549 */ 550 if (dmub->fw_version == 0) 551 dmub->fw_version = fw_info->fw_version; 552 } 553 554 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 555 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 556 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 557 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 558 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 559 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 560 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 561 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE; 562 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 563 564 out->fb_size = 565 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 566 567 out->gart_size = 568 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 569 570 return DMUB_STATUS_OK; 571 } 572 573 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 574 const struct dmub_srv_memory_params *params, 575 struct dmub_srv_fb_info *out) 576 { 577 uint32_t i; 578 579 if (!dmub->sw_init) 580 return DMUB_STATUS_INVALID; 581 582 memset(out, 0, sizeof(*out)); 583 584 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 585 return DMUB_STATUS_INVALID; 586 587 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 588 const struct dmub_region *reg = 589 ¶ms->region_info->regions[i]; 590 591 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 592 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 593 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 594 } else { 595 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 596 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 597 } 598 599 out->fb[i].size = reg->top - reg->base; 600 } 601 602 out->num_fb = DMUB_NUM_WINDOWS; 603 604 return DMUB_STATUS_OK; 605 } 606 607 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 608 bool *is_supported) 609 { 610 *is_supported = false; 611 612 if (!dmub->sw_init) 613 return DMUB_STATUS_INVALID; 614 615 if (dmub->hw_funcs.is_supported) 616 *is_supported = dmub->hw_funcs.is_supported(dmub); 617 618 return DMUB_STATUS_OK; 619 } 620 621 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 622 { 623 *is_hw_init = false; 624 625 if (!dmub->sw_init) 626 return DMUB_STATUS_INVALID; 627 628 if (!dmub->hw_init) 629 return DMUB_STATUS_OK; 630 631 if (dmub->hw_funcs.is_hw_init) 632 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 633 634 return DMUB_STATUS_OK; 635 } 636 637 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 638 const struct dmub_srv_hw_params *params) 639 { 640 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 641 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 642 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 643 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 644 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 645 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 646 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 647 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 648 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 649 650 struct dmub_rb_init_params rb_params, outbox0_rb_params; 651 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 652 struct dmub_region inbox1, outbox1, outbox0; 653 654 if (!dmub->sw_init) 655 return DMUB_STATUS_INVALID; 656 657 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 658 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 659 ASSERT(0); 660 return DMUB_STATUS_INVALID; 661 } 662 663 dmub->fb_base = params->fb_base; 664 dmub->fb_offset = params->fb_offset; 665 dmub->psp_version = params->psp_version; 666 667 if (dmub->hw_funcs.reset) 668 dmub->hw_funcs.reset(dmub); 669 670 /* reset the cache of the last wptr as well now that hw is reset */ 671 dmub->inbox1_last_wptr = 0; 672 673 cw0.offset.quad_part = inst_fb->gpu_addr; 674 cw0.region.base = DMUB_CW0_BASE; 675 cw0.region.top = cw0.region.base + inst_fb->size - 1; 676 677 cw1.offset.quad_part = stack_fb->gpu_addr; 678 cw1.region.base = DMUB_CW1_BASE; 679 cw1.region.top = cw1.region.base + stack_fb->size - 1; 680 681 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 682 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 683 684 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 685 /** 686 * Read back all the instruction memory so we don't hang the 687 * DMCUB when backdoor loading if the write from x86 hasn't been 688 * flushed yet. This only occurs in backdoor loading. 689 */ 690 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 691 dmub_flush_buffer_mem(inst_fb); 692 693 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 694 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 695 else 696 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 697 } 698 699 cw2.offset.quad_part = data_fb->gpu_addr; 700 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 701 cw2.region.top = cw2.region.base + data_fb->size; 702 703 cw3.offset.quad_part = bios_fb->gpu_addr; 704 cw3.region.base = DMUB_CW3_BASE; 705 cw3.region.top = cw3.region.base + bios_fb->size; 706 707 cw4.offset.quad_part = mail_fb->gpu_addr; 708 cw4.region.base = DMUB_CW4_BASE; 709 cw4.region.top = cw4.region.base + mail_fb->size; 710 711 /** 712 * Doubled the mailbox region to accomodate inbox and outbox. 713 * Note: Currently, currently total mailbox size is 16KB. It is split 714 * equally into 8KB between inbox and outbox. If this config is 715 * changed, then uncached base address configuration of outbox1 716 * has to be updated in funcs->setup_out_mailbox. 717 */ 718 inbox1.base = cw4.region.base; 719 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 720 outbox1.base = inbox1.top; 721 outbox1.top = inbox1.top + DMUB_RB_SIZE; 722 723 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 724 cw5.region.base = DMUB_CW5_BASE; 725 cw5.region.top = cw5.region.base + tracebuff_fb->size; 726 727 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 728 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 729 730 cw6.offset.quad_part = fw_state_fb->gpu_addr; 731 cw6.region.base = DMUB_CW6_BASE; 732 cw6.region.top = cw6.region.base + fw_state_fb->size; 733 734 dmub->fw_state = (void *)((uintptr_t)(fw_state_fb->cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET); 735 736 region6.offset.quad_part = shared_state_fb->gpu_addr; 737 region6.region.base = DMUB_CW6_BASE; 738 region6.region.top = region6.region.base + shared_state_fb->size; 739 740 dmub->shared_state = shared_state_fb->cpu_addr; 741 742 dmub->scratch_mem_fb = *scratch_mem_fb; 743 744 if (dmub->hw_funcs.setup_windows) 745 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 746 747 if (dmub->hw_funcs.setup_outbox0) 748 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 749 750 if (dmub->hw_funcs.setup_mailbox) 751 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 752 if (dmub->hw_funcs.setup_out_mailbox) 753 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 754 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 755 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 756 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 757 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 758 759 dmub_memset(&rb_params, 0, sizeof(rb_params)); 760 rb_params.ctx = dmub; 761 rb_params.base_address = mail_fb->cpu_addr; 762 rb_params.capacity = DMUB_RB_SIZE; 763 dmub_rb_init(&dmub->inbox1.rb, &rb_params); 764 765 // Initialize outbox1 ring buffer 766 rb_params.ctx = dmub; 767 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 768 rb_params.capacity = DMUB_RB_SIZE; 769 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 770 771 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 772 outbox0_rb_params.ctx = dmub; 773 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 774 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 775 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 776 777 /* Report to DMUB what features are supported by current driver */ 778 if (dmub->hw_funcs.enable_dmub_boot_options) 779 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 780 781 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 782 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 783 params->skip_panel_power_sequence); 784 785 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 786 dmub->hw_funcs.reset_release(dmub); 787 788 dmub->hw_init = true; 789 dmub->power_state = DMUB_POWER_STATE_D0; 790 791 return DMUB_STATUS_OK; 792 } 793 794 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 795 { 796 if (!dmub->sw_init) 797 return DMUB_STATUS_INVALID; 798 799 if (dmub->hw_funcs.reset) 800 dmub->hw_funcs.reset(dmub); 801 802 /* mailboxes have been reset in hw, so reset the sw state as well */ 803 dmub->inbox1_last_wptr = 0; 804 dmub->inbox1.rb.wrpt = 0; 805 dmub->inbox1.rb.rptr = 0; 806 dmub->inbox1.num_reported = 0; 807 dmub->inbox1.num_submitted = 0; 808 dmub->reg_inbox0.num_reported = 0; 809 dmub->reg_inbox0.num_submitted = 0; 810 dmub->reg_inbox0.is_pending = 0; 811 dmub->outbox0_rb.wrpt = 0; 812 dmub->outbox0_rb.rptr = 0; 813 dmub->outbox1_rb.wrpt = 0; 814 dmub->outbox1_rb.rptr = 0; 815 816 dmub->hw_init = false; 817 818 return DMUB_STATUS_OK; 819 } 820 821 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 822 const union dmub_rb_cmd *cmd) 823 { 824 if (!dmub->hw_init) 825 return DMUB_STATUS_INVALID; 826 827 if (dmub->power_state != DMUB_POWER_STATE_D0) 828 return DMUB_STATUS_POWER_STATE_D3; 829 830 if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 831 dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 832 return DMUB_STATUS_HW_FAILURE; 833 } 834 835 if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 836 dmub->inbox1.num_submitted++; 837 return DMUB_STATUS_OK; 838 } 839 840 return DMUB_STATUS_QUEUE_FULL; 841 } 842 843 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 844 { 845 struct dmub_rb flush_rb; 846 847 if (!dmub->hw_init) 848 return DMUB_STATUS_INVALID; 849 850 if (dmub->power_state != DMUB_POWER_STATE_D0) 851 return DMUB_STATUS_POWER_STATE_D3; 852 853 /** 854 * Read back all the queued commands to ensure that they've 855 * been flushed to framebuffer memory. Otherwise DMCUB might 856 * read back stale, fully invalid or partially invalid data. 857 */ 858 flush_rb = dmub->inbox1.rb; 859 flush_rb.rptr = dmub->inbox1_last_wptr; 860 dmub_rb_flush_pending(&flush_rb); 861 862 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 863 864 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 865 866 return DMUB_STATUS_OK; 867 } 868 869 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 870 { 871 if (!dmub->hw_funcs.is_hw_powered_up) 872 return true; 873 874 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 875 return false; 876 877 return true; 878 } 879 880 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 881 uint32_t timeout_us) 882 { 883 uint32_t i; 884 885 if (!dmub->hw_init) 886 return DMUB_STATUS_INVALID; 887 888 for (i = 0; i <= timeout_us; i += 100) { 889 if (dmub_srv_is_hw_pwr_up(dmub)) 890 return DMUB_STATUS_OK; 891 892 udelay(100); 893 } 894 895 return DMUB_STATUS_TIMEOUT; 896 } 897 898 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 899 uint32_t timeout_us) 900 { 901 uint32_t i; 902 bool hw_on = true; 903 904 if (!dmub->hw_init) 905 return DMUB_STATUS_INVALID; 906 907 for (i = 0; i <= timeout_us; i += 100) { 908 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 909 910 if (dmub->hw_funcs.is_hw_powered_up) 911 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 912 913 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 914 return DMUB_STATUS_OK; 915 916 udelay(100); 917 } 918 919 return DMUB_STATUS_TIMEOUT; 920 } 921 922 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 923 { 924 if (dmub->reg_inbox0.is_pending) { 925 dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 926 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 927 928 if (!dmub->reg_inbox0.is_pending) { 929 /* ack the rsp interrupt */ 930 if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 931 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 932 933 /* only update the reported count if commands aren't being batched */ 934 if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 935 dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 936 } 937 } 938 } 939 } 940 941 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 942 uint32_t timeout_us) 943 { 944 uint32_t i; 945 const uint32_t polling_interval_us = 1; 946 struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 947 struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 948 const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 949 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 950 951 if (!dmub->hw_init || 952 !dmub->hw_funcs.get_inbox1_wptr) 953 return DMUB_STATUS_INVALID; 954 955 for (i = 0; i <= timeout_us; i += polling_interval_us) { 956 scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 957 scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 958 959 scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 960 dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 961 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 962 963 if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 964 return DMUB_STATUS_HW_FAILURE; 965 966 /* check current HW state first, but use command submission vs reported as a fallback */ 967 if ((dmub_rb_empty(&scratch_inbox1.rb) || 968 inbox1->num_reported >= scratch_inbox1.num_submitted) && 969 (!scratch_reg_inbox0.is_pending || 970 reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 971 return DMUB_STATUS_OK; 972 973 udelay(polling_interval_us); 974 } 975 976 return DMUB_STATUS_TIMEOUT; 977 } 978 979 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 980 uint32_t timeout_us) 981 { 982 enum dmub_status status; 983 uint32_t i; 984 const uint32_t polling_interval_us = 1; 985 986 if (!dmub->hw_init) 987 return DMUB_STATUS_INVALID; 988 989 for (i = 0; i < timeout_us; i += polling_interval_us) { 990 status = dmub_srv_update_inbox_status(dmub); 991 992 if (status != DMUB_STATUS_OK) 993 return status; 994 995 /* check for idle */ 996 if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 997 return DMUB_STATUS_OK; 998 999 udelay(polling_interval_us); 1000 } 1001 1002 return DMUB_STATUS_TIMEOUT; 1003 } 1004 1005 enum dmub_status 1006 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 1007 enum dmub_gpint_command command_code, 1008 uint16_t param, uint32_t timeout_us) 1009 { 1010 union dmub_gpint_data_register reg; 1011 uint32_t i; 1012 1013 if (!dmub->sw_init) 1014 return DMUB_STATUS_INVALID; 1015 1016 if (!dmub->hw_funcs.set_gpint) 1017 return DMUB_STATUS_INVALID; 1018 1019 if (!dmub->hw_funcs.is_gpint_acked) 1020 return DMUB_STATUS_INVALID; 1021 1022 reg.bits.status = 1; 1023 reg.bits.command_code = command_code; 1024 reg.bits.param = param; 1025 1026 dmub->hw_funcs.set_gpint(dmub, reg); 1027 1028 for (i = 0; i < timeout_us; ++i) { 1029 udelay(1); 1030 1031 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 1032 return DMUB_STATUS_OK; 1033 } 1034 1035 return DMUB_STATUS_TIMEOUT; 1036 } 1037 1038 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 1039 uint32_t *response) 1040 { 1041 *response = 0; 1042 1043 if (!dmub->sw_init) 1044 return DMUB_STATUS_INVALID; 1045 1046 if (!dmub->hw_funcs.get_gpint_response) 1047 return DMUB_STATUS_INVALID; 1048 1049 *response = dmub->hw_funcs.get_gpint_response(dmub); 1050 1051 return DMUB_STATUS_OK; 1052 } 1053 1054 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 1055 uint32_t *dataout) 1056 { 1057 *dataout = 0; 1058 1059 if (!dmub->sw_init) 1060 return DMUB_STATUS_INVALID; 1061 1062 if (!dmub->hw_funcs.get_gpint_dataout) 1063 return DMUB_STATUS_INVALID; 1064 1065 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 1066 1067 return DMUB_STATUS_OK; 1068 } 1069 1070 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1071 union dmub_fw_boot_status *status) 1072 { 1073 status->all = 0; 1074 1075 if (!dmub->sw_init) 1076 return DMUB_STATUS_INVALID; 1077 1078 if (dmub->hw_funcs.get_fw_status) 1079 *status = dmub->hw_funcs.get_fw_status(dmub); 1080 1081 return DMUB_STATUS_OK; 1082 } 1083 1084 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1085 union dmub_fw_boot_options *option) 1086 { 1087 option->all = 0; 1088 1089 if (!dmub->sw_init) 1090 return DMUB_STATUS_INVALID; 1091 1092 if (dmub->hw_funcs.get_fw_boot_option) 1093 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1094 1095 return DMUB_STATUS_OK; 1096 } 1097 1098 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1099 bool skip) 1100 { 1101 if (!dmub->sw_init) 1102 return DMUB_STATUS_INVALID; 1103 1104 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1105 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1106 1107 return DMUB_STATUS_OK; 1108 } 1109 1110 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1111 void *entry) 1112 { 1113 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1114 uint64_t *dst = (uint64_t *)entry; 1115 uint8_t i; 1116 uint8_t loop_count; 1117 1118 if (rb->rptr == rb->wrpt) 1119 return false; 1120 1121 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1122 // copying data 1123 for (i = 0; i < loop_count; i++) 1124 *dst++ = *src++; 1125 1126 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1127 1128 rb->rptr %= rb->capacity; 1129 1130 return true; 1131 } 1132 1133 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1134 { 1135 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1136 1137 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1138 } 1139 1140 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1141 { 1142 if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1143 return false; 1144 dmub->hw_funcs.get_diagnostic_data(dmub); 1145 return true; 1146 } 1147 1148 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1149 { 1150 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1151 return false; 1152 1153 return dmub->hw_funcs.should_detect(dmub); 1154 } 1155 1156 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1157 { 1158 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1159 return DMUB_STATUS_INVALID; 1160 1161 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1162 return DMUB_STATUS_OK; 1163 } 1164 1165 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1166 { 1167 uint32_t i = 0; 1168 uint32_t ack = 0; 1169 1170 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1171 return DMUB_STATUS_INVALID; 1172 1173 for (i = 0; i <= timeout_us; i++) { 1174 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1175 if (ack) 1176 return DMUB_STATUS_OK; 1177 udelay(1); 1178 } 1179 return DMUB_STATUS_TIMEOUT; 1180 } 1181 1182 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1183 union dmub_inbox0_data_register data) 1184 { 1185 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1186 return DMUB_STATUS_INVALID; 1187 1188 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1189 return DMUB_STATUS_OK; 1190 } 1191 1192 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1193 { 1194 if (dmub->hw_funcs.subvp_save_surf_addr) { 1195 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1196 addr, 1197 subvp_index); 1198 } 1199 } 1200 1201 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1202 { 1203 if (!dmub || !dmub->hw_init) 1204 return; 1205 1206 dmub->power_state = dmub_srv_power_state; 1207 } 1208 1209 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1210 { 1211 uint32_t num_pending = 0; 1212 1213 if (!dmub->hw_init) 1214 return DMUB_STATUS_INVALID; 1215 1216 if (dmub->power_state != DMUB_POWER_STATE_D0) 1217 return DMUB_STATUS_POWER_STATE_D3; 1218 1219 if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1220 !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1221 return DMUB_STATUS_INVALID; 1222 1223 if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1224 num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1225 else 1226 /* num_submitted wrapped */ 1227 num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1228 (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1229 1230 if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1231 return DMUB_STATUS_QUEUE_FULL; 1232 1233 /* clear last rsp ack and send message */ 1234 dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1235 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1236 1237 dmub->reg_inbox0.num_submitted++; 1238 dmub->reg_inbox0.is_pending = true; 1239 dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1240 1241 return DMUB_STATUS_OK; 1242 } 1243 1244 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1245 union dmub_rb_cmd *cmd_rsp) 1246 { 1247 if (dmub) { 1248 if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1249 dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1250 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1251 } else { 1252 dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1253 } 1254 } 1255 } 1256 1257 static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1258 { 1259 if (!dmub || !dmub->sw_init) 1260 return DMUB_STATUS_INVALID; 1261 1262 dmub->reg_inbox0.is_pending = 0; 1263 dmub->reg_inbox0.is_multi_pending = 0; 1264 1265 return DMUB_STATUS_OK; 1266 } 1267 1268 static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1269 { 1270 if (!dmub->sw_init) 1271 return DMUB_STATUS_INVALID; 1272 1273 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1274 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1275 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1276 1277 if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1278 return DMUB_STATUS_HW_FAILURE; 1279 } else { 1280 dmub->inbox1.rb.rptr = rptr; 1281 dmub->inbox1.rb.wrpt = wptr; 1282 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1283 } 1284 } 1285 1286 return DMUB_STATUS_OK; 1287 } 1288 1289 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1290 { 1291 enum dmub_status status; 1292 1293 status = dmub_srv_sync_reg_inbox0(dmub); 1294 if (status != DMUB_STATUS_OK) 1295 return status; 1296 1297 status = dmub_srv_sync_inbox1(dmub); 1298 if (status != DMUB_STATUS_OK) 1299 return status; 1300 1301 return DMUB_STATUS_OK; 1302 } 1303 1304 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1305 uint32_t timeout_us, 1306 uint32_t num_free_required) 1307 { 1308 enum dmub_status status; 1309 uint32_t i; 1310 const uint32_t polling_interval_us = 1; 1311 1312 if (!dmub->hw_init) 1313 return DMUB_STATUS_INVALID; 1314 1315 for (i = 0; i < timeout_us; i += polling_interval_us) { 1316 status = dmub_srv_update_inbox_status(dmub); 1317 1318 if (status != DMUB_STATUS_OK) 1319 return status; 1320 1321 /* check for space in inbox1 */ 1322 if (dmub_rb_num_free(&dmub->inbox1.rb) >= num_free_required) 1323 return DMUB_STATUS_OK; 1324 1325 udelay(polling_interval_us); 1326 } 1327 1328 return DMUB_STATUS_TIMEOUT; 1329 } 1330 1331 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) 1332 { 1333 uint32_t rptr; 1334 1335 if (!dmub->hw_init) 1336 return DMUB_STATUS_INVALID; 1337 1338 if (dmub->power_state != DMUB_POWER_STATE_D0) 1339 return DMUB_STATUS_POWER_STATE_D3; 1340 1341 /* update inbox1 state */ 1342 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1343 1344 if (rptr > dmub->inbox1.rb.capacity) 1345 return DMUB_STATUS_HW_FAILURE; 1346 1347 if (dmub->inbox1.rb.rptr > rptr) { 1348 /* rb wrapped */ 1349 dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1350 } else { 1351 dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1352 } 1353 dmub->inbox1.rb.rptr = rptr; 1354 1355 /* update reg_inbox0 */ 1356 dmub_srv_update_reg_inbox0_status(dmub); 1357 1358 return DMUB_STATUS_OK; 1359 } 1360