1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "os_types.h" 41 /* 42 * Note: the DMUB service is standalone. No additional headers should be 43 * added below or above this line unless they reside within the DMUB 44 * folder. 45 */ 46 47 /* Alignment for framebuffer memory. */ 48 #define DMUB_FB_ALIGNMENT (1024 * 1024) 49 50 /* Stack size. */ 51 #define DMUB_STACK_SIZE (128 * 1024) 52 53 /* Context size. */ 54 #define DMUB_CONTEXT_SIZE (512 * 1024) 55 56 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 57 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 58 59 /* Default state size if meta is absent. */ 60 #define DMUB_FW_STATE_SIZE (64 * 1024) 61 62 /* Default tracebuffer size if meta is absent. */ 63 #define DMUB_TRACE_BUFFER_SIZE (64 * 1024) 64 65 66 /* Default scratch mem size. */ 67 #define DMUB_SCRATCH_MEM_SIZE (1024) 68 69 /* Number of windows in use. */ 70 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 71 /* Base addresses. */ 72 73 #define DMUB_CW0_BASE (0x60000000) 74 #define DMUB_CW1_BASE (0x61000000) 75 #define DMUB_CW3_BASE (0x63000000) 76 #define DMUB_CW4_BASE (0x64000000) 77 #define DMUB_CW5_BASE (0x65000000) 78 #define DMUB_CW6_BASE (0x66000000) 79 80 #define DMUB_REGION5_BASE (0xA0000000) 81 #define DMUB_REGION6_BASE (0xC0000000) 82 83 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 84 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 85 86 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 87 { 88 return (val + factor - 1) / factor * factor; 89 } 90 91 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 92 { 93 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 94 uint8_t buf[64]; 95 uint32_t pos, end; 96 97 /** 98 * Read 64-byte chunks since we don't want to store a 99 * large temporary buffer for this purpose. 100 */ 101 end = fb->size / sizeof(buf) * sizeof(buf); 102 103 for (pos = 0; pos < end; pos += sizeof(buf)) 104 dmub_memcpy(buf, base + pos, sizeof(buf)); 105 106 /* Read anything leftover into the buffer. */ 107 if (end < fb->size) 108 dmub_memcpy(buf, base + pos, fb->size - end); 109 } 110 111 static const struct dmub_fw_meta_info * 112 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 113 { 114 const union dmub_fw_meta *meta; 115 116 if (!blob || !blob_size) 117 return NULL; 118 119 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 120 return NULL; 121 122 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 123 sizeof(union dmub_fw_meta)); 124 125 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 126 return NULL; 127 128 return &meta->info; 129 } 130 131 static const struct dmub_fw_meta_info * 132 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 133 { 134 const struct dmub_fw_meta_info *info = NULL; 135 136 if (params->fw_bss_data && params->bss_data_size) { 137 /* Legacy metadata region. */ 138 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 139 params->bss_data_size, 140 DMUB_FW_META_OFFSET); 141 } else if (params->fw_inst_const && params->inst_const_size) { 142 /* Combined metadata region - can be aligned to 16-bytes. */ 143 uint32_t i; 144 145 for (i = 0; i < 16; ++i) { 146 info = dmub_get_fw_meta_info_from_blob( 147 params->fw_inst_const, params->inst_const_size, i); 148 149 if (info) 150 break; 151 } 152 } 153 154 return info; 155 } 156 157 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 158 { 159 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 160 161 switch (asic) { 162 case DMUB_ASIC_DCN20: 163 case DMUB_ASIC_DCN21: 164 case DMUB_ASIC_DCN30: 165 case DMUB_ASIC_DCN301: 166 case DMUB_ASIC_DCN302: 167 case DMUB_ASIC_DCN303: 168 dmub->regs = &dmub_srv_dcn20_regs; 169 170 funcs->reset = dmub_dcn20_reset; 171 funcs->reset_release = dmub_dcn20_reset_release; 172 funcs->backdoor_load = dmub_dcn20_backdoor_load; 173 funcs->setup_windows = dmub_dcn20_setup_windows; 174 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 175 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 176 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 177 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 178 funcs->is_supported = dmub_dcn20_is_supported; 179 funcs->is_hw_init = dmub_dcn20_is_hw_init; 180 funcs->set_gpint = dmub_dcn20_set_gpint; 181 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 182 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 183 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 184 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 185 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 186 funcs->get_current_time = dmub_dcn20_get_current_time; 187 188 // Out mailbox register access functions for RN and above 189 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 190 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 191 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 192 193 //outbox0 call stacks 194 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 195 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 196 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 197 198 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 199 200 if (asic == DMUB_ASIC_DCN21) 201 dmub->regs = &dmub_srv_dcn21_regs; 202 203 if (asic == DMUB_ASIC_DCN30) { 204 dmub->regs = &dmub_srv_dcn30_regs; 205 206 funcs->backdoor_load = dmub_dcn30_backdoor_load; 207 funcs->setup_windows = dmub_dcn30_setup_windows; 208 } 209 if (asic == DMUB_ASIC_DCN301) { 210 dmub->regs = &dmub_srv_dcn301_regs; 211 212 funcs->backdoor_load = dmub_dcn30_backdoor_load; 213 funcs->setup_windows = dmub_dcn30_setup_windows; 214 } 215 if (asic == DMUB_ASIC_DCN302) { 216 dmub->regs = &dmub_srv_dcn302_regs; 217 218 funcs->backdoor_load = dmub_dcn30_backdoor_load; 219 funcs->setup_windows = dmub_dcn30_setup_windows; 220 } 221 if (asic == DMUB_ASIC_DCN303) { 222 dmub->regs = &dmub_srv_dcn303_regs; 223 224 funcs->backdoor_load = dmub_dcn30_backdoor_load; 225 funcs->setup_windows = dmub_dcn30_setup_windows; 226 } 227 break; 228 229 case DMUB_ASIC_DCN31: 230 case DMUB_ASIC_DCN31B: 231 case DMUB_ASIC_DCN314: 232 case DMUB_ASIC_DCN315: 233 case DMUB_ASIC_DCN316: 234 if (asic == DMUB_ASIC_DCN314) { 235 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 236 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 237 } else if (asic == DMUB_ASIC_DCN315) { 238 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 239 } else if (asic == DMUB_ASIC_DCN316) { 240 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 241 } else { 242 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 243 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 244 } 245 funcs->reset = dmub_dcn31_reset; 246 funcs->reset_release = dmub_dcn31_reset_release; 247 funcs->backdoor_load = dmub_dcn31_backdoor_load; 248 funcs->setup_windows = dmub_dcn31_setup_windows; 249 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 250 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 251 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 252 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 253 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 254 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 255 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 256 funcs->is_supported = dmub_dcn31_is_supported; 257 funcs->is_hw_init = dmub_dcn31_is_hw_init; 258 funcs->set_gpint = dmub_dcn31_set_gpint; 259 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 260 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 261 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 262 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 263 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 264 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 265 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 266 //outbox0 call stacks 267 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 268 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 269 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 270 271 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 272 funcs->should_detect = dmub_dcn31_should_detect; 273 funcs->get_current_time = dmub_dcn31_get_current_time; 274 275 break; 276 277 case DMUB_ASIC_DCN32: 278 case DMUB_ASIC_DCN321: 279 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 280 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 281 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 282 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 283 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 284 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 285 funcs->reset = dmub_dcn32_reset; 286 funcs->reset_release = dmub_dcn32_reset_release; 287 funcs->backdoor_load = dmub_dcn32_backdoor_load; 288 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 289 funcs->setup_windows = dmub_dcn32_setup_windows; 290 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 291 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 292 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 293 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 294 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 295 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 296 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 297 funcs->is_supported = dmub_dcn32_is_supported; 298 funcs->is_hw_init = dmub_dcn32_is_hw_init; 299 funcs->set_gpint = dmub_dcn32_set_gpint; 300 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 301 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 302 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 303 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 304 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 305 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 306 307 /* outbox0 call stacks */ 308 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 309 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 310 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 311 funcs->get_current_time = dmub_dcn32_get_current_time; 312 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 313 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 314 315 break; 316 317 case DMUB_ASIC_DCN35: 318 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 319 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 320 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 321 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 322 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 323 funcs->reset = dmub_dcn35_reset; 324 funcs->reset_release = dmub_dcn35_reset_release; 325 funcs->backdoor_load = dmub_dcn35_backdoor_load; 326 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 327 funcs->setup_windows = dmub_dcn35_setup_windows; 328 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 329 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 330 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 331 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 332 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 333 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 334 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 335 funcs->is_supported = dmub_dcn35_is_supported; 336 funcs->is_hw_init = dmub_dcn35_is_hw_init; 337 funcs->set_gpint = dmub_dcn35_set_gpint; 338 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 339 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 340 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 341 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 342 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 343 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 344 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 345 //outbox0 call stacks 346 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 347 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 348 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 349 350 funcs->get_current_time = dmub_dcn35_get_current_time; 351 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 352 353 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 354 355 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 356 funcs->should_detect = dmub_dcn35_should_detect; 357 break; 358 359 default: 360 return false; 361 } 362 363 return true; 364 } 365 366 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 367 const struct dmub_srv_create_params *params) 368 { 369 enum dmub_status status = DMUB_STATUS_OK; 370 371 dmub_memset(dmub, 0, sizeof(*dmub)); 372 373 dmub->funcs = params->funcs; 374 dmub->user_ctx = params->user_ctx; 375 dmub->asic = params->asic; 376 dmub->fw_version = params->fw_version; 377 dmub->is_virtual = params->is_virtual; 378 379 /* Setup asic dependent hardware funcs. */ 380 if (!dmub_srv_hw_setup(dmub, params->asic)) { 381 status = DMUB_STATUS_INVALID; 382 goto cleanup; 383 } 384 385 /* Override (some) hardware funcs based on user params. */ 386 if (params->hw_funcs) { 387 if (params->hw_funcs->emul_get_inbox1_rptr) 388 dmub->hw_funcs.emul_get_inbox1_rptr = 389 params->hw_funcs->emul_get_inbox1_rptr; 390 391 if (params->hw_funcs->emul_set_inbox1_wptr) 392 dmub->hw_funcs.emul_set_inbox1_wptr = 393 params->hw_funcs->emul_set_inbox1_wptr; 394 395 if (params->hw_funcs->is_supported) 396 dmub->hw_funcs.is_supported = 397 params->hw_funcs->is_supported; 398 } 399 400 /* Sanity checks for required hw func pointers. */ 401 if (!dmub->hw_funcs.get_inbox1_rptr || 402 !dmub->hw_funcs.set_inbox1_wptr) { 403 status = DMUB_STATUS_INVALID; 404 goto cleanup; 405 } 406 407 cleanup: 408 if (status == DMUB_STATUS_OK) 409 dmub->sw_init = true; 410 else 411 dmub_srv_destroy(dmub); 412 413 return status; 414 } 415 416 void dmub_srv_destroy(struct dmub_srv *dmub) 417 { 418 dmub_memset(dmub, 0, sizeof(*dmub)); 419 } 420 421 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 422 struct dmub_srv_region_info *out, 423 const uint32_t *window_sizes, 424 enum dmub_window_memory_type memory_type) 425 { 426 uint32_t i, top = 0; 427 428 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 429 if (params->window_memory_type[i] == memory_type) { 430 struct dmub_region *region = &out->regions[i]; 431 432 region->base = dmub_align(top, 256); 433 region->top = region->base + dmub_align(window_sizes[i], 64); 434 top = region->top; 435 } 436 } 437 438 return dmub_align(top, 4096); 439 } 440 441 enum dmub_status 442 dmub_srv_calc_region_info(struct dmub_srv *dmub, 443 const struct dmub_srv_region_params *params, 444 struct dmub_srv_region_info *out) 445 { 446 const struct dmub_fw_meta_info *fw_info; 447 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 448 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 449 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 450 451 if (!dmub->sw_init) 452 return DMUB_STATUS_INVALID; 453 454 memset(out, 0, sizeof(*out)); 455 memset(window_sizes, 0, sizeof(window_sizes)); 456 457 out->num_regions = DMUB_NUM_WINDOWS; 458 459 fw_info = dmub_get_fw_meta_info(params); 460 461 if (fw_info) { 462 fw_state_size = fw_info->fw_region_size; 463 trace_buffer_size = fw_info->trace_buffer_size; 464 465 /** 466 * If DM didn't fill in a version, then fill it in based on 467 * the firmware meta now that we have it. 468 * 469 * TODO: Make it easier for driver to extract this out to 470 * pass during creation. 471 */ 472 if (dmub->fw_version == 0) 473 dmub->fw_version = fw_info->fw_version; 474 } 475 476 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 477 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 478 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 479 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 480 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 481 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 482 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 483 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE; 484 window_sizes[DMUB_WINDOW_SHARED_STATE] = DMUB_FW_HEADER_SHARED_STATE_SIZE; 485 486 out->fb_size = 487 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 488 489 out->gart_size = 490 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 491 492 return DMUB_STATUS_OK; 493 } 494 495 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 496 const struct dmub_srv_memory_params *params, 497 struct dmub_srv_fb_info *out) 498 { 499 uint32_t i; 500 501 if (!dmub->sw_init) 502 return DMUB_STATUS_INVALID; 503 504 memset(out, 0, sizeof(*out)); 505 506 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 507 return DMUB_STATUS_INVALID; 508 509 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 510 const struct dmub_region *reg = 511 ¶ms->region_info->regions[i]; 512 513 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 514 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 515 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 516 } else { 517 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 518 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 519 } 520 521 out->fb[i].size = reg->top - reg->base; 522 } 523 524 out->num_fb = DMUB_NUM_WINDOWS; 525 526 return DMUB_STATUS_OK; 527 } 528 529 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 530 bool *is_supported) 531 { 532 *is_supported = false; 533 534 if (!dmub->sw_init) 535 return DMUB_STATUS_INVALID; 536 537 if (dmub->hw_funcs.is_supported) 538 *is_supported = dmub->hw_funcs.is_supported(dmub); 539 540 return DMUB_STATUS_OK; 541 } 542 543 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 544 { 545 *is_hw_init = false; 546 547 if (!dmub->sw_init) 548 return DMUB_STATUS_INVALID; 549 550 if (!dmub->hw_init) 551 return DMUB_STATUS_OK; 552 553 if (dmub->hw_funcs.is_hw_init) 554 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 555 556 return DMUB_STATUS_OK; 557 } 558 559 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 560 const struct dmub_srv_hw_params *params) 561 { 562 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 563 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 564 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 565 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 566 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 567 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 568 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 569 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 570 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 571 572 struct dmub_rb_init_params rb_params, outbox0_rb_params; 573 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 574 struct dmub_region inbox1, outbox1, outbox0; 575 576 if (!dmub->sw_init) 577 return DMUB_STATUS_INVALID; 578 579 if (!inst_fb || !stack_fb || !data_fb || !bios_fb || !mail_fb || 580 !tracebuff_fb || !fw_state_fb || !scratch_mem_fb) { 581 ASSERT(0); 582 return DMUB_STATUS_INVALID; 583 } 584 585 dmub->fb_base = params->fb_base; 586 dmub->fb_offset = params->fb_offset; 587 dmub->psp_version = params->psp_version; 588 589 if (dmub->hw_funcs.reset) 590 dmub->hw_funcs.reset(dmub); 591 592 /* reset the cache of the last wptr as well now that hw is reset */ 593 dmub->inbox1_last_wptr = 0; 594 595 cw0.offset.quad_part = inst_fb->gpu_addr; 596 cw0.region.base = DMUB_CW0_BASE; 597 cw0.region.top = cw0.region.base + inst_fb->size - 1; 598 599 cw1.offset.quad_part = stack_fb->gpu_addr; 600 cw1.region.base = DMUB_CW1_BASE; 601 cw1.region.top = cw1.region.base + stack_fb->size - 1; 602 603 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 604 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 605 606 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 607 /** 608 * Read back all the instruction memory so we don't hang the 609 * DMCUB when backdoor loading if the write from x86 hasn't been 610 * flushed yet. This only occurs in backdoor loading. 611 */ 612 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 613 dmub_flush_buffer_mem(inst_fb); 614 615 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 616 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 617 else 618 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 619 } 620 621 cw2.offset.quad_part = data_fb->gpu_addr; 622 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 623 cw2.region.top = cw2.region.base + data_fb->size; 624 625 cw3.offset.quad_part = bios_fb->gpu_addr; 626 cw3.region.base = DMUB_CW3_BASE; 627 cw3.region.top = cw3.region.base + bios_fb->size; 628 629 cw4.offset.quad_part = mail_fb->gpu_addr; 630 cw4.region.base = DMUB_CW4_BASE; 631 cw4.region.top = cw4.region.base + mail_fb->size; 632 633 /** 634 * Doubled the mailbox region to accomodate inbox and outbox. 635 * Note: Currently, currently total mailbox size is 16KB. It is split 636 * equally into 8KB between inbox and outbox. If this config is 637 * changed, then uncached base address configuration of outbox1 638 * has to be updated in funcs->setup_out_mailbox. 639 */ 640 inbox1.base = cw4.region.base; 641 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 642 outbox1.base = inbox1.top; 643 outbox1.top = cw4.region.top; 644 645 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 646 cw5.region.base = DMUB_CW5_BASE; 647 cw5.region.top = cw5.region.base + tracebuff_fb->size; 648 649 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 650 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 651 652 cw6.offset.quad_part = fw_state_fb->gpu_addr; 653 cw6.region.base = DMUB_CW6_BASE; 654 cw6.region.top = cw6.region.base + fw_state_fb->size; 655 656 dmub->fw_state = fw_state_fb->cpu_addr; 657 658 region6.offset.quad_part = shared_state_fb->gpu_addr; 659 region6.region.base = DMUB_CW6_BASE; 660 region6.region.top = region6.region.base + shared_state_fb->size; 661 662 dmub->shared_state = shared_state_fb->cpu_addr; 663 664 dmub->scratch_mem_fb = *scratch_mem_fb; 665 666 if (dmub->hw_funcs.setup_windows) 667 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 668 669 if (dmub->hw_funcs.setup_outbox0) 670 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 671 672 if (dmub->hw_funcs.setup_mailbox) 673 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 674 if (dmub->hw_funcs.setup_out_mailbox) 675 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 676 677 dmub_memset(&rb_params, 0, sizeof(rb_params)); 678 rb_params.ctx = dmub; 679 rb_params.base_address = mail_fb->cpu_addr; 680 rb_params.capacity = DMUB_RB_SIZE; 681 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 682 683 // Initialize outbox1 ring buffer 684 rb_params.ctx = dmub; 685 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 686 rb_params.capacity = DMUB_RB_SIZE; 687 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 688 689 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 690 outbox0_rb_params.ctx = dmub; 691 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 692 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 693 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 694 695 /* Report to DMUB what features are supported by current driver */ 696 if (dmub->hw_funcs.enable_dmub_boot_options) 697 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 698 699 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 700 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 701 params->skip_panel_power_sequence); 702 703 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 704 dmub->hw_funcs.reset_release(dmub); 705 706 dmub->hw_init = true; 707 dmub->power_state = DMUB_POWER_STATE_D0; 708 709 return DMUB_STATUS_OK; 710 } 711 712 enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 713 { 714 if (!dmub->sw_init) 715 return DMUB_STATUS_INVALID; 716 717 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 718 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 719 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 720 721 if (rptr > dmub->inbox1_rb.capacity || wptr > dmub->inbox1_rb.capacity) { 722 return DMUB_STATUS_HW_FAILURE; 723 } else { 724 dmub->inbox1_rb.rptr = rptr; 725 dmub->inbox1_rb.wrpt = wptr; 726 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 727 } 728 } 729 730 return DMUB_STATUS_OK; 731 } 732 733 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 734 { 735 if (!dmub->sw_init) 736 return DMUB_STATUS_INVALID; 737 738 if (dmub->hw_funcs.reset) 739 dmub->hw_funcs.reset(dmub); 740 741 /* mailboxes have been reset in hw, so reset the sw state as well */ 742 dmub->inbox1_last_wptr = 0; 743 dmub->inbox1_rb.wrpt = 0; 744 dmub->inbox1_rb.rptr = 0; 745 dmub->outbox0_rb.wrpt = 0; 746 dmub->outbox0_rb.rptr = 0; 747 dmub->outbox1_rb.wrpt = 0; 748 dmub->outbox1_rb.rptr = 0; 749 750 dmub->hw_init = false; 751 752 return DMUB_STATUS_OK; 753 } 754 755 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 756 const union dmub_rb_cmd *cmd) 757 { 758 if (!dmub->hw_init) 759 return DMUB_STATUS_INVALID; 760 761 if (dmub->power_state != DMUB_POWER_STATE_D0) 762 return DMUB_STATUS_POWER_STATE_D3; 763 764 if (dmub->inbox1_rb.rptr > dmub->inbox1_rb.capacity || 765 dmub->inbox1_rb.wrpt > dmub->inbox1_rb.capacity) { 766 return DMUB_STATUS_HW_FAILURE; 767 } 768 769 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 770 return DMUB_STATUS_OK; 771 772 return DMUB_STATUS_QUEUE_FULL; 773 } 774 775 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 776 { 777 struct dmub_rb flush_rb; 778 779 if (!dmub->hw_init) 780 return DMUB_STATUS_INVALID; 781 782 if (dmub->power_state != DMUB_POWER_STATE_D0) 783 return DMUB_STATUS_POWER_STATE_D3; 784 785 /** 786 * Read back all the queued commands to ensure that they've 787 * been flushed to framebuffer memory. Otherwise DMCUB might 788 * read back stale, fully invalid or partially invalid data. 789 */ 790 flush_rb = dmub->inbox1_rb; 791 flush_rb.rptr = dmub->inbox1_last_wptr; 792 dmub_rb_flush_pending(&flush_rb); 793 794 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 795 796 dmub->inbox1_last_wptr = dmub->inbox1_rb.wrpt; 797 798 return DMUB_STATUS_OK; 799 } 800 801 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 802 { 803 if (!dmub->hw_funcs.is_hw_powered_up) 804 return true; 805 806 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 807 return false; 808 809 return true; 810 } 811 812 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 813 uint32_t timeout_us) 814 { 815 uint32_t i; 816 817 if (!dmub->hw_init) 818 return DMUB_STATUS_INVALID; 819 820 for (i = 0; i <= timeout_us; i += 100) { 821 if (dmub_srv_is_hw_pwr_up(dmub)) 822 return DMUB_STATUS_OK; 823 824 udelay(100); 825 } 826 827 return DMUB_STATUS_TIMEOUT; 828 } 829 830 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 831 uint32_t timeout_us) 832 { 833 uint32_t i; 834 bool hw_on = true; 835 836 if (!dmub->hw_init) 837 return DMUB_STATUS_INVALID; 838 839 for (i = 0; i <= timeout_us; i += 100) { 840 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 841 842 if (dmub->hw_funcs.is_hw_powered_up) 843 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 844 845 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 846 return DMUB_STATUS_OK; 847 848 udelay(100); 849 } 850 851 return DMUB_STATUS_TIMEOUT; 852 } 853 854 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 855 uint32_t timeout_us) 856 { 857 uint32_t i, rptr; 858 859 if (!dmub->hw_init) 860 return DMUB_STATUS_INVALID; 861 862 for (i = 0; i <= timeout_us; ++i) { 863 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 864 865 if (rptr > dmub->inbox1_rb.capacity) 866 return DMUB_STATUS_HW_FAILURE; 867 868 dmub->inbox1_rb.rptr = rptr; 869 870 if (dmub_rb_empty(&dmub->inbox1_rb)) 871 return DMUB_STATUS_OK; 872 873 udelay(1); 874 } 875 876 return DMUB_STATUS_TIMEOUT; 877 } 878 879 enum dmub_status 880 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 881 enum dmub_gpint_command command_code, 882 uint16_t param, uint32_t timeout_us) 883 { 884 union dmub_gpint_data_register reg; 885 uint32_t i; 886 887 if (!dmub->sw_init) 888 return DMUB_STATUS_INVALID; 889 890 if (!dmub->hw_funcs.set_gpint) 891 return DMUB_STATUS_INVALID; 892 893 if (!dmub->hw_funcs.is_gpint_acked) 894 return DMUB_STATUS_INVALID; 895 896 reg.bits.status = 1; 897 reg.bits.command_code = command_code; 898 reg.bits.param = param; 899 900 dmub->hw_funcs.set_gpint(dmub, reg); 901 902 for (i = 0; i < timeout_us; ++i) { 903 udelay(1); 904 905 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 906 return DMUB_STATUS_OK; 907 } 908 909 return DMUB_STATUS_TIMEOUT; 910 } 911 912 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 913 uint32_t *response) 914 { 915 *response = 0; 916 917 if (!dmub->sw_init) 918 return DMUB_STATUS_INVALID; 919 920 if (!dmub->hw_funcs.get_gpint_response) 921 return DMUB_STATUS_INVALID; 922 923 *response = dmub->hw_funcs.get_gpint_response(dmub); 924 925 return DMUB_STATUS_OK; 926 } 927 928 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 929 uint32_t *dataout) 930 { 931 *dataout = 0; 932 933 if (!dmub->sw_init) 934 return DMUB_STATUS_INVALID; 935 936 if (!dmub->hw_funcs.get_gpint_dataout) 937 return DMUB_STATUS_INVALID; 938 939 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 940 941 return DMUB_STATUS_OK; 942 } 943 944 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 945 union dmub_fw_boot_status *status) 946 { 947 status->all = 0; 948 949 if (!dmub->sw_init) 950 return DMUB_STATUS_INVALID; 951 952 if (dmub->hw_funcs.get_fw_status) 953 *status = dmub->hw_funcs.get_fw_status(dmub); 954 955 return DMUB_STATUS_OK; 956 } 957 958 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 959 union dmub_fw_boot_options *option) 960 { 961 option->all = 0; 962 963 if (!dmub->sw_init) 964 return DMUB_STATUS_INVALID; 965 966 if (dmub->hw_funcs.get_fw_boot_option) 967 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 968 969 return DMUB_STATUS_OK; 970 } 971 972 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 973 bool skip) 974 { 975 if (!dmub->sw_init) 976 return DMUB_STATUS_INVALID; 977 978 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 979 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 980 981 return DMUB_STATUS_OK; 982 } 983 984 enum dmub_status dmub_srv_cmd_with_reply_data(struct dmub_srv *dmub, 985 union dmub_rb_cmd *cmd) 986 { 987 enum dmub_status status = DMUB_STATUS_OK; 988 989 // Queue command 990 status = dmub_srv_cmd_queue(dmub, cmd); 991 992 if (status != DMUB_STATUS_OK) 993 return status; 994 995 // Execute command 996 status = dmub_srv_cmd_execute(dmub); 997 998 if (status != DMUB_STATUS_OK) 999 return status; 1000 1001 // Wait for DMUB to process command 1002 status = dmub_srv_wait_for_idle(dmub, 100000); 1003 1004 if (status != DMUB_STATUS_OK) 1005 return status; 1006 1007 // Copy data back from ring buffer into command 1008 dmub_rb_get_return_data(&dmub->inbox1_rb, cmd); 1009 1010 return status; 1011 } 1012 1013 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1014 void *entry) 1015 { 1016 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1017 uint64_t *dst = (uint64_t *)entry; 1018 uint8_t i; 1019 uint8_t loop_count; 1020 1021 if (rb->rptr == rb->wrpt) 1022 return false; 1023 1024 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1025 // copying data 1026 for (i = 0; i < loop_count; i++) 1027 *dst++ = *src++; 1028 1029 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1030 1031 rb->rptr %= rb->capacity; 1032 1033 return true; 1034 } 1035 1036 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1037 { 1038 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1039 1040 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1041 } 1042 1043 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 1044 { 1045 if (!dmub || !dmub->hw_funcs.get_diagnostic_data || !diag_data) 1046 return false; 1047 dmub->hw_funcs.get_diagnostic_data(dmub, diag_data); 1048 return true; 1049 } 1050 1051 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1052 { 1053 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1054 return false; 1055 1056 return dmub->hw_funcs.should_detect(dmub); 1057 } 1058 1059 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1060 { 1061 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1062 return DMUB_STATUS_INVALID; 1063 1064 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1065 return DMUB_STATUS_OK; 1066 } 1067 1068 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1069 { 1070 uint32_t i = 0; 1071 uint32_t ack = 0; 1072 1073 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1074 return DMUB_STATUS_INVALID; 1075 1076 for (i = 0; i <= timeout_us; i++) { 1077 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1078 if (ack) 1079 return DMUB_STATUS_OK; 1080 udelay(1); 1081 } 1082 return DMUB_STATUS_TIMEOUT; 1083 } 1084 1085 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1086 union dmub_inbox0_data_register data) 1087 { 1088 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1089 return DMUB_STATUS_INVALID; 1090 1091 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1092 return DMUB_STATUS_OK; 1093 } 1094 1095 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1096 { 1097 if (dmub->hw_funcs.subvp_save_surf_addr) { 1098 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1099 addr, 1100 subvp_index); 1101 } 1102 } 1103 1104 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1105 { 1106 if (!dmub || !dmub->hw_init) 1107 return; 1108 1109 dmub->power_state = dmub_srv_power_state; 1110 } 1111