1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_cmd.h" 30 #include "dmub_dcn30.h" 31 #include "dmub_dcn301.h" 32 #include "dmub_dcn302.h" 33 #include "dmub_dcn303.h" 34 #include "dmub_dcn31.h" 35 #include "dmub_dcn314.h" 36 #include "dmub_dcn315.h" 37 #include "dmub_dcn316.h" 38 #include "dmub_dcn32.h" 39 #include "dmub_dcn35.h" 40 #include "dmub_dcn351.h" 41 #include "dmub_dcn36.h" 42 #include "dmub_dcn401.h" 43 #include "os_types.h" 44 /* 45 * Note: the DMUB service is standalone. No additional headers should be 46 * added below or above this line unless they reside within the DMUB 47 * folder. 48 */ 49 50 /* Alignment for framebuffer memory. */ 51 #define DMUB_FB_ALIGNMENT (1024 * 1024) 52 53 /* Stack size. */ 54 #define DMUB_STACK_SIZE (128 * 1024) 55 56 /* Context size. */ 57 #define DMUB_CONTEXT_SIZE (512 * 1024) 58 59 /* Mailbox size : Ring buffers are required for both inbox and outbox */ 60 #define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE)) 61 62 /* Default state size if meta is absent. */ 63 #define DMUB_FW_STATE_SIZE (64 * 1024) 64 65 /* Default scratch mem size. */ 66 #define DMUB_SCRATCH_MEM_SIZE (1024) 67 68 /* Default indirect buffer size. */ 69 #define DMUB_IB_MEM_SIZE (2560) 70 71 /* Default LSDMA ring buffer size. */ 72 #define DMUB_LSDMA_RB_SIZE (64 * 1024) 73 74 /* Number of windows in use. */ 75 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 76 /* Base addresses. */ 77 78 #define DMUB_CW0_BASE (0x60000000) 79 #define DMUB_CW1_BASE (0x61000000) 80 #define DMUB_CW3_BASE (0x63000000) 81 #define DMUB_CW4_BASE (0x64000000) 82 #define DMUB_CW5_BASE (0x65000000) 83 #define DMUB_CW6_BASE (0x66000000) 84 85 #define DMUB_REGION5_BASE (0xA0000000) 86 #define DMUB_REGION6_BASE (0xC0000000) 87 88 static struct dmub_srv_dcn32_regs dmub_srv_dcn32_regs; 89 static struct dmub_srv_dcn35_regs dmub_srv_dcn35_regs; 90 91 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 92 { 93 return (val + factor - 1) / factor * factor; 94 } 95 96 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 97 { 98 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 99 uint8_t buf[64]; 100 uint32_t pos, end; 101 102 /** 103 * Read 64-byte chunks since we don't want to store a 104 * large temporary buffer for this purpose. 105 */ 106 end = fb->size / sizeof(buf) * sizeof(buf); 107 108 for (pos = 0; pos < end; pos += sizeof(buf)) 109 dmub_memcpy(buf, base + pos, sizeof(buf)); 110 111 /* Read anything leftover into the buffer. */ 112 if (end < fb->size) 113 dmub_memcpy(buf, base + pos, fb->size - end); 114 } 115 116 static const struct dmub_fw_meta_info * 117 dmub_get_fw_meta_info_from_blob(const uint8_t *blob, uint32_t blob_size, uint32_t meta_offset) 118 { 119 const union dmub_fw_meta *meta; 120 121 if (!blob || !blob_size) 122 return NULL; 123 124 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 125 return NULL; 126 127 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 128 sizeof(union dmub_fw_meta)); 129 130 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 131 return NULL; 132 133 return &meta->info; 134 } 135 136 static const struct dmub_fw_meta_info * 137 dmub_get_fw_meta_info(const struct dmub_srv_fw_meta_info_params *params) 138 { 139 const struct dmub_fw_meta_info *info = NULL; 140 141 if (params->fw_bss_data && params->bss_data_size) { 142 /* Legacy metadata region. */ 143 info = dmub_get_fw_meta_info_from_blob(params->fw_bss_data, 144 params->bss_data_size, 145 DMUB_FW_META_OFFSET); 146 } else if (params->fw_inst_const && params->inst_const_size) { 147 /* Combined metadata region - can be aligned to 16-bytes. */ 148 uint32_t i; 149 150 for (i = 0; i < 16; ++i) { 151 info = dmub_get_fw_meta_info_from_blob( 152 params->fw_inst_const, params->inst_const_size, i); 153 154 if (info) 155 break; 156 } 157 } 158 159 return info; 160 } 161 162 enum dmub_status 163 dmub_srv_get_fw_meta_info_from_raw_fw(struct dmub_srv_fw_meta_info_params *params, 164 struct dmub_fw_meta_info *fw_info_out) 165 { 166 const struct dmub_fw_meta_info *fw_info = NULL; 167 uint32_t inst_const_size_temp = params->inst_const_size; 168 169 /* First try custom psp footer size, if present */ 170 if (params->custom_psp_footer_size) { 171 params->inst_const_size -= params->custom_psp_footer_size; 172 fw_info = dmub_get_fw_meta_info(params); 173 if (fw_info) { 174 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 175 return DMUB_STATUS_OK; 176 } 177 params->inst_const_size = inst_const_size_temp; 178 } 179 180 /* Try 256-byte psp footer size */ 181 params->inst_const_size -= PSP_FOOTER_BYTES_256; 182 fw_info = dmub_get_fw_meta_info(params); 183 if (fw_info) { 184 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 185 return DMUB_STATUS_OK; 186 } 187 188 /* Try 512-byte psp footer size - final attempt */ 189 params->inst_const_size -= PSP_FOOTER_BYTES_256; // 256 bytes already subtracted, subtract 256 again 190 fw_info = dmub_get_fw_meta_info(params); 191 if (fw_info) { 192 memcpy(fw_info_out, fw_info, sizeof(*fw_info)); 193 return DMUB_STATUS_OK; 194 } 195 196 /* Restore original inst_const_size and subtract default PSP footer size - default behaviour */ 197 params->inst_const_size = inst_const_size_temp - PSP_FOOTER_BYTES_256; 198 199 return DMUB_STATUS_INVALID; 200 } 201 202 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 203 { 204 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 205 206 /* default to specifying now inbox type */ 207 enum dmub_inbox_cmd_interface_type default_inbox_type = DMUB_CMD_INTERFACE_DEFAULT; 208 209 switch (asic) { 210 case DMUB_ASIC_DCN20: 211 case DMUB_ASIC_DCN21: 212 case DMUB_ASIC_DCN30: 213 case DMUB_ASIC_DCN301: 214 case DMUB_ASIC_DCN302: 215 case DMUB_ASIC_DCN303: 216 dmub->regs = &dmub_srv_dcn20_regs; 217 218 funcs->reset = dmub_dcn20_reset; 219 funcs->reset_release = dmub_dcn20_reset_release; 220 funcs->backdoor_load = dmub_dcn20_backdoor_load; 221 funcs->setup_windows = dmub_dcn20_setup_windows; 222 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 223 funcs->get_inbox1_wptr = dmub_dcn20_get_inbox1_wptr; 224 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 225 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 226 funcs->is_supported = dmub_dcn20_is_supported; 227 funcs->is_hw_init = dmub_dcn20_is_hw_init; 228 funcs->set_gpint = dmub_dcn20_set_gpint; 229 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 230 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 231 funcs->get_fw_status = dmub_dcn20_get_fw_boot_status; 232 funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options; 233 funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence; 234 funcs->get_current_time = dmub_dcn20_get_current_time; 235 236 // Out mailbox register access functions for RN and above 237 funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox; 238 funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr; 239 funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr; 240 241 //outbox0 call stacks 242 funcs->setup_outbox0 = dmub_dcn20_setup_outbox0; 243 funcs->get_outbox0_wptr = dmub_dcn20_get_outbox0_wptr; 244 funcs->set_outbox0_rptr = dmub_dcn20_set_outbox0_rptr; 245 246 funcs->get_diagnostic_data = dmub_dcn20_get_diagnostic_data; 247 248 if (asic == DMUB_ASIC_DCN21) 249 dmub->regs = &dmub_srv_dcn21_regs; 250 251 if (asic == DMUB_ASIC_DCN30) { 252 dmub->regs = &dmub_srv_dcn30_regs; 253 254 funcs->backdoor_load = dmub_dcn30_backdoor_load; 255 funcs->setup_windows = dmub_dcn30_setup_windows; 256 } 257 if (asic == DMUB_ASIC_DCN301) { 258 dmub->regs = &dmub_srv_dcn301_regs; 259 260 funcs->backdoor_load = dmub_dcn30_backdoor_load; 261 funcs->setup_windows = dmub_dcn30_setup_windows; 262 } 263 if (asic == DMUB_ASIC_DCN302) { 264 dmub->regs = &dmub_srv_dcn302_regs; 265 266 funcs->backdoor_load = dmub_dcn30_backdoor_load; 267 funcs->setup_windows = dmub_dcn30_setup_windows; 268 } 269 if (asic == DMUB_ASIC_DCN303) { 270 dmub->regs = &dmub_srv_dcn303_regs; 271 272 funcs->backdoor_load = dmub_dcn30_backdoor_load; 273 funcs->setup_windows = dmub_dcn30_setup_windows; 274 } 275 break; 276 277 case DMUB_ASIC_DCN31: 278 case DMUB_ASIC_DCN31B: 279 case DMUB_ASIC_DCN314: 280 case DMUB_ASIC_DCN315: 281 case DMUB_ASIC_DCN316: 282 if (asic == DMUB_ASIC_DCN314) { 283 dmub->regs_dcn31 = &dmub_srv_dcn314_regs; 284 funcs->is_psrsu_supported = dmub_dcn314_is_psrsu_supported; 285 } else if (asic == DMUB_ASIC_DCN315) { 286 dmub->regs_dcn31 = &dmub_srv_dcn315_regs; 287 } else if (asic == DMUB_ASIC_DCN316) { 288 dmub->regs_dcn31 = &dmub_srv_dcn316_regs; 289 } else { 290 dmub->regs_dcn31 = &dmub_srv_dcn31_regs; 291 funcs->is_psrsu_supported = dmub_dcn31_is_psrsu_supported; 292 } 293 funcs->reset = dmub_dcn31_reset; 294 funcs->reset_release = dmub_dcn31_reset_release; 295 funcs->backdoor_load = dmub_dcn31_backdoor_load; 296 funcs->setup_windows = dmub_dcn31_setup_windows; 297 funcs->setup_mailbox = dmub_dcn31_setup_mailbox; 298 funcs->get_inbox1_wptr = dmub_dcn31_get_inbox1_wptr; 299 funcs->get_inbox1_rptr = dmub_dcn31_get_inbox1_rptr; 300 funcs->set_inbox1_wptr = dmub_dcn31_set_inbox1_wptr; 301 funcs->setup_out_mailbox = dmub_dcn31_setup_out_mailbox; 302 funcs->get_outbox1_wptr = dmub_dcn31_get_outbox1_wptr; 303 funcs->set_outbox1_rptr = dmub_dcn31_set_outbox1_rptr; 304 funcs->is_supported = dmub_dcn31_is_supported; 305 funcs->is_hw_init = dmub_dcn31_is_hw_init; 306 funcs->set_gpint = dmub_dcn31_set_gpint; 307 funcs->is_gpint_acked = dmub_dcn31_is_gpint_acked; 308 funcs->get_gpint_response = dmub_dcn31_get_gpint_response; 309 funcs->get_gpint_dataout = dmub_dcn31_get_gpint_dataout; 310 funcs->get_fw_status = dmub_dcn31_get_fw_boot_status; 311 funcs->get_fw_boot_option = dmub_dcn31_get_fw_boot_option; 312 funcs->enable_dmub_boot_options = dmub_dcn31_enable_dmub_boot_options; 313 funcs->skip_dmub_panel_power_sequence = dmub_dcn31_skip_dmub_panel_power_sequence; 314 //outbox0 call stacks 315 funcs->setup_outbox0 = dmub_dcn31_setup_outbox0; 316 funcs->get_outbox0_wptr = dmub_dcn31_get_outbox0_wptr; 317 funcs->set_outbox0_rptr = dmub_dcn31_set_outbox0_rptr; 318 319 funcs->get_diagnostic_data = dmub_dcn31_get_diagnostic_data; 320 funcs->should_detect = dmub_dcn31_should_detect; 321 funcs->get_current_time = dmub_dcn31_get_current_time; 322 323 break; 324 325 case DMUB_ASIC_DCN32: 326 case DMUB_ASIC_DCN321: 327 dmub->regs_dcn32 = &dmub_srv_dcn32_regs; 328 funcs->configure_dmub_in_system_memory = dmub_dcn32_configure_dmub_in_system_memory; 329 funcs->send_inbox0_cmd = dmub_dcn32_send_inbox0_cmd; 330 funcs->clear_inbox0_ack_register = dmub_dcn32_clear_inbox0_ack_register; 331 funcs->read_inbox0_ack_register = dmub_dcn32_read_inbox0_ack_register; 332 funcs->subvp_save_surf_addr = dmub_dcn32_save_surf_addr; 333 funcs->reset = dmub_dcn32_reset; 334 funcs->reset_release = dmub_dcn32_reset_release; 335 funcs->backdoor_load = dmub_dcn32_backdoor_load; 336 funcs->backdoor_load_zfb_mode = dmub_dcn32_backdoor_load_zfb_mode; 337 funcs->setup_windows = dmub_dcn32_setup_windows; 338 funcs->setup_mailbox = dmub_dcn32_setup_mailbox; 339 funcs->get_inbox1_wptr = dmub_dcn32_get_inbox1_wptr; 340 funcs->get_inbox1_rptr = dmub_dcn32_get_inbox1_rptr; 341 funcs->set_inbox1_wptr = dmub_dcn32_set_inbox1_wptr; 342 funcs->setup_out_mailbox = dmub_dcn32_setup_out_mailbox; 343 funcs->get_outbox1_wptr = dmub_dcn32_get_outbox1_wptr; 344 funcs->set_outbox1_rptr = dmub_dcn32_set_outbox1_rptr; 345 funcs->is_supported = dmub_dcn32_is_supported; 346 funcs->is_hw_init = dmub_dcn32_is_hw_init; 347 funcs->set_gpint = dmub_dcn32_set_gpint; 348 funcs->is_gpint_acked = dmub_dcn32_is_gpint_acked; 349 funcs->get_gpint_response = dmub_dcn32_get_gpint_response; 350 funcs->get_gpint_dataout = dmub_dcn32_get_gpint_dataout; 351 funcs->get_fw_status = dmub_dcn32_get_fw_boot_status; 352 funcs->enable_dmub_boot_options = dmub_dcn32_enable_dmub_boot_options; 353 funcs->skip_dmub_panel_power_sequence = dmub_dcn32_skip_dmub_panel_power_sequence; 354 355 /* outbox0 call stacks */ 356 funcs->setup_outbox0 = dmub_dcn32_setup_outbox0; 357 funcs->get_outbox0_wptr = dmub_dcn32_get_outbox0_wptr; 358 funcs->set_outbox0_rptr = dmub_dcn32_set_outbox0_rptr; 359 funcs->get_current_time = dmub_dcn32_get_current_time; 360 funcs->get_diagnostic_data = dmub_dcn32_get_diagnostic_data; 361 funcs->init_reg_offsets = dmub_srv_dcn32_regs_init; 362 363 break; 364 365 case DMUB_ASIC_DCN35: 366 case DMUB_ASIC_DCN351: 367 case DMUB_ASIC_DCN36: 368 dmub->regs_dcn35 = &dmub_srv_dcn35_regs; 369 funcs->configure_dmub_in_system_memory = dmub_dcn35_configure_dmub_in_system_memory; 370 funcs->send_inbox0_cmd = dmub_dcn35_send_inbox0_cmd; 371 funcs->clear_inbox0_ack_register = dmub_dcn35_clear_inbox0_ack_register; 372 funcs->read_inbox0_ack_register = dmub_dcn35_read_inbox0_ack_register; 373 funcs->reset = dmub_dcn35_reset; 374 funcs->reset_release = dmub_dcn35_reset_release; 375 funcs->backdoor_load = dmub_dcn35_backdoor_load; 376 funcs->backdoor_load_zfb_mode = dmub_dcn35_backdoor_load_zfb_mode; 377 funcs->setup_windows = dmub_dcn35_setup_windows; 378 funcs->setup_mailbox = dmub_dcn35_setup_mailbox; 379 funcs->get_inbox1_wptr = dmub_dcn35_get_inbox1_wptr; 380 funcs->get_inbox1_rptr = dmub_dcn35_get_inbox1_rptr; 381 funcs->set_inbox1_wptr = dmub_dcn35_set_inbox1_wptr; 382 funcs->setup_out_mailbox = dmub_dcn35_setup_out_mailbox; 383 funcs->get_outbox1_wptr = dmub_dcn35_get_outbox1_wptr; 384 funcs->set_outbox1_rptr = dmub_dcn35_set_outbox1_rptr; 385 funcs->is_supported = dmub_dcn35_is_supported; 386 funcs->is_hw_init = dmub_dcn35_is_hw_init; 387 funcs->set_gpint = dmub_dcn35_set_gpint; 388 funcs->is_gpint_acked = dmub_dcn35_is_gpint_acked; 389 funcs->get_gpint_response = dmub_dcn35_get_gpint_response; 390 funcs->get_gpint_dataout = dmub_dcn35_get_gpint_dataout; 391 funcs->get_fw_status = dmub_dcn35_get_fw_boot_status; 392 funcs->get_fw_boot_option = dmub_dcn35_get_fw_boot_option; 393 funcs->enable_dmub_boot_options = dmub_dcn35_enable_dmub_boot_options; 394 funcs->skip_dmub_panel_power_sequence = dmub_dcn35_skip_dmub_panel_power_sequence; 395 //outbox0 call stacks 396 funcs->setup_outbox0 = dmub_dcn35_setup_outbox0; 397 funcs->get_outbox0_wptr = dmub_dcn35_get_outbox0_wptr; 398 funcs->set_outbox0_rptr = dmub_dcn35_set_outbox0_rptr; 399 400 funcs->get_current_time = dmub_dcn35_get_current_time; 401 funcs->get_diagnostic_data = dmub_dcn35_get_diagnostic_data; 402 funcs->get_preos_fw_info = dmub_dcn35_get_preos_fw_info; 403 404 funcs->init_reg_offsets = dmub_srv_dcn35_regs_init; 405 if (asic == DMUB_ASIC_DCN351) 406 funcs->init_reg_offsets = dmub_srv_dcn351_regs_init; 407 if (asic == DMUB_ASIC_DCN36) 408 funcs->init_reg_offsets = dmub_srv_dcn36_regs_init; 409 410 funcs->is_hw_powered_up = dmub_dcn35_is_hw_powered_up; 411 funcs->should_detect = dmub_dcn35_should_detect; 412 break; 413 414 case DMUB_ASIC_DCN401: 415 dmub->regs_dcn401 = &dmub_srv_dcn401_regs; 416 funcs->configure_dmub_in_system_memory = dmub_dcn401_configure_dmub_in_system_memory; 417 funcs->send_inbox0_cmd = dmub_dcn401_send_inbox0_cmd; 418 funcs->clear_inbox0_ack_register = dmub_dcn401_clear_inbox0_ack_register; 419 funcs->read_inbox0_ack_register = dmub_dcn401_read_inbox0_ack_register; 420 funcs->reset = dmub_dcn401_reset; 421 funcs->reset_release = dmub_dcn401_reset_release; 422 funcs->backdoor_load = dmub_dcn401_backdoor_load; 423 funcs->backdoor_load_zfb_mode = dmub_dcn401_backdoor_load_zfb_mode; 424 funcs->setup_windows = dmub_dcn401_setup_windows; 425 funcs->setup_mailbox = dmub_dcn401_setup_mailbox; 426 funcs->get_inbox1_wptr = dmub_dcn401_get_inbox1_wptr; 427 funcs->get_inbox1_rptr = dmub_dcn401_get_inbox1_rptr; 428 funcs->set_inbox1_wptr = dmub_dcn401_set_inbox1_wptr; 429 funcs->setup_out_mailbox = dmub_dcn401_setup_out_mailbox; 430 funcs->get_outbox1_wptr = dmub_dcn401_get_outbox1_wptr; 431 funcs->set_outbox1_rptr = dmub_dcn401_set_outbox1_rptr; 432 funcs->is_supported = dmub_dcn401_is_supported; 433 funcs->is_hw_init = dmub_dcn401_is_hw_init; 434 funcs->set_gpint = dmub_dcn401_set_gpint; 435 funcs->is_gpint_acked = dmub_dcn401_is_gpint_acked; 436 funcs->get_gpint_response = dmub_dcn401_get_gpint_response; 437 funcs->get_gpint_dataout = dmub_dcn401_get_gpint_dataout; 438 funcs->get_fw_status = dmub_dcn401_get_fw_boot_status; 439 funcs->enable_dmub_boot_options = dmub_dcn401_enable_dmub_boot_options; 440 funcs->skip_dmub_panel_power_sequence = dmub_dcn401_skip_dmub_panel_power_sequence; 441 //outbox0 call stacks 442 funcs->setup_outbox0 = dmub_dcn401_setup_outbox0; 443 funcs->get_outbox0_wptr = dmub_dcn401_get_outbox0_wptr; 444 funcs->set_outbox0_rptr = dmub_dcn401_set_outbox0_rptr; 445 446 funcs->get_current_time = dmub_dcn401_get_current_time; 447 funcs->get_diagnostic_data = dmub_dcn401_get_diagnostic_data; 448 449 funcs->send_reg_inbox0_cmd_msg = dmub_dcn401_send_reg_inbox0_cmd_msg; 450 funcs->read_reg_inbox0_rsp_int_status = dmub_dcn401_read_reg_inbox0_rsp_int_status; 451 funcs->read_reg_inbox0_cmd_rsp = dmub_dcn401_read_reg_inbox0_cmd_rsp; 452 funcs->write_reg_inbox0_rsp_int_ack = dmub_dcn401_write_reg_inbox0_rsp_int_ack; 453 funcs->clear_reg_inbox0_rsp_int_ack = dmub_dcn401_clear_reg_inbox0_rsp_int_ack; 454 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 455 default_inbox_type = DMUB_CMD_INTERFACE_FB; // still default to FB for now 456 457 funcs->write_reg_outbox0_rdy_int_ack = dmub_dcn401_write_reg_outbox0_rdy_int_ack; 458 funcs->read_reg_outbox0_msg = dmub_dcn401_read_reg_outbox0_msg; 459 funcs->write_reg_outbox0_rsp = dmub_dcn401_write_reg_outbox0_rsp; 460 funcs->read_reg_outbox0_rdy_int_status = dmub_dcn401_read_reg_outbox0_rdy_int_status; 461 funcs->read_reg_outbox0_rsp_int_status = dmub_dcn401_read_reg_outbox0_rsp_int_status; 462 funcs->enable_reg_inbox0_rsp_int = dmub_dcn401_enable_reg_inbox0_rsp_int; 463 funcs->enable_reg_outbox0_rdy_int = dmub_dcn401_enable_reg_outbox0_rdy_int; 464 break; 465 default: 466 return false; 467 } 468 469 /* set default inbox type if not overriden */ 470 if (dmub->inbox_type == DMUB_CMD_INTERFACE_DEFAULT) { 471 if (default_inbox_type != DMUB_CMD_INTERFACE_DEFAULT) { 472 /* use default inbox type as specified by DCN rev */ 473 dmub->inbox_type = default_inbox_type; 474 } else if (funcs->send_reg_inbox0_cmd_msg) { 475 /* prefer reg as default inbox type if present */ 476 dmub->inbox_type = DMUB_CMD_INTERFACE_REG; 477 } else { 478 /* use fb as fallback */ 479 dmub->inbox_type = DMUB_CMD_INTERFACE_FB; 480 } 481 } 482 483 return true; 484 } 485 486 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 487 const struct dmub_srv_create_params *params) 488 { 489 enum dmub_status status = DMUB_STATUS_OK; 490 491 dmub_memset(dmub, 0, sizeof(*dmub)); 492 493 dmub->funcs = params->funcs; 494 dmub->user_ctx = params->user_ctx; 495 dmub->asic = params->asic; 496 dmub->fw_version = params->fw_version; 497 dmub->is_virtual = params->is_virtual; 498 dmub->inbox_type = params->inbox_type; 499 500 /* Setup asic dependent hardware funcs. */ 501 if (!dmub_srv_hw_setup(dmub, params->asic)) { 502 status = DMUB_STATUS_INVALID; 503 goto cleanup; 504 } 505 506 /* Override (some) hardware funcs based on user params. */ 507 if (params->hw_funcs) { 508 if (params->hw_funcs->emul_get_inbox1_rptr) 509 dmub->hw_funcs.emul_get_inbox1_rptr = 510 params->hw_funcs->emul_get_inbox1_rptr; 511 512 if (params->hw_funcs->emul_set_inbox1_wptr) 513 dmub->hw_funcs.emul_set_inbox1_wptr = 514 params->hw_funcs->emul_set_inbox1_wptr; 515 516 if (params->hw_funcs->is_supported) 517 dmub->hw_funcs.is_supported = 518 params->hw_funcs->is_supported; 519 } 520 521 /* Sanity checks for required hw func pointers. */ 522 if (!dmub->hw_funcs.get_inbox1_rptr || 523 !dmub->hw_funcs.set_inbox1_wptr) { 524 status = DMUB_STATUS_INVALID; 525 goto cleanup; 526 } 527 528 cleanup: 529 if (status == DMUB_STATUS_OK) 530 dmub->sw_init = true; 531 else 532 dmub_srv_destroy(dmub); 533 534 return status; 535 } 536 537 void dmub_srv_destroy(struct dmub_srv *dmub) 538 { 539 dmub_memset(dmub, 0, sizeof(*dmub)); 540 } 541 542 static uint32_t dmub_srv_calc_regions_for_memory_type(const struct dmub_srv_region_params *params, 543 struct dmub_srv_region_info *out, 544 const uint32_t *window_sizes, 545 enum dmub_window_memory_type memory_type) 546 { 547 uint32_t i, top = 0; 548 549 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 550 if (params->window_memory_type[i] == memory_type) { 551 struct dmub_region *region = &out->regions[i]; 552 553 region->base = dmub_align(top, 256); 554 region->top = region->base + dmub_align(window_sizes[i], 64); 555 top = region->top; 556 } 557 } 558 559 return dmub_align(top, 4096); 560 } 561 562 enum dmub_status 563 dmub_srv_calc_region_info(struct dmub_srv *dmub, 564 const struct dmub_srv_region_params *params, 565 struct dmub_srv_region_info *out) 566 { 567 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 568 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 569 uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE; 570 uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 }; 571 572 if (!dmub->sw_init) 573 return DMUB_STATUS_INVALID; 574 575 memset(out, 0, sizeof(*out)); 576 memset(window_sizes, 0, sizeof(window_sizes)); 577 578 out->num_regions = DMUB_NUM_WINDOWS; 579 580 if (params->fw_info) { 581 memcpy(&dmub->meta_info, params->fw_info, sizeof(*params->fw_info)); 582 583 fw_state_size = params->fw_info->fw_region_size; 584 trace_buffer_size = params->fw_info->trace_buffer_size; 585 shared_state_size = params->fw_info->shared_state_size; 586 587 /** 588 * If DM didn't fill in a version, then fill it in based on 589 * the firmware meta now that we have it. 590 * 591 * TODO: Make it easier for driver to extract this out to 592 * pass during creation. 593 */ 594 if (dmub->fw_version == 0) 595 dmub->fw_version = params->fw_info->fw_version; 596 } 597 598 window_sizes[DMUB_WINDOW_0_INST_CONST] = params->inst_const_size; 599 window_sizes[DMUB_WINDOW_1_STACK] = DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 600 window_sizes[DMUB_WINDOW_2_BSS_DATA] = params->bss_data_size; 601 window_sizes[DMUB_WINDOW_3_VBIOS] = params->vbios_size; 602 window_sizes[DMUB_WINDOW_4_MAILBOX] = DMUB_MAILBOX_SIZE; 603 window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size; 604 window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size; 605 window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = dmub_align(DMUB_SCRATCH_MEM_SIZE, 64); 606 window_sizes[DMUB_WINDOW_IB_MEM] = DMUB_IB_MEM_SIZE; 607 window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size); 608 window_sizes[DMUB_WINDOW_LSDMA_BUFFER] = DMUB_LSDMA_RB_SIZE; 609 window_sizes[DMUB_WINDOW_CURSOR_OFFLOAD] = dmub_align(sizeof(struct dmub_cursor_offload_v1), 64); 610 611 out->fb_size = 612 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB); 613 614 out->gart_size = 615 dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_GART); 616 617 return DMUB_STATUS_OK; 618 } 619 620 enum dmub_status dmub_srv_calc_mem_info(struct dmub_srv *dmub, 621 const struct dmub_srv_memory_params *params, 622 struct dmub_srv_fb_info *out) 623 { 624 uint32_t i; 625 626 if (!dmub->sw_init) 627 return DMUB_STATUS_INVALID; 628 629 memset(out, 0, sizeof(*out)); 630 631 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 632 return DMUB_STATUS_INVALID; 633 634 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 635 const struct dmub_region *reg = 636 ¶ms->region_info->regions[i]; 637 638 if (params->window_memory_type[i] == DMUB_WINDOW_MEMORY_TYPE_GART) { 639 out->fb[i].cpu_addr = (uint8_t *)params->cpu_gart_addr + reg->base; 640 out->fb[i].gpu_addr = params->gpu_gart_addr + reg->base; 641 } else { 642 out->fb[i].cpu_addr = (uint8_t *)params->cpu_fb_addr + reg->base; 643 out->fb[i].gpu_addr = params->gpu_fb_addr + reg->base; 644 } 645 646 out->fb[i].size = reg->top - reg->base; 647 } 648 649 out->num_fb = DMUB_NUM_WINDOWS; 650 651 return DMUB_STATUS_OK; 652 } 653 654 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 655 bool *is_supported) 656 { 657 *is_supported = false; 658 659 if (!dmub->sw_init) 660 return DMUB_STATUS_INVALID; 661 662 if (dmub->hw_funcs.is_supported) 663 *is_supported = dmub->hw_funcs.is_supported(dmub); 664 665 return DMUB_STATUS_OK; 666 } 667 668 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 669 { 670 *is_hw_init = false; 671 672 if (!dmub->sw_init) 673 return DMUB_STATUS_INVALID; 674 675 if (!dmub->hw_init) 676 return DMUB_STATUS_OK; 677 678 if (dmub->hw_funcs.is_hw_init) 679 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 680 681 return DMUB_STATUS_OK; 682 } 683 684 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 685 const struct dmub_srv_hw_params *params) 686 { 687 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 688 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 689 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 690 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 691 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 692 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 693 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 694 struct dmub_fb *shared_state_fb = params->fb[DMUB_WINDOW_SHARED_STATE]; 695 696 struct dmub_rb_init_params rb_params, outbox0_rb_params; 697 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6, region6; 698 struct dmub_region inbox1, outbox1, outbox0; 699 700 uint32_t i; 701 702 if (!dmub->sw_init) 703 return DMUB_STATUS_INVALID; 704 705 for (i = 0; i < DMUB_WINDOW_TOTAL; ++i) { 706 if (!params->fb[i]) { 707 ASSERT(0); 708 return DMUB_STATUS_INVALID; 709 } 710 } 711 712 dmub->fb_base = params->fb_base; 713 dmub->fb_offset = params->fb_offset; 714 dmub->psp_version = params->psp_version; 715 716 if (dmub->hw_funcs.reset) 717 dmub->hw_funcs.reset(dmub); 718 719 /* reset the cache of the last wptr as well now that hw is reset */ 720 dmub->inbox1_last_wptr = 0; 721 722 cw0.offset.quad_part = inst_fb->gpu_addr; 723 cw0.region.base = DMUB_CW0_BASE; 724 cw0.region.top = cw0.region.base + inst_fb->size - 1; 725 726 cw1.offset.quad_part = stack_fb->gpu_addr; 727 cw1.region.base = DMUB_CW1_BASE; 728 cw1.region.top = cw1.region.base + stack_fb->size - 1; 729 730 if (params->fw_in_system_memory && dmub->hw_funcs.configure_dmub_in_system_memory) 731 dmub->hw_funcs.configure_dmub_in_system_memory(dmub); 732 733 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) { 734 /** 735 * Read back all the instruction memory so we don't hang the 736 * DMCUB when backdoor loading if the write from x86 hasn't been 737 * flushed yet. This only occurs in backdoor loading. 738 */ 739 if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU) 740 dmub_flush_buffer_mem(inst_fb); 741 742 if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode) 743 dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1); 744 else 745 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 746 } 747 748 cw2.offset.quad_part = data_fb->gpu_addr; 749 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 750 cw2.region.top = cw2.region.base + data_fb->size; 751 752 cw3.offset.quad_part = bios_fb->gpu_addr; 753 cw3.region.base = DMUB_CW3_BASE; 754 cw3.region.top = cw3.region.base + bios_fb->size; 755 756 cw4.offset.quad_part = mail_fb->gpu_addr; 757 cw4.region.base = DMUB_CW4_BASE; 758 cw4.region.top = cw4.region.base + mail_fb->size; 759 760 /** 761 * Doubled the mailbox region to accomodate inbox and outbox. 762 * Note: Currently, currently total mailbox size is 16KB. It is split 763 * equally into 8KB between inbox and outbox. If this config is 764 * changed, then uncached base address configuration of outbox1 765 * has to be updated in funcs->setup_out_mailbox. 766 */ 767 inbox1.base = cw4.region.base; 768 inbox1.top = cw4.region.base + DMUB_RB_SIZE; 769 outbox1.base = inbox1.top; 770 outbox1.top = inbox1.top + DMUB_RB_SIZE; 771 772 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 773 cw5.region.base = DMUB_CW5_BASE; 774 cw5.region.top = cw5.region.base + tracebuff_fb->size; 775 776 outbox0.base = DMUB_REGION5_BASE + TRACE_BUFFER_ENTRY_OFFSET; 777 outbox0.top = outbox0.base + tracebuff_fb->size - TRACE_BUFFER_ENTRY_OFFSET; 778 779 cw6.offset.quad_part = fw_state_fb->gpu_addr; 780 cw6.region.base = DMUB_CW6_BASE; 781 cw6.region.top = cw6.region.base + fw_state_fb->size; 782 783 dmub->fw_state = (void *)((uintptr_t)(fw_state_fb->cpu_addr) + DMUB_DEBUG_FW_STATE_OFFSET); 784 785 region6.offset.quad_part = shared_state_fb->gpu_addr; 786 region6.region.base = DMUB_CW6_BASE; 787 region6.region.top = region6.region.base + shared_state_fb->size; 788 789 dmub->shared_state = shared_state_fb->cpu_addr; 790 791 dmub->scratch_mem_fb = *params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 792 dmub->ib_mem_gart = *params->fb[DMUB_WINDOW_IB_MEM]; 793 794 dmub->cursor_offload_fb = *params->fb[DMUB_WINDOW_CURSOR_OFFLOAD]; 795 dmub->cursor_offload_v1 = (struct dmub_cursor_offload_v1 *)dmub->cursor_offload_fb.cpu_addr; 796 797 if (dmub->hw_funcs.setup_windows) 798 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, &cw5, &cw6, ®ion6); 799 800 if (dmub->hw_funcs.setup_outbox0) 801 dmub->hw_funcs.setup_outbox0(dmub, &outbox0); 802 803 if (dmub->hw_funcs.setup_mailbox) 804 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 805 if (dmub->hw_funcs.setup_out_mailbox) 806 dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1); 807 if (dmub->hw_funcs.enable_reg_inbox0_rsp_int) 808 dmub->hw_funcs.enable_reg_inbox0_rsp_int(dmub, true); 809 if (dmub->hw_funcs.enable_reg_outbox0_rdy_int) 810 dmub->hw_funcs.enable_reg_outbox0_rdy_int(dmub, true); 811 812 dmub_memset(&rb_params, 0, sizeof(rb_params)); 813 rb_params.ctx = dmub; 814 rb_params.base_address = mail_fb->cpu_addr; 815 rb_params.capacity = DMUB_RB_SIZE; 816 dmub_rb_init(&dmub->inbox1.rb, &rb_params); 817 818 // Initialize outbox1 ring buffer 819 rb_params.ctx = dmub; 820 rb_params.base_address = (void *) ((uint8_t *) (mail_fb->cpu_addr) + DMUB_RB_SIZE); 821 rb_params.capacity = DMUB_RB_SIZE; 822 dmub_rb_init(&dmub->outbox1_rb, &rb_params); 823 824 dmub_memset(&outbox0_rb_params, 0, sizeof(outbox0_rb_params)); 825 outbox0_rb_params.ctx = dmub; 826 outbox0_rb_params.base_address = (void *)((uintptr_t)(tracebuff_fb->cpu_addr) + TRACE_BUFFER_ENTRY_OFFSET); 827 outbox0_rb_params.capacity = tracebuff_fb->size - dmub_align(TRACE_BUFFER_ENTRY_OFFSET, 64); 828 dmub_rb_init(&dmub->outbox0_rb, &outbox0_rb_params); 829 830 /* Report to DMUB what features are supported by current driver */ 831 if (dmub->hw_funcs.enable_dmub_boot_options) 832 dmub->hw_funcs.enable_dmub_boot_options(dmub, params); 833 834 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 835 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, 836 params->skip_panel_power_sequence); 837 838 if (dmub->hw_funcs.reset_release && !dmub->is_virtual) 839 dmub->hw_funcs.reset_release(dmub); 840 841 dmub->hw_init = true; 842 dmub->power_state = DMUB_POWER_STATE_D0; 843 844 return DMUB_STATUS_OK; 845 } 846 847 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 848 { 849 if (!dmub->sw_init) 850 return DMUB_STATUS_INVALID; 851 852 if (dmub->hw_funcs.reset) 853 dmub->hw_funcs.reset(dmub); 854 855 /* mailboxes have been reset in hw, so reset the sw state as well */ 856 dmub->inbox1_last_wptr = 0; 857 dmub->inbox1.rb.wrpt = 0; 858 dmub->inbox1.rb.rptr = 0; 859 dmub->inbox1.num_reported = 0; 860 dmub->inbox1.num_submitted = 0; 861 dmub->reg_inbox0.num_reported = 0; 862 dmub->reg_inbox0.num_submitted = 0; 863 dmub->reg_inbox0.is_pending = 0; 864 dmub->outbox0_rb.wrpt = 0; 865 dmub->outbox0_rb.rptr = 0; 866 dmub->outbox1_rb.wrpt = 0; 867 dmub->outbox1_rb.rptr = 0; 868 869 dmub->hw_init = false; 870 871 return DMUB_STATUS_OK; 872 } 873 874 enum dmub_status dmub_srv_fb_cmd_queue(struct dmub_srv *dmub, 875 const union dmub_rb_cmd *cmd) 876 { 877 if (!dmub->hw_init) 878 return DMUB_STATUS_INVALID; 879 880 if (dmub->power_state != DMUB_POWER_STATE_D0) 881 return DMUB_STATUS_POWER_STATE_D3; 882 883 if (dmub->inbox1.rb.rptr > dmub->inbox1.rb.capacity || 884 dmub->inbox1.rb.wrpt > dmub->inbox1.rb.capacity) { 885 return DMUB_STATUS_HW_FAILURE; 886 } 887 888 if (dmub_rb_push_front(&dmub->inbox1.rb, cmd)) { 889 dmub->inbox1.num_submitted++; 890 return DMUB_STATUS_OK; 891 } 892 893 return DMUB_STATUS_QUEUE_FULL; 894 } 895 896 enum dmub_status dmub_srv_fb_cmd_execute(struct dmub_srv *dmub) 897 { 898 struct dmub_rb flush_rb; 899 900 if (!dmub->hw_init) 901 return DMUB_STATUS_INVALID; 902 903 if (dmub->power_state != DMUB_POWER_STATE_D0) 904 return DMUB_STATUS_POWER_STATE_D3; 905 906 /** 907 * Read back all the queued commands to ensure that they've 908 * been flushed to framebuffer memory. Otherwise DMCUB might 909 * read back stale, fully invalid or partially invalid data. 910 */ 911 flush_rb = dmub->inbox1.rb; 912 flush_rb.rptr = dmub->inbox1_last_wptr; 913 dmub_rb_flush_pending(&flush_rb); 914 915 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1.rb.wrpt); 916 917 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 918 919 return DMUB_STATUS_OK; 920 } 921 922 bool dmub_srv_is_hw_pwr_up(struct dmub_srv *dmub) 923 { 924 if (!dmub->hw_funcs.is_hw_powered_up) 925 return true; 926 927 if (!dmub->hw_funcs.is_hw_powered_up(dmub)) 928 return false; 929 930 return true; 931 } 932 933 enum dmub_status dmub_srv_wait_for_hw_pwr_up(struct dmub_srv *dmub, 934 uint32_t timeout_us) 935 { 936 uint32_t i; 937 938 if (!dmub->hw_init) 939 return DMUB_STATUS_INVALID; 940 941 for (i = 0; i <= timeout_us; i += 100) { 942 if (dmub_srv_is_hw_pwr_up(dmub)) 943 return DMUB_STATUS_OK; 944 945 udelay(100); 946 } 947 948 return DMUB_STATUS_TIMEOUT; 949 } 950 951 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 952 uint32_t timeout_us) 953 { 954 uint32_t i; 955 bool hw_on = true; 956 957 if (!dmub->hw_init) 958 return DMUB_STATUS_INVALID; 959 960 for (i = 0; i <= timeout_us; i += 100) { 961 union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub); 962 963 if (dmub->hw_funcs.is_hw_powered_up) 964 hw_on = dmub->hw_funcs.is_hw_powered_up(dmub); 965 966 if (status.bits.dal_fw && status.bits.mailbox_rdy && hw_on) 967 return DMUB_STATUS_OK; 968 969 udelay(100); 970 } 971 972 return DMUB_STATUS_TIMEOUT; 973 } 974 975 static void dmub_srv_update_reg_inbox0_status(struct dmub_srv *dmub) 976 { 977 if (dmub->reg_inbox0.is_pending) { 978 dmub->reg_inbox0.is_pending = dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 979 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 980 981 if (!dmub->reg_inbox0.is_pending) { 982 /* ack the rsp interrupt */ 983 if (dmub->hw_funcs.write_reg_inbox0_rsp_int_ack) 984 dmub->hw_funcs.write_reg_inbox0_rsp_int_ack(dmub); 985 986 /* only update the reported count if commands aren't being batched */ 987 if (!dmub->reg_inbox0.is_pending && !dmub->reg_inbox0.is_multi_pending) { 988 dmub->reg_inbox0.num_reported = dmub->reg_inbox0.num_submitted; 989 } 990 } 991 } 992 } 993 994 enum dmub_status dmub_srv_wait_for_pending(struct dmub_srv *dmub, 995 uint32_t timeout_us) 996 { 997 uint32_t i; 998 const uint32_t polling_interval_us = 1; 999 struct dmub_srv_inbox scratch_reg_inbox0 = dmub->reg_inbox0; 1000 struct dmub_srv_inbox scratch_inbox1 = dmub->inbox1; 1001 const volatile struct dmub_srv_inbox *reg_inbox0 = &dmub->reg_inbox0; 1002 const volatile struct dmub_srv_inbox *inbox1 = &dmub->inbox1; 1003 1004 if (!dmub->hw_init || 1005 !dmub->hw_funcs.get_inbox1_wptr) 1006 return DMUB_STATUS_INVALID; 1007 1008 for (i = 0; i <= timeout_us; i += polling_interval_us) { 1009 scratch_inbox1.rb.wrpt = dmub->hw_funcs.get_inbox1_wptr(dmub); 1010 scratch_inbox1.rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1011 1012 scratch_reg_inbox0.is_pending = scratch_reg_inbox0.is_pending && 1013 dmub->hw_funcs.read_reg_inbox0_rsp_int_status && 1014 !dmub->hw_funcs.read_reg_inbox0_rsp_int_status(dmub); 1015 1016 if (scratch_inbox1.rb.rptr > dmub->inbox1.rb.capacity) 1017 return DMUB_STATUS_HW_FAILURE; 1018 1019 /* check current HW state first, but use command submission vs reported as a fallback */ 1020 if ((dmub_rb_empty(&scratch_inbox1.rb) || 1021 inbox1->num_reported >= scratch_inbox1.num_submitted) && 1022 (!scratch_reg_inbox0.is_pending || 1023 reg_inbox0->num_reported >= scratch_reg_inbox0.num_submitted)) 1024 return DMUB_STATUS_OK; 1025 1026 udelay(polling_interval_us); 1027 } 1028 1029 return DMUB_STATUS_TIMEOUT; 1030 } 1031 1032 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 1033 uint32_t timeout_us) 1034 { 1035 enum dmub_status status; 1036 uint32_t i; 1037 const uint32_t polling_interval_us = 1; 1038 1039 if (!dmub->hw_init) 1040 return DMUB_STATUS_INVALID; 1041 1042 for (i = 0; i < timeout_us; i += polling_interval_us) { 1043 status = dmub_srv_update_inbox_status(dmub); 1044 1045 if (status != DMUB_STATUS_OK) 1046 return status; 1047 1048 /* check for idle */ 1049 if (dmub_rb_empty(&dmub->inbox1.rb) && !dmub->reg_inbox0.is_pending) 1050 return DMUB_STATUS_OK; 1051 1052 udelay(polling_interval_us); 1053 } 1054 1055 return DMUB_STATUS_TIMEOUT; 1056 } 1057 1058 enum dmub_status 1059 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 1060 enum dmub_gpint_command command_code, 1061 uint16_t param, uint32_t timeout_us) 1062 { 1063 union dmub_gpint_data_register reg; 1064 uint32_t i; 1065 1066 if (!dmub->sw_init) 1067 return DMUB_STATUS_INVALID; 1068 1069 if (!dmub->hw_funcs.set_gpint) 1070 return DMUB_STATUS_INVALID; 1071 1072 if (!dmub->hw_funcs.is_gpint_acked) 1073 return DMUB_STATUS_INVALID; 1074 1075 reg.bits.status = 1; 1076 reg.bits.command_code = command_code; 1077 reg.bits.param = param; 1078 1079 dmub->hw_funcs.set_gpint(dmub, reg); 1080 1081 for (i = 0; i < timeout_us; ++i) { 1082 udelay(1); 1083 1084 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 1085 return DMUB_STATUS_OK; 1086 } 1087 1088 return DMUB_STATUS_TIMEOUT; 1089 } 1090 1091 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 1092 uint32_t *response) 1093 { 1094 *response = 0; 1095 1096 if (!dmub->sw_init) 1097 return DMUB_STATUS_INVALID; 1098 1099 if (!dmub->hw_funcs.get_gpint_response) 1100 return DMUB_STATUS_INVALID; 1101 1102 *response = dmub->hw_funcs.get_gpint_response(dmub); 1103 1104 return DMUB_STATUS_OK; 1105 } 1106 1107 enum dmub_status dmub_srv_get_gpint_dataout(struct dmub_srv *dmub, 1108 uint32_t *dataout) 1109 { 1110 *dataout = 0; 1111 1112 if (!dmub->sw_init) 1113 return DMUB_STATUS_INVALID; 1114 1115 if (!dmub->hw_funcs.get_gpint_dataout) 1116 return DMUB_STATUS_INVALID; 1117 1118 *dataout = dmub->hw_funcs.get_gpint_dataout(dmub); 1119 1120 return DMUB_STATUS_OK; 1121 } 1122 1123 enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub, 1124 union dmub_fw_boot_status *status) 1125 { 1126 status->all = 0; 1127 1128 if (!dmub->sw_init) 1129 return DMUB_STATUS_INVALID; 1130 1131 if (dmub->hw_funcs.get_fw_status) 1132 *status = dmub->hw_funcs.get_fw_status(dmub); 1133 1134 return DMUB_STATUS_OK; 1135 } 1136 1137 enum dmub_status dmub_srv_get_fw_boot_option(struct dmub_srv *dmub, 1138 union dmub_fw_boot_options *option) 1139 { 1140 option->all = 0; 1141 1142 if (!dmub->sw_init) 1143 return DMUB_STATUS_INVALID; 1144 1145 if (dmub->hw_funcs.get_fw_boot_option) 1146 *option = dmub->hw_funcs.get_fw_boot_option(dmub); 1147 1148 return DMUB_STATUS_OK; 1149 } 1150 1151 enum dmub_status dmub_srv_set_skip_panel_power_sequence(struct dmub_srv *dmub, 1152 bool skip) 1153 { 1154 if (!dmub->sw_init) 1155 return DMUB_STATUS_INVALID; 1156 1157 if (dmub->hw_funcs.skip_dmub_panel_power_sequence && !dmub->is_virtual) 1158 dmub->hw_funcs.skip_dmub_panel_power_sequence(dmub, skip); 1159 1160 return DMUB_STATUS_OK; 1161 } 1162 1163 static inline bool dmub_rb_out_trace_buffer_front(struct dmub_rb *rb, 1164 void *entry) 1165 { 1166 const uint64_t *src = (const uint64_t *)(rb->base_address) + rb->rptr / sizeof(uint64_t); 1167 uint64_t *dst = (uint64_t *)entry; 1168 uint8_t i; 1169 uint8_t loop_count; 1170 1171 if (rb->rptr == rb->wrpt) 1172 return false; 1173 1174 loop_count = sizeof(struct dmcub_trace_buf_entry) / sizeof(uint64_t); 1175 // copying data 1176 for (i = 0; i < loop_count; i++) 1177 *dst++ = *src++; 1178 1179 rb->rptr += sizeof(struct dmcub_trace_buf_entry); 1180 1181 rb->rptr %= rb->capacity; 1182 1183 return true; 1184 } 1185 1186 bool dmub_srv_get_outbox0_msg(struct dmub_srv *dmub, struct dmcub_trace_buf_entry *entry) 1187 { 1188 dmub->outbox0_rb.wrpt = dmub->hw_funcs.get_outbox0_wptr(dmub); 1189 1190 return dmub_rb_out_trace_buffer_front(&dmub->outbox0_rb, (void *)entry); 1191 } 1192 1193 bool dmub_srv_get_diagnostic_data(struct dmub_srv *dmub) 1194 { 1195 if (!dmub || !dmub->hw_funcs.get_diagnostic_data) 1196 return false; 1197 dmub->hw_funcs.get_diagnostic_data(dmub); 1198 return true; 1199 } 1200 1201 bool dmub_srv_should_detect(struct dmub_srv *dmub) 1202 { 1203 if (!dmub->hw_init || !dmub->hw_funcs.should_detect) 1204 return false; 1205 1206 return dmub->hw_funcs.should_detect(dmub); 1207 } 1208 1209 enum dmub_status dmub_srv_clear_inbox0_ack(struct dmub_srv *dmub) 1210 { 1211 if (!dmub->hw_init || !dmub->hw_funcs.clear_inbox0_ack_register) 1212 return DMUB_STATUS_INVALID; 1213 1214 dmub->hw_funcs.clear_inbox0_ack_register(dmub); 1215 return DMUB_STATUS_OK; 1216 } 1217 1218 enum dmub_status dmub_srv_wait_for_inbox0_ack(struct dmub_srv *dmub, uint32_t timeout_us) 1219 { 1220 uint32_t i = 0; 1221 uint32_t ack = 0; 1222 1223 if (!dmub->hw_init || !dmub->hw_funcs.read_inbox0_ack_register) 1224 return DMUB_STATUS_INVALID; 1225 1226 for (i = 0; i <= timeout_us; i++) { 1227 ack = dmub->hw_funcs.read_inbox0_ack_register(dmub); 1228 if (ack) 1229 return DMUB_STATUS_OK; 1230 udelay(1); 1231 } 1232 return DMUB_STATUS_TIMEOUT; 1233 } 1234 1235 enum dmub_status dmub_srv_send_inbox0_cmd(struct dmub_srv *dmub, 1236 union dmub_inbox0_data_register data) 1237 { 1238 if (!dmub->hw_init || !dmub->hw_funcs.send_inbox0_cmd) 1239 return DMUB_STATUS_INVALID; 1240 1241 dmub->hw_funcs.send_inbox0_cmd(dmub, data); 1242 return DMUB_STATUS_OK; 1243 } 1244 1245 void dmub_srv_subvp_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 1246 { 1247 if (dmub->hw_funcs.subvp_save_surf_addr) { 1248 dmub->hw_funcs.subvp_save_surf_addr(dmub, 1249 addr, 1250 subvp_index); 1251 } 1252 } 1253 1254 void dmub_srv_set_power_state(struct dmub_srv *dmub, enum dmub_srv_power_state_type dmub_srv_power_state) 1255 { 1256 if (!dmub || !dmub->hw_init) 1257 return; 1258 1259 dmub->power_state = dmub_srv_power_state; 1260 } 1261 1262 enum dmub_status dmub_srv_reg_cmd_execute(struct dmub_srv *dmub, union dmub_rb_cmd *cmd) 1263 { 1264 uint32_t num_pending = 0; 1265 1266 if (!dmub->hw_init) 1267 return DMUB_STATUS_INVALID; 1268 1269 if (dmub->power_state != DMUB_POWER_STATE_D0) 1270 return DMUB_STATUS_POWER_STATE_D3; 1271 1272 if (!dmub->hw_funcs.send_reg_inbox0_cmd_msg || 1273 !dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack) 1274 return DMUB_STATUS_INVALID; 1275 1276 if (dmub->reg_inbox0.num_submitted >= dmub->reg_inbox0.num_reported) 1277 num_pending = dmub->reg_inbox0.num_submitted - dmub->reg_inbox0.num_reported; 1278 else 1279 /* num_submitted wrapped */ 1280 num_pending = DMUB_REG_INBOX0_RB_MAX_ENTRY - 1281 (dmub->reg_inbox0.num_reported - dmub->reg_inbox0.num_submitted); 1282 1283 if (num_pending >= DMUB_REG_INBOX0_RB_MAX_ENTRY) 1284 return DMUB_STATUS_QUEUE_FULL; 1285 1286 /* clear last rsp ack and send message */ 1287 dmub->hw_funcs.clear_reg_inbox0_rsp_int_ack(dmub); 1288 dmub->hw_funcs.send_reg_inbox0_cmd_msg(dmub, cmd); 1289 1290 dmub->reg_inbox0.num_submitted++; 1291 dmub->reg_inbox0.is_pending = true; 1292 dmub->reg_inbox0.is_multi_pending = cmd->cmd_common.header.multi_cmd_pending; 1293 1294 return DMUB_STATUS_OK; 1295 } 1296 1297 void dmub_srv_cmd_get_response(struct dmub_srv *dmub, 1298 union dmub_rb_cmd *cmd_rsp) 1299 { 1300 if (dmub) { 1301 if (dmub->inbox_type == DMUB_CMD_INTERFACE_REG && 1302 dmub->hw_funcs.read_reg_inbox0_cmd_rsp) { 1303 dmub->hw_funcs.read_reg_inbox0_cmd_rsp(dmub, cmd_rsp); 1304 } else { 1305 dmub_rb_get_return_data(&dmub->inbox1.rb, cmd_rsp); 1306 } 1307 } 1308 } 1309 1310 static enum dmub_status dmub_srv_sync_reg_inbox0(struct dmub_srv *dmub) 1311 { 1312 if (!dmub || !dmub->sw_init) 1313 return DMUB_STATUS_INVALID; 1314 1315 dmub->reg_inbox0.is_pending = 0; 1316 dmub->reg_inbox0.is_multi_pending = 0; 1317 1318 return DMUB_STATUS_OK; 1319 } 1320 1321 static enum dmub_status dmub_srv_sync_inbox1(struct dmub_srv *dmub) 1322 { 1323 if (!dmub->sw_init) 1324 return DMUB_STATUS_INVALID; 1325 1326 if (dmub->hw_funcs.get_inbox1_rptr && dmub->hw_funcs.get_inbox1_wptr) { 1327 uint32_t rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1328 uint32_t wptr = dmub->hw_funcs.get_inbox1_wptr(dmub); 1329 1330 if (rptr > dmub->inbox1.rb.capacity || wptr > dmub->inbox1.rb.capacity) { 1331 return DMUB_STATUS_HW_FAILURE; 1332 } else { 1333 dmub->inbox1.rb.rptr = rptr; 1334 dmub->inbox1.rb.wrpt = wptr; 1335 dmub->inbox1_last_wptr = dmub->inbox1.rb.wrpt; 1336 } 1337 } 1338 1339 return DMUB_STATUS_OK; 1340 } 1341 1342 enum dmub_status dmub_srv_sync_inboxes(struct dmub_srv *dmub) 1343 { 1344 enum dmub_status status; 1345 1346 status = dmub_srv_sync_reg_inbox0(dmub); 1347 if (status != DMUB_STATUS_OK) 1348 return status; 1349 1350 status = dmub_srv_sync_inbox1(dmub); 1351 if (status != DMUB_STATUS_OK) 1352 return status; 1353 1354 return DMUB_STATUS_OK; 1355 } 1356 1357 enum dmub_status dmub_srv_wait_for_inbox_free(struct dmub_srv *dmub, 1358 uint32_t timeout_us, 1359 uint32_t num_free_required) 1360 { 1361 enum dmub_status status; 1362 uint32_t i; 1363 const uint32_t polling_interval_us = 1; 1364 1365 if (!dmub->hw_init) 1366 return DMUB_STATUS_INVALID; 1367 1368 for (i = 0; i < timeout_us; i += polling_interval_us) { 1369 status = dmub_srv_update_inbox_status(dmub); 1370 1371 if (status != DMUB_STATUS_OK) 1372 return status; 1373 1374 /* check for space in inbox1 */ 1375 if (dmub_rb_num_free(&dmub->inbox1.rb) >= num_free_required) 1376 return DMUB_STATUS_OK; 1377 1378 udelay(polling_interval_us); 1379 } 1380 1381 return DMUB_STATUS_TIMEOUT; 1382 } 1383 1384 enum dmub_status dmub_srv_update_inbox_status(struct dmub_srv *dmub) 1385 { 1386 uint32_t rptr; 1387 1388 if (!dmub->hw_init) 1389 return DMUB_STATUS_INVALID; 1390 1391 if (dmub->power_state != DMUB_POWER_STATE_D0) 1392 return DMUB_STATUS_POWER_STATE_D3; 1393 1394 /* update inbox1 state */ 1395 rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 1396 1397 if (rptr > dmub->inbox1.rb.capacity) 1398 return DMUB_STATUS_HW_FAILURE; 1399 1400 if (dmub->inbox1.rb.rptr > rptr) { 1401 /* rb wrapped */ 1402 dmub->inbox1.num_reported += (rptr + dmub->inbox1.rb.capacity - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1403 } else { 1404 dmub->inbox1.num_reported += (rptr - dmub->inbox1.rb.rptr) / DMUB_RB_CMD_SIZE; 1405 } 1406 dmub->inbox1.rb.rptr = rptr; 1407 1408 /* update reg_inbox0 */ 1409 dmub_srv_update_reg_inbox0_status(dmub); 1410 1411 return DMUB_STATUS_OK; 1412 } 1413 1414 bool dmub_srv_get_preos_info(struct dmub_srv *dmub) 1415 { 1416 if (!dmub || !dmub->hw_funcs.get_preos_fw_info) 1417 return false; 1418 1419 return dmub->hw_funcs.get_preos_fw_info(dmub); 1420 } 1421