1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dmub_reg.h" 27 #include "../dmub_srv.h" 28 29 struct dmub_reg_value_masks { 30 uint32_t value; 31 uint32_t mask; 32 }; 33 34 static inline void 35 set_reg_field_value_masks(struct dmub_reg_value_masks *field_value_mask, 36 uint32_t value, uint32_t mask, uint8_t shift) 37 { 38 field_value_mask->value = 39 (field_value_mask->value & ~mask) | (mask & (value << shift)); 40 field_value_mask->mask = field_value_mask->mask | mask; 41 } 42 43 static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, 44 uint32_t addr, int n, uint8_t shift1, 45 uint32_t mask1, uint32_t field_value1, 46 va_list ap) 47 { 48 (void)addr; 49 uint32_t shift, mask, field_value; 50 int i = 1; 51 52 /* gather all bits value/mask getting updated in this register */ 53 set_reg_field_value_masks(field_value_mask, field_value1, mask1, 54 shift1); 55 56 while (i < n) { 57 shift = va_arg(ap, uint32_t); 58 mask = va_arg(ap, uint32_t); 59 field_value = va_arg(ap, uint32_t); 60 61 ASSERT(shift <= 0xFF); 62 set_reg_field_value_masks(field_value_mask, field_value, mask, 63 (uint8_t)shift); 64 i++; 65 } 66 } 67 68 static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask, 69 uint8_t shift) 70 { 71 return (mask & reg_value) >> shift; 72 } 73 74 void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, 75 uint32_t mask1, uint32_t field_value1, ...) 76 { 77 struct dmub_reg_value_masks field_value_mask = { 0 }; 78 uint32_t reg_val; 79 va_list ap; 80 81 va_start(ap, field_value1); 82 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 83 field_value1, ap); 84 va_end(ap); 85 86 reg_val = srv->funcs.reg_read(srv->user_ctx, addr); 87 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; 88 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); 89 } 90 91 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, 92 uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) 93 { 94 struct dmub_reg_value_masks field_value_mask = { 0 }; 95 va_list ap; 96 97 va_start(ap, field_value1); 98 set_reg_field_values(&field_value_mask, addr, n, shift1, mask1, 99 field_value1, ap); 100 va_end(ap); 101 102 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; 103 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); 104 } 105 106 void dmub_reg_get(struct dmub_srv *srv, uint32_t addr, uint8_t shift, 107 uint32_t mask, uint32_t *field_value) 108 { 109 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr); 110 *field_value = get_reg_field_value_ex(reg_val, mask, shift); 111 } 112