xref: /linux/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn42b.c (revision 9611c0ce215a66770ccbe5c126bf57ba8c31bcad)
1*827d94e6SMatthew Stewart /* SPDX-License-Identifier: MIT */
2*827d94e6SMatthew Stewart /* Copyright 2026 Advanced Micro Devices, Inc. */
3*827d94e6SMatthew Stewart 
4*827d94e6SMatthew Stewart #include "../dmub_srv.h"
5*827d94e6SMatthew Stewart #include "dmub_reg.h"
6*827d94e6SMatthew Stewart #include "dmub_dcn42b.h"
7*827d94e6SMatthew Stewart 
8*827d94e6SMatthew Stewart #include "dcn/dcn_4_2_1_offset.h"
9*827d94e6SMatthew Stewart #include "dcn/dcn_4_2_1_sh_mask.h"
10*827d94e6SMatthew Stewart 
11*827d94e6SMatthew Stewart #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
12*827d94e6SMatthew Stewart #define CTX dmub
13*827d94e6SMatthew Stewart #define REGS dmub->regs_dcn42
14*827d94e6SMatthew Stewart #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
15*827d94e6SMatthew Stewart 
16*827d94e6SMatthew Stewart void dmub_srv_dcn42b_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
17*827d94e6SMatthew Stewart {
18*827d94e6SMatthew Stewart 	struct dmub_srv_dcn42_regs *regs = dmub->regs_dcn42;
19*827d94e6SMatthew Stewart #define REG_STRUCT regs
20*827d94e6SMatthew Stewart 
21*827d94e6SMatthew Stewart #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
22*827d94e6SMatthew Stewart 	DMUB_DCN42_REGS()
23*827d94e6SMatthew Stewart 	DMCUB_INTERNAL_REGS()
24*827d94e6SMatthew Stewart #undef DMUB_SR
25*827d94e6SMatthew Stewart 
26*827d94e6SMatthew Stewart #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
27*827d94e6SMatthew Stewart 	DMUB_DCN42_FIELDS()
28*827d94e6SMatthew Stewart #undef DMUB_SF
29*827d94e6SMatthew Stewart 
30*827d94e6SMatthew Stewart #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
31*827d94e6SMatthew Stewart 	DMUB_DCN42_FIELDS()
32*827d94e6SMatthew Stewart #undef DMUB_SF
33*827d94e6SMatthew Stewart #undef REG_STRUCT
34*827d94e6SMatthew Stewart }
35