1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include "../dmub_srv.h" 6 #include "dmub_reg.h" 7 #include "dmub_dcn401.h" 8 9 #include "dcn/dcn_4_1_0_offset.h" 10 #include "dcn/dcn_4_1_0_sh_mask.h" 11 12 #define DCN_BASE__INST0_SEG2 0x000034C0 13 14 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg 15 #define CTX dmub 16 #define REGS dmub->regs_dcn401 17 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) 18 19 const struct dmub_srv_dcn401_regs dmub_srv_dcn401_regs = { 20 #define DMUB_SR(reg) REG_OFFSET_EXP(reg), 21 { 22 DMUB_DCN401_REGS() 23 DMCUB_INTERNAL_REGS() 24 }, 25 #undef DMUB_SR 26 27 #define DMUB_SF(reg, field) FD_MASK(reg, field), 28 { DMUB_DCN401_FIELDS() }, 29 #undef DMUB_SF 30 31 #define DMUB_SF(reg, field) FD_SHIFT(reg, field), 32 { DMUB_DCN401_FIELDS() }, 33 #undef DMUB_SF 34 }; 35 36 static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub, 37 uint64_t *fb_base, 38 uint64_t *fb_offset) 39 { 40 uint32_t tmp; 41 42 if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { 43 *fb_base = dmub->soc_fb_info.fb_base; 44 *fb_offset = dmub->soc_fb_info.fb_offset; 45 return; 46 } 47 48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 49 *fb_base = (uint64_t)tmp << 24; 50 51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 52 *fb_offset = (uint64_t)tmp << 24; 53 } 54 55 static inline void dmub_dcn401_translate_addr(const union dmub_addr *addr_in, 56 uint64_t fb_base, 57 uint64_t fb_offset, 58 union dmub_addr *addr_out) 59 { 60 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 61 } 62 63 void dmub_dcn401_reset(struct dmub_srv *dmub) 64 { 65 union dmub_gpint_data_register cmd; 66 const uint32_t timeout_us = 1 * 1000 * 1000; //1s 67 const uint32_t poll_delay_us = 1; //1us 68 uint32_t i = 0; 69 uint32_t enabled, in_reset, scratch, pwait_mode; 70 71 REG_GET(DMCUB_CNTL, 72 DMCUB_ENABLE, &enabled); 73 REG_GET(DMCUB_CNTL2, 74 DMCUB_SOFT_RESET, &in_reset); 75 76 if (enabled && in_reset == 0) { 77 cmd.bits.status = 1; 78 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 79 cmd.bits.param = 0; 80 81 dmub->hw_funcs.set_gpint(dmub, cmd); 82 83 for (; i < timeout_us; i++) { 84 scratch = REG_READ(DMCUB_SCRATCH7); 85 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 86 break; 87 88 udelay(poll_delay_us); 89 } 90 91 for (; i < timeout_us; i++) { 92 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 93 if (pwait_mode & (1 << 0)) 94 break; 95 96 udelay(poll_delay_us); 97 } 98 } 99 100 if (enabled) { 101 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 102 udelay(1); 103 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 104 } 105 106 if (i >= timeout_us) { 107 /* timeout should never occur */ 108 BREAK_TO_DEBUGGER(); 109 } 110 111 REG_UPDATE(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE, 0); 112 REG_UPDATE(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE, 0); 113 REG_UPDATE(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE, 0); 114 REG_UPDATE(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE, 0); 115 REG_UPDATE(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, 0); 116 REG_UPDATE(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE, 0); 117 118 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 119 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 120 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 121 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 122 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 123 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 124 REG_WRITE(DMCUB_SCRATCH0, 0); 125 126 /* Clear the GPINT command manually so we don't reset again. */ 127 cmd.all = 0; 128 dmub->hw_funcs.set_gpint(dmub, cmd); 129 } 130 131 void dmub_dcn401_reset_release(struct dmub_srv *dmub) 132 { 133 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 134 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 135 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 136 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 137 } 138 139 void dmub_dcn401_backdoor_load(struct dmub_srv *dmub, 140 const struct dmub_window *cw0, 141 const struct dmub_window *cw1) 142 { 143 union dmub_addr offset; 144 uint64_t fb_base, fb_offset; 145 146 dmub_dcn401_get_fb_base_offset(dmub, &fb_base, &fb_offset); 147 148 /* reset and disable DMCUB and MMHUBBUB DMUIF */ 149 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 150 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 151 152 dmub_dcn401_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 153 154 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 155 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 156 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 157 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 158 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 159 DMCUB_REGION3_CW0_ENABLE, 1); 160 161 dmub_dcn401_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 162 163 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 164 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 165 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 166 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 167 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 168 DMCUB_REGION3_CW1_ENABLE, 1); 169 170 /* release DMCUB reset only to prevent premature execution */ 171 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 172 0x20); 173 } 174 175 void dmub_dcn401_backdoor_load_zfb_mode(struct dmub_srv *dmub, 176 const struct dmub_window *cw0, 177 const struct dmub_window *cw1) 178 { 179 union dmub_addr offset; 180 181 /* reset and disable DMCUB and MMHUBBUB DMUIF */ 182 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 183 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 184 185 offset = cw0->offset; 186 187 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 188 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 189 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 190 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 191 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 192 DMCUB_REGION3_CW0_ENABLE, 1); 193 194 offset = cw1->offset; 195 196 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 197 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 198 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 199 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 200 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 201 DMCUB_REGION3_CW1_ENABLE, 1); 202 203 /* release DMCUB reset only to prevent premature execution */ 204 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 205 0x20); 206 } 207 208 void dmub_dcn401_setup_windows(struct dmub_srv *dmub, 209 const struct dmub_window *cw2, 210 const struct dmub_window *cw3, 211 const struct dmub_window *cw4, 212 const struct dmub_window *cw5, 213 const struct dmub_window *cw6, 214 const struct dmub_window *region6) 215 { 216 (void)cw2; 217 union dmub_addr offset; 218 219 offset = cw3->offset; 220 221 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 222 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 223 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 224 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 225 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 226 DMCUB_REGION3_CW3_ENABLE, 1); 227 228 offset = cw4->offset; 229 230 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 231 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 232 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 233 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 234 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 235 DMCUB_REGION3_CW4_ENABLE, 1); 236 237 offset = cw5->offset; 238 239 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 240 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 241 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 242 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 243 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 244 DMCUB_REGION3_CW5_ENABLE, 1); 245 246 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 247 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 248 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 249 DMCUB_REGION5_TOP_ADDRESS, 250 cw5->region.top - cw5->region.base - 1, 251 DMCUB_REGION5_ENABLE, 1); 252 253 offset = cw6->offset; 254 255 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 256 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 257 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 258 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 259 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 260 DMCUB_REGION3_CW6_ENABLE, 1); 261 262 offset = region6->offset; 263 264 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part); 265 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); 266 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, 267 DMCUB_REGION6_TOP_ADDRESS, 268 region6->region.top - region6->region.base - 1, 269 DMCUB_REGION6_ENABLE, 1); 270 } 271 272 void dmub_dcn401_setup_mailbox(struct dmub_srv *dmub, 273 const struct dmub_region *inbox1) 274 { 275 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 276 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 277 } 278 279 uint32_t dmub_dcn401_get_inbox1_wptr(struct dmub_srv *dmub) 280 { 281 return REG_READ(DMCUB_INBOX1_WPTR); 282 } 283 284 uint32_t dmub_dcn401_get_inbox1_rptr(struct dmub_srv *dmub) 285 { 286 return REG_READ(DMCUB_INBOX1_RPTR); 287 } 288 289 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 290 { 291 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 292 } 293 294 void dmub_dcn401_setup_out_mailbox(struct dmub_srv *dmub, 295 const struct dmub_region *outbox1) 296 { 297 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 298 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 299 } 300 301 uint32_t dmub_dcn401_get_outbox1_wptr(struct dmub_srv *dmub) 302 { 303 /** 304 * outbox1 wptr register is accessed without locks (dal & dc) 305 * and to be called only by dmub_srv_stat_get_notification() 306 */ 307 return REG_READ(DMCUB_OUTBOX1_WPTR); 308 } 309 310 void dmub_dcn401_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 311 { 312 /** 313 * outbox1 rptr register is accessed without locks (dal & dc) 314 * and to be called only by dmub_srv_stat_get_notification() 315 */ 316 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 317 } 318 319 bool dmub_dcn401_is_hw_init(struct dmub_srv *dmub) 320 { 321 union dmub_fw_boot_status status; 322 uint32_t is_hw_init; 323 324 status.all = REG_READ(DMCUB_SCRATCH0); 325 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); 326 327 return is_hw_init != 0 && status.bits.dal_fw; 328 } 329 330 bool dmub_dcn401_is_supported(struct dmub_srv *dmub) 331 { 332 uint32_t supported = 0; 333 334 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 335 336 return supported; 337 } 338 339 void dmub_dcn401_set_gpint(struct dmub_srv *dmub, 340 union dmub_gpint_data_register reg) 341 { 342 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 343 } 344 345 bool dmub_dcn401_is_gpint_acked(struct dmub_srv *dmub, 346 union dmub_gpint_data_register reg) 347 { 348 union dmub_gpint_data_register test; 349 350 reg.bits.status = 0; 351 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 352 353 return test.all == reg.all; 354 } 355 356 uint32_t dmub_dcn401_get_gpint_response(struct dmub_srv *dmub) 357 { 358 return REG_READ(DMCUB_SCRATCH7); 359 } 360 361 uint32_t dmub_dcn401_get_gpint_dataout(struct dmub_srv *dmub) 362 { 363 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 364 365 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 366 367 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 368 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 369 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 370 371 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 372 373 return dataout; 374 } 375 376 union dmub_fw_boot_status dmub_dcn401_get_fw_boot_status(struct dmub_srv *dmub) 377 { 378 union dmub_fw_boot_status status; 379 380 status.all = REG_READ(DMCUB_SCRATCH0); 381 return status; 382 } 383 384 void dmub_dcn401_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 385 { 386 union dmub_fw_boot_options boot_options = {0}; 387 388 boot_options.bits.z10_disable = params->disable_z10; 389 390 boot_options.bits.skip_phy_access = params->disallow_phy_access; 391 392 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 393 } 394 395 void dmub_dcn401_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 396 { 397 union dmub_fw_boot_options boot_options; 398 boot_options.all = REG_READ(DMCUB_SCRATCH14); 399 boot_options.bits.skip_phy_init_panel_sequence = skip; 400 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 401 } 402 403 void dmub_dcn401_setup_outbox0(struct dmub_srv *dmub, 404 const struct dmub_region *outbox0) 405 { 406 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 407 408 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 409 } 410 411 uint32_t dmub_dcn401_get_outbox0_wptr(struct dmub_srv *dmub) 412 { 413 return REG_READ(DMCUB_OUTBOX0_WPTR); 414 } 415 416 void dmub_dcn401_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 417 { 418 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 419 } 420 421 uint32_t dmub_dcn401_get_current_time(struct dmub_srv *dmub) 422 { 423 return REG_READ(DMCUB_TIMER_CURRENT); 424 } 425 426 void dmub_dcn401_get_diagnostic_data(struct dmub_srv *dmub) 427 { 428 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset, is_pwait; 429 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 430 struct dmub_timeout_info timeout = {0}; 431 432 if (!dmub) 433 return; 434 435 /* timeout data filled externally, cache before resetting memory */ 436 timeout = dmub->debug.timeout_info; 437 memset(&dmub->debug, 0, sizeof(dmub->debug)); 438 dmub->debug.timeout_info = timeout; 439 440 dmub->debug.dmcub_version = dmub->fw_version; 441 442 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 443 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 444 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 445 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 446 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 447 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 448 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 449 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 450 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 451 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 452 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 453 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 454 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 455 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 456 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 457 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 458 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 459 460 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 461 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 462 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 463 464 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 465 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 466 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 467 468 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 469 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 470 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 471 472 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 473 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 474 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 475 476 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 477 ASSERT(is_dmub_enabled <= 0xFF); 478 dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 479 480 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 481 ASSERT(is_pwait <= 0xFF); 482 dmub->debug.is_pwait = (uint8_t)is_pwait; 483 484 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 485 ASSERT(is_soft_reset <= 0xFF); 486 dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 487 488 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 489 ASSERT(is_sec_reset <= 0xFF); 490 dmub->debug.is_dmcub_secure_reset = (uint8_t)is_sec_reset; 491 492 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 493 ASSERT(is_traceport_enabled <= 0xFF); 494 dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 495 496 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 497 ASSERT(is_cw0_enabled <= 0xFF); 498 dmub->debug.is_cw0_enabled = (uint8_t)is_cw0_enabled; 499 500 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 501 ASSERT(is_cw6_enabled <= 0xFF); 502 dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 503 504 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 505 } 506 void dmub_dcn401_configure_dmub_in_system_memory(struct dmub_srv *dmub) 507 { 508 /* DMCUB_REGION3_TMR_AXI_SPACE values: 509 * 0b011 (0x3) - FB physical address 510 * 0b100 (0x4) - GPU virtual address 511 * 512 * Default value is 0x3 (FB Physical address for TMR). When programming 513 * DMUB to be in system memory, change to 0x4. The system memory allocated 514 * is accessible by both GPU and CPU, so we use GPU virtual address. 515 */ 516 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); 517 } 518 519 void dmub_dcn401_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) 520 { 521 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); 522 } 523 524 void dmub_dcn401_clear_inbox0_ack_register(struct dmub_srv *dmub) 525 { 526 REG_WRITE(DMCUB_SCRATCH17, 0); 527 } 528 529 uint32_t dmub_dcn401_read_inbox0_ack_register(struct dmub_srv *dmub) 530 { 531 return REG_READ(DMCUB_SCRATCH17); 532 } 533 534 void dmub_dcn401_send_reg_inbox0_cmd_msg(struct dmub_srv *dmub, 535 union dmub_rb_cmd *cmd) 536 { 537 uint32_t *dwords = (uint32_t *)cmd; 538 int32_t payload_size_bytes = cmd->cmd_common.header.payload_bytes; 539 uint32_t msg_index; 540 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 541 542 /* read remaining data based on payload size */ 543 for (msg_index = 0; msg_index < 15; msg_index++) { 544 if (payload_size_bytes <= msg_index * 4) { 545 break; 546 } 547 548 switch (msg_index) { 549 case 0: 550 REG_WRITE(DMCUB_REG_INBOX0_MSG0, dwords[msg_index + 1]); 551 break; 552 case 1: 553 REG_WRITE(DMCUB_REG_INBOX0_MSG1, dwords[msg_index + 1]); 554 break; 555 case 2: 556 REG_WRITE(DMCUB_REG_INBOX0_MSG2, dwords[msg_index + 1]); 557 break; 558 case 3: 559 REG_WRITE(DMCUB_REG_INBOX0_MSG3, dwords[msg_index + 1]); 560 break; 561 case 4: 562 REG_WRITE(DMCUB_REG_INBOX0_MSG4, dwords[msg_index + 1]); 563 break; 564 case 5: 565 REG_WRITE(DMCUB_REG_INBOX0_MSG5, dwords[msg_index + 1]); 566 break; 567 case 6: 568 REG_WRITE(DMCUB_REG_INBOX0_MSG6, dwords[msg_index + 1]); 569 break; 570 case 7: 571 REG_WRITE(DMCUB_REG_INBOX0_MSG7, dwords[msg_index + 1]); 572 break; 573 case 8: 574 REG_WRITE(DMCUB_REG_INBOX0_MSG8, dwords[msg_index + 1]); 575 break; 576 case 9: 577 REG_WRITE(DMCUB_REG_INBOX0_MSG9, dwords[msg_index + 1]); 578 break; 579 case 10: 580 REG_WRITE(DMCUB_REG_INBOX0_MSG10, dwords[msg_index + 1]); 581 break; 582 case 11: 583 REG_WRITE(DMCUB_REG_INBOX0_MSG11, dwords[msg_index + 1]); 584 break; 585 case 12: 586 REG_WRITE(DMCUB_REG_INBOX0_MSG12, dwords[msg_index + 1]); 587 break; 588 case 13: 589 REG_WRITE(DMCUB_REG_INBOX0_MSG13, dwords[msg_index + 1]); 590 break; 591 case 14: 592 REG_WRITE(DMCUB_REG_INBOX0_MSG14, dwords[msg_index + 1]); 593 break; 594 } 595 } 596 597 /* writing to INBOX RDY register will trigger DMUB REG INBOX0 RDY 598 * interrupt. 599 */ 600 REG_WRITE(DMCUB_REG_INBOX0_RDY, dwords[0]); 601 } 602 603 uint32_t dmub_dcn401_read_reg_inbox0_rsp_int_status(struct dmub_srv *dmub) 604 { 605 uint32_t status; 606 607 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_STAT, &status); 608 return status; 609 } 610 611 void dmub_dcn401_read_reg_inbox0_cmd_rsp(struct dmub_srv *dmub, 612 union dmub_rb_cmd *cmd) 613 { 614 uint32_t *dwords = (uint32_t *)cmd; 615 616 static_assert(sizeof(*cmd) == 64, "DMUB command size mismatch"); 617 618 dwords[0] = REG_READ(DMCUB_REG_INBOX0_RSP); 619 dwords[1] = REG_READ(DMCUB_REG_INBOX0_MSG0); 620 dwords[2] = REG_READ(DMCUB_REG_INBOX0_MSG1); 621 dwords[3] = REG_READ(DMCUB_REG_INBOX0_MSG2); 622 dwords[4] = REG_READ(DMCUB_REG_INBOX0_MSG3); 623 dwords[5] = REG_READ(DMCUB_REG_INBOX0_MSG4); 624 dwords[6] = REG_READ(DMCUB_REG_INBOX0_MSG5); 625 dwords[7] = REG_READ(DMCUB_REG_INBOX0_MSG6); 626 dwords[8] = REG_READ(DMCUB_REG_INBOX0_MSG7); 627 dwords[9] = REG_READ(DMCUB_REG_INBOX0_MSG8); 628 dwords[10] = REG_READ(DMCUB_REG_INBOX0_MSG9); 629 dwords[11] = REG_READ(DMCUB_REG_INBOX0_MSG10); 630 dwords[12] = REG_READ(DMCUB_REG_INBOX0_MSG11); 631 dwords[13] = REG_READ(DMCUB_REG_INBOX0_MSG12); 632 dwords[14] = REG_READ(DMCUB_REG_INBOX0_MSG13); 633 dwords[15] = REG_READ(DMCUB_REG_INBOX0_MSG14); 634 } 635 636 void dmub_dcn401_write_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 637 { 638 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 1); 639 } 640 641 void dmub_dcn401_clear_reg_inbox0_rsp_int_ack(struct dmub_srv *dmub) 642 { 643 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_ACK, 0); 644 } 645 646 void dmub_dcn401_enable_reg_inbox0_rsp_int(struct dmub_srv *dmub, bool enable) 647 { 648 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_INBOX0_RSP_INT_EN, enable ? 1:0); 649 } 650 651 void dmub_dcn401_write_reg_outbox0_rdy_int_ack(struct dmub_srv *dmub) 652 { 653 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 1); 654 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_ACK, 0); 655 } 656 657 void dmub_dcn401_read_reg_outbox0_msg(struct dmub_srv *dmub, uint32_t *msg) 658 { 659 *msg = REG_READ(DMCUB_REG_OUTBOX0_MSG0); 660 } 661 662 void dmub_dcn401_write_reg_outbox0_rsp(struct dmub_srv *dmub, uint32_t *rsp) 663 { 664 REG_WRITE(DMCUB_REG_OUTBOX0_RSP, *rsp); 665 } 666 667 uint32_t dmub_dcn401_read_reg_outbox0_rsp_int_status(struct dmub_srv *dmub) 668 { 669 uint32_t status; 670 671 REG_GET(DMCUB_INTERRUPT_STATUS, DMCUB_REG_OUTBOX0_RSP_INT_STAT, &status); 672 return status; 673 } 674 675 void dmub_dcn401_enable_reg_outbox0_rdy_int(struct dmub_srv *dmub, bool enable) 676 { 677 REG_UPDATE(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_EN, enable ? 1:0); 678 } 679 680 uint32_t dmub_dcn401_read_reg_outbox0_rdy_int_status(struct dmub_srv *dmub) 681 { 682 uint32_t status; 683 684 REG_GET(HOST_INTERRUPT_CSR, HOST_REG_OUTBOX0_RDY_INT_STAT, &status); 685 return status; 686 } 687