xref: /linux/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn351.c (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 /* SPDX-License-Identifier: MIT */
2 /* Copyright 2024 Advanced Micro Devices, Inc. */
3 
4 #include "../dmub_srv.h"
5 #include "dmub_reg.h"
6 #include "dmub_dcn351.h"
7 
8 #include "dcn/dcn_3_5_1_offset.h"
9 #include "dcn/dcn_3_5_1_sh_mask.h"
10 
11 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
12 #define CTX dmub
13 #define REGS dmub->regs_dcn35
14 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
15 
16 void dmub_srv_dcn351_regs_init(struct dmub_srv *dmub, struct dc_context *ctx)
17 {
18 	struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35;
19 #define REG_STRUCT regs
20 
21 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg);
22 	DMUB_DCN35_REGS()
23 	DMCUB_INTERNAL_REGS()
24 #undef DMUB_SR
25 
26 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field);
27 	DMUB_DCN35_FIELDS()
28 #undef DMUB_SF
29 
30 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field);
31 	DMUB_DCN35_FIELDS()
32 #undef DMUB_SF
33 #undef REG_STRUCT
34 }
35