1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dc_types.h" 28 #include "dmub_reg.h" 29 #include "dmub_dcn35.h" 30 #include "dc/dc_types.h" 31 32 #include "dcn/dcn_3_5_0_offset.h" 33 #include "dcn/dcn_3_5_0_sh_mask.h" 34 35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 36 #define CTX dmub 37 #define REGS dmub->regs_dcn35 38 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 39 40 void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) { 41 struct dmub_srv_dcn35_regs *regs = dmub->regs_dcn35; 42 #define REG_STRUCT regs 43 44 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); 45 DMUB_DCN35_REGS() 46 DMCUB_INTERNAL_REGS() 47 #undef DMUB_SR 48 49 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); 50 DMUB_DCN35_FIELDS() 51 #undef DMUB_SF 52 53 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); 54 DMUB_DCN35_FIELDS() 55 #undef DMUB_SF 56 #undef REG_STRUCT 57 } 58 59 static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub, 60 uint64_t *fb_base, 61 uint64_t *fb_offset) 62 { 63 uint32_t tmp; 64 65 /* 66 if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) { 67 *fb_base = dmub->soc_fb_info.fb_base; 68 *fb_offset = dmub->soc_fb_info.fb_offset; 69 return; 70 } 71 */ 72 73 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 74 *fb_base = (uint64_t)tmp << 24; 75 76 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 77 *fb_offset = (uint64_t)tmp << 24; 78 } 79 80 static inline void dmub_dcn35_translate_addr(const union dmub_addr *addr_in, 81 uint64_t fb_base, 82 uint64_t fb_offset, 83 union dmub_addr *addr_out) 84 { 85 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 86 } 87 88 void dmub_dcn35_reset(struct dmub_srv *dmub) 89 { 90 union dmub_gpint_data_register cmd; 91 const uint32_t timeout = 100000; 92 uint32_t in_reset, is_enabled, scratch, i, pwait_mode; 93 94 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 95 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 96 97 if (in_reset == 0 && is_enabled != 0) { 98 cmd.bits.status = 1; 99 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 100 cmd.bits.param = 0; 101 102 dmub->hw_funcs.set_gpint(dmub, cmd); 103 104 for (i = 0; i < timeout; ++i) { 105 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 106 break; 107 108 udelay(1); 109 } 110 111 for (i = 0; i < timeout; ++i) { 112 scratch = REG_READ(DMCUB_SCRATCH7); 113 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 114 break; 115 116 udelay(1); 117 } 118 119 for (i = 0; i < timeout; ++i) { 120 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 121 if (pwait_mode & (1 << 0)) 122 break; 123 124 udelay(1); 125 } 126 /* Force reset in case we timed out, DMCUB is likely hung. */ 127 } 128 129 if (is_enabled) { 130 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 131 udelay(1); 132 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 133 } 134 135 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 136 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 137 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 138 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 139 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 140 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 141 REG_WRITE(DMCUB_SCRATCH0, 0); 142 143 /* Clear the GPINT command manually so we don't send anything during boot. */ 144 cmd.all = 0; 145 dmub->hw_funcs.set_gpint(dmub, cmd); 146 } 147 148 void dmub_dcn35_reset_release(struct dmub_srv *dmub) 149 { 150 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 151 152 REG_UPDATE_3(DMU_CLK_CNTL, 153 LONO_DISPCLK_GATE_DISABLE, 1, 154 LONO_SOCCLK_GATE_DISABLE, 1, 155 LONO_DMCUBCLK_GATE_DISABLE, 1); 156 157 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 158 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 159 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 160 } 161 162 void dmub_dcn35_backdoor_load(struct dmub_srv *dmub, 163 const struct dmub_window *cw0, 164 const struct dmub_window *cw1) 165 { 166 union dmub_addr offset; 167 uint64_t fb_base, fb_offset; 168 169 dmub_dcn35_get_fb_base_offset(dmub, &fb_base, &fb_offset); 170 171 dmub_dcn35_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 172 173 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 174 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 175 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 176 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 177 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 178 DMCUB_REGION3_CW0_ENABLE, 1); 179 180 dmub_dcn35_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 181 182 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 183 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 184 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 185 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 186 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 187 DMCUB_REGION3_CW1_ENABLE, 1); 188 189 /* TODO: Do we need to set DMCUB_MEM_UNIT_ID? */ 190 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0); 191 } 192 193 void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub, 194 const struct dmub_window *cw0, 195 const struct dmub_window *cw1) 196 { 197 union dmub_addr offset; 198 199 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 200 offset = cw0->offset; 201 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 202 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 203 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 204 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 205 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 206 DMCUB_REGION3_CW0_ENABLE, 1); 207 offset = cw1->offset; 208 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 209 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 210 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 211 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 212 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 213 DMCUB_REGION3_CW1_ENABLE, 1); 214 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 215 0x20); 216 } 217 void dmub_dcn35_setup_windows(struct dmub_srv *dmub, 218 const struct dmub_window *cw2, 219 const struct dmub_window *cw3, 220 const struct dmub_window *cw4, 221 const struct dmub_window *cw5, 222 const struct dmub_window *cw6, 223 const struct dmub_window *region6) 224 { 225 (void)cw2; 226 union dmub_addr offset; 227 228 offset = cw3->offset; 229 230 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 231 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 232 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 233 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 234 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 235 DMCUB_REGION3_CW3_ENABLE, 1); 236 237 offset = cw4->offset; 238 239 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 240 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 241 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 242 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 243 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 244 DMCUB_REGION3_CW4_ENABLE, 1); 245 246 offset = cw5->offset; 247 248 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 249 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 250 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 251 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 252 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 253 DMCUB_REGION3_CW5_ENABLE, 1); 254 255 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 256 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 257 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 258 DMCUB_REGION5_TOP_ADDRESS, 259 cw5->region.top - cw5->region.base - 1, 260 DMCUB_REGION5_ENABLE, 1); 261 262 offset = cw6->offset; 263 264 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 265 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 266 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 267 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 268 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 269 DMCUB_REGION3_CW6_ENABLE, 1); 270 271 offset = region6->offset; 272 273 REG_WRITE(DMCUB_REGION6_OFFSET, offset.u.low_part); 274 REG_WRITE(DMCUB_REGION6_OFFSET_HIGH, offset.u.high_part); 275 REG_SET_2(DMCUB_REGION6_TOP_ADDRESS, 0, 276 DMCUB_REGION6_TOP_ADDRESS, 277 region6->region.top - region6->region.base - 1, 278 DMCUB_REGION6_ENABLE, 1); 279 } 280 281 void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub, 282 const struct dmub_region *inbox1) 283 { 284 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 285 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 286 } 287 288 uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub) 289 { 290 return REG_READ(DMCUB_INBOX1_WPTR); 291 } 292 293 uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub) 294 { 295 return REG_READ(DMCUB_INBOX1_RPTR); 296 } 297 298 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 299 { 300 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 301 } 302 303 void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub, 304 const struct dmub_region *outbox1) 305 { 306 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 307 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 308 } 309 310 uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub) 311 { 312 /** 313 * outbox1 wptr register is accessed without locks (dal & dc) 314 * and to be called only by dmub_srv_stat_get_notification() 315 */ 316 return REG_READ(DMCUB_OUTBOX1_WPTR); 317 } 318 319 void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 320 { 321 /** 322 * outbox1 rptr register is accessed without locks (dal & dc) 323 * and to be called only by dmub_srv_stat_get_notification() 324 */ 325 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 326 } 327 328 bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub) 329 { 330 union dmub_fw_boot_status status; 331 uint32_t is_enable; 332 333 status.all = REG_READ(DMCUB_SCRATCH0); 334 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); 335 336 return is_enable != 0 && status.bits.dal_fw; 337 } 338 339 bool dmub_dcn35_is_supported(struct dmub_srv *dmub) 340 { 341 uint32_t supported = 0; 342 343 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 344 345 return supported; 346 } 347 348 void dmub_dcn35_set_gpint(struct dmub_srv *dmub, 349 union dmub_gpint_data_register reg) 350 { 351 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 352 } 353 354 bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub, 355 union dmub_gpint_data_register reg) 356 { 357 union dmub_gpint_data_register test; 358 359 reg.bits.status = 0; 360 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 361 362 return test.all == reg.all; 363 } 364 365 uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub) 366 { 367 return REG_READ(DMCUB_SCRATCH7); 368 } 369 370 uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub) 371 { 372 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 373 374 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 375 376 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 377 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 378 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 379 380 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 381 382 return dataout; 383 } 384 385 union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub) 386 { 387 union dmub_fw_boot_status status; 388 389 status.all = REG_READ(DMCUB_SCRATCH0); 390 return status; 391 } 392 393 union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub) 394 { 395 union dmub_fw_boot_options option; 396 397 option.all = REG_READ(DMCUB_SCRATCH14); 398 return option; 399 } 400 401 void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 402 { 403 union dmub_fw_boot_options boot_options = {0}; 404 405 if (!dmub->dpia_supported) { 406 dmub->dpia_supported = dmub_dcn35_get_fw_boot_option(dmub).bits.enable_dpia != 0; 407 } 408 409 boot_options.bits.z10_disable = params->disable_z10; 410 boot_options.bits.dpia_supported = params->dpia_supported; 411 boot_options.bits.enable_dpia = dmub->dpia_supported && !params->disable_dpia; 412 boot_options.bits.usb4_cm_version = params->usb4_cm_version; 413 boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; 414 boot_options.bits.power_optimization = params->power_optimization; 415 boot_options.bits.disable_clk_ds = params->disallow_dispclk_dppclk_ds; 416 boot_options.bits.disable_clk_gate = params->disable_clock_gate; 417 boot_options.bits.ips_disable = params->disable_ips; 418 boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; 419 boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; 420 boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; 421 boot_options.bits.lower_hbr3_phy_ssc = params->lower_hbr3_phy_ssc; 422 boot_options.bits.disable_dpia_bw_allocation = params->disable_dpia_bw_allocation; 423 boot_options.bits.bootcrc_en_at_preos = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_preos; 424 boot_options.bits.bootcrc_en_at_S0i3 = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_en_at_S0i3; 425 boot_options.bits.bootcrc_boot_mode = dmub_dcn35_get_fw_boot_option(dmub).bits.bootcrc_boot_mode; 426 427 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 428 } 429 430 void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 431 { 432 union dmub_fw_boot_options boot_options; 433 boot_options.all = REG_READ(DMCUB_SCRATCH14); 434 boot_options.bits.skip_phy_init_panel_sequence = skip; 435 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 436 } 437 438 void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub, 439 const struct dmub_region *outbox0) 440 { 441 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 442 443 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 444 } 445 446 uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub) 447 { 448 return REG_READ(DMCUB_OUTBOX0_WPTR); 449 } 450 451 void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 452 { 453 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 454 } 455 456 uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub) 457 { 458 return REG_READ(DMCUB_TIMER_CURRENT); 459 } 460 461 void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub) 462 { 463 uint32_t is_dmub_enabled, is_soft_reset, is_pwait; 464 uint32_t is_traceport_enabled, is_cw6_enabled; 465 struct dmub_timeout_info timeout = {0}; 466 467 if (!dmub) 468 return; 469 470 /* timeout data filled externally, cache before resetting memory */ 471 timeout = dmub->debug.timeout_info; 472 memset(&dmub->debug, 0, sizeof(dmub->debug)); 473 dmub->debug.timeout_info = timeout; 474 475 dmub->debug.dmcub_version = dmub->fw_version; 476 477 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 478 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 479 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 480 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 481 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 482 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 483 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 484 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 485 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 486 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 487 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 488 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 489 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 490 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 491 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 492 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 493 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 494 495 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 496 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 497 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 498 499 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 500 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 501 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 502 503 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 504 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 505 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 506 507 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 508 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 509 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 510 511 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 512 ASSERT(is_dmub_enabled <= 0xFF); 513 dmub->debug.is_dmcub_enabled = (uint8_t)is_dmub_enabled; 514 515 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 516 ASSERT(is_pwait <= 0xFF); 517 dmub->debug.is_pwait = (uint8_t)is_pwait; 518 519 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 520 ASSERT(is_soft_reset <= 0xFF); 521 dmub->debug.is_dmcub_soft_reset = (uint8_t)is_soft_reset; 522 523 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 524 ASSERT(is_traceport_enabled <= 0xFF); 525 dmub->debug.is_traceport_en = (uint8_t)is_traceport_enabled; 526 527 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 528 ASSERT(is_cw6_enabled <= 0xFF); 529 dmub->debug.is_cw6_enabled = (uint8_t)is_cw6_enabled; 530 531 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 532 } 533 534 bool dmub_dcn35_get_preos_fw_info(struct dmub_srv *dmub) 535 { 536 uint64_t region3_cw5_offset; 537 uint32_t top_addr, top_addr_enable, offset_low; 538 uint32_t offset_high, base_addr, fw_version; 539 bool is_vbios_fw = false; 540 541 memset(&dmub->preos_info, 0, sizeof(dmub->preos_info)); 542 543 fw_version = REG_READ(DMCUB_SCRATCH1); 544 is_vbios_fw = ((fw_version >> 6) & 0x01) ? true : false; 545 if (!is_vbios_fw) 546 return false; 547 548 dmub->preos_info.boot_status = REG_READ(DMCUB_SCRATCH0); 549 dmub->preos_info.fw_version = REG_READ(DMCUB_SCRATCH1); 550 dmub->preos_info.boot_options = REG_READ(DMCUB_SCRATCH14); 551 REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 552 DMCUB_REGION3_CW5_ENABLE, &top_addr_enable); 553 if (top_addr_enable) { 554 dmub_dcn35_get_fb_base_offset(dmub, 555 &dmub->preos_info.fb_base, &dmub->preos_info.fb_offset); 556 offset_low = REG_READ(DMCUB_REGION3_CW5_OFFSET); 557 offset_high = REG_READ(DMCUB_REGION3_CW5_OFFSET_HIGH); 558 region3_cw5_offset = ((uint64_t)offset_high << 32) | offset_low; 559 dmub->preos_info.trace_buffer_phy_addr = region3_cw5_offset 560 - dmub->preos_info.fb_base + dmub->preos_info.fb_offset; 561 562 REG_GET(DMCUB_REGION3_CW5_TOP_ADDRESS, 563 DMCUB_REGION3_CW5_TOP_ADDRESS, &top_addr); 564 base_addr = REG_READ(DMCUB_REGION3_CW5_BASE_ADDRESS) & 0x1FFFFFFF; 565 dmub->preos_info.trace_buffer_size = 566 (top_addr > base_addr) ? (top_addr - base_addr + 1) : 0; 567 } 568 569 return true; 570 } 571 572 void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub) 573 { 574 /* DMCUB_REGION3_TMR_AXI_SPACE values: 575 * 0b011 (0x3) - FB physical address 576 * 0b100 (0x4) - GPU virtual address 577 * 578 * Default value is 0x3 (FB Physical address for TMR). When programming 579 * DMUB to be in system memory, change to 0x4. The system memory allocated 580 * is accessible by both GPU and CPU, so we use GPU virtual address. 581 */ 582 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); 583 } 584 585 bool dmub_dcn35_should_detect(struct dmub_srv *dmub) 586 { 587 uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0); 588 bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0; 589 return should_detect; 590 } 591 592 void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) 593 { 594 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); 595 } 596 597 void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub) 598 { 599 REG_WRITE(DMCUB_SCRATCH17, 0); 600 } 601 602 uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub) 603 { 604 return REG_READ(DMCUB_SCRATCH17); 605 } 606 607 bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub) 608 { 609 union dmub_fw_boot_status status; 610 uint32_t is_enable; 611 612 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); 613 if (is_enable == 0) 614 return false; 615 616 status.all = REG_READ(DMCUB_SCRATCH0); 617 618 return (status.bits.dal_fw && status.bits.hw_power_init_done && status.bits.mailbox_rdy) || 619 (!status.bits.dal_fw && status.bits.mailbox_rdy); 620 } 621