1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_reg.h" 28 #include "dmub_dcn32.h" 29 #include "dc/dc_types.h" 30 #include "dc_hw_types.h" 31 32 #include "dcn/dcn_3_2_0_offset.h" 33 #include "dcn/dcn_3_2_0_sh_mask.h" 34 35 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 36 #define CTX dmub 37 #define REGS dmub->regs_dcn32 38 #define REG_OFFSET_EXP(reg_name) BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 39 40 void dmub_srv_dcn32_regs_init(struct dmub_srv *dmub, struct dc_context *ctx) 41 { 42 struct dmub_srv_dcn32_regs *regs = dmub->regs_dcn32; 43 44 #define REG_STRUCT regs 45 46 #define DMUB_SR(reg) REG_STRUCT->offset.reg = REG_OFFSET_EXP(reg); 47 DMUB_DCN32_REGS() 48 DMCUB_INTERNAL_REGS() 49 #undef DMUB_SR 50 51 #define DMUB_SF(reg, field) REG_STRUCT->mask.reg##__##field = FD_MASK(reg, field); 52 DMUB_DCN32_FIELDS() 53 #undef DMUB_SF 54 55 #define DMUB_SF(reg, field) REG_STRUCT->shift.reg##__##field = FD_SHIFT(reg, field); 56 DMUB_DCN32_FIELDS() 57 #undef DMUB_SF 58 59 #undef REG_STRUCT 60 } 61 62 static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub, 63 uint64_t *fb_base, 64 uint64_t *fb_offset) 65 { 66 uint32_t tmp; 67 68 if (dmub->fb_base || dmub->fb_offset) { 69 *fb_base = dmub->fb_base; 70 *fb_offset = dmub->fb_offset; 71 return; 72 } 73 74 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 75 *fb_base = (uint64_t)tmp << 24; 76 77 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 78 *fb_offset = (uint64_t)tmp << 24; 79 } 80 81 static inline void dmub_dcn32_translate_addr(const union dmub_addr *addr_in, 82 uint64_t fb_base, 83 uint64_t fb_offset, 84 union dmub_addr *addr_out) 85 { 86 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 87 } 88 89 void dmub_dcn32_reset(struct dmub_srv *dmub) 90 { 91 union dmub_gpint_data_register cmd; 92 const uint32_t timeout = 100000; 93 uint32_t in_reset, is_enabled, scratch, i, pwait_mode; 94 95 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 96 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); 97 98 if (in_reset == 0 && is_enabled != 0) { 99 cmd.bits.status = 1; 100 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 101 cmd.bits.param = 0; 102 103 dmub->hw_funcs.set_gpint(dmub, cmd); 104 105 for (i = 0; i < timeout; ++i) { 106 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 107 break; 108 109 udelay(1); 110 } 111 112 for (i = 0; i < timeout; ++i) { 113 scratch = REG_READ(DMCUB_SCRATCH7); 114 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 115 break; 116 117 udelay(1); 118 } 119 120 for (i = 0; i < timeout; ++i) { 121 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 122 if (pwait_mode & (1 << 0)) 123 break; 124 125 udelay(1); 126 } 127 /* Force reset in case we timed out, DMCUB is likely hung. */ 128 } 129 130 if (is_enabled) { 131 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 132 udelay(1); 133 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 134 } 135 136 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 137 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 138 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 139 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 140 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 141 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 142 REG_WRITE(DMCUB_SCRATCH0, 0); 143 144 /* Clear the GPINT command manually so we don't send anything during boot. */ 145 cmd.all = 0; 146 dmub->hw_funcs.set_gpint(dmub, cmd); 147 } 148 149 void dmub_dcn32_reset_release(struct dmub_srv *dmub) 150 { 151 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 152 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 153 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 154 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 155 } 156 157 void dmub_dcn32_backdoor_load(struct dmub_srv *dmub, 158 const struct dmub_window *cw0, 159 const struct dmub_window *cw1) 160 { 161 union dmub_addr offset; 162 uint64_t fb_base, fb_offset; 163 164 dmub_dcn32_get_fb_base_offset(dmub, &fb_base, &fb_offset); 165 166 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 167 168 dmub_dcn32_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 169 170 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 171 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 172 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 173 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 174 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 175 DMCUB_REGION3_CW0_ENABLE, 1); 176 177 dmub_dcn32_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 178 179 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 180 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 181 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 182 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 183 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 184 DMCUB_REGION3_CW1_ENABLE, 1); 185 186 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 187 0x20); 188 } 189 190 void dmub_dcn32_backdoor_load_zfb_mode(struct dmub_srv *dmub, 191 const struct dmub_window *cw0, 192 const struct dmub_window *cw1) 193 { 194 union dmub_addr offset; 195 196 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 197 198 offset = cw0->offset; 199 200 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 201 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 202 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 203 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 204 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 205 DMCUB_REGION3_CW0_ENABLE, 1); 206 207 offset = cw1->offset; 208 209 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 210 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 211 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 212 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 213 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 214 DMCUB_REGION3_CW1_ENABLE, 1); 215 216 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 217 0x20); 218 } 219 220 void dmub_dcn32_setup_windows(struct dmub_srv *dmub, 221 const struct dmub_window *cw2, 222 const struct dmub_window *cw3, 223 const struct dmub_window *cw4, 224 const struct dmub_window *cw5, 225 const struct dmub_window *cw6, 226 const struct dmub_window *region6) 227 { 228 union dmub_addr offset; 229 230 offset = cw3->offset; 231 232 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 233 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 234 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 235 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 236 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 237 DMCUB_REGION3_CW3_ENABLE, 1); 238 239 offset = cw4->offset; 240 241 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 242 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 243 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 244 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 245 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 246 DMCUB_REGION3_CW4_ENABLE, 1); 247 248 offset = cw5->offset; 249 250 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 251 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 252 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 253 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 254 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 255 DMCUB_REGION3_CW5_ENABLE, 1); 256 257 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 258 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 259 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 260 DMCUB_REGION5_TOP_ADDRESS, 261 cw5->region.top - cw5->region.base - 1, 262 DMCUB_REGION5_ENABLE, 1); 263 264 offset = cw6->offset; 265 266 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 267 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 268 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 269 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 270 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 271 DMCUB_REGION3_CW6_ENABLE, 1); 272 } 273 274 void dmub_dcn32_setup_mailbox(struct dmub_srv *dmub, 275 const struct dmub_region *inbox1) 276 { 277 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 278 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 279 } 280 281 uint32_t dmub_dcn32_get_inbox1_wptr(struct dmub_srv *dmub) 282 { 283 return REG_READ(DMCUB_INBOX1_WPTR); 284 } 285 286 uint32_t dmub_dcn32_get_inbox1_rptr(struct dmub_srv *dmub) 287 { 288 return REG_READ(DMCUB_INBOX1_RPTR); 289 } 290 291 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 292 { 293 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 294 } 295 296 void dmub_dcn32_setup_out_mailbox(struct dmub_srv *dmub, 297 const struct dmub_region *outbox1) 298 { 299 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 300 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 301 } 302 303 uint32_t dmub_dcn32_get_outbox1_wptr(struct dmub_srv *dmub) 304 { 305 /** 306 * outbox1 wptr register is accessed without locks (dal & dc) 307 * and to be called only by dmub_srv_stat_get_notification() 308 */ 309 return REG_READ(DMCUB_OUTBOX1_WPTR); 310 } 311 312 void dmub_dcn32_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 313 { 314 /** 315 * outbox1 rptr register is accessed without locks (dal & dc) 316 * and to be called only by dmub_srv_stat_get_notification() 317 */ 318 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 319 } 320 321 bool dmub_dcn32_is_hw_init(struct dmub_srv *dmub) 322 { 323 union dmub_fw_boot_status status; 324 uint32_t is_hw_init; 325 326 status.all = REG_READ(DMCUB_SCRATCH0); 327 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); 328 329 return is_hw_init != 0 && status.bits.dal_fw; 330 } 331 332 bool dmub_dcn32_is_supported(struct dmub_srv *dmub) 333 { 334 uint32_t supported = 0; 335 336 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 337 338 return supported; 339 } 340 341 void dmub_dcn32_set_gpint(struct dmub_srv *dmub, 342 union dmub_gpint_data_register reg) 343 { 344 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 345 } 346 347 bool dmub_dcn32_is_gpint_acked(struct dmub_srv *dmub, 348 union dmub_gpint_data_register reg) 349 { 350 union dmub_gpint_data_register test; 351 352 reg.bits.status = 0; 353 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 354 355 return test.all == reg.all; 356 } 357 358 uint32_t dmub_dcn32_get_gpint_response(struct dmub_srv *dmub) 359 { 360 return REG_READ(DMCUB_SCRATCH7); 361 } 362 363 uint32_t dmub_dcn32_get_gpint_dataout(struct dmub_srv *dmub) 364 { 365 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 366 367 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 368 369 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 370 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 371 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 372 373 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 374 375 return dataout; 376 } 377 378 union dmub_fw_boot_status dmub_dcn32_get_fw_boot_status(struct dmub_srv *dmub) 379 { 380 union dmub_fw_boot_status status; 381 382 status.all = REG_READ(DMCUB_SCRATCH0); 383 return status; 384 } 385 386 void dmub_dcn32_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 387 { 388 union dmub_fw_boot_options boot_options = {0}; 389 390 boot_options.bits.z10_disable = params->disable_z10; 391 392 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 393 } 394 395 void dmub_dcn32_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 396 { 397 union dmub_fw_boot_options boot_options; 398 boot_options.all = REG_READ(DMCUB_SCRATCH14); 399 boot_options.bits.skip_phy_init_panel_sequence = skip; 400 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 401 } 402 403 void dmub_dcn32_setup_outbox0(struct dmub_srv *dmub, 404 const struct dmub_region *outbox0) 405 { 406 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 407 408 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 409 } 410 411 uint32_t dmub_dcn32_get_outbox0_wptr(struct dmub_srv *dmub) 412 { 413 return REG_READ(DMCUB_OUTBOX0_WPTR); 414 } 415 416 void dmub_dcn32_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 417 { 418 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 419 } 420 421 uint32_t dmub_dcn32_get_current_time(struct dmub_srv *dmub) 422 { 423 return REG_READ(DMCUB_TIMER_CURRENT); 424 } 425 426 void dmub_dcn32_get_diagnostic_data(struct dmub_srv *dmub) 427 { 428 uint32_t is_dmub_enabled, is_soft_reset, is_pwait; 429 uint32_t is_traceport_enabled, is_cw6_enabled; 430 struct dmub_timeout_info timeout = {0}; 431 432 if (!dmub) 433 return; 434 435 /* timeout data filled externally, cache before resetting memory */ 436 timeout = dmub->debug.timeout_info; 437 memset(&dmub->debug, 0, sizeof(dmub->debug)); 438 dmub->debug.timeout_info = timeout; 439 440 dmub->debug.dmcub_version = dmub->fw_version; 441 442 dmub->debug.scratch[0] = REG_READ(DMCUB_SCRATCH0); 443 dmub->debug.scratch[1] = REG_READ(DMCUB_SCRATCH1); 444 dmub->debug.scratch[2] = REG_READ(DMCUB_SCRATCH2); 445 dmub->debug.scratch[3] = REG_READ(DMCUB_SCRATCH3); 446 dmub->debug.scratch[4] = REG_READ(DMCUB_SCRATCH4); 447 dmub->debug.scratch[5] = REG_READ(DMCUB_SCRATCH5); 448 dmub->debug.scratch[6] = REG_READ(DMCUB_SCRATCH6); 449 dmub->debug.scratch[7] = REG_READ(DMCUB_SCRATCH7); 450 dmub->debug.scratch[8] = REG_READ(DMCUB_SCRATCH8); 451 dmub->debug.scratch[9] = REG_READ(DMCUB_SCRATCH9); 452 dmub->debug.scratch[10] = REG_READ(DMCUB_SCRATCH10); 453 dmub->debug.scratch[11] = REG_READ(DMCUB_SCRATCH11); 454 dmub->debug.scratch[12] = REG_READ(DMCUB_SCRATCH12); 455 dmub->debug.scratch[13] = REG_READ(DMCUB_SCRATCH13); 456 dmub->debug.scratch[14] = REG_READ(DMCUB_SCRATCH14); 457 dmub->debug.scratch[15] = REG_READ(DMCUB_SCRATCH15); 458 dmub->debug.scratch[16] = REG_READ(DMCUB_SCRATCH16); 459 460 dmub->debug.undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 461 dmub->debug.inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 462 dmub->debug.data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 463 464 dmub->debug.inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 465 dmub->debug.inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 466 dmub->debug.inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 467 468 dmub->debug.inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 469 dmub->debug.inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 470 dmub->debug.inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 471 472 dmub->debug.outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 473 dmub->debug.outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 474 dmub->debug.outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 475 476 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 477 dmub->debug.is_dmcub_enabled = is_dmub_enabled; 478 479 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &is_pwait); 480 dmub->debug.is_pwait = is_pwait; 481 482 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 483 dmub->debug.is_dmcub_soft_reset = is_soft_reset; 484 485 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 486 dmub->debug.is_traceport_en = is_traceport_enabled; 487 488 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 489 dmub->debug.is_cw6_enabled = is_cw6_enabled; 490 491 dmub->debug.gpint_datain0 = REG_READ(DMCUB_GPINT_DATAIN0); 492 } 493 void dmub_dcn32_configure_dmub_in_system_memory(struct dmub_srv *dmub) 494 { 495 /* DMCUB_REGION3_TMR_AXI_SPACE values: 496 * 0b011 (0x3) - FB physical address 497 * 0b100 (0x4) - GPU virtual address 498 * 499 * Default value is 0x3 (FB Physical address for TMR). When programming 500 * DMUB to be in system memory, change to 0x4. The system memory allocated 501 * is accessible by both GPU and CPU, so we use GPU virtual address. 502 */ 503 REG_WRITE(DMCUB_REGION3_TMR_AXI_SPACE, 0x4); 504 } 505 506 void dmub_dcn32_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data) 507 { 508 REG_WRITE(DMCUB_INBOX0_WPTR, data.inbox0_cmd_common.all); 509 } 510 511 void dmub_dcn32_clear_inbox0_ack_register(struct dmub_srv *dmub) 512 { 513 REG_WRITE(DMCUB_SCRATCH17, 0); 514 } 515 516 uint32_t dmub_dcn32_read_inbox0_ack_register(struct dmub_srv *dmub) 517 { 518 return REG_READ(DMCUB_SCRATCH17); 519 } 520 521 void dmub_dcn32_save_surf_addr(struct dmub_srv *dmub, const struct dc_plane_address *addr, uint8_t subvp_index) 522 { 523 uint32_t index = 0; 524 525 if (subvp_index == 0) { 526 index = REG_READ(DMCUB_SCRATCH15); 527 if (index) { 528 REG_WRITE(DMCUB_SCRATCH9, addr->grph.addr.low_part); 529 REG_WRITE(DMCUB_SCRATCH11, addr->grph.meta_addr.low_part); 530 } else { 531 REG_WRITE(DMCUB_SCRATCH12, addr->grph.addr.low_part); 532 REG_WRITE(DMCUB_SCRATCH13, addr->grph.meta_addr.low_part); 533 } 534 REG_WRITE(DMCUB_SCRATCH15, !index); 535 } else if (subvp_index == 1) { 536 index = REG_READ(DMCUB_SCRATCH23); 537 if (index) { 538 REG_WRITE(DMCUB_SCRATCH18, addr->grph.addr.low_part); 539 REG_WRITE(DMCUB_SCRATCH19, addr->grph.meta_addr.low_part); 540 } else { 541 REG_WRITE(DMCUB_SCRATCH20, addr->grph.addr.low_part); 542 REG_WRITE(DMCUB_SCRATCH22, addr->grph.meta_addr.low_part); 543 } 544 REG_WRITE(DMCUB_SCRATCH23, !index); 545 } else { 546 return; 547 } 548 } 549