1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_reg.h" 28 #include "dmub_dcn31.h" 29 30 #include "yellow_carp_offset.h" 31 #include "dcn/dcn_3_1_2_offset.h" 32 #include "dcn/dcn_3_1_2_sh_mask.h" 33 34 #define BASE_INNER(seg) DCN_BASE__INST0_SEG##seg 35 #define CTX dmub 36 #define REGS dmub->regs_dcn31 37 #define REG_OFFSET_EXP(reg_name) (BASE(reg##reg_name##_BASE_IDX) + reg##reg_name) 38 39 const struct dmub_srv_dcn31_regs dmub_srv_dcn31_regs = { 40 #define DMUB_SR(reg) REG_OFFSET_EXP(reg), 41 { 42 DMUB_DCN31_REGS() 43 DMCUB_INTERNAL_REGS() 44 }, 45 #undef DMUB_SR 46 47 #define DMUB_SF(reg, field) FD_MASK(reg, field), 48 { DMUB_DCN31_FIELDS() }, 49 #undef DMUB_SF 50 51 #define DMUB_SF(reg, field) FD_SHIFT(reg, field), 52 { DMUB_DCN31_FIELDS() }, 53 #undef DMUB_SF 54 }; 55 56 static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub, 57 uint64_t *fb_base, 58 uint64_t *fb_offset) 59 { 60 uint32_t tmp; 61 62 if (dmub->fb_base || dmub->fb_offset) { 63 *fb_base = dmub->fb_base; 64 *fb_offset = dmub->fb_offset; 65 return; 66 } 67 68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); 69 *fb_base = (uint64_t)tmp << 24; 70 71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); 72 *fb_offset = (uint64_t)tmp << 24; 73 } 74 75 static inline void dmub_dcn31_translate_addr(const union dmub_addr *addr_in, 76 uint64_t fb_base, 77 uint64_t fb_offset, 78 union dmub_addr *addr_out) 79 { 80 addr_out->quad_part = addr_in->quad_part - fb_base + fb_offset; 81 } 82 83 void dmub_dcn31_reset(struct dmub_srv *dmub) 84 { 85 union dmub_gpint_data_register cmd; 86 const uint32_t timeout = 100; 87 uint32_t in_reset, scratch, i, pwait_mode; 88 89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); 90 91 if (in_reset == 0) { 92 cmd.bits.status = 1; 93 cmd.bits.command_code = DMUB_GPINT__STOP_FW; 94 cmd.bits.param = 0; 95 96 dmub->hw_funcs.set_gpint(dmub, cmd); 97 98 /** 99 * Timeout covers both the ACK and the wait 100 * for remaining work to finish. 101 */ 102 103 for (i = 0; i < timeout; ++i) { 104 if (dmub->hw_funcs.is_gpint_acked(dmub, cmd)) 105 break; 106 107 udelay(1); 108 } 109 110 for (i = 0; i < timeout; ++i) { 111 scratch = dmub->hw_funcs.get_gpint_response(dmub); 112 if (scratch == DMUB_GPINT__STOP_FW_RESPONSE) 113 break; 114 115 udelay(1); 116 } 117 118 for (i = 0; i < timeout; ++i) { 119 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); 120 if (pwait_mode & (1 << 0)) 121 break; 122 123 udelay(1); 124 } 125 /* Force reset in case we timed out, DMCUB is likely hung. */ 126 } 127 128 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 1); 129 REG_UPDATE(DMCUB_CNTL, DMCUB_ENABLE, 0); 130 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 1); 131 REG_WRITE(DMCUB_INBOX1_RPTR, 0); 132 REG_WRITE(DMCUB_INBOX1_WPTR, 0); 133 REG_WRITE(DMCUB_OUTBOX1_RPTR, 0); 134 REG_WRITE(DMCUB_OUTBOX1_WPTR, 0); 135 REG_WRITE(DMCUB_OUTBOX0_RPTR, 0); 136 REG_WRITE(DMCUB_OUTBOX0_WPTR, 0); 137 REG_WRITE(DMCUB_SCRATCH0, 0); 138 139 /* Clear the GPINT command manually so we don't send anything during boot. */ 140 cmd.all = 0; 141 dmub->hw_funcs.set_gpint(dmub, cmd); 142 } 143 144 void dmub_dcn31_reset_release(struct dmub_srv *dmub) 145 { 146 REG_UPDATE(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET, 0); 147 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF); 148 REG_UPDATE_2(DMCUB_CNTL, DMCUB_ENABLE, 1, DMCUB_TRACEPORT_EN, 1); 149 REG_UPDATE(DMCUB_CNTL2, DMCUB_SOFT_RESET, 0); 150 } 151 152 void dmub_dcn31_backdoor_load(struct dmub_srv *dmub, 153 const struct dmub_window *cw0, 154 const struct dmub_window *cw1) 155 { 156 union dmub_addr offset; 157 uint64_t fb_base, fb_offset; 158 159 dmub_dcn31_get_fb_base_offset(dmub, &fb_base, &fb_offset); 160 161 REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1); 162 163 dmub_dcn31_translate_addr(&cw0->offset, fb_base, fb_offset, &offset); 164 165 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part); 166 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part); 167 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base); 168 REG_SET_2(DMCUB_REGION3_CW0_TOP_ADDRESS, 0, 169 DMCUB_REGION3_CW0_TOP_ADDRESS, cw0->region.top, 170 DMCUB_REGION3_CW0_ENABLE, 1); 171 172 dmub_dcn31_translate_addr(&cw1->offset, fb_base, fb_offset, &offset); 173 174 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part); 175 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part); 176 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base); 177 REG_SET_2(DMCUB_REGION3_CW1_TOP_ADDRESS, 0, 178 DMCUB_REGION3_CW1_TOP_ADDRESS, cw1->region.top, 179 DMCUB_REGION3_CW1_ENABLE, 1); 180 181 REG_UPDATE_2(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 0, DMCUB_MEM_UNIT_ID, 182 0x20); 183 } 184 185 void dmub_dcn31_setup_windows(struct dmub_srv *dmub, 186 const struct dmub_window *cw2, 187 const struct dmub_window *cw3, 188 const struct dmub_window *cw4, 189 const struct dmub_window *cw5, 190 const struct dmub_window *cw6, 191 const struct dmub_window *region6) 192 { 193 union dmub_addr offset; 194 195 offset = cw3->offset; 196 197 REG_WRITE(DMCUB_REGION3_CW3_OFFSET, offset.u.low_part); 198 REG_WRITE(DMCUB_REGION3_CW3_OFFSET_HIGH, offset.u.high_part); 199 REG_WRITE(DMCUB_REGION3_CW3_BASE_ADDRESS, cw3->region.base); 200 REG_SET_2(DMCUB_REGION3_CW3_TOP_ADDRESS, 0, 201 DMCUB_REGION3_CW3_TOP_ADDRESS, cw3->region.top, 202 DMCUB_REGION3_CW3_ENABLE, 1); 203 204 offset = cw4->offset; 205 206 REG_WRITE(DMCUB_REGION3_CW4_OFFSET, offset.u.low_part); 207 REG_WRITE(DMCUB_REGION3_CW4_OFFSET_HIGH, offset.u.high_part); 208 REG_WRITE(DMCUB_REGION3_CW4_BASE_ADDRESS, cw4->region.base); 209 REG_SET_2(DMCUB_REGION3_CW4_TOP_ADDRESS, 0, 210 DMCUB_REGION3_CW4_TOP_ADDRESS, cw4->region.top, 211 DMCUB_REGION3_CW4_ENABLE, 1); 212 213 offset = cw5->offset; 214 215 REG_WRITE(DMCUB_REGION3_CW5_OFFSET, offset.u.low_part); 216 REG_WRITE(DMCUB_REGION3_CW5_OFFSET_HIGH, offset.u.high_part); 217 REG_WRITE(DMCUB_REGION3_CW5_BASE_ADDRESS, cw5->region.base); 218 REG_SET_2(DMCUB_REGION3_CW5_TOP_ADDRESS, 0, 219 DMCUB_REGION3_CW5_TOP_ADDRESS, cw5->region.top, 220 DMCUB_REGION3_CW5_ENABLE, 1); 221 222 REG_WRITE(DMCUB_REGION5_OFFSET, offset.u.low_part); 223 REG_WRITE(DMCUB_REGION5_OFFSET_HIGH, offset.u.high_part); 224 REG_SET_2(DMCUB_REGION5_TOP_ADDRESS, 0, 225 DMCUB_REGION5_TOP_ADDRESS, 226 cw5->region.top - cw5->region.base - 1, 227 DMCUB_REGION5_ENABLE, 1); 228 229 offset = cw6->offset; 230 231 REG_WRITE(DMCUB_REGION3_CW6_OFFSET, offset.u.low_part); 232 REG_WRITE(DMCUB_REGION3_CW6_OFFSET_HIGH, offset.u.high_part); 233 REG_WRITE(DMCUB_REGION3_CW6_BASE_ADDRESS, cw6->region.base); 234 REG_SET_2(DMCUB_REGION3_CW6_TOP_ADDRESS, 0, 235 DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top, 236 DMCUB_REGION3_CW6_ENABLE, 1); 237 } 238 239 void dmub_dcn31_setup_mailbox(struct dmub_srv *dmub, 240 const struct dmub_region *inbox1) 241 { 242 REG_WRITE(DMCUB_INBOX1_BASE_ADDRESS, inbox1->base); 243 REG_WRITE(DMCUB_INBOX1_SIZE, inbox1->top - inbox1->base); 244 } 245 246 uint32_t dmub_dcn31_get_inbox1_wptr(struct dmub_srv *dmub) 247 { 248 return REG_READ(DMCUB_INBOX1_WPTR); 249 } 250 251 uint32_t dmub_dcn31_get_inbox1_rptr(struct dmub_srv *dmub) 252 { 253 return REG_READ(DMCUB_INBOX1_RPTR); 254 } 255 256 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) 257 { 258 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); 259 } 260 261 void dmub_dcn31_setup_out_mailbox(struct dmub_srv *dmub, 262 const struct dmub_region *outbox1) 263 { 264 REG_WRITE(DMCUB_OUTBOX1_BASE_ADDRESS, outbox1->base); 265 REG_WRITE(DMCUB_OUTBOX1_SIZE, outbox1->top - outbox1->base); 266 } 267 268 uint32_t dmub_dcn31_get_outbox1_wptr(struct dmub_srv *dmub) 269 { 270 /** 271 * outbox1 wptr register is accessed without locks (dal & dc) 272 * and to be called only by dmub_srv_stat_get_notification() 273 */ 274 return REG_READ(DMCUB_OUTBOX1_WPTR); 275 } 276 277 void dmub_dcn31_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 278 { 279 /** 280 * outbox1 rptr register is accessed without locks (dal & dc) 281 * and to be called only by dmub_srv_stat_get_notification() 282 */ 283 REG_WRITE(DMCUB_OUTBOX1_RPTR, rptr_offset); 284 } 285 286 bool dmub_dcn31_is_hw_init(struct dmub_srv *dmub) 287 { 288 union dmub_fw_boot_status status; 289 uint32_t is_enable; 290 291 status.all = REG_READ(DMCUB_SCRATCH0); 292 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); 293 294 return is_enable != 0 && status.bits.dal_fw; 295 } 296 297 bool dmub_dcn31_is_supported(struct dmub_srv *dmub) 298 { 299 uint32_t supported = 0; 300 301 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); 302 303 return supported; 304 } 305 306 bool dmub_dcn31_is_psrsu_supported(struct dmub_srv *dmub) 307 { 308 return dmub->fw_version >= DMUB_FW_VERSION(4, 0, 59); 309 } 310 311 void dmub_dcn31_set_gpint(struct dmub_srv *dmub, 312 union dmub_gpint_data_register reg) 313 { 314 REG_WRITE(DMCUB_GPINT_DATAIN1, reg.all); 315 } 316 317 bool dmub_dcn31_is_gpint_acked(struct dmub_srv *dmub, 318 union dmub_gpint_data_register reg) 319 { 320 union dmub_gpint_data_register test; 321 322 reg.bits.status = 0; 323 test.all = REG_READ(DMCUB_GPINT_DATAIN1); 324 325 return test.all == reg.all; 326 } 327 328 uint32_t dmub_dcn31_get_gpint_response(struct dmub_srv *dmub) 329 { 330 return REG_READ(DMCUB_SCRATCH7); 331 } 332 333 uint32_t dmub_dcn31_get_gpint_dataout(struct dmub_srv *dmub) 334 { 335 uint32_t dataout = REG_READ(DMCUB_GPINT_DATAOUT); 336 337 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 0); 338 339 REG_WRITE(DMCUB_GPINT_DATAOUT, 0); 340 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 1); 341 REG_UPDATE(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK, 0); 342 343 REG_UPDATE(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN, 1); 344 345 return dataout; 346 } 347 348 union dmub_fw_boot_status dmub_dcn31_get_fw_boot_status(struct dmub_srv *dmub) 349 { 350 union dmub_fw_boot_status status; 351 352 status.all = REG_READ(DMCUB_SCRATCH0); 353 return status; 354 } 355 356 union dmub_fw_boot_options dmub_dcn31_get_fw_boot_option(struct dmub_srv *dmub) 357 { 358 union dmub_fw_boot_options option; 359 360 option.all = REG_READ(DMCUB_SCRATCH14); 361 return option; 362 } 363 364 void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params) 365 { 366 union dmub_fw_boot_options boot_options = {0}; 367 368 boot_options.bits.z10_disable = params->disable_z10; 369 boot_options.bits.dpia_supported = params->dpia_supported; 370 boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1; 371 boot_options.bits.usb4_cm_version = params->usb4_cm_version; 372 boot_options.bits.dpia_hpd_int_enable_supported = params->dpia_hpd_int_enable_supported; 373 boot_options.bits.power_optimization = params->power_optimization; 374 375 boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0; 376 377 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 378 } 379 380 void dmub_dcn31_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip) 381 { 382 union dmub_fw_boot_options boot_options; 383 boot_options.all = REG_READ(DMCUB_SCRATCH14); 384 boot_options.bits.skip_phy_init_panel_sequence = skip; 385 REG_WRITE(DMCUB_SCRATCH14, boot_options.all); 386 } 387 388 void dmub_dcn31_setup_outbox0(struct dmub_srv *dmub, 389 const struct dmub_region *outbox0) 390 { 391 REG_WRITE(DMCUB_OUTBOX0_BASE_ADDRESS, outbox0->base); 392 393 REG_WRITE(DMCUB_OUTBOX0_SIZE, outbox0->top - outbox0->base); 394 } 395 396 uint32_t dmub_dcn31_get_outbox0_wptr(struct dmub_srv *dmub) 397 { 398 return REG_READ(DMCUB_OUTBOX0_WPTR); 399 } 400 401 void dmub_dcn31_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset) 402 { 403 REG_WRITE(DMCUB_OUTBOX0_RPTR, rptr_offset); 404 } 405 406 uint32_t dmub_dcn31_get_current_time(struct dmub_srv *dmub) 407 { 408 return REG_READ(DMCUB_TIMER_CURRENT); 409 } 410 411 void dmub_dcn31_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) 412 { 413 uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; 414 uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled; 415 416 if (!dmub || !diag_data) 417 return; 418 419 memset(diag_data, 0, sizeof(*diag_data)); 420 421 diag_data->dmcub_version = dmub->fw_version; 422 423 diag_data->scratch[0] = REG_READ(DMCUB_SCRATCH0); 424 diag_data->scratch[1] = REG_READ(DMCUB_SCRATCH1); 425 diag_data->scratch[2] = REG_READ(DMCUB_SCRATCH2); 426 diag_data->scratch[3] = REG_READ(DMCUB_SCRATCH3); 427 diag_data->scratch[4] = REG_READ(DMCUB_SCRATCH4); 428 diag_data->scratch[5] = REG_READ(DMCUB_SCRATCH5); 429 diag_data->scratch[6] = REG_READ(DMCUB_SCRATCH6); 430 diag_data->scratch[7] = REG_READ(DMCUB_SCRATCH7); 431 diag_data->scratch[8] = REG_READ(DMCUB_SCRATCH8); 432 diag_data->scratch[9] = REG_READ(DMCUB_SCRATCH9); 433 diag_data->scratch[10] = REG_READ(DMCUB_SCRATCH10); 434 diag_data->scratch[11] = REG_READ(DMCUB_SCRATCH11); 435 diag_data->scratch[12] = REG_READ(DMCUB_SCRATCH12); 436 diag_data->scratch[13] = REG_READ(DMCUB_SCRATCH13); 437 diag_data->scratch[14] = REG_READ(DMCUB_SCRATCH14); 438 diag_data->scratch[15] = REG_READ(DMCUB_SCRATCH15); 439 440 diag_data->undefined_address_fault_addr = REG_READ(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR); 441 diag_data->inst_fetch_fault_addr = REG_READ(DMCUB_INST_FETCH_FAULT_ADDR); 442 diag_data->data_write_fault_addr = REG_READ(DMCUB_DATA_WRITE_FAULT_ADDR); 443 444 diag_data->inbox1_rptr = REG_READ(DMCUB_INBOX1_RPTR); 445 diag_data->inbox1_wptr = REG_READ(DMCUB_INBOX1_WPTR); 446 diag_data->inbox1_size = REG_READ(DMCUB_INBOX1_SIZE); 447 448 diag_data->inbox0_rptr = REG_READ(DMCUB_INBOX0_RPTR); 449 diag_data->inbox0_wptr = REG_READ(DMCUB_INBOX0_WPTR); 450 diag_data->inbox0_size = REG_READ(DMCUB_INBOX0_SIZE); 451 452 diag_data->outbox1_rptr = REG_READ(DMCUB_OUTBOX1_RPTR); 453 diag_data->outbox1_wptr = REG_READ(DMCUB_OUTBOX1_WPTR); 454 diag_data->outbox1_size = REG_READ(DMCUB_OUTBOX1_SIZE); 455 456 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); 457 diag_data->is_dmcub_enabled = is_dmub_enabled; 458 459 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); 460 diag_data->is_dmcub_soft_reset = is_soft_reset; 461 462 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); 463 diag_data->is_dmcub_secure_reset = is_sec_reset; 464 465 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); 466 diag_data->is_traceport_en = is_traceport_enabled; 467 468 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); 469 diag_data->is_cw0_enabled = is_cw0_enabled; 470 471 REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled); 472 diag_data->is_cw6_enabled = is_cw6_enabled; 473 diag_data->timeout_info = dmub->debug; 474 } 475 476 bool dmub_dcn31_should_detect(struct dmub_srv *dmub) 477 { 478 uint32_t fw_boot_status = REG_READ(DMCUB_SCRATCH0); 479 bool should_detect = (fw_boot_status & DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED) != 0; 480 return should_detect; 481 } 482 483