1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 } bitfields; 229 230 /** 231 * Union for debug flags. 232 */ 233 uint32_t u32All; 234 }; 235 236 /** 237 * DMUB visual confirm color 238 */ 239 struct dmub_feature_caps { 240 /** 241 * Max PSR version supported by FW. 242 */ 243 uint8_t psr; 244 uint8_t fw_assisted_mclk_switch; 245 uint8_t reserved[6]; 246 }; 247 248 struct dmub_visual_confirm_color { 249 /** 250 * Maximum 10 bits color value 251 */ 252 uint16_t color_r_cr; 253 uint16_t color_g_y; 254 uint16_t color_b_cb; 255 uint16_t panel_inst; 256 }; 257 258 #if defined(__cplusplus) 259 } 260 #endif 261 262 //============================================================================== 263 //</DMUB_TYPES>================================================================= 264 //============================================================================== 265 //< DMUB_META>================================================================== 266 //============================================================================== 267 #pragma pack(push, 1) 268 269 /* Magic value for identifying dmub_fw_meta_info */ 270 #define DMUB_FW_META_MAGIC 0x444D5542 271 272 /* Offset from the end of the file to the dmub_fw_meta_info */ 273 #define DMUB_FW_META_OFFSET 0x24 274 275 /** 276 * struct dmub_fw_meta_info - metadata associated with fw binary 277 * 278 * NOTE: This should be considered a stable API. Fields should 279 * not be repurposed or reordered. New fields should be 280 * added instead to extend the structure. 281 * 282 * @magic_value: magic value identifying DMUB firmware meta info 283 * @fw_region_size: size of the firmware state region 284 * @trace_buffer_size: size of the tracebuffer region 285 * @fw_version: the firmware version information 286 * @dal_fw: 1 if the firmware is DAL 287 */ 288 struct dmub_fw_meta_info { 289 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 290 uint32_t fw_region_size; /**< size of the firmware state region */ 291 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 292 uint32_t fw_version; /**< the firmware version information */ 293 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 294 uint8_t reserved[3]; /**< padding bits */ 295 }; 296 297 /** 298 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 299 */ 300 union dmub_fw_meta { 301 struct dmub_fw_meta_info info; /**< metadata info */ 302 uint8_t reserved[64]; /**< padding bits */ 303 }; 304 305 #pragma pack(pop) 306 307 //============================================================================== 308 //< DMUB Trace Buffer>================================================================ 309 //============================================================================== 310 /** 311 * dmub_trace_code_t - firmware trace code, 32-bits 312 */ 313 typedef uint32_t dmub_trace_code_t; 314 315 /** 316 * struct dmcub_trace_buf_entry - Firmware trace entry 317 */ 318 struct dmcub_trace_buf_entry { 319 dmub_trace_code_t trace_code; /**< trace code for the event */ 320 uint32_t tick_count; /**< the tick count at time of trace */ 321 uint32_t param0; /**< trace defined parameter 0 */ 322 uint32_t param1; /**< trace defined parameter 1 */ 323 }; 324 325 //============================================================================== 326 //< DMUB_STATUS>================================================================ 327 //============================================================================== 328 329 /** 330 * DMCUB scratch registers can be used to determine firmware status. 331 * Current scratch register usage is as follows: 332 * 333 * SCRATCH0: FW Boot Status register 334 * SCRATCH5: LVTMA Status Register 335 * SCRATCH15: FW Boot Options register 336 */ 337 338 /** 339 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 340 */ 341 union dmub_fw_boot_status { 342 struct { 343 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 344 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 345 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 346 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 347 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 348 uint32_t reserved : 1; 349 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 350 351 } bits; /**< status bits */ 352 uint32_t all; /**< 32-bit access to status bits */ 353 }; 354 355 /** 356 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 357 */ 358 enum dmub_fw_boot_status_bit { 359 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 360 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 361 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 362 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 363 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 364 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 365 }; 366 367 /* Register bit definition for SCRATCH5 */ 368 union dmub_lvtma_status { 369 struct { 370 uint32_t psp_ok : 1; 371 uint32_t edp_on : 1; 372 uint32_t reserved : 30; 373 } bits; 374 uint32_t all; 375 }; 376 377 enum dmub_lvtma_status_bit { 378 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 379 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 380 }; 381 382 /** 383 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 384 */ 385 union dmub_fw_boot_options { 386 struct { 387 uint32_t pemu_env : 1; /**< 1 if PEMU */ 388 uint32_t fpga_env : 1; /**< 1 if FPGA */ 389 uint32_t optimized_init : 1; /**< 1 if optimized init */ 390 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 391 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 392 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 393 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 394 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 395 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 396 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 397 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 398 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 399 uint32_t power_optimization: 1; 400 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 401 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 402 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 403 404 uint32_t reserved : 17; /**< reserved */ 405 } bits; /**< boot bits */ 406 uint32_t all; /**< 32-bit access to bits */ 407 }; 408 409 enum dmub_fw_boot_options_bit { 410 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 411 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 412 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 413 }; 414 415 //============================================================================== 416 //</DMUB_STATUS>================================================================ 417 //============================================================================== 418 //< DMUB_VBIOS>================================================================= 419 //============================================================================== 420 421 /* 422 * enum dmub_cmd_vbios_type - VBIOS commands. 423 * 424 * Command IDs should be treated as stable ABI. 425 * Do not reuse or modify IDs. 426 */ 427 enum dmub_cmd_vbios_type { 428 /** 429 * Configures the DIG encoder. 430 */ 431 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 432 /** 433 * Controls the PHY. 434 */ 435 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 436 /** 437 * Sets the pixel clock/symbol clock. 438 */ 439 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 440 /** 441 * Enables or disables power gating. 442 */ 443 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 444 /** 445 * Controls embedded panels. 446 */ 447 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 448 /** 449 * Query DP alt status on a transmitter. 450 */ 451 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 452 }; 453 454 //============================================================================== 455 //</DMUB_VBIOS>================================================================= 456 //============================================================================== 457 //< DMUB_GPINT>================================================================= 458 //============================================================================== 459 460 /** 461 * The shifts and masks below may alternatively be used to format and read 462 * the command register bits. 463 */ 464 465 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 466 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 467 468 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 469 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 470 471 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 472 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 473 474 /** 475 * Command responses. 476 */ 477 478 /** 479 * Return response for DMUB_GPINT__STOP_FW command. 480 */ 481 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 482 483 /** 484 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 485 */ 486 union dmub_gpint_data_register { 487 struct { 488 uint32_t param : 16; /**< 16-bit parameter */ 489 uint32_t command_code : 12; /**< GPINT command */ 490 uint32_t status : 4; /**< Command status bit */ 491 } bits; /**< GPINT bit access */ 492 uint32_t all; /**< GPINT 32-bit access */ 493 }; 494 495 /* 496 * enum dmub_gpint_command - GPINT command to DMCUB FW 497 * 498 * Command IDs should be treated as stable ABI. 499 * Do not reuse or modify IDs. 500 */ 501 enum dmub_gpint_command { 502 /** 503 * Invalid command, ignored. 504 */ 505 DMUB_GPINT__INVALID_COMMAND = 0, 506 /** 507 * DESC: Queries the firmware version. 508 * RETURN: Firmware version. 509 */ 510 DMUB_GPINT__GET_FW_VERSION = 1, 511 /** 512 * DESC: Halts the firmware. 513 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 514 */ 515 DMUB_GPINT__STOP_FW = 2, 516 /** 517 * DESC: Get PSR state from FW. 518 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 519 */ 520 DMUB_GPINT__GET_PSR_STATE = 7, 521 /** 522 * DESC: Notifies DMCUB of the currently active streams. 523 * ARGS: Stream mask, 1 bit per active stream index. 524 */ 525 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 526 /** 527 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 528 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 529 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 530 * RETURN: PSR residency in milli-percent. 531 */ 532 DMUB_GPINT__PSR_RESIDENCY = 9, 533 534 /** 535 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 536 */ 537 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 538 }; 539 540 /** 541 * INBOX0 generic command definition 542 */ 543 union dmub_inbox0_cmd_common { 544 struct { 545 uint32_t command_code: 8; /**< INBOX0 command code */ 546 uint32_t param: 24; /**< 24-bit parameter */ 547 } bits; 548 uint32_t all; 549 }; 550 551 /** 552 * INBOX0 hw_lock command definition 553 */ 554 union dmub_inbox0_cmd_lock_hw { 555 struct { 556 uint32_t command_code: 8; 557 558 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 559 uint32_t hw_lock_client: 2; 560 561 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 562 uint32_t otg_inst: 3; 563 uint32_t opp_inst: 3; 564 uint32_t dig_inst: 3; 565 566 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 567 uint32_t lock_pipe: 1; 568 uint32_t lock_cursor: 1; 569 uint32_t lock_dig: 1; 570 uint32_t triple_buffer_lock: 1; 571 572 uint32_t lock: 1; /**< Lock */ 573 uint32_t should_release: 1; /**< Release */ 574 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 575 } bits; 576 uint32_t all; 577 }; 578 579 union dmub_inbox0_data_register { 580 union dmub_inbox0_cmd_common inbox0_cmd_common; 581 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 582 }; 583 584 enum dmub_inbox0_command { 585 /** 586 * DESC: Invalid command, ignored. 587 */ 588 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 589 /** 590 * DESC: Notification to acquire/release HW lock 591 * ARGS: 592 */ 593 DMUB_INBOX0_CMD__HW_LOCK = 1, 594 }; 595 //============================================================================== 596 //</DMUB_GPINT>================================================================= 597 //============================================================================== 598 //< DMUB_CMD>=================================================================== 599 //============================================================================== 600 601 /** 602 * Size in bytes of each DMUB command. 603 */ 604 #define DMUB_RB_CMD_SIZE 64 605 606 /** 607 * Maximum number of items in the DMUB ringbuffer. 608 */ 609 #define DMUB_RB_MAX_ENTRY 128 610 611 /** 612 * Ringbuffer size in bytes. 613 */ 614 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 615 616 /** 617 * REG_SET mask for reg offload. 618 */ 619 #define REG_SET_MASK 0xFFFF 620 621 /* 622 * enum dmub_cmd_type - DMUB inbox command. 623 * 624 * Command IDs should be treated as stable ABI. 625 * Do not reuse or modify IDs. 626 */ 627 enum dmub_cmd_type { 628 /** 629 * Invalid command. 630 */ 631 DMUB_CMD__NULL = 0, 632 /** 633 * Read modify write register sequence offload. 634 */ 635 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 636 /** 637 * Field update register sequence offload. 638 */ 639 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 640 /** 641 * Burst write sequence offload. 642 */ 643 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 644 /** 645 * Reg wait sequence offload. 646 */ 647 DMUB_CMD__REG_REG_WAIT = 4, 648 /** 649 * Workaround to avoid HUBP underflow during NV12 playback. 650 */ 651 DMUB_CMD__PLAT_54186_WA = 5, 652 /** 653 * Command type used to query FW feature caps. 654 */ 655 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 656 /** 657 * Command type used to get visual confirm color. 658 */ 659 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 660 /** 661 * Command type used for all PSR commands. 662 */ 663 DMUB_CMD__PSR = 64, 664 /** 665 * Command type used for all MALL commands. 666 */ 667 DMUB_CMD__MALL = 65, 668 /** 669 * Command type used for all ABM commands. 670 */ 671 DMUB_CMD__ABM = 66, 672 /** 673 * Command type used to update dirty rects in FW. 674 */ 675 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 676 /** 677 * Command type used to update cursor info in FW. 678 */ 679 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 680 /** 681 * Command type used for HW locking in FW. 682 */ 683 DMUB_CMD__HW_LOCK = 69, 684 /** 685 * Command type used to access DP AUX. 686 */ 687 DMUB_CMD__DP_AUX_ACCESS = 70, 688 /** 689 * Command type used for OUTBOX1 notification enable 690 */ 691 DMUB_CMD__OUTBOX1_ENABLE = 71, 692 693 /** 694 * Command type used for all idle optimization commands. 695 */ 696 DMUB_CMD__IDLE_OPT = 72, 697 /** 698 * Command type used for all clock manager commands. 699 */ 700 DMUB_CMD__CLK_MGR = 73, 701 /** 702 * Command type used for all panel control commands. 703 */ 704 DMUB_CMD__PANEL_CNTL = 74, 705 /** 706 * Command type used for <TODO:description> 707 */ 708 DMUB_CMD__CAB_FOR_SS = 75, 709 710 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 711 712 /** 713 * Command type used for interfacing with DPIA. 714 */ 715 DMUB_CMD__DPIA = 77, 716 /** 717 * Command type used for EDID CEA parsing 718 */ 719 DMUB_CMD__EDID_CEA = 79, 720 /** 721 * Command type used for getting usbc cable ID 722 */ 723 DMUB_CMD_GET_USBC_CABLE_ID = 81, 724 /** 725 * Command type used to query HPD state. 726 */ 727 DMUB_CMD__QUERY_HPD_STATE = 82, 728 /** 729 * Command type used for all VBIOS interface commands. 730 */ 731 DMUB_CMD__VBIOS = 128, 732 }; 733 734 /** 735 * enum dmub_out_cmd_type - DMUB outbox commands. 736 */ 737 enum dmub_out_cmd_type { 738 /** 739 * Invalid outbox command, ignored. 740 */ 741 DMUB_OUT_CMD__NULL = 0, 742 /** 743 * Command type used for DP AUX Reply data notification 744 */ 745 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 746 /** 747 * Command type used for DP HPD event notification 748 */ 749 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 750 /** 751 * Command type used for SET_CONFIG Reply notification 752 */ 753 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 754 }; 755 756 /* DMUB_CMD__DPIA command sub-types. */ 757 enum dmub_cmd_dpia_type { 758 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 759 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 760 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 761 }; 762 763 enum dmub_cmd_header_sub_type { 764 DMUB_CMD__SUB_TYPE_GENERAL = 0, 765 DMUB_CMD__SUB_TYPE_CURSOR_POSITION = 1 766 }; 767 768 #pragma pack(push, 1) 769 770 /** 771 * struct dmub_cmd_header - Common command header fields. 772 */ 773 struct dmub_cmd_header { 774 unsigned int type : 8; /**< command type */ 775 unsigned int sub_type : 8; /**< command sub type */ 776 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 777 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 778 unsigned int reserved0 : 6; /**< reserved bits */ 779 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 780 unsigned int reserved1 : 2; /**< reserved bits */ 781 }; 782 783 /* 784 * struct dmub_cmd_read_modify_write_sequence - Read modify write 785 * 786 * 60 payload bytes can hold up to 5 sets of read modify writes, 787 * each take 3 dwords. 788 * 789 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 790 * 791 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 792 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 793 */ 794 struct dmub_cmd_read_modify_write_sequence { 795 uint32_t addr; /**< register address */ 796 uint32_t modify_mask; /**< modify mask */ 797 uint32_t modify_value; /**< modify value */ 798 }; 799 800 /** 801 * Maximum number of ops in read modify write sequence. 802 */ 803 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 804 805 /** 806 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 807 */ 808 struct dmub_rb_cmd_read_modify_write { 809 struct dmub_cmd_header header; /**< command header */ 810 /** 811 * Read modify write sequence. 812 */ 813 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 814 }; 815 816 /* 817 * Update a register with specified masks and values sequeunce 818 * 819 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 820 * 821 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 822 * 823 * 824 * USE CASE: 825 * 1. auto-increment register where additional read would update pointer and produce wrong result 826 * 2. toggle a bit without read in the middle 827 */ 828 829 struct dmub_cmd_reg_field_update_sequence { 830 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 831 uint32_t modify_value; /**< value to update with */ 832 }; 833 834 /** 835 * Maximum number of ops in field update sequence. 836 */ 837 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 838 839 /** 840 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 841 */ 842 struct dmub_rb_cmd_reg_field_update_sequence { 843 struct dmub_cmd_header header; /**< command header */ 844 uint32_t addr; /**< register address */ 845 /** 846 * Field update sequence. 847 */ 848 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 849 }; 850 851 852 /** 853 * Maximum number of burst write values. 854 */ 855 #define DMUB_BURST_WRITE_VALUES__MAX 14 856 857 /* 858 * struct dmub_rb_cmd_burst_write - Burst write 859 * 860 * support use case such as writing out LUTs. 861 * 862 * 60 payload bytes can hold up to 14 values to write to given address 863 * 864 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 865 */ 866 struct dmub_rb_cmd_burst_write { 867 struct dmub_cmd_header header; /**< command header */ 868 uint32_t addr; /**< register start address */ 869 /** 870 * Burst write register values. 871 */ 872 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 873 }; 874 875 /** 876 * struct dmub_rb_cmd_common - Common command header 877 */ 878 struct dmub_rb_cmd_common { 879 struct dmub_cmd_header header; /**< command header */ 880 /** 881 * Padding to RB_CMD_SIZE 882 */ 883 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 884 }; 885 886 /** 887 * struct dmub_cmd_reg_wait_data - Register wait data 888 */ 889 struct dmub_cmd_reg_wait_data { 890 uint32_t addr; /**< Register address */ 891 uint32_t mask; /**< Mask for register bits */ 892 uint32_t condition_field_value; /**< Value to wait for */ 893 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 894 }; 895 896 /** 897 * struct dmub_rb_cmd_reg_wait - Register wait command 898 */ 899 struct dmub_rb_cmd_reg_wait { 900 struct dmub_cmd_header header; /**< Command header */ 901 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 902 }; 903 904 /** 905 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 906 * 907 * Reprograms surface parameters to avoid underflow. 908 */ 909 struct dmub_cmd_PLAT_54186_wa { 910 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 911 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 912 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 913 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 914 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 915 struct { 916 uint8_t hubp_inst : 4; /**< HUBP instance */ 917 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 918 uint8_t immediate :1; /**< Immediate flip */ 919 uint8_t vmid : 4; /**< VMID */ 920 uint8_t grph_stereo : 1; /**< 1 if stereo */ 921 uint32_t reserved : 21; /**< Reserved */ 922 } flip_params; /**< Pageflip parameters */ 923 uint32_t reserved[9]; /**< Reserved bits */ 924 }; 925 926 /** 927 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 928 */ 929 struct dmub_rb_cmd_PLAT_54186_wa { 930 struct dmub_cmd_header header; /**< Command header */ 931 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 932 }; 933 934 /** 935 * struct dmub_rb_cmd_mall - MALL command data. 936 */ 937 struct dmub_rb_cmd_mall { 938 struct dmub_cmd_header header; /**< Common command header */ 939 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 940 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 941 uint32_t tmr_delay; /**< Timer delay */ 942 uint32_t tmr_scale; /**< Timer scale */ 943 uint16_t cursor_width; /**< Cursor width in pixels */ 944 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 945 uint16_t cursor_height; /**< Cursor height in pixels */ 946 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 947 uint8_t debug_bits; /**< Debug bits */ 948 949 uint8_t reserved1; /**< Reserved bits */ 950 uint8_t reserved2; /**< Reserved bits */ 951 }; 952 953 /** 954 * enum dmub_cmd_cab_type - TODO: 955 */ 956 enum dmub_cmd_cab_type { 957 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 958 DMUB_CMD__CAB_NO_DCN_REQ = 1, 959 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 960 }; 961 962 /** 963 * struct dmub_rb_cmd_cab_for_ss - TODO: 964 */ 965 struct dmub_rb_cmd_cab_for_ss { 966 struct dmub_cmd_header header; 967 uint8_t cab_alloc_ways; /* total number of ways */ 968 uint8_t debug_bits; /* debug bits */ 969 }; 970 971 enum mclk_switch_mode { 972 NONE = 0, 973 FPO = 1, 974 SUBVP = 2, 975 VBLANK = 3, 976 }; 977 978 /* Per pipe struct which stores the MCLK switch mode 979 * data to be sent to DMUB. 980 * Named "v2" for now -- once FPO and SUBVP are fully merged 981 * the type name can be updated 982 */ 983 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 984 union { 985 struct { 986 uint32_t pix_clk_100hz; 987 uint16_t main_vblank_start; 988 uint16_t main_vblank_end; 989 uint16_t mall_region_lines; 990 uint16_t prefetch_lines; 991 uint16_t prefetch_to_mall_start_lines; 992 uint16_t processing_delay_lines; 993 uint16_t htotal; // required to calculate line time for multi-display cases 994 uint16_t vtotal; 995 uint8_t main_pipe_index; 996 uint8_t phantom_pipe_index; 997 /* Since the microschedule is calculated in terms of OTG lines, 998 * include any scaling factors to make sure when we get accurate 999 * conversion when programming MALL_START_LINE (which is in terms 1000 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1001 * is 1/2 (numerator = 1, denominator = 2). 1002 */ 1003 uint8_t scale_factor_numerator; 1004 uint8_t scale_factor_denominator; 1005 uint8_t is_drr; 1006 uint8_t main_split_pipe_index; 1007 uint8_t phantom_split_pipe_index; 1008 } subvp_data; 1009 1010 struct { 1011 uint32_t pix_clk_100hz; 1012 uint16_t vblank_start; 1013 uint16_t vblank_end; 1014 uint16_t vstartup_start; 1015 uint16_t vtotal; 1016 uint16_t htotal; 1017 uint8_t vblank_pipe_index; 1018 uint8_t padding[2]; 1019 struct { 1020 uint8_t drr_in_use; 1021 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1022 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1023 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1024 uint8_t use_ramping; // Use ramping or not 1025 } drr_info; // DRR considered as part of SubVP + VBLANK case 1026 } vblank_data; 1027 } pipe_config; 1028 1029 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1030 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1031 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1032 */ 1033 uint8_t mode; // enum mclk_switch_mode 1034 }; 1035 1036 /** 1037 * Config data for Sub-VP and FPO 1038 * Named "v2" for now -- once FPO and SUBVP are fully merged 1039 * the type name can be updated 1040 */ 1041 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1042 uint16_t watermark_a_cache; 1043 uint8_t vertical_int_margin_us; 1044 uint8_t pstate_allow_width_us; 1045 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1046 }; 1047 1048 /** 1049 * DMUB rb command definition for Sub-VP and FPO 1050 * Named "v2" for now -- once FPO and SUBVP are fully merged 1051 * the type name can be updated 1052 */ 1053 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1054 struct dmub_cmd_header header; 1055 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1056 }; 1057 1058 /** 1059 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1060 */ 1061 enum dmub_cmd_idle_opt_type { 1062 /** 1063 * DCN hardware restore. 1064 */ 1065 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1066 1067 /** 1068 * DCN hardware save. 1069 */ 1070 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1071 }; 1072 1073 /** 1074 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1075 */ 1076 struct dmub_rb_cmd_idle_opt_dcn_restore { 1077 struct dmub_cmd_header header; /**< header */ 1078 }; 1079 1080 /** 1081 * struct dmub_clocks - Clock update notification. 1082 */ 1083 struct dmub_clocks { 1084 uint32_t dispclk_khz; /**< dispclk kHz */ 1085 uint32_t dppclk_khz; /**< dppclk kHz */ 1086 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1087 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1088 }; 1089 1090 /** 1091 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1092 */ 1093 enum dmub_cmd_clk_mgr_type { 1094 /** 1095 * Notify DMCUB of clock update. 1096 */ 1097 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1098 }; 1099 1100 /** 1101 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1102 */ 1103 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1104 struct dmub_cmd_header header; /**< header */ 1105 struct dmub_clocks clocks; /**< clock data */ 1106 }; 1107 1108 /** 1109 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1110 */ 1111 struct dmub_cmd_digx_encoder_control_data { 1112 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1113 }; 1114 1115 /** 1116 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1117 */ 1118 struct dmub_rb_cmd_digx_encoder_control { 1119 struct dmub_cmd_header header; /**< header */ 1120 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1121 }; 1122 1123 /** 1124 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1125 */ 1126 struct dmub_cmd_set_pixel_clock_data { 1127 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1128 }; 1129 1130 /** 1131 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1132 */ 1133 struct dmub_rb_cmd_set_pixel_clock { 1134 struct dmub_cmd_header header; /**< header */ 1135 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1136 }; 1137 1138 /** 1139 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1140 */ 1141 struct dmub_cmd_enable_disp_power_gating_data { 1142 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1143 }; 1144 1145 /** 1146 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1147 */ 1148 struct dmub_rb_cmd_enable_disp_power_gating { 1149 struct dmub_cmd_header header; /**< header */ 1150 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1151 }; 1152 1153 /** 1154 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1155 */ 1156 struct dmub_dig_transmitter_control_data_v1_7 { 1157 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1158 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1159 union { 1160 uint8_t digmode; /**< enum atom_encode_mode_def */ 1161 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1162 } mode_laneset; 1163 uint8_t lanenum; /**< Number of lanes */ 1164 union { 1165 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1166 } symclk_units; 1167 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1168 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1169 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1170 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1171 uint8_t reserved1; /**< For future use */ 1172 uint8_t reserved2[3]; /**< For future use */ 1173 uint32_t reserved3[11]; /**< For future use */ 1174 }; 1175 1176 /** 1177 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1178 */ 1179 union dmub_cmd_dig1_transmitter_control_data { 1180 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1181 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1182 }; 1183 1184 /** 1185 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1186 */ 1187 struct dmub_rb_cmd_dig1_transmitter_control { 1188 struct dmub_cmd_header header; /**< header */ 1189 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1190 }; 1191 1192 /** 1193 * DPIA tunnel command parameters. 1194 */ 1195 struct dmub_cmd_dig_dpia_control_data { 1196 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1197 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1198 union { 1199 uint8_t digmode; /** enum atom_encode_mode_def */ 1200 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1201 } mode_laneset; 1202 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1203 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1204 uint8_t hpdsel; /** =0: HPD is not assigned */ 1205 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1206 uint8_t dpia_id; /** Index of DPIA */ 1207 uint8_t fec_rdy : 1; 1208 uint8_t reserved : 7; 1209 uint32_t reserved1; 1210 }; 1211 1212 /** 1213 * DMUB command for DPIA tunnel control. 1214 */ 1215 struct dmub_rb_cmd_dig1_dpia_control { 1216 struct dmub_cmd_header header; 1217 struct dmub_cmd_dig_dpia_control_data dpia_control; 1218 }; 1219 1220 /** 1221 * SET_CONFIG Command Payload 1222 */ 1223 struct set_config_cmd_payload { 1224 uint8_t msg_type; /* set config message type */ 1225 uint8_t msg_data; /* set config message data */ 1226 }; 1227 1228 /** 1229 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1230 */ 1231 struct dmub_cmd_set_config_control_data { 1232 struct set_config_cmd_payload cmd_pkt; 1233 uint8_t instance; /* DPIA instance */ 1234 uint8_t immed_status; /* Immediate status returned in case of error */ 1235 }; 1236 1237 /** 1238 * DMUB command structure for SET_CONFIG command. 1239 */ 1240 struct dmub_rb_cmd_set_config_access { 1241 struct dmub_cmd_header header; /* header */ 1242 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1243 }; 1244 1245 /** 1246 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1247 */ 1248 struct dmub_cmd_mst_alloc_slots_control_data { 1249 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1250 uint8_t instance; /* DPIA instance */ 1251 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1252 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1253 }; 1254 1255 /** 1256 * DMUB command structure for SET_ command. 1257 */ 1258 struct dmub_rb_cmd_set_mst_alloc_slots { 1259 struct dmub_cmd_header header; /* header */ 1260 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1261 }; 1262 1263 /** 1264 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1265 */ 1266 struct dmub_rb_cmd_dpphy_init { 1267 struct dmub_cmd_header header; /**< header */ 1268 uint8_t reserved[60]; /**< reserved bits */ 1269 }; 1270 1271 /** 1272 * enum dp_aux_request_action - DP AUX request command listing. 1273 * 1274 * 4 AUX request command bits are shifted to high nibble. 1275 */ 1276 enum dp_aux_request_action { 1277 /** I2C-over-AUX write request */ 1278 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1279 /** I2C-over-AUX read request */ 1280 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1281 /** I2C-over-AUX write status request */ 1282 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1283 /** I2C-over-AUX write request with MOT=1 */ 1284 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1285 /** I2C-over-AUX read request with MOT=1 */ 1286 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1287 /** I2C-over-AUX write status request with MOT=1 */ 1288 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1289 /** Native AUX write request */ 1290 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1291 /** Native AUX read request */ 1292 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1293 }; 1294 1295 /** 1296 * enum aux_return_code_type - DP AUX process return code listing. 1297 */ 1298 enum aux_return_code_type { 1299 /** AUX process succeeded */ 1300 AUX_RET_SUCCESS = 0, 1301 /** AUX process failed with unknown reason */ 1302 AUX_RET_ERROR_UNKNOWN, 1303 /** AUX process completed with invalid reply */ 1304 AUX_RET_ERROR_INVALID_REPLY, 1305 /** AUX process timed out */ 1306 AUX_RET_ERROR_TIMEOUT, 1307 /** HPD was low during AUX process */ 1308 AUX_RET_ERROR_HPD_DISCON, 1309 /** Failed to acquire AUX engine */ 1310 AUX_RET_ERROR_ENGINE_ACQUIRE, 1311 /** AUX request not supported */ 1312 AUX_RET_ERROR_INVALID_OPERATION, 1313 /** AUX process not available */ 1314 AUX_RET_ERROR_PROTOCOL_ERROR, 1315 }; 1316 1317 /** 1318 * enum aux_channel_type - DP AUX channel type listing. 1319 */ 1320 enum aux_channel_type { 1321 /** AUX thru Legacy DP AUX */ 1322 AUX_CHANNEL_LEGACY_DDC, 1323 /** AUX thru DPIA DP tunneling */ 1324 AUX_CHANNEL_DPIA 1325 }; 1326 1327 /** 1328 * struct aux_transaction_parameters - DP AUX request transaction data 1329 */ 1330 struct aux_transaction_parameters { 1331 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1332 uint8_t action; /**< enum dp_aux_request_action */ 1333 uint8_t length; /**< DP AUX request data length */ 1334 uint8_t reserved; /**< For future use */ 1335 uint32_t address; /**< DP AUX address */ 1336 uint8_t data[16]; /**< DP AUX write data */ 1337 }; 1338 1339 /** 1340 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1341 */ 1342 struct dmub_cmd_dp_aux_control_data { 1343 uint8_t instance; /**< AUX instance or DPIA instance */ 1344 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1345 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1346 uint8_t reserved0; /**< For future use */ 1347 uint16_t timeout; /**< timeout time in us */ 1348 uint16_t reserved1; /**< For future use */ 1349 enum aux_channel_type type; /**< enum aux_channel_type */ 1350 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1351 }; 1352 1353 /** 1354 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1355 */ 1356 struct dmub_rb_cmd_dp_aux_access { 1357 /** 1358 * Command header. 1359 */ 1360 struct dmub_cmd_header header; 1361 /** 1362 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1363 */ 1364 struct dmub_cmd_dp_aux_control_data aux_control; 1365 }; 1366 1367 /** 1368 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1369 */ 1370 struct dmub_rb_cmd_outbox1_enable { 1371 /** 1372 * Command header. 1373 */ 1374 struct dmub_cmd_header header; 1375 /** 1376 * enable: 0x0 -> disable outbox1 notification (default value) 1377 * 0x1 -> enable outbox1 notification 1378 */ 1379 uint32_t enable; 1380 }; 1381 1382 /* DP AUX Reply command - OutBox Cmd */ 1383 /** 1384 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1385 */ 1386 struct aux_reply_data { 1387 /** 1388 * Aux cmd 1389 */ 1390 uint8_t command; 1391 /** 1392 * Aux reply data length (max: 16 bytes) 1393 */ 1394 uint8_t length; 1395 /** 1396 * Alignment only 1397 */ 1398 uint8_t pad[2]; 1399 /** 1400 * Aux reply data 1401 */ 1402 uint8_t data[16]; 1403 }; 1404 1405 /** 1406 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1407 */ 1408 struct aux_reply_control_data { 1409 /** 1410 * Reserved for future use 1411 */ 1412 uint32_t handle; 1413 /** 1414 * Aux Instance 1415 */ 1416 uint8_t instance; 1417 /** 1418 * Aux transaction result: definition in enum aux_return_code_type 1419 */ 1420 uint8_t result; 1421 /** 1422 * Alignment only 1423 */ 1424 uint16_t pad; 1425 }; 1426 1427 /** 1428 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1429 */ 1430 struct dmub_rb_cmd_dp_aux_reply { 1431 /** 1432 * Command header. 1433 */ 1434 struct dmub_cmd_header header; 1435 /** 1436 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1437 */ 1438 struct aux_reply_control_data control; 1439 /** 1440 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1441 */ 1442 struct aux_reply_data reply_data; 1443 }; 1444 1445 /* DP HPD Notify command - OutBox Cmd */ 1446 /** 1447 * DP HPD Type 1448 */ 1449 enum dp_hpd_type { 1450 /** 1451 * Normal DP HPD 1452 */ 1453 DP_HPD = 0, 1454 /** 1455 * DP HPD short pulse 1456 */ 1457 DP_IRQ 1458 }; 1459 1460 /** 1461 * DP HPD Status 1462 */ 1463 enum dp_hpd_status { 1464 /** 1465 * DP_HPD status low 1466 */ 1467 DP_HPD_UNPLUG = 0, 1468 /** 1469 * DP_HPD status high 1470 */ 1471 DP_HPD_PLUG 1472 }; 1473 1474 /** 1475 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1476 */ 1477 struct dp_hpd_data { 1478 /** 1479 * DP HPD instance 1480 */ 1481 uint8_t instance; 1482 /** 1483 * HPD type 1484 */ 1485 uint8_t hpd_type; 1486 /** 1487 * HPD status: only for type: DP_HPD to indicate status 1488 */ 1489 uint8_t hpd_status; 1490 /** 1491 * Alignment only 1492 */ 1493 uint8_t pad; 1494 }; 1495 1496 /** 1497 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1498 */ 1499 struct dmub_rb_cmd_dp_hpd_notify { 1500 /** 1501 * Command header. 1502 */ 1503 struct dmub_cmd_header header; 1504 /** 1505 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1506 */ 1507 struct dp_hpd_data hpd_data; 1508 }; 1509 1510 /** 1511 * Definition of a SET_CONFIG reply from DPOA. 1512 */ 1513 enum set_config_status { 1514 SET_CONFIG_PENDING = 0, 1515 SET_CONFIG_ACK_RECEIVED, 1516 SET_CONFIG_RX_TIMEOUT, 1517 SET_CONFIG_UNKNOWN_ERROR, 1518 }; 1519 1520 /** 1521 * Definition of a set_config reply 1522 */ 1523 struct set_config_reply_control_data { 1524 uint8_t instance; /* DPIA Instance */ 1525 uint8_t status; /* Set Config reply */ 1526 uint16_t pad; /* Alignment */ 1527 }; 1528 1529 /** 1530 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1531 */ 1532 struct dmub_rb_cmd_dp_set_config_reply { 1533 struct dmub_cmd_header header; 1534 struct set_config_reply_control_data set_config_reply_control; 1535 }; 1536 1537 /** 1538 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1539 */ 1540 struct dmub_cmd_hpd_state_query_data { 1541 uint8_t instance; /**< HPD instance or DPIA instance */ 1542 uint8_t result; /**< For returning HPD state */ 1543 uint16_t pad; /** < Alignment */ 1544 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1545 enum aux_return_code_type status; /**< for returning the status of command */ 1546 }; 1547 1548 /** 1549 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1550 */ 1551 struct dmub_rb_cmd_query_hpd_state { 1552 /** 1553 * Command header. 1554 */ 1555 struct dmub_cmd_header header; 1556 /** 1557 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1558 */ 1559 struct dmub_cmd_hpd_state_query_data data; 1560 }; 1561 1562 /* 1563 * Command IDs should be treated as stable ABI. 1564 * Do not reuse or modify IDs. 1565 */ 1566 1567 /** 1568 * PSR command sub-types. 1569 */ 1570 enum dmub_cmd_psr_type { 1571 /** 1572 * Set PSR version support. 1573 */ 1574 DMUB_CMD__PSR_SET_VERSION = 0, 1575 /** 1576 * Copy driver-calculated parameters to PSR state. 1577 */ 1578 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1579 /** 1580 * Enable PSR. 1581 */ 1582 DMUB_CMD__PSR_ENABLE = 2, 1583 1584 /** 1585 * Disable PSR. 1586 */ 1587 DMUB_CMD__PSR_DISABLE = 3, 1588 1589 /** 1590 * Set PSR level. 1591 * PSR level is a 16-bit value dicated by driver that 1592 * will enable/disable different functionality. 1593 */ 1594 DMUB_CMD__PSR_SET_LEVEL = 4, 1595 1596 /** 1597 * Forces PSR enabled until an explicit PSR disable call. 1598 */ 1599 DMUB_CMD__PSR_FORCE_STATIC = 5, 1600 /** 1601 * Set vtotal in psr active for FreeSync PSR. 1602 */ 1603 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1604 /** 1605 * Set PSR power option 1606 */ 1607 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1608 }; 1609 1610 enum dmub_cmd_fams_type { 1611 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1612 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1613 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1614 /** 1615 * For SubVP set manual trigger in FW because it 1616 * triggers DRR_UPDATE_PENDING which SubVP relies 1617 * on (for any SubVP cases that use a DRR display) 1618 */ 1619 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1620 }; 1621 1622 /** 1623 * PSR versions. 1624 */ 1625 enum psr_version { 1626 /** 1627 * PSR version 1. 1628 */ 1629 PSR_VERSION_1 = 0, 1630 /** 1631 * Freesync PSR SU. 1632 */ 1633 PSR_VERSION_SU_1 = 1, 1634 /** 1635 * PSR not supported. 1636 */ 1637 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1638 }; 1639 1640 /** 1641 * enum dmub_cmd_mall_type - MALL commands 1642 */ 1643 enum dmub_cmd_mall_type { 1644 /** 1645 * Allows display refresh from MALL. 1646 */ 1647 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1648 /** 1649 * Disallows display refresh from MALL. 1650 */ 1651 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1652 /** 1653 * Cursor copy for MALL. 1654 */ 1655 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1656 /** 1657 * Controls DF requests. 1658 */ 1659 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1660 }; 1661 1662 /** 1663 * PHY Link rate for DP. 1664 */ 1665 enum phy_link_rate { 1666 /** 1667 * not supported. 1668 */ 1669 PHY_RATE_UNKNOWN = 0, 1670 /** 1671 * Rate_1 (RBR) - 1.62 Gbps/Lane 1672 */ 1673 PHY_RATE_162 = 1, 1674 /** 1675 * Rate_2 - 2.16 Gbps/Lane 1676 */ 1677 PHY_RATE_216 = 2, 1678 /** 1679 * Rate_3 - 2.43 Gbps/Lane 1680 */ 1681 PHY_RATE_243 = 3, 1682 /** 1683 * Rate_4 (HBR) - 2.70 Gbps/Lane 1684 */ 1685 PHY_RATE_270 = 4, 1686 /** 1687 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1688 */ 1689 PHY_RATE_324 = 5, 1690 /** 1691 * Rate_6 - 4.32 Gbps/Lane 1692 */ 1693 PHY_RATE_432 = 6, 1694 /** 1695 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1696 */ 1697 PHY_RATE_540 = 7, 1698 /** 1699 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1700 */ 1701 PHY_RATE_810 = 8, 1702 /** 1703 * UHBR10 - 10.0 Gbps/Lane 1704 */ 1705 PHY_RATE_1000 = 9, 1706 /** 1707 * UHBR13.5 - 13.5 Gbps/Lane 1708 */ 1709 PHY_RATE_1350 = 10, 1710 /** 1711 * UHBR10 - 20.0 Gbps/Lane 1712 */ 1713 PHY_RATE_2000 = 11, 1714 }; 1715 1716 /** 1717 * enum dmub_phy_fsm_state - PHY FSM states. 1718 * PHY FSM state to transit to during PSR enable/disable. 1719 */ 1720 enum dmub_phy_fsm_state { 1721 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1722 DMUB_PHY_FSM_RESET, 1723 DMUB_PHY_FSM_RESET_RELEASED, 1724 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1725 DMUB_PHY_FSM_INITIALIZED, 1726 DMUB_PHY_FSM_CALIBRATED, 1727 DMUB_PHY_FSM_CALIBRATED_LP, 1728 DMUB_PHY_FSM_CALIBRATED_PG, 1729 DMUB_PHY_FSM_POWER_DOWN, 1730 DMUB_PHY_FSM_PLL_EN, 1731 DMUB_PHY_FSM_TX_EN, 1732 DMUB_PHY_FSM_FAST_LP, 1733 }; 1734 1735 /** 1736 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1737 */ 1738 struct dmub_cmd_psr_copy_settings_data { 1739 /** 1740 * Flags that can be set by driver to change some PSR behaviour. 1741 */ 1742 union dmub_psr_debug_flags debug; 1743 /** 1744 * 16-bit value dicated by driver that will enable/disable different functionality. 1745 */ 1746 uint16_t psr_level; 1747 /** 1748 * DPP HW instance. 1749 */ 1750 uint8_t dpp_inst; 1751 /** 1752 * MPCC HW instance. 1753 * Not used in dmub fw, 1754 * dmub fw will get active opp by reading odm registers. 1755 */ 1756 uint8_t mpcc_inst; 1757 /** 1758 * OPP HW instance. 1759 * Not used in dmub fw, 1760 * dmub fw will get active opp by reading odm registers. 1761 */ 1762 uint8_t opp_inst; 1763 /** 1764 * OTG HW instance. 1765 */ 1766 uint8_t otg_inst; 1767 /** 1768 * DIG FE HW instance. 1769 */ 1770 uint8_t digfe_inst; 1771 /** 1772 * DIG BE HW instance. 1773 */ 1774 uint8_t digbe_inst; 1775 /** 1776 * DP PHY HW instance. 1777 */ 1778 uint8_t dpphy_inst; 1779 /** 1780 * AUX HW instance. 1781 */ 1782 uint8_t aux_inst; 1783 /** 1784 * Determines if SMU optimzations are enabled/disabled. 1785 */ 1786 uint8_t smu_optimizations_en; 1787 /** 1788 * Unused. 1789 * TODO: Remove. 1790 */ 1791 uint8_t frame_delay; 1792 /** 1793 * If RFB setup time is greater than the total VBLANK time, 1794 * it is not possible for the sink to capture the video frame 1795 * in the same frame the SDP is sent. In this case, 1796 * the frame capture indication bit should be set and an extra 1797 * static frame should be transmitted to the sink. 1798 */ 1799 uint8_t frame_cap_ind; 1800 /** 1801 * Granularity of Y offset supported by sink. 1802 */ 1803 uint8_t su_y_granularity; 1804 /** 1805 * Indicates whether sink should start capturing 1806 * immediately following active scan line, 1807 * or starting with the 2nd active scan line. 1808 */ 1809 uint8_t line_capture_indication; 1810 /** 1811 * Multi-display optimizations are implemented on certain ASICs. 1812 */ 1813 uint8_t multi_disp_optimizations_en; 1814 /** 1815 * The last possible line SDP may be transmitted without violating 1816 * the RFB setup time or entering the active video frame. 1817 */ 1818 uint16_t init_sdp_deadline; 1819 /** 1820 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1821 */ 1822 uint8_t rate_control_caps ; 1823 /* 1824 * Force PSRSU always doing full frame update 1825 */ 1826 uint8_t force_ffu_mode; 1827 /** 1828 * Length of each horizontal line in us. 1829 */ 1830 uint32_t line_time_in_us; 1831 /** 1832 * FEC enable status in driver 1833 */ 1834 uint8_t fec_enable_status; 1835 /** 1836 * FEC re-enable delay when PSR exit. 1837 * unit is 100us, range form 0~255(0xFF). 1838 */ 1839 uint8_t fec_enable_delay_in100us; 1840 /** 1841 * PSR control version. 1842 */ 1843 uint8_t cmd_version; 1844 /** 1845 * Panel Instance. 1846 * Panel isntance to identify which psr_state to use 1847 * Currently the support is only for 0 or 1 1848 */ 1849 uint8_t panel_inst; 1850 /* 1851 * DSC enable status in driver 1852 */ 1853 uint8_t dsc_enable_status; 1854 /* 1855 * Use FSM state for PSR power up/down 1856 */ 1857 uint8_t use_phy_fsm; 1858 /** 1859 * Explicit padding to 2 byte boundary. 1860 */ 1861 uint8_t pad3[2]; 1862 }; 1863 1864 /** 1865 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1866 */ 1867 struct dmub_rb_cmd_psr_copy_settings { 1868 /** 1869 * Command header. 1870 */ 1871 struct dmub_cmd_header header; 1872 /** 1873 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1874 */ 1875 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1876 }; 1877 1878 /** 1879 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1880 */ 1881 struct dmub_cmd_psr_set_level_data { 1882 /** 1883 * 16-bit value dicated by driver that will enable/disable different functionality. 1884 */ 1885 uint16_t psr_level; 1886 /** 1887 * PSR control version. 1888 */ 1889 uint8_t cmd_version; 1890 /** 1891 * Panel Instance. 1892 * Panel isntance to identify which psr_state to use 1893 * Currently the support is only for 0 or 1 1894 */ 1895 uint8_t panel_inst; 1896 }; 1897 1898 /** 1899 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1900 */ 1901 struct dmub_rb_cmd_psr_set_level { 1902 /** 1903 * Command header. 1904 */ 1905 struct dmub_cmd_header header; 1906 /** 1907 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1908 */ 1909 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1910 }; 1911 1912 struct dmub_rb_cmd_psr_enable_data { 1913 /** 1914 * PSR control version. 1915 */ 1916 uint8_t cmd_version; 1917 /** 1918 * Panel Instance. 1919 * Panel isntance to identify which psr_state to use 1920 * Currently the support is only for 0 or 1 1921 */ 1922 uint8_t panel_inst; 1923 /** 1924 * Phy state to enter. 1925 * Values to use are defined in dmub_phy_fsm_state 1926 */ 1927 uint8_t phy_fsm_state; 1928 /** 1929 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1930 * Set this using enum phy_link_rate. 1931 * This does not support HDMI/DP2 for now. 1932 */ 1933 uint8_t phy_rate; 1934 }; 1935 1936 /** 1937 * Definition of a DMUB_CMD__PSR_ENABLE command. 1938 * PSR enable/disable is controlled using the sub_type. 1939 */ 1940 struct dmub_rb_cmd_psr_enable { 1941 /** 1942 * Command header. 1943 */ 1944 struct dmub_cmd_header header; 1945 1946 struct dmub_rb_cmd_psr_enable_data data; 1947 }; 1948 1949 /** 1950 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1951 */ 1952 struct dmub_cmd_psr_set_version_data { 1953 /** 1954 * PSR version that FW should implement. 1955 */ 1956 enum psr_version version; 1957 /** 1958 * PSR control version. 1959 */ 1960 uint8_t cmd_version; 1961 /** 1962 * Panel Instance. 1963 * Panel isntance to identify which psr_state to use 1964 * Currently the support is only for 0 or 1 1965 */ 1966 uint8_t panel_inst; 1967 /** 1968 * Explicit padding to 4 byte boundary. 1969 */ 1970 uint8_t pad[2]; 1971 }; 1972 1973 /** 1974 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 1975 */ 1976 struct dmub_rb_cmd_psr_set_version { 1977 /** 1978 * Command header. 1979 */ 1980 struct dmub_cmd_header header; 1981 /** 1982 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1983 */ 1984 struct dmub_cmd_psr_set_version_data psr_set_version_data; 1985 }; 1986 1987 struct dmub_cmd_psr_force_static_data { 1988 /** 1989 * PSR control version. 1990 */ 1991 uint8_t cmd_version; 1992 /** 1993 * Panel Instance. 1994 * Panel isntance to identify which psr_state to use 1995 * Currently the support is only for 0 or 1 1996 */ 1997 uint8_t panel_inst; 1998 /** 1999 * Explicit padding to 4 byte boundary. 2000 */ 2001 uint8_t pad[2]; 2002 }; 2003 2004 /** 2005 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2006 */ 2007 struct dmub_rb_cmd_psr_force_static { 2008 /** 2009 * Command header. 2010 */ 2011 struct dmub_cmd_header header; 2012 /** 2013 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2014 */ 2015 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2016 }; 2017 2018 /** 2019 * PSR SU debug flags. 2020 */ 2021 union dmub_psr_su_debug_flags { 2022 /** 2023 * PSR SU debug flags. 2024 */ 2025 struct { 2026 /** 2027 * Update dirty rect in SW only. 2028 */ 2029 uint8_t update_dirty_rect_only : 1; 2030 /** 2031 * Reset the cursor/plane state before processing the call. 2032 */ 2033 uint8_t reset_state : 1; 2034 } bitfields; 2035 2036 /** 2037 * Union for debug flags. 2038 */ 2039 uint32_t u32All; 2040 }; 2041 2042 /** 2043 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2044 * This triggers a selective update for PSR SU. 2045 */ 2046 struct dmub_cmd_update_dirty_rect_data { 2047 /** 2048 * Dirty rects from OS. 2049 */ 2050 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2051 /** 2052 * PSR SU debug flags. 2053 */ 2054 union dmub_psr_su_debug_flags debug_flags; 2055 /** 2056 * OTG HW instance. 2057 */ 2058 uint8_t pipe_idx; 2059 /** 2060 * Number of dirty rects. 2061 */ 2062 uint8_t dirty_rect_count; 2063 /** 2064 * PSR control version. 2065 */ 2066 uint8_t cmd_version; 2067 /** 2068 * Panel Instance. 2069 * Panel isntance to identify which psr_state to use 2070 * Currently the support is only for 0 or 1 2071 */ 2072 uint8_t panel_inst; 2073 }; 2074 2075 /** 2076 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2077 */ 2078 struct dmub_rb_cmd_update_dirty_rect { 2079 /** 2080 * Command header. 2081 */ 2082 struct dmub_cmd_header header; 2083 /** 2084 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2085 */ 2086 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2087 }; 2088 2089 /** 2090 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2091 */ 2092 struct dmub_cmd_update_cursor_info_data { 2093 /** 2094 * Cursor dirty rects. 2095 */ 2096 struct dmub_rect cursor_rect; 2097 /** 2098 * PSR SU debug flags. 2099 */ 2100 union dmub_psr_su_debug_flags debug_flags; 2101 /** 2102 * Cursor enable/disable. 2103 */ 2104 uint8_t enable; 2105 /** 2106 * OTG HW instance. 2107 */ 2108 uint8_t pipe_idx; 2109 /** 2110 * PSR control version. 2111 */ 2112 uint8_t cmd_version; 2113 /** 2114 * Panel Instance. 2115 * Panel isntance to identify which psr_state to use 2116 * Currently the support is only for 0 or 1 2117 */ 2118 uint8_t panel_inst; 2119 }; 2120 /** 2121 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2122 */ 2123 struct dmub_rb_cmd_update_cursor_info { 2124 /** 2125 * Command header. 2126 */ 2127 struct dmub_cmd_header header; 2128 /** 2129 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2130 */ 2131 struct dmub_cmd_update_cursor_info_data update_cursor_info_data; 2132 }; 2133 2134 /** 2135 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2136 */ 2137 struct dmub_cmd_psr_set_vtotal_data { 2138 /** 2139 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2140 */ 2141 uint16_t psr_vtotal_idle; 2142 /** 2143 * PSR control version. 2144 */ 2145 uint8_t cmd_version; 2146 /** 2147 * Panel Instance. 2148 * Panel isntance to identify which psr_state to use 2149 * Currently the support is only for 0 or 1 2150 */ 2151 uint8_t panel_inst; 2152 /* 2153 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2154 */ 2155 uint16_t psr_vtotal_su; 2156 /** 2157 * Explicit padding to 4 byte boundary. 2158 */ 2159 uint8_t pad2[2]; 2160 }; 2161 2162 /** 2163 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2164 */ 2165 struct dmub_rb_cmd_psr_set_vtotal { 2166 /** 2167 * Command header. 2168 */ 2169 struct dmub_cmd_header header; 2170 /** 2171 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2172 */ 2173 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2174 }; 2175 2176 /** 2177 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2178 */ 2179 struct dmub_cmd_psr_set_power_opt_data { 2180 /** 2181 * PSR control version. 2182 */ 2183 uint8_t cmd_version; 2184 /** 2185 * Panel Instance. 2186 * Panel isntance to identify which psr_state to use 2187 * Currently the support is only for 0 or 1 2188 */ 2189 uint8_t panel_inst; 2190 /** 2191 * Explicit padding to 4 byte boundary. 2192 */ 2193 uint8_t pad[2]; 2194 /** 2195 * PSR power option 2196 */ 2197 uint32_t power_opt; 2198 }; 2199 2200 /** 2201 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2202 */ 2203 struct dmub_rb_cmd_psr_set_power_opt { 2204 /** 2205 * Command header. 2206 */ 2207 struct dmub_cmd_header header; 2208 /** 2209 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2210 */ 2211 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2212 }; 2213 2214 /** 2215 * Set of HW components that can be locked. 2216 * 2217 * Note: If updating with more HW components, fields 2218 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2219 */ 2220 union dmub_hw_lock_flags { 2221 /** 2222 * Set of HW components that can be locked. 2223 */ 2224 struct { 2225 /** 2226 * Lock/unlock OTG master update lock. 2227 */ 2228 uint8_t lock_pipe : 1; 2229 /** 2230 * Lock/unlock cursor. 2231 */ 2232 uint8_t lock_cursor : 1; 2233 /** 2234 * Lock/unlock global update lock. 2235 */ 2236 uint8_t lock_dig : 1; 2237 /** 2238 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2239 */ 2240 uint8_t triple_buffer_lock : 1; 2241 } bits; 2242 2243 /** 2244 * Union for HW Lock flags. 2245 */ 2246 uint8_t u8All; 2247 }; 2248 2249 /** 2250 * Instances of HW to be locked. 2251 * 2252 * Note: If updating with more HW components, fields 2253 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2254 */ 2255 struct dmub_hw_lock_inst_flags { 2256 /** 2257 * OTG HW instance for OTG master update lock. 2258 */ 2259 uint8_t otg_inst; 2260 /** 2261 * OPP instance for cursor lock. 2262 */ 2263 uint8_t opp_inst; 2264 /** 2265 * OTG HW instance for global update lock. 2266 * TODO: Remove, and re-use otg_inst. 2267 */ 2268 uint8_t dig_inst; 2269 /** 2270 * Explicit pad to 4 byte boundary. 2271 */ 2272 uint8_t pad; 2273 }; 2274 2275 /** 2276 * Clients that can acquire the HW Lock Manager. 2277 * 2278 * Note: If updating with more clients, fields in 2279 * dmub_inbox0_cmd_lock_hw must be updated to match. 2280 */ 2281 enum hw_lock_client { 2282 /** 2283 * Driver is the client of HW Lock Manager. 2284 */ 2285 HW_LOCK_CLIENT_DRIVER = 0, 2286 /** 2287 * PSR SU is the client of HW Lock Manager. 2288 */ 2289 HW_LOCK_CLIENT_PSR_SU = 1, 2290 /** 2291 * Invalid client. 2292 */ 2293 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2294 }; 2295 2296 /** 2297 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2298 */ 2299 struct dmub_cmd_lock_hw_data { 2300 /** 2301 * Specifies the client accessing HW Lock Manager. 2302 */ 2303 enum hw_lock_client client; 2304 /** 2305 * HW instances to be locked. 2306 */ 2307 struct dmub_hw_lock_inst_flags inst_flags; 2308 /** 2309 * Which components to be locked. 2310 */ 2311 union dmub_hw_lock_flags hw_locks; 2312 /** 2313 * Specifies lock/unlock. 2314 */ 2315 uint8_t lock; 2316 /** 2317 * HW can be unlocked separately from releasing the HW Lock Mgr. 2318 * This flag is set if the client wishes to release the object. 2319 */ 2320 uint8_t should_release; 2321 /** 2322 * Explicit padding to 4 byte boundary. 2323 */ 2324 uint8_t pad; 2325 }; 2326 2327 /** 2328 * Definition of a DMUB_CMD__HW_LOCK command. 2329 * Command is used by driver and FW. 2330 */ 2331 struct dmub_rb_cmd_lock_hw { 2332 /** 2333 * Command header. 2334 */ 2335 struct dmub_cmd_header header; 2336 /** 2337 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2338 */ 2339 struct dmub_cmd_lock_hw_data lock_hw_data; 2340 }; 2341 2342 /** 2343 * ABM command sub-types. 2344 */ 2345 enum dmub_cmd_abm_type { 2346 /** 2347 * Initialize parameters for ABM algorithm. 2348 * Data is passed through an indirect buffer. 2349 */ 2350 DMUB_CMD__ABM_INIT_CONFIG = 0, 2351 /** 2352 * Set OTG and panel HW instance. 2353 */ 2354 DMUB_CMD__ABM_SET_PIPE = 1, 2355 /** 2356 * Set user requested backklight level. 2357 */ 2358 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2359 /** 2360 * Set ABM operating/aggression level. 2361 */ 2362 DMUB_CMD__ABM_SET_LEVEL = 3, 2363 /** 2364 * Set ambient light level. 2365 */ 2366 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2367 /** 2368 * Enable/disable fractional duty cycle for backlight PWM. 2369 */ 2370 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2371 2372 /** 2373 * unregister vertical interrupt after steady state is reached 2374 */ 2375 DMUB_CMD__ABM_PAUSE = 6, 2376 }; 2377 2378 /** 2379 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2380 * Requirements: 2381 * - Padded explicitly to 32-bit boundary. 2382 * - Must ensure this structure matches the one on driver-side, 2383 * otherwise it won't be aligned. 2384 */ 2385 struct abm_config_table { 2386 /** 2387 * Gamma curve thresholds, used for crgb conversion. 2388 */ 2389 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2390 /** 2391 * Gamma curve offsets, used for crgb conversion. 2392 */ 2393 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2394 /** 2395 * Gamma curve slopes, used for crgb conversion. 2396 */ 2397 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2398 /** 2399 * Custom backlight curve thresholds. 2400 */ 2401 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2402 /** 2403 * Custom backlight curve offsets. 2404 */ 2405 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2406 /** 2407 * Ambient light thresholds. 2408 */ 2409 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2410 /** 2411 * Minimum programmable backlight. 2412 */ 2413 uint16_t min_abm_backlight; // 122B 2414 /** 2415 * Minimum reduction values. 2416 */ 2417 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2418 /** 2419 * Maximum reduction values. 2420 */ 2421 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2422 /** 2423 * Bright positive gain. 2424 */ 2425 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2426 /** 2427 * Dark negative gain. 2428 */ 2429 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2430 /** 2431 * Hybrid factor. 2432 */ 2433 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2434 /** 2435 * Contrast factor. 2436 */ 2437 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2438 /** 2439 * Deviation gain. 2440 */ 2441 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2442 /** 2443 * Minimum knee. 2444 */ 2445 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2446 /** 2447 * Maximum knee. 2448 */ 2449 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2450 /** 2451 * Unused. 2452 */ 2453 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2454 /** 2455 * Explicit padding to 4 byte boundary. 2456 */ 2457 uint8_t pad3[3]; // 229B 2458 /** 2459 * Backlight ramp reduction. 2460 */ 2461 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2462 /** 2463 * Backlight ramp start. 2464 */ 2465 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2466 }; 2467 2468 /** 2469 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2470 */ 2471 struct dmub_cmd_abm_set_pipe_data { 2472 /** 2473 * OTG HW instance. 2474 */ 2475 uint8_t otg_inst; 2476 2477 /** 2478 * Panel Control HW instance. 2479 */ 2480 uint8_t panel_inst; 2481 2482 /** 2483 * Controls how ABM will interpret a set pipe or set level command. 2484 */ 2485 uint8_t set_pipe_option; 2486 2487 /** 2488 * Unused. 2489 * TODO: Remove. 2490 */ 2491 uint8_t ramping_boundary; 2492 }; 2493 2494 /** 2495 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2496 */ 2497 struct dmub_rb_cmd_abm_set_pipe { 2498 /** 2499 * Command header. 2500 */ 2501 struct dmub_cmd_header header; 2502 2503 /** 2504 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2505 */ 2506 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2507 }; 2508 2509 /** 2510 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2511 */ 2512 struct dmub_cmd_abm_set_backlight_data { 2513 /** 2514 * Number of frames to ramp to backlight user level. 2515 */ 2516 uint32_t frame_ramp; 2517 2518 /** 2519 * Requested backlight level from user. 2520 */ 2521 uint32_t backlight_user_level; 2522 2523 /** 2524 * ABM control version. 2525 */ 2526 uint8_t version; 2527 2528 /** 2529 * Panel Control HW instance mask. 2530 * Bit 0 is Panel Control HW instance 0. 2531 * Bit 1 is Panel Control HW instance 1. 2532 */ 2533 uint8_t panel_mask; 2534 2535 /** 2536 * Explicit padding to 4 byte boundary. 2537 */ 2538 uint8_t pad[2]; 2539 }; 2540 2541 /** 2542 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2543 */ 2544 struct dmub_rb_cmd_abm_set_backlight { 2545 /** 2546 * Command header. 2547 */ 2548 struct dmub_cmd_header header; 2549 2550 /** 2551 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2552 */ 2553 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2554 }; 2555 2556 /** 2557 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2558 */ 2559 struct dmub_cmd_abm_set_level_data { 2560 /** 2561 * Set current ABM operating/aggression level. 2562 */ 2563 uint32_t level; 2564 2565 /** 2566 * ABM control version. 2567 */ 2568 uint8_t version; 2569 2570 /** 2571 * Panel Control HW instance mask. 2572 * Bit 0 is Panel Control HW instance 0. 2573 * Bit 1 is Panel Control HW instance 1. 2574 */ 2575 uint8_t panel_mask; 2576 2577 /** 2578 * Explicit padding to 4 byte boundary. 2579 */ 2580 uint8_t pad[2]; 2581 }; 2582 2583 /** 2584 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2585 */ 2586 struct dmub_rb_cmd_abm_set_level { 2587 /** 2588 * Command header. 2589 */ 2590 struct dmub_cmd_header header; 2591 2592 /** 2593 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2594 */ 2595 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2596 }; 2597 2598 /** 2599 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2600 */ 2601 struct dmub_cmd_abm_set_ambient_level_data { 2602 /** 2603 * Ambient light sensor reading from OS. 2604 */ 2605 uint32_t ambient_lux; 2606 2607 /** 2608 * ABM control version. 2609 */ 2610 uint8_t version; 2611 2612 /** 2613 * Panel Control HW instance mask. 2614 * Bit 0 is Panel Control HW instance 0. 2615 * Bit 1 is Panel Control HW instance 1. 2616 */ 2617 uint8_t panel_mask; 2618 2619 /** 2620 * Explicit padding to 4 byte boundary. 2621 */ 2622 uint8_t pad[2]; 2623 }; 2624 2625 /** 2626 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2627 */ 2628 struct dmub_rb_cmd_abm_set_ambient_level { 2629 /** 2630 * Command header. 2631 */ 2632 struct dmub_cmd_header header; 2633 2634 /** 2635 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2636 */ 2637 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2638 }; 2639 2640 /** 2641 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2642 */ 2643 struct dmub_cmd_abm_set_pwm_frac_data { 2644 /** 2645 * Enable/disable fractional duty cycle for backlight PWM. 2646 * TODO: Convert to uint8_t. 2647 */ 2648 uint32_t fractional_pwm; 2649 2650 /** 2651 * ABM control version. 2652 */ 2653 uint8_t version; 2654 2655 /** 2656 * Panel Control HW instance mask. 2657 * Bit 0 is Panel Control HW instance 0. 2658 * Bit 1 is Panel Control HW instance 1. 2659 */ 2660 uint8_t panel_mask; 2661 2662 /** 2663 * Explicit padding to 4 byte boundary. 2664 */ 2665 uint8_t pad[2]; 2666 }; 2667 2668 /** 2669 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2670 */ 2671 struct dmub_rb_cmd_abm_set_pwm_frac { 2672 /** 2673 * Command header. 2674 */ 2675 struct dmub_cmd_header header; 2676 2677 /** 2678 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2679 */ 2680 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2681 }; 2682 2683 /** 2684 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2685 */ 2686 struct dmub_cmd_abm_init_config_data { 2687 /** 2688 * Location of indirect buffer used to pass init data to ABM. 2689 */ 2690 union dmub_addr src; 2691 2692 /** 2693 * Indirect buffer length. 2694 */ 2695 uint16_t bytes; 2696 2697 2698 /** 2699 * ABM control version. 2700 */ 2701 uint8_t version; 2702 2703 /** 2704 * Panel Control HW instance mask. 2705 * Bit 0 is Panel Control HW instance 0. 2706 * Bit 1 is Panel Control HW instance 1. 2707 */ 2708 uint8_t panel_mask; 2709 2710 /** 2711 * Explicit padding to 4 byte boundary. 2712 */ 2713 uint8_t pad[2]; 2714 }; 2715 2716 /** 2717 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2718 */ 2719 struct dmub_rb_cmd_abm_init_config { 2720 /** 2721 * Command header. 2722 */ 2723 struct dmub_cmd_header header; 2724 2725 /** 2726 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2727 */ 2728 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2729 }; 2730 2731 /** 2732 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2733 */ 2734 2735 struct dmub_cmd_abm_pause_data { 2736 2737 /** 2738 * Panel Control HW instance mask. 2739 * Bit 0 is Panel Control HW instance 0. 2740 * Bit 1 is Panel Control HW instance 1. 2741 */ 2742 uint8_t panel_mask; 2743 2744 /** 2745 * OTG hw instance 2746 */ 2747 uint8_t otg_inst; 2748 2749 /** 2750 * Enable or disable ABM pause 2751 */ 2752 uint8_t enable; 2753 2754 /** 2755 * Explicit padding to 4 byte boundary. 2756 */ 2757 uint8_t pad[1]; 2758 }; 2759 2760 /** 2761 * Definition of a DMUB_CMD__ABM_PAUSE command. 2762 */ 2763 struct dmub_rb_cmd_abm_pause { 2764 /** 2765 * Command header. 2766 */ 2767 struct dmub_cmd_header header; 2768 2769 /** 2770 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2771 */ 2772 struct dmub_cmd_abm_pause_data abm_pause_data; 2773 }; 2774 2775 /** 2776 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2777 */ 2778 struct dmub_cmd_query_feature_caps_data { 2779 /** 2780 * DMUB feature capabilities. 2781 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2782 */ 2783 struct dmub_feature_caps feature_caps; 2784 }; 2785 2786 /** 2787 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2788 */ 2789 struct dmub_rb_cmd_query_feature_caps { 2790 /** 2791 * Command header. 2792 */ 2793 struct dmub_cmd_header header; 2794 /** 2795 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2796 */ 2797 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2798 }; 2799 2800 /** 2801 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2802 */ 2803 struct dmub_cmd_visual_confirm_color_data { 2804 /** 2805 * DMUB feature capabilities. 2806 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2807 */ 2808 struct dmub_visual_confirm_color visual_confirm_color; 2809 }; 2810 2811 /** 2812 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2813 */ 2814 struct dmub_rb_cmd_get_visual_confirm_color { 2815 /** 2816 * Command header. 2817 */ 2818 struct dmub_cmd_header header; 2819 /** 2820 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2821 */ 2822 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2823 }; 2824 2825 struct dmub_optc_state { 2826 uint32_t v_total_max; 2827 uint32_t v_total_min; 2828 uint32_t v_total_mid; 2829 uint32_t v_total_mid_frame_num; 2830 uint32_t tg_inst; 2831 uint32_t enable_manual_trigger; 2832 uint32_t clear_force_vsync; 2833 }; 2834 2835 struct dmub_rb_cmd_drr_update { 2836 struct dmub_cmd_header header; 2837 struct dmub_optc_state dmub_optc_state_req; 2838 }; 2839 2840 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2841 uint32_t pix_clk_100hz; 2842 uint8_t max_ramp_step; 2843 uint8_t pipes; 2844 uint8_t min_refresh_in_hz; 2845 uint8_t padding[1]; 2846 }; 2847 2848 struct dmub_cmd_fw_assisted_mclk_switch_config { 2849 uint8_t fams_enabled; 2850 uint8_t visual_confirm_enabled; 2851 uint8_t padding[2]; 2852 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2853 }; 2854 2855 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2856 struct dmub_cmd_header header; 2857 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2858 }; 2859 2860 /** 2861 * enum dmub_cmd_panel_cntl_type - Panel control command. 2862 */ 2863 enum dmub_cmd_panel_cntl_type { 2864 /** 2865 * Initializes embedded panel hardware blocks. 2866 */ 2867 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2868 /** 2869 * Queries backlight info for the embedded panel. 2870 */ 2871 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2872 }; 2873 2874 /** 2875 * struct dmub_cmd_panel_cntl_data - Panel control data. 2876 */ 2877 struct dmub_cmd_panel_cntl_data { 2878 uint32_t inst; /**< panel instance */ 2879 uint32_t current_backlight; /* in/out */ 2880 uint32_t bl_pwm_cntl; /* in/out */ 2881 uint32_t bl_pwm_period_cntl; /* in/out */ 2882 uint32_t bl_pwm_ref_div1; /* in/out */ 2883 uint8_t is_backlight_on : 1; /* in/out */ 2884 uint8_t is_powered_on : 1; /* in/out */ 2885 uint8_t padding[3]; 2886 uint32_t bl_pwm_ref_div2; /* in/out */ 2887 uint8_t reserved[4]; 2888 }; 2889 2890 /** 2891 * struct dmub_rb_cmd_panel_cntl - Panel control command. 2892 */ 2893 struct dmub_rb_cmd_panel_cntl { 2894 struct dmub_cmd_header header; /**< header */ 2895 struct dmub_cmd_panel_cntl_data data; /**< payload */ 2896 }; 2897 2898 /** 2899 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2900 */ 2901 struct dmub_cmd_lvtma_control_data { 2902 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 2903 uint8_t reserved_0[3]; /**< For future use */ 2904 uint8_t panel_inst; /**< LVTMA control instance */ 2905 uint8_t reserved_1[3]; /**< For future use */ 2906 }; 2907 2908 /** 2909 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2910 */ 2911 struct dmub_rb_cmd_lvtma_control { 2912 /** 2913 * Command header. 2914 */ 2915 struct dmub_cmd_header header; 2916 /** 2917 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 2918 */ 2919 struct dmub_cmd_lvtma_control_data data; 2920 }; 2921 2922 /** 2923 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2924 */ 2925 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 2926 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2927 uint8_t is_usb; /**< is phy is usb */ 2928 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 2929 uint8_t is_dp4; /**< is dp in 4 lane */ 2930 }; 2931 2932 /** 2933 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 2934 */ 2935 struct dmub_rb_cmd_transmitter_query_dp_alt { 2936 struct dmub_cmd_header header; /**< header */ 2937 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 2938 }; 2939 2940 /** 2941 * Maximum number of bytes a chunk sent to DMUB for parsing 2942 */ 2943 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 2944 2945 /** 2946 * Represent a chunk of CEA blocks sent to DMUB for parsing 2947 */ 2948 struct dmub_cmd_send_edid_cea { 2949 uint16_t offset; /**< offset into the CEA block */ 2950 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 2951 uint16_t cea_total_length; /**< total length of the CEA block */ 2952 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 2953 uint8_t pad[3]; /**< padding and for future expansion */ 2954 }; 2955 2956 /** 2957 * Result of VSDB parsing from CEA block 2958 */ 2959 struct dmub_cmd_edid_cea_amd_vsdb { 2960 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 2961 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 2962 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 2963 uint16_t min_frame_rate; /**< Maximum frame rate */ 2964 uint16_t max_frame_rate; /**< Minimum frame rate */ 2965 }; 2966 2967 /** 2968 * Result of sending a CEA chunk 2969 */ 2970 struct dmub_cmd_edid_cea_ack { 2971 uint16_t offset; /**< offset of the chunk into the CEA block */ 2972 uint8_t success; /**< 1 if this sending of chunk succeeded */ 2973 uint8_t pad; /**< padding and for future expansion */ 2974 }; 2975 2976 /** 2977 * Specify whether the result is an ACK/NACK or the parsing has finished 2978 */ 2979 enum dmub_cmd_edid_cea_reply_type { 2980 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 2981 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 2982 }; 2983 2984 /** 2985 * Definition of a DMUB_CMD__EDID_CEA command. 2986 */ 2987 struct dmub_rb_cmd_edid_cea { 2988 struct dmub_cmd_header header; /**< Command header */ 2989 union dmub_cmd_edid_cea_data { 2990 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 2991 struct dmub_cmd_edid_cea_output { /**< output with results */ 2992 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 2993 union { 2994 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 2995 struct dmub_cmd_edid_cea_ack ack; 2996 }; 2997 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 2998 } data; /**< Command data */ 2999 3000 }; 3001 3002 /** 3003 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3004 */ 3005 struct dmub_cmd_cable_id_input { 3006 uint8_t phy_inst; /**< phy inst for cable id data */ 3007 }; 3008 3009 /** 3010 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3011 */ 3012 struct dmub_cmd_cable_id_output { 3013 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3014 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3015 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3016 uint8_t RESERVED :2; /**< reserved means not defined */ 3017 }; 3018 3019 /** 3020 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3021 */ 3022 struct dmub_rb_cmd_get_usbc_cable_id { 3023 struct dmub_cmd_header header; /**< Command header */ 3024 /** 3025 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3026 */ 3027 union dmub_cmd_cable_id_data { 3028 struct dmub_cmd_cable_id_input input; /**< Input */ 3029 struct dmub_cmd_cable_id_output output; /**< Output */ 3030 uint8_t output_raw; /**< Raw data output */ 3031 } data; 3032 }; 3033 3034 /** 3035 * union dmub_rb_cmd - DMUB inbox command. 3036 */ 3037 union dmub_rb_cmd { 3038 /** 3039 * Elements shared with all commands. 3040 */ 3041 struct dmub_rb_cmd_common cmd_common; 3042 /** 3043 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3044 */ 3045 struct dmub_rb_cmd_read_modify_write read_modify_write; 3046 /** 3047 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3048 */ 3049 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3050 /** 3051 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3052 */ 3053 struct dmub_rb_cmd_burst_write burst_write; 3054 /** 3055 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3056 */ 3057 struct dmub_rb_cmd_reg_wait reg_wait; 3058 /** 3059 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3060 */ 3061 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3062 /** 3063 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3064 */ 3065 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3066 /** 3067 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3068 */ 3069 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3070 /** 3071 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3072 */ 3073 struct dmub_rb_cmd_dpphy_init dpphy_init; 3074 /** 3075 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3076 */ 3077 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3078 /** 3079 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3080 */ 3081 struct dmub_rb_cmd_psr_set_version psr_set_version; 3082 /** 3083 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3084 */ 3085 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3086 /** 3087 * Definition of a DMUB_CMD__PSR_ENABLE command. 3088 */ 3089 struct dmub_rb_cmd_psr_enable psr_enable; 3090 /** 3091 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3092 */ 3093 struct dmub_rb_cmd_psr_set_level psr_set_level; 3094 /** 3095 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3096 */ 3097 struct dmub_rb_cmd_psr_force_static psr_force_static; 3098 /** 3099 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3100 */ 3101 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3102 /** 3103 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3104 */ 3105 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3106 /** 3107 * Definition of a DMUB_CMD__HW_LOCK command. 3108 * Command is used by driver and FW. 3109 */ 3110 struct dmub_rb_cmd_lock_hw lock_hw; 3111 /** 3112 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3113 */ 3114 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3115 /** 3116 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3117 */ 3118 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3119 /** 3120 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3121 */ 3122 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3123 /** 3124 * Definition of a DMUB_CMD__MALL command. 3125 */ 3126 struct dmub_rb_cmd_mall mall; 3127 /** 3128 * Definition of a DMUB_CMD__CAB command. 3129 */ 3130 struct dmub_rb_cmd_cab_for_ss cab; 3131 3132 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3133 3134 /** 3135 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3136 */ 3137 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3138 3139 /** 3140 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3141 */ 3142 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3143 3144 /** 3145 * Definition of DMUB_CMD__PANEL_CNTL commands. 3146 */ 3147 struct dmub_rb_cmd_panel_cntl panel_cntl; 3148 /** 3149 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3150 */ 3151 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3152 3153 /** 3154 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3155 */ 3156 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3157 3158 /** 3159 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3160 */ 3161 struct dmub_rb_cmd_abm_set_level abm_set_level; 3162 3163 /** 3164 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3165 */ 3166 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3167 3168 /** 3169 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3170 */ 3171 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3172 3173 /** 3174 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3175 */ 3176 struct dmub_rb_cmd_abm_init_config abm_init_config; 3177 3178 /** 3179 * Definition of a DMUB_CMD__ABM_PAUSE command. 3180 */ 3181 struct dmub_rb_cmd_abm_pause abm_pause; 3182 3183 /** 3184 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3185 */ 3186 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3187 3188 /** 3189 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3190 */ 3191 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3192 3193 /** 3194 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3195 */ 3196 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3197 3198 /** 3199 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3200 */ 3201 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3202 struct dmub_rb_cmd_drr_update drr_update; 3203 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3204 3205 /** 3206 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3207 */ 3208 struct dmub_rb_cmd_lvtma_control lvtma_control; 3209 /** 3210 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3211 */ 3212 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3213 /** 3214 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3215 */ 3216 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3217 /** 3218 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3219 */ 3220 struct dmub_rb_cmd_set_config_access set_config_access; 3221 /** 3222 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3223 */ 3224 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3225 /** 3226 * Definition of a DMUB_CMD__EDID_CEA command. 3227 */ 3228 struct dmub_rb_cmd_edid_cea edid_cea; 3229 /** 3230 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3231 */ 3232 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3233 3234 /** 3235 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3236 */ 3237 struct dmub_rb_cmd_query_hpd_state query_hpd; 3238 }; 3239 3240 /** 3241 * union dmub_rb_out_cmd - Outbox command 3242 */ 3243 union dmub_rb_out_cmd { 3244 /** 3245 * Parameters common to every command. 3246 */ 3247 struct dmub_rb_cmd_common cmd_common; 3248 /** 3249 * AUX reply command. 3250 */ 3251 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3252 /** 3253 * HPD notify command. 3254 */ 3255 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3256 /** 3257 * SET_CONFIG reply command. 3258 */ 3259 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3260 }; 3261 #pragma pack(pop) 3262 3263 3264 //============================================================================== 3265 //</DMUB_CMD>=================================================================== 3266 //============================================================================== 3267 //< DMUB_RB>==================================================================== 3268 //============================================================================== 3269 3270 #if defined(__cplusplus) 3271 extern "C" { 3272 #endif 3273 3274 /** 3275 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3276 */ 3277 struct dmub_rb_init_params { 3278 void *ctx; /**< Caller provided context pointer */ 3279 void *base_address; /**< CPU base address for ring's data */ 3280 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3281 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3282 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3283 }; 3284 3285 /** 3286 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3287 */ 3288 struct dmub_rb { 3289 void *base_address; /**< CPU address for the ring's data */ 3290 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3291 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3292 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3293 3294 void *ctx; /**< Caller provided context pointer */ 3295 void *dmub; /**< Pointer to the DMUB interface */ 3296 }; 3297 3298 /** 3299 * @brief Checks if the ringbuffer is empty. 3300 * 3301 * @param rb DMUB Ringbuffer 3302 * @return true if empty 3303 * @return false otherwise 3304 */ 3305 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3306 { 3307 return (rb->wrpt == rb->rptr); 3308 } 3309 3310 /** 3311 * @brief Checks if the ringbuffer is full 3312 * 3313 * @param rb DMUB Ringbuffer 3314 * @return true if full 3315 * @return false otherwise 3316 */ 3317 static inline bool dmub_rb_full(struct dmub_rb *rb) 3318 { 3319 uint32_t data_count; 3320 3321 if (rb->wrpt >= rb->rptr) 3322 data_count = rb->wrpt - rb->rptr; 3323 else 3324 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3325 3326 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3327 } 3328 3329 /** 3330 * @brief Pushes a command into the ringbuffer 3331 * 3332 * @param rb DMUB ringbuffer 3333 * @param cmd The command to push 3334 * @return true if the ringbuffer was not full 3335 * @return false otherwise 3336 */ 3337 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3338 const union dmub_rb_cmd *cmd) 3339 { 3340 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3341 const uint64_t *src = (const uint64_t *)cmd; 3342 uint8_t i; 3343 3344 if (dmub_rb_full(rb)) 3345 return false; 3346 3347 // copying data 3348 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3349 *dst++ = *src++; 3350 3351 rb->wrpt += DMUB_RB_CMD_SIZE; 3352 3353 if (rb->wrpt >= rb->capacity) 3354 rb->wrpt %= rb->capacity; 3355 3356 return true; 3357 } 3358 3359 /** 3360 * @brief Pushes a command into the DMUB outbox ringbuffer 3361 * 3362 * @param rb DMUB outbox ringbuffer 3363 * @param cmd Outbox command 3364 * @return true if not full 3365 * @return false otherwise 3366 */ 3367 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3368 const union dmub_rb_out_cmd *cmd) 3369 { 3370 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3371 const uint8_t *src = (const uint8_t *)cmd; 3372 3373 if (dmub_rb_full(rb)) 3374 return false; 3375 3376 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3377 3378 rb->wrpt += DMUB_RB_CMD_SIZE; 3379 3380 if (rb->wrpt >= rb->capacity) 3381 rb->wrpt %= rb->capacity; 3382 3383 return true; 3384 } 3385 3386 /** 3387 * @brief Returns the next unprocessed command in the ringbuffer. 3388 * 3389 * @param rb DMUB ringbuffer 3390 * @param cmd The command to return 3391 * @return true if not empty 3392 * @return false otherwise 3393 */ 3394 static inline bool dmub_rb_front(struct dmub_rb *rb, 3395 union dmub_rb_cmd **cmd) 3396 { 3397 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3398 3399 if (dmub_rb_empty(rb)) 3400 return false; 3401 3402 *cmd = (union dmub_rb_cmd *)rb_cmd; 3403 3404 return true; 3405 } 3406 3407 /** 3408 * @brief Determines the next ringbuffer offset. 3409 * 3410 * @param rb DMUB inbox ringbuffer 3411 * @param num_cmds Number of commands 3412 * @param next_rptr The next offset in the ringbuffer 3413 */ 3414 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3415 uint32_t num_cmds, 3416 uint32_t *next_rptr) 3417 { 3418 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3419 3420 if (*next_rptr >= rb->capacity) 3421 *next_rptr %= rb->capacity; 3422 } 3423 3424 /** 3425 * @brief Returns a pointer to a command in the inbox. 3426 * 3427 * @param rb DMUB inbox ringbuffer 3428 * @param cmd The inbox command to return 3429 * @param rptr The ringbuffer offset 3430 * @return true if not empty 3431 * @return false otherwise 3432 */ 3433 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3434 union dmub_rb_cmd **cmd, 3435 uint32_t rptr) 3436 { 3437 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3438 3439 if (dmub_rb_empty(rb)) 3440 return false; 3441 3442 *cmd = (union dmub_rb_cmd *)rb_cmd; 3443 3444 return true; 3445 } 3446 3447 /** 3448 * @brief Returns the next unprocessed command in the outbox. 3449 * 3450 * @param rb DMUB outbox ringbuffer 3451 * @param cmd The outbox command to return 3452 * @return true if not empty 3453 * @return false otherwise 3454 */ 3455 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3456 union dmub_rb_out_cmd *cmd) 3457 { 3458 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3459 uint64_t *dst = (uint64_t *)cmd; 3460 uint8_t i; 3461 3462 if (dmub_rb_empty(rb)) 3463 return false; 3464 3465 // copying data 3466 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3467 *dst++ = *src++; 3468 3469 return true; 3470 } 3471 3472 /** 3473 * @brief Removes the front entry in the ringbuffer. 3474 * 3475 * @param rb DMUB ringbuffer 3476 * @return true if the command was removed 3477 * @return false if there were no commands 3478 */ 3479 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3480 { 3481 if (dmub_rb_empty(rb)) 3482 return false; 3483 3484 rb->rptr += DMUB_RB_CMD_SIZE; 3485 3486 if (rb->rptr >= rb->capacity) 3487 rb->rptr %= rb->capacity; 3488 3489 return true; 3490 } 3491 3492 /** 3493 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3494 * 3495 * Avoids a race condition where DMCUB accesses memory while 3496 * there are still writes in flight to framebuffer. 3497 * 3498 * @param rb DMUB ringbuffer 3499 */ 3500 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3501 { 3502 uint32_t rptr = rb->rptr; 3503 uint32_t wptr = rb->wrpt; 3504 3505 while (rptr != wptr) { 3506 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3507 uint8_t i; 3508 3509 /* Don't remove this. 3510 * The contents need to actually be read from the ring buffer 3511 * for this function to be effective. 3512 */ 3513 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3514 (void)READ_ONCE(*data++); 3515 3516 rptr += DMUB_RB_CMD_SIZE; 3517 if (rptr >= rb->capacity) 3518 rptr %= rb->capacity; 3519 } 3520 } 3521 3522 /** 3523 * @brief Initializes a DMCUB ringbuffer 3524 * 3525 * @param rb DMUB ringbuffer 3526 * @param init_params initial configuration for the ringbuffer 3527 */ 3528 static inline void dmub_rb_init(struct dmub_rb *rb, 3529 struct dmub_rb_init_params *init_params) 3530 { 3531 rb->base_address = init_params->base_address; 3532 rb->capacity = init_params->capacity; 3533 rb->rptr = init_params->read_ptr; 3534 rb->wrpt = init_params->write_ptr; 3535 } 3536 3537 /** 3538 * @brief Copies output data from in/out commands into the given command. 3539 * 3540 * @param rb DMUB ringbuffer 3541 * @param cmd Command to copy data into 3542 */ 3543 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3544 union dmub_rb_cmd *cmd) 3545 { 3546 // Copy rb entry back into command 3547 uint8_t *rd_ptr = (rb->rptr == 0) ? 3548 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3549 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3550 3551 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3552 } 3553 3554 #if defined(__cplusplus) 3555 } 3556 #endif 3557 3558 //============================================================================== 3559 //</DMUB_RB>==================================================================== 3560 //============================================================================== 3561 3562 #endif /* _DMUB_CMD_H_ */ 3563