1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4) 30 #include "dmub_fw_types.h" 31 #include "include_legacy/atomfirmware.h" 32 33 #if defined(_TEST_HARNESS) 34 #include <string.h> 35 #endif 36 #else 37 38 #include <asm/byteorder.h> 39 #include <linux/types.h> 40 #include <linux/string.h> 41 #include <linux/delay.h> 42 43 #include "atomfirmware.h" 44 45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4) 46 47 //<DMUB_TYPES>================================================================== 48 /* Basic type definitions. */ 49 50 #define __forceinline inline 51 52 /** 53 * Flag from driver to indicate that ABM should be disabled gradually 54 * by slowly reversing all backlight programming and pixel compensation. 55 */ 56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 57 58 /** 59 * Flag from driver to indicate that ABM should be disabled immediately 60 * and undo all backlight programming and pixel compensation. 61 */ 62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 63 64 /** 65 * Flag from driver to indicate that ABM should be disabled immediately 66 * and keep the current backlight programming and pixel compensation. 67 */ 68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 69 70 /** 71 * Flag from driver to set the current ABM pipe index or ABM operating level. 72 */ 73 #define SET_ABM_PIPE_NORMAL 1 74 75 /** 76 * Number of ambient light levels in ABM algorithm. 77 */ 78 #define NUM_AMBI_LEVEL 5 79 80 /** 81 * Number of operating/aggression levels in ABM algorithm. 82 */ 83 #define NUM_AGGR_LEVEL 4 84 85 /** 86 * Number of segments in the gamma curve. 87 */ 88 #define NUM_POWER_FN_SEGS 8 89 90 /** 91 * Number of segments in the backlight curve. 92 */ 93 #define NUM_BL_CURVE_SEGS 16 94 95 /* Maximum number of SubVP streams */ 96 #define DMUB_MAX_SUBVP_STREAMS 2 97 98 /* Maximum number of streams on any ASIC. */ 99 #define DMUB_MAX_STREAMS 6 100 101 /* Maximum number of planes on any ASIC. */ 102 #define DMUB_MAX_PLANES 6 103 104 /* Trace buffer offset for entry */ 105 #define TRACE_BUFFER_ENTRY_OFFSET 16 106 107 /** 108 * Maximum number of dirty rects supported by FW. 109 */ 110 #define DMUB_MAX_DIRTY_RECTS 3 111 112 /** 113 * 114 * PSR control version legacy 115 */ 116 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 117 /** 118 * PSR control version with multi edp support 119 */ 120 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 121 122 123 /** 124 * ABM control version legacy 125 */ 126 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 127 128 /** 129 * ABM control version with multi edp support 130 */ 131 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 132 133 /** 134 * Physical framebuffer address location, 64-bit. 135 */ 136 #ifndef PHYSICAL_ADDRESS_LOC 137 #define PHYSICAL_ADDRESS_LOC union large_integer 138 #endif 139 140 /** 141 * OS/FW agnostic memcpy 142 */ 143 #ifndef dmub_memcpy 144 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 145 #endif 146 147 /** 148 * OS/FW agnostic memset 149 */ 150 #ifndef dmub_memset 151 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 152 #endif 153 154 #if defined(__cplusplus) 155 extern "C" { 156 #endif 157 158 /** 159 * OS/FW agnostic udelay 160 */ 161 #ifndef dmub_udelay 162 #define dmub_udelay(microseconds) udelay(microseconds) 163 #endif 164 165 /** 166 * union dmub_addr - DMUB physical/virtual 64-bit address. 167 */ 168 union dmub_addr { 169 struct { 170 uint32_t low_part; /**< Lower 32 bits */ 171 uint32_t high_part; /**< Upper 32 bits */ 172 } u; /*<< Low/high bit access */ 173 uint64_t quad_part; /*<< 64 bit address */ 174 }; 175 176 /** 177 * Dirty rect definition. 178 */ 179 struct dmub_rect { 180 /** 181 * Dirty rect x offset. 182 */ 183 uint32_t x; 184 185 /** 186 * Dirty rect y offset. 187 */ 188 uint32_t y; 189 190 /** 191 * Dirty rect width. 192 */ 193 uint32_t width; 194 195 /** 196 * Dirty rect height. 197 */ 198 uint32_t height; 199 }; 200 201 /** 202 * Flags that can be set by driver to change some PSR behaviour. 203 */ 204 union dmub_psr_debug_flags { 205 /** 206 * Debug flags. 207 */ 208 struct { 209 /** 210 * Enable visual confirm in FW. 211 */ 212 uint32_t visual_confirm : 1; 213 214 /** 215 * Force all selective updates to bw full frame updates. 216 */ 217 uint32_t force_full_frame_update : 1; 218 219 /** 220 * Use HW Lock Mgr object to do HW locking in FW. 221 */ 222 uint32_t use_hw_lock_mgr : 1; 223 224 /** 225 * Use TPS3 signal when restore main link. 226 */ 227 uint32_t force_wakeup_by_tps3 : 1; 228 229 /** 230 * Back to back flip, therefore cannot power down PHY 231 */ 232 uint32_t back_to_back_flip : 1; 233 234 } bitfields; 235 236 /** 237 * Union for debug flags. 238 */ 239 uint32_t u32All; 240 }; 241 242 /** 243 * DMUB visual confirm color 244 */ 245 struct dmub_feature_caps { 246 /** 247 * Max PSR version supported by FW. 248 */ 249 uint8_t psr; 250 uint8_t fw_assisted_mclk_switch; 251 uint8_t reserved[6]; 252 }; 253 254 struct dmub_visual_confirm_color { 255 /** 256 * Maximum 10 bits color value 257 */ 258 uint16_t color_r_cr; 259 uint16_t color_g_y; 260 uint16_t color_b_cb; 261 uint16_t panel_inst; 262 }; 263 264 #if defined(__cplusplus) 265 } 266 #endif 267 268 //============================================================================== 269 //</DMUB_TYPES>================================================================= 270 //============================================================================== 271 //< DMUB_META>================================================================== 272 //============================================================================== 273 #pragma pack(push, 1) 274 275 /* Magic value for identifying dmub_fw_meta_info */ 276 #define DMUB_FW_META_MAGIC 0x444D5542 277 278 /* Offset from the end of the file to the dmub_fw_meta_info */ 279 #define DMUB_FW_META_OFFSET 0x24 280 281 /** 282 * struct dmub_fw_meta_info - metadata associated with fw binary 283 * 284 * NOTE: This should be considered a stable API. Fields should 285 * not be repurposed or reordered. New fields should be 286 * added instead to extend the structure. 287 * 288 * @magic_value: magic value identifying DMUB firmware meta info 289 * @fw_region_size: size of the firmware state region 290 * @trace_buffer_size: size of the tracebuffer region 291 * @fw_version: the firmware version information 292 * @dal_fw: 1 if the firmware is DAL 293 */ 294 struct dmub_fw_meta_info { 295 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 296 uint32_t fw_region_size; /**< size of the firmware state region */ 297 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 298 uint32_t fw_version; /**< the firmware version information */ 299 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 300 uint8_t reserved[3]; /**< padding bits */ 301 }; 302 303 /** 304 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 305 */ 306 union dmub_fw_meta { 307 struct dmub_fw_meta_info info; /**< metadata info */ 308 uint8_t reserved[64]; /**< padding bits */ 309 }; 310 311 #pragma pack(pop) 312 313 //============================================================================== 314 //< DMUB Trace Buffer>================================================================ 315 //============================================================================== 316 /** 317 * dmub_trace_code_t - firmware trace code, 32-bits 318 */ 319 typedef uint32_t dmub_trace_code_t; 320 321 /** 322 * struct dmcub_trace_buf_entry - Firmware trace entry 323 */ 324 struct dmcub_trace_buf_entry { 325 dmub_trace_code_t trace_code; /**< trace code for the event */ 326 uint32_t tick_count; /**< the tick count at time of trace */ 327 uint32_t param0; /**< trace defined parameter 0 */ 328 uint32_t param1; /**< trace defined parameter 1 */ 329 }; 330 331 //============================================================================== 332 //< DMUB_STATUS>================================================================ 333 //============================================================================== 334 335 /** 336 * DMCUB scratch registers can be used to determine firmware status. 337 * Current scratch register usage is as follows: 338 * 339 * SCRATCH0: FW Boot Status register 340 * SCRATCH5: LVTMA Status Register 341 * SCRATCH15: FW Boot Options register 342 */ 343 344 /** 345 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 346 */ 347 union dmub_fw_boot_status { 348 struct { 349 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 350 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 351 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 352 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 353 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 354 uint32_t reserved : 1; 355 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 356 357 } bits; /**< status bits */ 358 uint32_t all; /**< 32-bit access to status bits */ 359 }; 360 361 /** 362 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 363 */ 364 enum dmub_fw_boot_status_bit { 365 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 366 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 367 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 368 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 369 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 370 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 371 }; 372 373 /* Register bit definition for SCRATCH5 */ 374 union dmub_lvtma_status { 375 struct { 376 uint32_t psp_ok : 1; 377 uint32_t edp_on : 1; 378 uint32_t reserved : 30; 379 } bits; 380 uint32_t all; 381 }; 382 383 enum dmub_lvtma_status_bit { 384 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 385 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 386 }; 387 388 /** 389 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 390 */ 391 union dmub_fw_boot_options { 392 struct { 393 uint32_t pemu_env : 1; /**< 1 if PEMU */ 394 uint32_t fpga_env : 1; /**< 1 if FPGA */ 395 uint32_t optimized_init : 1; /**< 1 if optimized init */ 396 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 397 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 398 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 399 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 400 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 401 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 402 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 403 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */ 404 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 405 uint32_t power_optimization: 1; 406 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 407 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 408 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 409 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 410 411 uint32_t reserved : 16; /**< reserved */ 412 } bits; /**< boot bits */ 413 uint32_t all; /**< 32-bit access to bits */ 414 }; 415 416 enum dmub_fw_boot_options_bit { 417 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 418 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 419 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 420 }; 421 422 //============================================================================== 423 //</DMUB_STATUS>================================================================ 424 //============================================================================== 425 //< DMUB_VBIOS>================================================================= 426 //============================================================================== 427 428 /* 429 * enum dmub_cmd_vbios_type - VBIOS commands. 430 * 431 * Command IDs should be treated as stable ABI. 432 * Do not reuse or modify IDs. 433 */ 434 enum dmub_cmd_vbios_type { 435 /** 436 * Configures the DIG encoder. 437 */ 438 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 439 /** 440 * Controls the PHY. 441 */ 442 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 443 /** 444 * Sets the pixel clock/symbol clock. 445 */ 446 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 447 /** 448 * Enables or disables power gating. 449 */ 450 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 451 /** 452 * Controls embedded panels. 453 */ 454 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 455 /** 456 * Query DP alt status on a transmitter. 457 */ 458 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 459 }; 460 461 //============================================================================== 462 //</DMUB_VBIOS>================================================================= 463 //============================================================================== 464 //< DMUB_GPINT>================================================================= 465 //============================================================================== 466 467 /** 468 * The shifts and masks below may alternatively be used to format and read 469 * the command register bits. 470 */ 471 472 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 473 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 474 475 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 476 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 477 478 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 479 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 480 481 /** 482 * Command responses. 483 */ 484 485 /** 486 * Return response for DMUB_GPINT__STOP_FW command. 487 */ 488 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 489 490 /** 491 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 492 */ 493 union dmub_gpint_data_register { 494 struct { 495 uint32_t param : 16; /**< 16-bit parameter */ 496 uint32_t command_code : 12; /**< GPINT command */ 497 uint32_t status : 4; /**< Command status bit */ 498 } bits; /**< GPINT bit access */ 499 uint32_t all; /**< GPINT 32-bit access */ 500 }; 501 502 /* 503 * enum dmub_gpint_command - GPINT command to DMCUB FW 504 * 505 * Command IDs should be treated as stable ABI. 506 * Do not reuse or modify IDs. 507 */ 508 enum dmub_gpint_command { 509 /** 510 * Invalid command, ignored. 511 */ 512 DMUB_GPINT__INVALID_COMMAND = 0, 513 /** 514 * DESC: Queries the firmware version. 515 * RETURN: Firmware version. 516 */ 517 DMUB_GPINT__GET_FW_VERSION = 1, 518 /** 519 * DESC: Halts the firmware. 520 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 521 */ 522 DMUB_GPINT__STOP_FW = 2, 523 /** 524 * DESC: Get PSR state from FW. 525 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 526 */ 527 DMUB_GPINT__GET_PSR_STATE = 7, 528 /** 529 * DESC: Notifies DMCUB of the currently active streams. 530 * ARGS: Stream mask, 1 bit per active stream index. 531 */ 532 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 533 /** 534 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 535 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 536 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 537 * RETURN: PSR residency in milli-percent. 538 */ 539 DMUB_GPINT__PSR_RESIDENCY = 9, 540 541 /** 542 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 543 */ 544 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 545 }; 546 547 /** 548 * INBOX0 generic command definition 549 */ 550 union dmub_inbox0_cmd_common { 551 struct { 552 uint32_t command_code: 8; /**< INBOX0 command code */ 553 uint32_t param: 24; /**< 24-bit parameter */ 554 } bits; 555 uint32_t all; 556 }; 557 558 /** 559 * INBOX0 hw_lock command definition 560 */ 561 union dmub_inbox0_cmd_lock_hw { 562 struct { 563 uint32_t command_code: 8; 564 565 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 566 uint32_t hw_lock_client: 2; 567 568 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 569 uint32_t otg_inst: 3; 570 uint32_t opp_inst: 3; 571 uint32_t dig_inst: 3; 572 573 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 574 uint32_t lock_pipe: 1; 575 uint32_t lock_cursor: 1; 576 uint32_t lock_dig: 1; 577 uint32_t triple_buffer_lock: 1; 578 579 uint32_t lock: 1; /**< Lock */ 580 uint32_t should_release: 1; /**< Release */ 581 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 582 } bits; 583 uint32_t all; 584 }; 585 586 union dmub_inbox0_data_register { 587 union dmub_inbox0_cmd_common inbox0_cmd_common; 588 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 589 }; 590 591 enum dmub_inbox0_command { 592 /** 593 * DESC: Invalid command, ignored. 594 */ 595 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 596 /** 597 * DESC: Notification to acquire/release HW lock 598 * ARGS: 599 */ 600 DMUB_INBOX0_CMD__HW_LOCK = 1, 601 }; 602 //============================================================================== 603 //</DMUB_GPINT>================================================================= 604 //============================================================================== 605 //< DMUB_CMD>=================================================================== 606 //============================================================================== 607 608 /** 609 * Size in bytes of each DMUB command. 610 */ 611 #define DMUB_RB_CMD_SIZE 64 612 613 /** 614 * Maximum number of items in the DMUB ringbuffer. 615 */ 616 #define DMUB_RB_MAX_ENTRY 128 617 618 /** 619 * Ringbuffer size in bytes. 620 */ 621 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 622 623 /** 624 * REG_SET mask for reg offload. 625 */ 626 #define REG_SET_MASK 0xFFFF 627 628 /* 629 * enum dmub_cmd_type - DMUB inbox command. 630 * 631 * Command IDs should be treated as stable ABI. 632 * Do not reuse or modify IDs. 633 */ 634 enum dmub_cmd_type { 635 /** 636 * Invalid command. 637 */ 638 DMUB_CMD__NULL = 0, 639 /** 640 * Read modify write register sequence offload. 641 */ 642 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 643 /** 644 * Field update register sequence offload. 645 */ 646 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 647 /** 648 * Burst write sequence offload. 649 */ 650 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 651 /** 652 * Reg wait sequence offload. 653 */ 654 DMUB_CMD__REG_REG_WAIT = 4, 655 /** 656 * Workaround to avoid HUBP underflow during NV12 playback. 657 */ 658 DMUB_CMD__PLAT_54186_WA = 5, 659 /** 660 * Command type used to query FW feature caps. 661 */ 662 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 663 /** 664 * Command type used to get visual confirm color. 665 */ 666 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 667 /** 668 * Command type used for all PSR commands. 669 */ 670 DMUB_CMD__PSR = 64, 671 /** 672 * Command type used for all MALL commands. 673 */ 674 DMUB_CMD__MALL = 65, 675 /** 676 * Command type used for all ABM commands. 677 */ 678 DMUB_CMD__ABM = 66, 679 /** 680 * Command type used to update dirty rects in FW. 681 */ 682 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 683 /** 684 * Command type used to update cursor info in FW. 685 */ 686 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 687 /** 688 * Command type used for HW locking in FW. 689 */ 690 DMUB_CMD__HW_LOCK = 69, 691 /** 692 * Command type used to access DP AUX. 693 */ 694 DMUB_CMD__DP_AUX_ACCESS = 70, 695 /** 696 * Command type used for OUTBOX1 notification enable 697 */ 698 DMUB_CMD__OUTBOX1_ENABLE = 71, 699 700 /** 701 * Command type used for all idle optimization commands. 702 */ 703 DMUB_CMD__IDLE_OPT = 72, 704 /** 705 * Command type used for all clock manager commands. 706 */ 707 DMUB_CMD__CLK_MGR = 73, 708 /** 709 * Command type used for all panel control commands. 710 */ 711 DMUB_CMD__PANEL_CNTL = 74, 712 /** 713 * Command type used for <TODO:description> 714 */ 715 DMUB_CMD__CAB_FOR_SS = 75, 716 717 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 718 719 /** 720 * Command type used for interfacing with DPIA. 721 */ 722 DMUB_CMD__DPIA = 77, 723 /** 724 * Command type used for EDID CEA parsing 725 */ 726 DMUB_CMD__EDID_CEA = 79, 727 /** 728 * Command type used for getting usbc cable ID 729 */ 730 DMUB_CMD_GET_USBC_CABLE_ID = 81, 731 /** 732 * Command type used to query HPD state. 733 */ 734 DMUB_CMD__QUERY_HPD_STATE = 82, 735 /** 736 * Command type used for all VBIOS interface commands. 737 */ 738 739 /** 740 * Command type used for all SECURE_DISPLAY commands. 741 */ 742 DMUB_CMD__SECURE_DISPLAY = 85, 743 744 /** 745 * Command type used to set DPIA HPD interrupt state 746 */ 747 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 748 749 DMUB_CMD__VBIOS = 128, 750 }; 751 752 /** 753 * enum dmub_out_cmd_type - DMUB outbox commands. 754 */ 755 enum dmub_out_cmd_type { 756 /** 757 * Invalid outbox command, ignored. 758 */ 759 DMUB_OUT_CMD__NULL = 0, 760 /** 761 * Command type used for DP AUX Reply data notification 762 */ 763 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 764 /** 765 * Command type used for DP HPD event notification 766 */ 767 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 768 /** 769 * Command type used for SET_CONFIG Reply notification 770 */ 771 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 772 }; 773 774 /* DMUB_CMD__DPIA command sub-types. */ 775 enum dmub_cmd_dpia_type { 776 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 777 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, 778 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 779 }; 780 781 #pragma pack(push, 1) 782 783 /** 784 * struct dmub_cmd_header - Common command header fields. 785 */ 786 struct dmub_cmd_header { 787 unsigned int type : 8; /**< command type */ 788 unsigned int sub_type : 8; /**< command sub type */ 789 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 790 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 791 unsigned int reserved0 : 6; /**< reserved bits */ 792 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 793 unsigned int reserved1 : 2; /**< reserved bits */ 794 }; 795 796 /* 797 * struct dmub_cmd_read_modify_write_sequence - Read modify write 798 * 799 * 60 payload bytes can hold up to 5 sets of read modify writes, 800 * each take 3 dwords. 801 * 802 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 803 * 804 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 805 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 806 */ 807 struct dmub_cmd_read_modify_write_sequence { 808 uint32_t addr; /**< register address */ 809 uint32_t modify_mask; /**< modify mask */ 810 uint32_t modify_value; /**< modify value */ 811 }; 812 813 /** 814 * Maximum number of ops in read modify write sequence. 815 */ 816 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 817 818 /** 819 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 820 */ 821 struct dmub_rb_cmd_read_modify_write { 822 struct dmub_cmd_header header; /**< command header */ 823 /** 824 * Read modify write sequence. 825 */ 826 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 827 }; 828 829 /* 830 * Update a register with specified masks and values sequeunce 831 * 832 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 833 * 834 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 835 * 836 * 837 * USE CASE: 838 * 1. auto-increment register where additional read would update pointer and produce wrong result 839 * 2. toggle a bit without read in the middle 840 */ 841 842 struct dmub_cmd_reg_field_update_sequence { 843 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 844 uint32_t modify_value; /**< value to update with */ 845 }; 846 847 /** 848 * Maximum number of ops in field update sequence. 849 */ 850 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 851 852 /** 853 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 854 */ 855 struct dmub_rb_cmd_reg_field_update_sequence { 856 struct dmub_cmd_header header; /**< command header */ 857 uint32_t addr; /**< register address */ 858 /** 859 * Field update sequence. 860 */ 861 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 862 }; 863 864 865 /** 866 * Maximum number of burst write values. 867 */ 868 #define DMUB_BURST_WRITE_VALUES__MAX 14 869 870 /* 871 * struct dmub_rb_cmd_burst_write - Burst write 872 * 873 * support use case such as writing out LUTs. 874 * 875 * 60 payload bytes can hold up to 14 values to write to given address 876 * 877 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 878 */ 879 struct dmub_rb_cmd_burst_write { 880 struct dmub_cmd_header header; /**< command header */ 881 uint32_t addr; /**< register start address */ 882 /** 883 * Burst write register values. 884 */ 885 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 886 }; 887 888 /** 889 * struct dmub_rb_cmd_common - Common command header 890 */ 891 struct dmub_rb_cmd_common { 892 struct dmub_cmd_header header; /**< command header */ 893 /** 894 * Padding to RB_CMD_SIZE 895 */ 896 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 897 }; 898 899 /** 900 * struct dmub_cmd_reg_wait_data - Register wait data 901 */ 902 struct dmub_cmd_reg_wait_data { 903 uint32_t addr; /**< Register address */ 904 uint32_t mask; /**< Mask for register bits */ 905 uint32_t condition_field_value; /**< Value to wait for */ 906 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 907 }; 908 909 /** 910 * struct dmub_rb_cmd_reg_wait - Register wait command 911 */ 912 struct dmub_rb_cmd_reg_wait { 913 struct dmub_cmd_header header; /**< Command header */ 914 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 915 }; 916 917 /** 918 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 919 * 920 * Reprograms surface parameters to avoid underflow. 921 */ 922 struct dmub_cmd_PLAT_54186_wa { 923 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 924 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 925 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 926 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 927 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 928 struct { 929 uint8_t hubp_inst : 4; /**< HUBP instance */ 930 uint8_t tmz_surface : 1; /**< TMZ enable or disable */ 931 uint8_t immediate :1; /**< Immediate flip */ 932 uint8_t vmid : 4; /**< VMID */ 933 uint8_t grph_stereo : 1; /**< 1 if stereo */ 934 uint32_t reserved : 21; /**< Reserved */ 935 } flip_params; /**< Pageflip parameters */ 936 uint32_t reserved[9]; /**< Reserved bits */ 937 }; 938 939 /** 940 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 941 */ 942 struct dmub_rb_cmd_PLAT_54186_wa { 943 struct dmub_cmd_header header; /**< Command header */ 944 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 945 }; 946 947 /** 948 * struct dmub_rb_cmd_mall - MALL command data. 949 */ 950 struct dmub_rb_cmd_mall { 951 struct dmub_cmd_header header; /**< Common command header */ 952 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 953 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 954 uint32_t tmr_delay; /**< Timer delay */ 955 uint32_t tmr_scale; /**< Timer scale */ 956 uint16_t cursor_width; /**< Cursor width in pixels */ 957 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 958 uint16_t cursor_height; /**< Cursor height in pixels */ 959 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 960 uint8_t debug_bits; /**< Debug bits */ 961 962 uint8_t reserved1; /**< Reserved bits */ 963 uint8_t reserved2; /**< Reserved bits */ 964 }; 965 966 /** 967 * enum dmub_cmd_cab_type - TODO: 968 */ 969 enum dmub_cmd_cab_type { 970 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 971 DMUB_CMD__CAB_NO_DCN_REQ = 1, 972 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 973 }; 974 975 /** 976 * struct dmub_rb_cmd_cab_for_ss - TODO: 977 */ 978 struct dmub_rb_cmd_cab_for_ss { 979 struct dmub_cmd_header header; 980 uint8_t cab_alloc_ways; /* total number of ways */ 981 uint8_t debug_bits; /* debug bits */ 982 }; 983 984 enum mclk_switch_mode { 985 NONE = 0, 986 FPO = 1, 987 SUBVP = 2, 988 VBLANK = 3, 989 }; 990 991 /* Per pipe struct which stores the MCLK switch mode 992 * data to be sent to DMUB. 993 * Named "v2" for now -- once FPO and SUBVP are fully merged 994 * the type name can be updated 995 */ 996 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 997 union { 998 struct { 999 uint32_t pix_clk_100hz; 1000 uint16_t main_vblank_start; 1001 uint16_t main_vblank_end; 1002 uint16_t mall_region_lines; 1003 uint16_t prefetch_lines; 1004 uint16_t prefetch_to_mall_start_lines; 1005 uint16_t processing_delay_lines; 1006 uint16_t htotal; // required to calculate line time for multi-display cases 1007 uint16_t vtotal; 1008 uint8_t main_pipe_index; 1009 uint8_t phantom_pipe_index; 1010 /* Since the microschedule is calculated in terms of OTG lines, 1011 * include any scaling factors to make sure when we get accurate 1012 * conversion when programming MALL_START_LINE (which is in terms 1013 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1014 * is 1/2 (numerator = 1, denominator = 2). 1015 */ 1016 uint8_t scale_factor_numerator; 1017 uint8_t scale_factor_denominator; 1018 uint8_t is_drr; 1019 uint8_t main_split_pipe_index; 1020 uint8_t phantom_split_pipe_index; 1021 } subvp_data; 1022 1023 struct { 1024 uint32_t pix_clk_100hz; 1025 uint16_t vblank_start; 1026 uint16_t vblank_end; 1027 uint16_t vstartup_start; 1028 uint16_t vtotal; 1029 uint16_t htotal; 1030 uint8_t vblank_pipe_index; 1031 uint8_t padding[2]; 1032 struct { 1033 uint8_t drr_in_use; 1034 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1035 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1036 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1037 uint8_t use_ramping; // Use ramping or not 1038 } drr_info; // DRR considered as part of SubVP + VBLANK case 1039 } vblank_data; 1040 } pipe_config; 1041 1042 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1043 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1044 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1045 */ 1046 uint8_t mode; // enum mclk_switch_mode 1047 }; 1048 1049 /** 1050 * Config data for Sub-VP and FPO 1051 * Named "v2" for now -- once FPO and SUBVP are fully merged 1052 * the type name can be updated 1053 */ 1054 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1055 uint16_t watermark_a_cache; 1056 uint8_t vertical_int_margin_us; 1057 uint8_t pstate_allow_width_us; 1058 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1059 }; 1060 1061 /** 1062 * DMUB rb command definition for Sub-VP and FPO 1063 * Named "v2" for now -- once FPO and SUBVP are fully merged 1064 * the type name can be updated 1065 */ 1066 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1067 struct dmub_cmd_header header; 1068 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1069 }; 1070 1071 /** 1072 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 1073 */ 1074 enum dmub_cmd_idle_opt_type { 1075 /** 1076 * DCN hardware restore. 1077 */ 1078 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 1079 1080 /** 1081 * DCN hardware save. 1082 */ 1083 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1 1084 }; 1085 1086 /** 1087 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 1088 */ 1089 struct dmub_rb_cmd_idle_opt_dcn_restore { 1090 struct dmub_cmd_header header; /**< header */ 1091 }; 1092 1093 /** 1094 * struct dmub_clocks - Clock update notification. 1095 */ 1096 struct dmub_clocks { 1097 uint32_t dispclk_khz; /**< dispclk kHz */ 1098 uint32_t dppclk_khz; /**< dppclk kHz */ 1099 uint32_t dcfclk_khz; /**< dcfclk kHz */ 1100 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 1101 }; 1102 1103 /** 1104 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 1105 */ 1106 enum dmub_cmd_clk_mgr_type { 1107 /** 1108 * Notify DMCUB of clock update. 1109 */ 1110 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 1111 }; 1112 1113 /** 1114 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 1115 */ 1116 struct dmub_rb_cmd_clk_mgr_notify_clocks { 1117 struct dmub_cmd_header header; /**< header */ 1118 struct dmub_clocks clocks; /**< clock data */ 1119 }; 1120 1121 /** 1122 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 1123 */ 1124 struct dmub_cmd_digx_encoder_control_data { 1125 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 1126 }; 1127 1128 /** 1129 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 1130 */ 1131 struct dmub_rb_cmd_digx_encoder_control { 1132 struct dmub_cmd_header header; /**< header */ 1133 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 1134 }; 1135 1136 /** 1137 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 1138 */ 1139 struct dmub_cmd_set_pixel_clock_data { 1140 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 1141 }; 1142 1143 /** 1144 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 1145 */ 1146 struct dmub_rb_cmd_set_pixel_clock { 1147 struct dmub_cmd_header header; /**< header */ 1148 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 1149 }; 1150 1151 /** 1152 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 1153 */ 1154 struct dmub_cmd_enable_disp_power_gating_data { 1155 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 1156 }; 1157 1158 /** 1159 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 1160 */ 1161 struct dmub_rb_cmd_enable_disp_power_gating { 1162 struct dmub_cmd_header header; /**< header */ 1163 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 1164 }; 1165 1166 /** 1167 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 1168 */ 1169 struct dmub_dig_transmitter_control_data_v1_7 { 1170 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 1171 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 1172 union { 1173 uint8_t digmode; /**< enum atom_encode_mode_def */ 1174 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 1175 } mode_laneset; 1176 uint8_t lanenum; /**< Number of lanes */ 1177 union { 1178 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 1179 } symclk_units; 1180 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 1181 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 1182 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 1183 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 1184 uint8_t reserved1; /**< For future use */ 1185 uint8_t reserved2[3]; /**< For future use */ 1186 uint32_t reserved3[11]; /**< For future use */ 1187 }; 1188 1189 /** 1190 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 1191 */ 1192 union dmub_cmd_dig1_transmitter_control_data { 1193 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 1194 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 1195 }; 1196 1197 /** 1198 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 1199 */ 1200 struct dmub_rb_cmd_dig1_transmitter_control { 1201 struct dmub_cmd_header header; /**< header */ 1202 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 1203 }; 1204 1205 /** 1206 * DPIA tunnel command parameters. 1207 */ 1208 struct dmub_cmd_dig_dpia_control_data { 1209 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 1210 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 1211 union { 1212 uint8_t digmode; /** enum atom_encode_mode_def */ 1213 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 1214 } mode_laneset; 1215 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 1216 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 1217 uint8_t hpdsel; /** =0: HPD is not assigned */ 1218 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 1219 uint8_t dpia_id; /** Index of DPIA */ 1220 uint8_t fec_rdy : 1; 1221 uint8_t reserved : 7; 1222 uint32_t reserved1; 1223 }; 1224 1225 /** 1226 * DMUB command for DPIA tunnel control. 1227 */ 1228 struct dmub_rb_cmd_dig1_dpia_control { 1229 struct dmub_cmd_header header; 1230 struct dmub_cmd_dig_dpia_control_data dpia_control; 1231 }; 1232 1233 /** 1234 * SET_CONFIG Command Payload 1235 */ 1236 struct set_config_cmd_payload { 1237 uint8_t msg_type; /* set config message type */ 1238 uint8_t msg_data; /* set config message data */ 1239 }; 1240 1241 /** 1242 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 1243 */ 1244 struct dmub_cmd_set_config_control_data { 1245 struct set_config_cmd_payload cmd_pkt; 1246 uint8_t instance; /* DPIA instance */ 1247 uint8_t immed_status; /* Immediate status returned in case of error */ 1248 }; 1249 1250 /** 1251 * DMUB command structure for SET_CONFIG command. 1252 */ 1253 struct dmub_rb_cmd_set_config_access { 1254 struct dmub_cmd_header header; /* header */ 1255 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 1256 }; 1257 1258 /** 1259 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 1260 */ 1261 struct dmub_cmd_mst_alloc_slots_control_data { 1262 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 1263 uint8_t instance; /* DPIA instance */ 1264 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 1265 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 1266 }; 1267 1268 /** 1269 * DMUB command structure for SET_ command. 1270 */ 1271 struct dmub_rb_cmd_set_mst_alloc_slots { 1272 struct dmub_cmd_header header; /* header */ 1273 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 1274 }; 1275 1276 /** 1277 * DMUB command structure for DPIA HPD int enable control. 1278 */ 1279 struct dmub_rb_cmd_dpia_hpd_int_enable { 1280 struct dmub_cmd_header header; /* header */ 1281 uint32_t enable; /* dpia hpd interrupt enable */ 1282 }; 1283 1284 /** 1285 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 1286 */ 1287 struct dmub_rb_cmd_dpphy_init { 1288 struct dmub_cmd_header header; /**< header */ 1289 uint8_t reserved[60]; /**< reserved bits */ 1290 }; 1291 1292 /** 1293 * enum dp_aux_request_action - DP AUX request command listing. 1294 * 1295 * 4 AUX request command bits are shifted to high nibble. 1296 */ 1297 enum dp_aux_request_action { 1298 /** I2C-over-AUX write request */ 1299 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 1300 /** I2C-over-AUX read request */ 1301 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 1302 /** I2C-over-AUX write status request */ 1303 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 1304 /** I2C-over-AUX write request with MOT=1 */ 1305 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 1306 /** I2C-over-AUX read request with MOT=1 */ 1307 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 1308 /** I2C-over-AUX write status request with MOT=1 */ 1309 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 1310 /** Native AUX write request */ 1311 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 1312 /** Native AUX read request */ 1313 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 1314 }; 1315 1316 /** 1317 * enum aux_return_code_type - DP AUX process return code listing. 1318 */ 1319 enum aux_return_code_type { 1320 /** AUX process succeeded */ 1321 AUX_RET_SUCCESS = 0, 1322 /** AUX process failed with unknown reason */ 1323 AUX_RET_ERROR_UNKNOWN, 1324 /** AUX process completed with invalid reply */ 1325 AUX_RET_ERROR_INVALID_REPLY, 1326 /** AUX process timed out */ 1327 AUX_RET_ERROR_TIMEOUT, 1328 /** HPD was low during AUX process */ 1329 AUX_RET_ERROR_HPD_DISCON, 1330 /** Failed to acquire AUX engine */ 1331 AUX_RET_ERROR_ENGINE_ACQUIRE, 1332 /** AUX request not supported */ 1333 AUX_RET_ERROR_INVALID_OPERATION, 1334 /** AUX process not available */ 1335 AUX_RET_ERROR_PROTOCOL_ERROR, 1336 }; 1337 1338 /** 1339 * enum aux_channel_type - DP AUX channel type listing. 1340 */ 1341 enum aux_channel_type { 1342 /** AUX thru Legacy DP AUX */ 1343 AUX_CHANNEL_LEGACY_DDC, 1344 /** AUX thru DPIA DP tunneling */ 1345 AUX_CHANNEL_DPIA 1346 }; 1347 1348 /** 1349 * struct aux_transaction_parameters - DP AUX request transaction data 1350 */ 1351 struct aux_transaction_parameters { 1352 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 1353 uint8_t action; /**< enum dp_aux_request_action */ 1354 uint8_t length; /**< DP AUX request data length */ 1355 uint8_t reserved; /**< For future use */ 1356 uint32_t address; /**< DP AUX address */ 1357 uint8_t data[16]; /**< DP AUX write data */ 1358 }; 1359 1360 /** 1361 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1362 */ 1363 struct dmub_cmd_dp_aux_control_data { 1364 uint8_t instance; /**< AUX instance or DPIA instance */ 1365 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 1366 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 1367 uint8_t reserved0; /**< For future use */ 1368 uint16_t timeout; /**< timeout time in us */ 1369 uint16_t reserved1; /**< For future use */ 1370 enum aux_channel_type type; /**< enum aux_channel_type */ 1371 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 1372 }; 1373 1374 /** 1375 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 1376 */ 1377 struct dmub_rb_cmd_dp_aux_access { 1378 /** 1379 * Command header. 1380 */ 1381 struct dmub_cmd_header header; 1382 /** 1383 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 1384 */ 1385 struct dmub_cmd_dp_aux_control_data aux_control; 1386 }; 1387 1388 /** 1389 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 1390 */ 1391 struct dmub_rb_cmd_outbox1_enable { 1392 /** 1393 * Command header. 1394 */ 1395 struct dmub_cmd_header header; 1396 /** 1397 * enable: 0x0 -> disable outbox1 notification (default value) 1398 * 0x1 -> enable outbox1 notification 1399 */ 1400 uint32_t enable; 1401 }; 1402 1403 /* DP AUX Reply command - OutBox Cmd */ 1404 /** 1405 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1406 */ 1407 struct aux_reply_data { 1408 /** 1409 * Aux cmd 1410 */ 1411 uint8_t command; 1412 /** 1413 * Aux reply data length (max: 16 bytes) 1414 */ 1415 uint8_t length; 1416 /** 1417 * Alignment only 1418 */ 1419 uint8_t pad[2]; 1420 /** 1421 * Aux reply data 1422 */ 1423 uint8_t data[16]; 1424 }; 1425 1426 /** 1427 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1428 */ 1429 struct aux_reply_control_data { 1430 /** 1431 * Reserved for future use 1432 */ 1433 uint32_t handle; 1434 /** 1435 * Aux Instance 1436 */ 1437 uint8_t instance; 1438 /** 1439 * Aux transaction result: definition in enum aux_return_code_type 1440 */ 1441 uint8_t result; 1442 /** 1443 * Alignment only 1444 */ 1445 uint16_t pad; 1446 }; 1447 1448 /** 1449 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 1450 */ 1451 struct dmub_rb_cmd_dp_aux_reply { 1452 /** 1453 * Command header. 1454 */ 1455 struct dmub_cmd_header header; 1456 /** 1457 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1458 */ 1459 struct aux_reply_control_data control; 1460 /** 1461 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 1462 */ 1463 struct aux_reply_data reply_data; 1464 }; 1465 1466 /* DP HPD Notify command - OutBox Cmd */ 1467 /** 1468 * DP HPD Type 1469 */ 1470 enum dp_hpd_type { 1471 /** 1472 * Normal DP HPD 1473 */ 1474 DP_HPD = 0, 1475 /** 1476 * DP HPD short pulse 1477 */ 1478 DP_IRQ 1479 }; 1480 1481 /** 1482 * DP HPD Status 1483 */ 1484 enum dp_hpd_status { 1485 /** 1486 * DP_HPD status low 1487 */ 1488 DP_HPD_UNPLUG = 0, 1489 /** 1490 * DP_HPD status high 1491 */ 1492 DP_HPD_PLUG 1493 }; 1494 1495 /** 1496 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1497 */ 1498 struct dp_hpd_data { 1499 /** 1500 * DP HPD instance 1501 */ 1502 uint8_t instance; 1503 /** 1504 * HPD type 1505 */ 1506 uint8_t hpd_type; 1507 /** 1508 * HPD status: only for type: DP_HPD to indicate status 1509 */ 1510 uint8_t hpd_status; 1511 /** 1512 * Alignment only 1513 */ 1514 uint8_t pad; 1515 }; 1516 1517 /** 1518 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1519 */ 1520 struct dmub_rb_cmd_dp_hpd_notify { 1521 /** 1522 * Command header. 1523 */ 1524 struct dmub_cmd_header header; 1525 /** 1526 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 1527 */ 1528 struct dp_hpd_data hpd_data; 1529 }; 1530 1531 /** 1532 * Definition of a SET_CONFIG reply from DPOA. 1533 */ 1534 enum set_config_status { 1535 SET_CONFIG_PENDING = 0, 1536 SET_CONFIG_ACK_RECEIVED, 1537 SET_CONFIG_RX_TIMEOUT, 1538 SET_CONFIG_UNKNOWN_ERROR, 1539 }; 1540 1541 /** 1542 * Definition of a set_config reply 1543 */ 1544 struct set_config_reply_control_data { 1545 uint8_t instance; /* DPIA Instance */ 1546 uint8_t status; /* Set Config reply */ 1547 uint16_t pad; /* Alignment */ 1548 }; 1549 1550 /** 1551 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 1552 */ 1553 struct dmub_rb_cmd_dp_set_config_reply { 1554 struct dmub_cmd_header header; 1555 struct set_config_reply_control_data set_config_reply_control; 1556 }; 1557 1558 /** 1559 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1560 */ 1561 struct dmub_cmd_hpd_state_query_data { 1562 uint8_t instance; /**< HPD instance or DPIA instance */ 1563 uint8_t result; /**< For returning HPD state */ 1564 uint16_t pad; /** < Alignment */ 1565 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 1566 enum aux_return_code_type status; /**< for returning the status of command */ 1567 }; 1568 1569 /** 1570 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 1571 */ 1572 struct dmub_rb_cmd_query_hpd_state { 1573 /** 1574 * Command header. 1575 */ 1576 struct dmub_cmd_header header; 1577 /** 1578 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 1579 */ 1580 struct dmub_cmd_hpd_state_query_data data; 1581 }; 1582 1583 /* 1584 * Command IDs should be treated as stable ABI. 1585 * Do not reuse or modify IDs. 1586 */ 1587 1588 /** 1589 * PSR command sub-types. 1590 */ 1591 enum dmub_cmd_psr_type { 1592 /** 1593 * Set PSR version support. 1594 */ 1595 DMUB_CMD__PSR_SET_VERSION = 0, 1596 /** 1597 * Copy driver-calculated parameters to PSR state. 1598 */ 1599 DMUB_CMD__PSR_COPY_SETTINGS = 1, 1600 /** 1601 * Enable PSR. 1602 */ 1603 DMUB_CMD__PSR_ENABLE = 2, 1604 1605 /** 1606 * Disable PSR. 1607 */ 1608 DMUB_CMD__PSR_DISABLE = 3, 1609 1610 /** 1611 * Set PSR level. 1612 * PSR level is a 16-bit value dicated by driver that 1613 * will enable/disable different functionality. 1614 */ 1615 DMUB_CMD__PSR_SET_LEVEL = 4, 1616 1617 /** 1618 * Forces PSR enabled until an explicit PSR disable call. 1619 */ 1620 DMUB_CMD__PSR_FORCE_STATIC = 5, 1621 /** 1622 * Set vtotal in psr active for FreeSync PSR. 1623 */ 1624 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 1625 /** 1626 * Set PSR power option 1627 */ 1628 DMUB_CMD__SET_PSR_POWER_OPT = 7, 1629 }; 1630 1631 enum dmub_cmd_fams_type { 1632 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 1633 DMUB_CMD__FAMS_DRR_UPDATE = 1, 1634 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 1635 /** 1636 * For SubVP set manual trigger in FW because it 1637 * triggers DRR_UPDATE_PENDING which SubVP relies 1638 * on (for any SubVP cases that use a DRR display) 1639 */ 1640 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 1641 }; 1642 1643 /** 1644 * PSR versions. 1645 */ 1646 enum psr_version { 1647 /** 1648 * PSR version 1. 1649 */ 1650 PSR_VERSION_1 = 0, 1651 /** 1652 * Freesync PSR SU. 1653 */ 1654 PSR_VERSION_SU_1 = 1, 1655 /** 1656 * PSR not supported. 1657 */ 1658 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF, 1659 }; 1660 1661 /** 1662 * enum dmub_cmd_mall_type - MALL commands 1663 */ 1664 enum dmub_cmd_mall_type { 1665 /** 1666 * Allows display refresh from MALL. 1667 */ 1668 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1669 /** 1670 * Disallows display refresh from MALL. 1671 */ 1672 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1673 /** 1674 * Cursor copy for MALL. 1675 */ 1676 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1677 /** 1678 * Controls DF requests. 1679 */ 1680 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1681 }; 1682 1683 /** 1684 * PHY Link rate for DP. 1685 */ 1686 enum phy_link_rate { 1687 /** 1688 * not supported. 1689 */ 1690 PHY_RATE_UNKNOWN = 0, 1691 /** 1692 * Rate_1 (RBR) - 1.62 Gbps/Lane 1693 */ 1694 PHY_RATE_162 = 1, 1695 /** 1696 * Rate_2 - 2.16 Gbps/Lane 1697 */ 1698 PHY_RATE_216 = 2, 1699 /** 1700 * Rate_3 - 2.43 Gbps/Lane 1701 */ 1702 PHY_RATE_243 = 3, 1703 /** 1704 * Rate_4 (HBR) - 2.70 Gbps/Lane 1705 */ 1706 PHY_RATE_270 = 4, 1707 /** 1708 * Rate_5 (RBR2)- 3.24 Gbps/Lane 1709 */ 1710 PHY_RATE_324 = 5, 1711 /** 1712 * Rate_6 - 4.32 Gbps/Lane 1713 */ 1714 PHY_RATE_432 = 6, 1715 /** 1716 * Rate_7 (HBR2)- 5.40 Gbps/Lane 1717 */ 1718 PHY_RATE_540 = 7, 1719 /** 1720 * Rate_8 (HBR3)- 8.10 Gbps/Lane 1721 */ 1722 PHY_RATE_810 = 8, 1723 /** 1724 * UHBR10 - 10.0 Gbps/Lane 1725 */ 1726 PHY_RATE_1000 = 9, 1727 /** 1728 * UHBR13.5 - 13.5 Gbps/Lane 1729 */ 1730 PHY_RATE_1350 = 10, 1731 /** 1732 * UHBR10 - 20.0 Gbps/Lane 1733 */ 1734 PHY_RATE_2000 = 11, 1735 }; 1736 1737 /** 1738 * enum dmub_phy_fsm_state - PHY FSM states. 1739 * PHY FSM state to transit to during PSR enable/disable. 1740 */ 1741 enum dmub_phy_fsm_state { 1742 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 1743 DMUB_PHY_FSM_RESET, 1744 DMUB_PHY_FSM_RESET_RELEASED, 1745 DMUB_PHY_FSM_SRAM_LOAD_DONE, 1746 DMUB_PHY_FSM_INITIALIZED, 1747 DMUB_PHY_FSM_CALIBRATED, 1748 DMUB_PHY_FSM_CALIBRATED_LP, 1749 DMUB_PHY_FSM_CALIBRATED_PG, 1750 DMUB_PHY_FSM_POWER_DOWN, 1751 DMUB_PHY_FSM_PLL_EN, 1752 DMUB_PHY_FSM_TX_EN, 1753 DMUB_PHY_FSM_FAST_LP, 1754 }; 1755 1756 /** 1757 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1758 */ 1759 struct dmub_cmd_psr_copy_settings_data { 1760 /** 1761 * Flags that can be set by driver to change some PSR behaviour. 1762 */ 1763 union dmub_psr_debug_flags debug; 1764 /** 1765 * 16-bit value dicated by driver that will enable/disable different functionality. 1766 */ 1767 uint16_t psr_level; 1768 /** 1769 * DPP HW instance. 1770 */ 1771 uint8_t dpp_inst; 1772 /** 1773 * MPCC HW instance. 1774 * Not used in dmub fw, 1775 * dmub fw will get active opp by reading odm registers. 1776 */ 1777 uint8_t mpcc_inst; 1778 /** 1779 * OPP HW instance. 1780 * Not used in dmub fw, 1781 * dmub fw will get active opp by reading odm registers. 1782 */ 1783 uint8_t opp_inst; 1784 /** 1785 * OTG HW instance. 1786 */ 1787 uint8_t otg_inst; 1788 /** 1789 * DIG FE HW instance. 1790 */ 1791 uint8_t digfe_inst; 1792 /** 1793 * DIG BE HW instance. 1794 */ 1795 uint8_t digbe_inst; 1796 /** 1797 * DP PHY HW instance. 1798 */ 1799 uint8_t dpphy_inst; 1800 /** 1801 * AUX HW instance. 1802 */ 1803 uint8_t aux_inst; 1804 /** 1805 * Determines if SMU optimzations are enabled/disabled. 1806 */ 1807 uint8_t smu_optimizations_en; 1808 /** 1809 * Unused. 1810 * TODO: Remove. 1811 */ 1812 uint8_t frame_delay; 1813 /** 1814 * If RFB setup time is greater than the total VBLANK time, 1815 * it is not possible for the sink to capture the video frame 1816 * in the same frame the SDP is sent. In this case, 1817 * the frame capture indication bit should be set and an extra 1818 * static frame should be transmitted to the sink. 1819 */ 1820 uint8_t frame_cap_ind; 1821 /** 1822 * Granularity of Y offset supported by sink. 1823 */ 1824 uint8_t su_y_granularity; 1825 /** 1826 * Indicates whether sink should start capturing 1827 * immediately following active scan line, 1828 * or starting with the 2nd active scan line. 1829 */ 1830 uint8_t line_capture_indication; 1831 /** 1832 * Multi-display optimizations are implemented on certain ASICs. 1833 */ 1834 uint8_t multi_disp_optimizations_en; 1835 /** 1836 * The last possible line SDP may be transmitted without violating 1837 * the RFB setup time or entering the active video frame. 1838 */ 1839 uint16_t init_sdp_deadline; 1840 /** 1841 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 1842 */ 1843 uint8_t rate_control_caps ; 1844 /* 1845 * Force PSRSU always doing full frame update 1846 */ 1847 uint8_t force_ffu_mode; 1848 /** 1849 * Length of each horizontal line in us. 1850 */ 1851 uint32_t line_time_in_us; 1852 /** 1853 * FEC enable status in driver 1854 */ 1855 uint8_t fec_enable_status; 1856 /** 1857 * FEC re-enable delay when PSR exit. 1858 * unit is 100us, range form 0~255(0xFF). 1859 */ 1860 uint8_t fec_enable_delay_in100us; 1861 /** 1862 * PSR control version. 1863 */ 1864 uint8_t cmd_version; 1865 /** 1866 * Panel Instance. 1867 * Panel isntance to identify which psr_state to use 1868 * Currently the support is only for 0 or 1 1869 */ 1870 uint8_t panel_inst; 1871 /* 1872 * DSC enable status in driver 1873 */ 1874 uint8_t dsc_enable_status; 1875 /* 1876 * Use FSM state for PSR power up/down 1877 */ 1878 uint8_t use_phy_fsm; 1879 /** 1880 * frame delay for frame re-lock 1881 */ 1882 uint8_t relock_delay_frame_cnt; 1883 /** 1884 * Explicit padding to 2 byte boundary. 1885 */ 1886 uint8_t pad3; 1887 }; 1888 1889 /** 1890 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 1891 */ 1892 struct dmub_rb_cmd_psr_copy_settings { 1893 /** 1894 * Command header. 1895 */ 1896 struct dmub_cmd_header header; 1897 /** 1898 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 1899 */ 1900 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 1901 }; 1902 1903 /** 1904 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 1905 */ 1906 struct dmub_cmd_psr_set_level_data { 1907 /** 1908 * 16-bit value dicated by driver that will enable/disable different functionality. 1909 */ 1910 uint16_t psr_level; 1911 /** 1912 * PSR control version. 1913 */ 1914 uint8_t cmd_version; 1915 /** 1916 * Panel Instance. 1917 * Panel isntance to identify which psr_state to use 1918 * Currently the support is only for 0 or 1 1919 */ 1920 uint8_t panel_inst; 1921 }; 1922 1923 /** 1924 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1925 */ 1926 struct dmub_rb_cmd_psr_set_level { 1927 /** 1928 * Command header. 1929 */ 1930 struct dmub_cmd_header header; 1931 /** 1932 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 1933 */ 1934 struct dmub_cmd_psr_set_level_data psr_set_level_data; 1935 }; 1936 1937 struct dmub_rb_cmd_psr_enable_data { 1938 /** 1939 * PSR control version. 1940 */ 1941 uint8_t cmd_version; 1942 /** 1943 * Panel Instance. 1944 * Panel isntance to identify which psr_state to use 1945 * Currently the support is only for 0 or 1 1946 */ 1947 uint8_t panel_inst; 1948 /** 1949 * Phy state to enter. 1950 * Values to use are defined in dmub_phy_fsm_state 1951 */ 1952 uint8_t phy_fsm_state; 1953 /** 1954 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 1955 * Set this using enum phy_link_rate. 1956 * This does not support HDMI/DP2 for now. 1957 */ 1958 uint8_t phy_rate; 1959 }; 1960 1961 /** 1962 * Definition of a DMUB_CMD__PSR_ENABLE command. 1963 * PSR enable/disable is controlled using the sub_type. 1964 */ 1965 struct dmub_rb_cmd_psr_enable { 1966 /** 1967 * Command header. 1968 */ 1969 struct dmub_cmd_header header; 1970 1971 struct dmub_rb_cmd_psr_enable_data data; 1972 }; 1973 1974 /** 1975 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 1976 */ 1977 struct dmub_cmd_psr_set_version_data { 1978 /** 1979 * PSR version that FW should implement. 1980 */ 1981 enum psr_version version; 1982 /** 1983 * PSR control version. 1984 */ 1985 uint8_t cmd_version; 1986 /** 1987 * Panel Instance. 1988 * Panel isntance to identify which psr_state to use 1989 * Currently the support is only for 0 or 1 1990 */ 1991 uint8_t panel_inst; 1992 /** 1993 * Explicit padding to 4 byte boundary. 1994 */ 1995 uint8_t pad[2]; 1996 }; 1997 1998 /** 1999 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 2000 */ 2001 struct dmub_rb_cmd_psr_set_version { 2002 /** 2003 * Command header. 2004 */ 2005 struct dmub_cmd_header header; 2006 /** 2007 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 2008 */ 2009 struct dmub_cmd_psr_set_version_data psr_set_version_data; 2010 }; 2011 2012 struct dmub_cmd_psr_force_static_data { 2013 /** 2014 * PSR control version. 2015 */ 2016 uint8_t cmd_version; 2017 /** 2018 * Panel Instance. 2019 * Panel isntance to identify which psr_state to use 2020 * Currently the support is only for 0 or 1 2021 */ 2022 uint8_t panel_inst; 2023 /** 2024 * Explicit padding to 4 byte boundary. 2025 */ 2026 uint8_t pad[2]; 2027 }; 2028 2029 /** 2030 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 2031 */ 2032 struct dmub_rb_cmd_psr_force_static { 2033 /** 2034 * Command header. 2035 */ 2036 struct dmub_cmd_header header; 2037 /** 2038 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 2039 */ 2040 struct dmub_cmd_psr_force_static_data psr_force_static_data; 2041 }; 2042 2043 /** 2044 * PSR SU debug flags. 2045 */ 2046 union dmub_psr_su_debug_flags { 2047 /** 2048 * PSR SU debug flags. 2049 */ 2050 struct { 2051 /** 2052 * Update dirty rect in SW only. 2053 */ 2054 uint8_t update_dirty_rect_only : 1; 2055 /** 2056 * Reset the cursor/plane state before processing the call. 2057 */ 2058 uint8_t reset_state : 1; 2059 } bitfields; 2060 2061 /** 2062 * Union for debug flags. 2063 */ 2064 uint32_t u32All; 2065 }; 2066 2067 /** 2068 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2069 * This triggers a selective update for PSR SU. 2070 */ 2071 struct dmub_cmd_update_dirty_rect_data { 2072 /** 2073 * Dirty rects from OS. 2074 */ 2075 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 2076 /** 2077 * PSR SU debug flags. 2078 */ 2079 union dmub_psr_su_debug_flags debug_flags; 2080 /** 2081 * OTG HW instance. 2082 */ 2083 uint8_t pipe_idx; 2084 /** 2085 * Number of dirty rects. 2086 */ 2087 uint8_t dirty_rect_count; 2088 /** 2089 * PSR control version. 2090 */ 2091 uint8_t cmd_version; 2092 /** 2093 * Panel Instance. 2094 * Panel isntance to identify which psr_state to use 2095 * Currently the support is only for 0 or 1 2096 */ 2097 uint8_t panel_inst; 2098 }; 2099 2100 /** 2101 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 2102 */ 2103 struct dmub_rb_cmd_update_dirty_rect { 2104 /** 2105 * Command header. 2106 */ 2107 struct dmub_cmd_header header; 2108 /** 2109 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 2110 */ 2111 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 2112 }; 2113 2114 /** 2115 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2116 */ 2117 union dmub_reg_cursor_control_cfg { 2118 struct { 2119 uint32_t cur_enable: 1; 2120 uint32_t reser0: 3; 2121 uint32_t cur_2x_magnify: 1; 2122 uint32_t reser1: 3; 2123 uint32_t mode: 3; 2124 uint32_t reser2: 5; 2125 uint32_t pitch: 2; 2126 uint32_t reser3: 6; 2127 uint32_t line_per_chunk: 5; 2128 uint32_t reser4: 3; 2129 } bits; 2130 uint32_t raw; 2131 }; 2132 struct dmub_cursor_position_cache_hubp { 2133 union dmub_reg_cursor_control_cfg cur_ctl; 2134 union dmub_reg_position_cfg { 2135 struct { 2136 uint32_t cur_x_pos: 16; 2137 uint32_t cur_y_pos: 16; 2138 } bits; 2139 uint32_t raw; 2140 } position; 2141 union dmub_reg_hot_spot_cfg { 2142 struct { 2143 uint32_t hot_x: 16; 2144 uint32_t hot_y: 16; 2145 } bits; 2146 uint32_t raw; 2147 } hot_spot; 2148 union dmub_reg_dst_offset_cfg { 2149 struct { 2150 uint32_t dst_x_offset: 13; 2151 uint32_t reserved: 19; 2152 } bits; 2153 uint32_t raw; 2154 } dst_offset; 2155 }; 2156 2157 union dmub_reg_cur0_control_cfg { 2158 struct { 2159 uint32_t cur0_enable: 1; 2160 uint32_t expansion_mode: 1; 2161 uint32_t reser0: 1; 2162 uint32_t cur0_rom_en: 1; 2163 uint32_t mode: 3; 2164 uint32_t reserved: 25; 2165 } bits; 2166 uint32_t raw; 2167 }; 2168 struct dmub_cursor_position_cache_dpp { 2169 union dmub_reg_cur0_control_cfg cur0_ctl; 2170 }; 2171 struct dmub_cursor_position_cfg { 2172 struct dmub_cursor_position_cache_hubp pHubp; 2173 struct dmub_cursor_position_cache_dpp pDpp; 2174 uint8_t pipe_idx; 2175 /* 2176 * Padding is required. To be 4 Bytes Aligned. 2177 */ 2178 uint8_t padding[3]; 2179 }; 2180 2181 struct dmub_cursor_attribute_cache_hubp { 2182 uint32_t SURFACE_ADDR_HIGH; 2183 uint32_t SURFACE_ADDR; 2184 union dmub_reg_cursor_control_cfg cur_ctl; 2185 union dmub_reg_cursor_size_cfg { 2186 struct { 2187 uint32_t width: 16; 2188 uint32_t height: 16; 2189 } bits; 2190 uint32_t raw; 2191 } size; 2192 union dmub_reg_cursor_settings_cfg { 2193 struct { 2194 uint32_t dst_y_offset: 8; 2195 uint32_t chunk_hdl_adjust: 2; 2196 uint32_t reserved: 22; 2197 } bits; 2198 uint32_t raw; 2199 } settings; 2200 }; 2201 struct dmub_cursor_attribute_cache_dpp { 2202 union dmub_reg_cur0_control_cfg cur0_ctl; 2203 }; 2204 struct dmub_cursor_attributes_cfg { 2205 struct dmub_cursor_attribute_cache_hubp aHubp; 2206 struct dmub_cursor_attribute_cache_dpp aDpp; 2207 }; 2208 2209 struct dmub_cmd_update_cursor_payload0 { 2210 /** 2211 * Cursor dirty rects. 2212 */ 2213 struct dmub_rect cursor_rect; 2214 /** 2215 * PSR SU debug flags. 2216 */ 2217 union dmub_psr_su_debug_flags debug_flags; 2218 /** 2219 * Cursor enable/disable. 2220 */ 2221 uint8_t enable; 2222 /** 2223 * OTG HW instance. 2224 */ 2225 uint8_t pipe_idx; 2226 /** 2227 * PSR control version. 2228 */ 2229 uint8_t cmd_version; 2230 /** 2231 * Panel Instance. 2232 * Panel isntance to identify which psr_state to use 2233 * Currently the support is only for 0 or 1 2234 */ 2235 uint8_t panel_inst; 2236 /** 2237 * Cursor Position Register. 2238 * Registers contains Hubp & Dpp modules 2239 */ 2240 struct dmub_cursor_position_cfg position_cfg; 2241 }; 2242 2243 struct dmub_cmd_update_cursor_payload1 { 2244 struct dmub_cursor_attributes_cfg attribute_cfg; 2245 }; 2246 2247 union dmub_cmd_update_cursor_info_data { 2248 struct dmub_cmd_update_cursor_payload0 payload0; 2249 struct dmub_cmd_update_cursor_payload1 payload1; 2250 }; 2251 /** 2252 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 2253 */ 2254 struct dmub_rb_cmd_update_cursor_info { 2255 /** 2256 * Command header. 2257 */ 2258 struct dmub_cmd_header header; 2259 /** 2260 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 2261 */ 2262 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 2263 }; 2264 2265 /** 2266 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2267 */ 2268 struct dmub_cmd_psr_set_vtotal_data { 2269 /** 2270 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 2271 */ 2272 uint16_t psr_vtotal_idle; 2273 /** 2274 * PSR control version. 2275 */ 2276 uint8_t cmd_version; 2277 /** 2278 * Panel Instance. 2279 * Panel isntance to identify which psr_state to use 2280 * Currently the support is only for 0 or 1 2281 */ 2282 uint8_t panel_inst; 2283 /* 2284 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 2285 */ 2286 uint16_t psr_vtotal_su; 2287 /** 2288 * Explicit padding to 4 byte boundary. 2289 */ 2290 uint8_t pad2[2]; 2291 }; 2292 2293 /** 2294 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2295 */ 2296 struct dmub_rb_cmd_psr_set_vtotal { 2297 /** 2298 * Command header. 2299 */ 2300 struct dmub_cmd_header header; 2301 /** 2302 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 2303 */ 2304 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 2305 }; 2306 2307 /** 2308 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 2309 */ 2310 struct dmub_cmd_psr_set_power_opt_data { 2311 /** 2312 * PSR control version. 2313 */ 2314 uint8_t cmd_version; 2315 /** 2316 * Panel Instance. 2317 * Panel isntance to identify which psr_state to use 2318 * Currently the support is only for 0 or 1 2319 */ 2320 uint8_t panel_inst; 2321 /** 2322 * Explicit padding to 4 byte boundary. 2323 */ 2324 uint8_t pad[2]; 2325 /** 2326 * PSR power option 2327 */ 2328 uint32_t power_opt; 2329 }; 2330 2331 /** 2332 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2333 */ 2334 struct dmub_rb_cmd_psr_set_power_opt { 2335 /** 2336 * Command header. 2337 */ 2338 struct dmub_cmd_header header; 2339 /** 2340 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 2341 */ 2342 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 2343 }; 2344 2345 /** 2346 * Set of HW components that can be locked. 2347 * 2348 * Note: If updating with more HW components, fields 2349 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2350 */ 2351 union dmub_hw_lock_flags { 2352 /** 2353 * Set of HW components that can be locked. 2354 */ 2355 struct { 2356 /** 2357 * Lock/unlock OTG master update lock. 2358 */ 2359 uint8_t lock_pipe : 1; 2360 /** 2361 * Lock/unlock cursor. 2362 */ 2363 uint8_t lock_cursor : 1; 2364 /** 2365 * Lock/unlock global update lock. 2366 */ 2367 uint8_t lock_dig : 1; 2368 /** 2369 * Triple buffer lock requires additional hw programming to usual OTG master lock. 2370 */ 2371 uint8_t triple_buffer_lock : 1; 2372 } bits; 2373 2374 /** 2375 * Union for HW Lock flags. 2376 */ 2377 uint8_t u8All; 2378 }; 2379 2380 /** 2381 * Instances of HW to be locked. 2382 * 2383 * Note: If updating with more HW components, fields 2384 * in dmub_inbox0_cmd_lock_hw must be updated to match. 2385 */ 2386 struct dmub_hw_lock_inst_flags { 2387 /** 2388 * OTG HW instance for OTG master update lock. 2389 */ 2390 uint8_t otg_inst; 2391 /** 2392 * OPP instance for cursor lock. 2393 */ 2394 uint8_t opp_inst; 2395 /** 2396 * OTG HW instance for global update lock. 2397 * TODO: Remove, and re-use otg_inst. 2398 */ 2399 uint8_t dig_inst; 2400 /** 2401 * Explicit pad to 4 byte boundary. 2402 */ 2403 uint8_t pad; 2404 }; 2405 2406 /** 2407 * Clients that can acquire the HW Lock Manager. 2408 * 2409 * Note: If updating with more clients, fields in 2410 * dmub_inbox0_cmd_lock_hw must be updated to match. 2411 */ 2412 enum hw_lock_client { 2413 /** 2414 * Driver is the client of HW Lock Manager. 2415 */ 2416 HW_LOCK_CLIENT_DRIVER = 0, 2417 /** 2418 * PSR SU is the client of HW Lock Manager. 2419 */ 2420 HW_LOCK_CLIENT_PSR_SU = 1, 2421 /** 2422 * Invalid client. 2423 */ 2424 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 2425 }; 2426 2427 /** 2428 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2429 */ 2430 struct dmub_cmd_lock_hw_data { 2431 /** 2432 * Specifies the client accessing HW Lock Manager. 2433 */ 2434 enum hw_lock_client client; 2435 /** 2436 * HW instances to be locked. 2437 */ 2438 struct dmub_hw_lock_inst_flags inst_flags; 2439 /** 2440 * Which components to be locked. 2441 */ 2442 union dmub_hw_lock_flags hw_locks; 2443 /** 2444 * Specifies lock/unlock. 2445 */ 2446 uint8_t lock; 2447 /** 2448 * HW can be unlocked separately from releasing the HW Lock Mgr. 2449 * This flag is set if the client wishes to release the object. 2450 */ 2451 uint8_t should_release; 2452 /** 2453 * Explicit padding to 4 byte boundary. 2454 */ 2455 uint8_t pad; 2456 }; 2457 2458 /** 2459 * Definition of a DMUB_CMD__HW_LOCK command. 2460 * Command is used by driver and FW. 2461 */ 2462 struct dmub_rb_cmd_lock_hw { 2463 /** 2464 * Command header. 2465 */ 2466 struct dmub_cmd_header header; 2467 /** 2468 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 2469 */ 2470 struct dmub_cmd_lock_hw_data lock_hw_data; 2471 }; 2472 2473 /** 2474 * ABM command sub-types. 2475 */ 2476 enum dmub_cmd_abm_type { 2477 /** 2478 * Initialize parameters for ABM algorithm. 2479 * Data is passed through an indirect buffer. 2480 */ 2481 DMUB_CMD__ABM_INIT_CONFIG = 0, 2482 /** 2483 * Set OTG and panel HW instance. 2484 */ 2485 DMUB_CMD__ABM_SET_PIPE = 1, 2486 /** 2487 * Set user requested backklight level. 2488 */ 2489 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 2490 /** 2491 * Set ABM operating/aggression level. 2492 */ 2493 DMUB_CMD__ABM_SET_LEVEL = 3, 2494 /** 2495 * Set ambient light level. 2496 */ 2497 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 2498 /** 2499 * Enable/disable fractional duty cycle for backlight PWM. 2500 */ 2501 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 2502 2503 /** 2504 * unregister vertical interrupt after steady state is reached 2505 */ 2506 DMUB_CMD__ABM_PAUSE = 6, 2507 }; 2508 2509 /** 2510 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 2511 * Requirements: 2512 * - Padded explicitly to 32-bit boundary. 2513 * - Must ensure this structure matches the one on driver-side, 2514 * otherwise it won't be aligned. 2515 */ 2516 struct abm_config_table { 2517 /** 2518 * Gamma curve thresholds, used for crgb conversion. 2519 */ 2520 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 2521 /** 2522 * Gamma curve offsets, used for crgb conversion. 2523 */ 2524 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 2525 /** 2526 * Gamma curve slopes, used for crgb conversion. 2527 */ 2528 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 2529 /** 2530 * Custom backlight curve thresholds. 2531 */ 2532 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 2533 /** 2534 * Custom backlight curve offsets. 2535 */ 2536 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 2537 /** 2538 * Ambient light thresholds. 2539 */ 2540 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 2541 /** 2542 * Minimum programmable backlight. 2543 */ 2544 uint16_t min_abm_backlight; // 122B 2545 /** 2546 * Minimum reduction values. 2547 */ 2548 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 2549 /** 2550 * Maximum reduction values. 2551 */ 2552 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 2553 /** 2554 * Bright positive gain. 2555 */ 2556 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 2557 /** 2558 * Dark negative gain. 2559 */ 2560 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 2561 /** 2562 * Hybrid factor. 2563 */ 2564 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 2565 /** 2566 * Contrast factor. 2567 */ 2568 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 2569 /** 2570 * Deviation gain. 2571 */ 2572 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 2573 /** 2574 * Minimum knee. 2575 */ 2576 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 2577 /** 2578 * Maximum knee. 2579 */ 2580 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 2581 /** 2582 * Unused. 2583 */ 2584 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 2585 /** 2586 * Explicit padding to 4 byte boundary. 2587 */ 2588 uint8_t pad3[3]; // 229B 2589 /** 2590 * Backlight ramp reduction. 2591 */ 2592 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 2593 /** 2594 * Backlight ramp start. 2595 */ 2596 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 2597 }; 2598 2599 /** 2600 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2601 */ 2602 struct dmub_cmd_abm_set_pipe_data { 2603 /** 2604 * OTG HW instance. 2605 */ 2606 uint8_t otg_inst; 2607 2608 /** 2609 * Panel Control HW instance. 2610 */ 2611 uint8_t panel_inst; 2612 2613 /** 2614 * Controls how ABM will interpret a set pipe or set level command. 2615 */ 2616 uint8_t set_pipe_option; 2617 2618 /** 2619 * Unused. 2620 * TODO: Remove. 2621 */ 2622 uint8_t ramping_boundary; 2623 }; 2624 2625 /** 2626 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 2627 */ 2628 struct dmub_rb_cmd_abm_set_pipe { 2629 /** 2630 * Command header. 2631 */ 2632 struct dmub_cmd_header header; 2633 2634 /** 2635 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 2636 */ 2637 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 2638 }; 2639 2640 /** 2641 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2642 */ 2643 struct dmub_cmd_abm_set_backlight_data { 2644 /** 2645 * Number of frames to ramp to backlight user level. 2646 */ 2647 uint32_t frame_ramp; 2648 2649 /** 2650 * Requested backlight level from user. 2651 */ 2652 uint32_t backlight_user_level; 2653 2654 /** 2655 * ABM control version. 2656 */ 2657 uint8_t version; 2658 2659 /** 2660 * Panel Control HW instance mask. 2661 * Bit 0 is Panel Control HW instance 0. 2662 * Bit 1 is Panel Control HW instance 1. 2663 */ 2664 uint8_t panel_mask; 2665 2666 /** 2667 * Explicit padding to 4 byte boundary. 2668 */ 2669 uint8_t pad[2]; 2670 }; 2671 2672 /** 2673 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 2674 */ 2675 struct dmub_rb_cmd_abm_set_backlight { 2676 /** 2677 * Command header. 2678 */ 2679 struct dmub_cmd_header header; 2680 2681 /** 2682 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 2683 */ 2684 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 2685 }; 2686 2687 /** 2688 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2689 */ 2690 struct dmub_cmd_abm_set_level_data { 2691 /** 2692 * Set current ABM operating/aggression level. 2693 */ 2694 uint32_t level; 2695 2696 /** 2697 * ABM control version. 2698 */ 2699 uint8_t version; 2700 2701 /** 2702 * Panel Control HW instance mask. 2703 * Bit 0 is Panel Control HW instance 0. 2704 * Bit 1 is Panel Control HW instance 1. 2705 */ 2706 uint8_t panel_mask; 2707 2708 /** 2709 * Explicit padding to 4 byte boundary. 2710 */ 2711 uint8_t pad[2]; 2712 }; 2713 2714 /** 2715 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 2716 */ 2717 struct dmub_rb_cmd_abm_set_level { 2718 /** 2719 * Command header. 2720 */ 2721 struct dmub_cmd_header header; 2722 2723 /** 2724 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 2725 */ 2726 struct dmub_cmd_abm_set_level_data abm_set_level_data; 2727 }; 2728 2729 /** 2730 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2731 */ 2732 struct dmub_cmd_abm_set_ambient_level_data { 2733 /** 2734 * Ambient light sensor reading from OS. 2735 */ 2736 uint32_t ambient_lux; 2737 2738 /** 2739 * ABM control version. 2740 */ 2741 uint8_t version; 2742 2743 /** 2744 * Panel Control HW instance mask. 2745 * Bit 0 is Panel Control HW instance 0. 2746 * Bit 1 is Panel Control HW instance 1. 2747 */ 2748 uint8_t panel_mask; 2749 2750 /** 2751 * Explicit padding to 4 byte boundary. 2752 */ 2753 uint8_t pad[2]; 2754 }; 2755 2756 /** 2757 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2758 */ 2759 struct dmub_rb_cmd_abm_set_ambient_level { 2760 /** 2761 * Command header. 2762 */ 2763 struct dmub_cmd_header header; 2764 2765 /** 2766 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 2767 */ 2768 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 2769 }; 2770 2771 /** 2772 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2773 */ 2774 struct dmub_cmd_abm_set_pwm_frac_data { 2775 /** 2776 * Enable/disable fractional duty cycle for backlight PWM. 2777 * TODO: Convert to uint8_t. 2778 */ 2779 uint32_t fractional_pwm; 2780 2781 /** 2782 * ABM control version. 2783 */ 2784 uint8_t version; 2785 2786 /** 2787 * Panel Control HW instance mask. 2788 * Bit 0 is Panel Control HW instance 0. 2789 * Bit 1 is Panel Control HW instance 1. 2790 */ 2791 uint8_t panel_mask; 2792 2793 /** 2794 * Explicit padding to 4 byte boundary. 2795 */ 2796 uint8_t pad[2]; 2797 }; 2798 2799 /** 2800 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 2801 */ 2802 struct dmub_rb_cmd_abm_set_pwm_frac { 2803 /** 2804 * Command header. 2805 */ 2806 struct dmub_cmd_header header; 2807 2808 /** 2809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 2810 */ 2811 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 2812 }; 2813 2814 /** 2815 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2816 */ 2817 struct dmub_cmd_abm_init_config_data { 2818 /** 2819 * Location of indirect buffer used to pass init data to ABM. 2820 */ 2821 union dmub_addr src; 2822 2823 /** 2824 * Indirect buffer length. 2825 */ 2826 uint16_t bytes; 2827 2828 2829 /** 2830 * ABM control version. 2831 */ 2832 uint8_t version; 2833 2834 /** 2835 * Panel Control HW instance mask. 2836 * Bit 0 is Panel Control HW instance 0. 2837 * Bit 1 is Panel Control HW instance 1. 2838 */ 2839 uint8_t panel_mask; 2840 2841 /** 2842 * Explicit padding to 4 byte boundary. 2843 */ 2844 uint8_t pad[2]; 2845 }; 2846 2847 /** 2848 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 2849 */ 2850 struct dmub_rb_cmd_abm_init_config { 2851 /** 2852 * Command header. 2853 */ 2854 struct dmub_cmd_header header; 2855 2856 /** 2857 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 2858 */ 2859 struct dmub_cmd_abm_init_config_data abm_init_config_data; 2860 }; 2861 2862 /** 2863 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2864 */ 2865 2866 struct dmub_cmd_abm_pause_data { 2867 2868 /** 2869 * Panel Control HW instance mask. 2870 * Bit 0 is Panel Control HW instance 0. 2871 * Bit 1 is Panel Control HW instance 1. 2872 */ 2873 uint8_t panel_mask; 2874 2875 /** 2876 * OTG hw instance 2877 */ 2878 uint8_t otg_inst; 2879 2880 /** 2881 * Enable or disable ABM pause 2882 */ 2883 uint8_t enable; 2884 2885 /** 2886 * Explicit padding to 4 byte boundary. 2887 */ 2888 uint8_t pad[1]; 2889 }; 2890 2891 /** 2892 * Definition of a DMUB_CMD__ABM_PAUSE command. 2893 */ 2894 struct dmub_rb_cmd_abm_pause { 2895 /** 2896 * Command header. 2897 */ 2898 struct dmub_cmd_header header; 2899 2900 /** 2901 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 2902 */ 2903 struct dmub_cmd_abm_pause_data abm_pause_data; 2904 }; 2905 2906 /** 2907 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2908 */ 2909 struct dmub_cmd_query_feature_caps_data { 2910 /** 2911 * DMUB feature capabilities. 2912 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2913 */ 2914 struct dmub_feature_caps feature_caps; 2915 }; 2916 2917 /** 2918 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 2919 */ 2920 struct dmub_rb_cmd_query_feature_caps { 2921 /** 2922 * Command header. 2923 */ 2924 struct dmub_cmd_header header; 2925 /** 2926 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 2927 */ 2928 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 2929 }; 2930 2931 /** 2932 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2933 */ 2934 struct dmub_cmd_visual_confirm_color_data { 2935 /** 2936 * DMUB feature capabilities. 2937 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 2938 */ 2939 struct dmub_visual_confirm_color visual_confirm_color; 2940 }; 2941 2942 /** 2943 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2944 */ 2945 struct dmub_rb_cmd_get_visual_confirm_color { 2946 /** 2947 * Command header. 2948 */ 2949 struct dmub_cmd_header header; 2950 /** 2951 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 2952 */ 2953 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 2954 }; 2955 2956 struct dmub_optc_state { 2957 uint32_t v_total_max; 2958 uint32_t v_total_min; 2959 uint32_t tg_inst; 2960 }; 2961 2962 struct dmub_rb_cmd_drr_update { 2963 struct dmub_cmd_header header; 2964 struct dmub_optc_state dmub_optc_state_req; 2965 }; 2966 2967 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 2968 uint32_t pix_clk_100hz; 2969 uint8_t max_ramp_step; 2970 uint8_t pipes; 2971 uint8_t min_refresh_in_hz; 2972 uint8_t padding[1]; 2973 }; 2974 2975 struct dmub_cmd_fw_assisted_mclk_switch_config { 2976 uint8_t fams_enabled; 2977 uint8_t visual_confirm_enabled; 2978 uint8_t padding[2]; 2979 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_STREAMS]; 2980 }; 2981 2982 struct dmub_rb_cmd_fw_assisted_mclk_switch { 2983 struct dmub_cmd_header header; 2984 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 2985 }; 2986 2987 /** 2988 * enum dmub_cmd_panel_cntl_type - Panel control command. 2989 */ 2990 enum dmub_cmd_panel_cntl_type { 2991 /** 2992 * Initializes embedded panel hardware blocks. 2993 */ 2994 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 2995 /** 2996 * Queries backlight info for the embedded panel. 2997 */ 2998 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 2999 }; 3000 3001 /** 3002 * struct dmub_cmd_panel_cntl_data - Panel control data. 3003 */ 3004 struct dmub_cmd_panel_cntl_data { 3005 uint32_t inst; /**< panel instance */ 3006 uint32_t current_backlight; /* in/out */ 3007 uint32_t bl_pwm_cntl; /* in/out */ 3008 uint32_t bl_pwm_period_cntl; /* in/out */ 3009 uint32_t bl_pwm_ref_div1; /* in/out */ 3010 uint8_t is_backlight_on : 1; /* in/out */ 3011 uint8_t is_powered_on : 1; /* in/out */ 3012 uint8_t padding[3]; 3013 uint32_t bl_pwm_ref_div2; /* in/out */ 3014 uint8_t reserved[4]; 3015 }; 3016 3017 /** 3018 * struct dmub_rb_cmd_panel_cntl - Panel control command. 3019 */ 3020 struct dmub_rb_cmd_panel_cntl { 3021 struct dmub_cmd_header header; /**< header */ 3022 struct dmub_cmd_panel_cntl_data data; /**< payload */ 3023 }; 3024 3025 /** 3026 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3027 */ 3028 struct dmub_cmd_lvtma_control_data { 3029 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 3030 uint8_t reserved_0[3]; /**< For future use */ 3031 uint8_t panel_inst; /**< LVTMA control instance */ 3032 uint8_t reserved_1[3]; /**< For future use */ 3033 }; 3034 3035 /** 3036 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3037 */ 3038 struct dmub_rb_cmd_lvtma_control { 3039 /** 3040 * Command header. 3041 */ 3042 struct dmub_cmd_header header; 3043 /** 3044 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3045 */ 3046 struct dmub_cmd_lvtma_control_data data; 3047 }; 3048 3049 /** 3050 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3051 */ 3052 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 3053 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 3054 uint8_t is_usb; /**< is phy is usb */ 3055 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 3056 uint8_t is_dp4; /**< is dp in 4 lane */ 3057 }; 3058 3059 /** 3060 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3061 */ 3062 struct dmub_rb_cmd_transmitter_query_dp_alt { 3063 struct dmub_cmd_header header; /**< header */ 3064 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 3065 }; 3066 3067 /** 3068 * Maximum number of bytes a chunk sent to DMUB for parsing 3069 */ 3070 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 3071 3072 /** 3073 * Represent a chunk of CEA blocks sent to DMUB for parsing 3074 */ 3075 struct dmub_cmd_send_edid_cea { 3076 uint16_t offset; /**< offset into the CEA block */ 3077 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 3078 uint16_t cea_total_length; /**< total length of the CEA block */ 3079 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 3080 uint8_t pad[3]; /**< padding and for future expansion */ 3081 }; 3082 3083 /** 3084 * Result of VSDB parsing from CEA block 3085 */ 3086 struct dmub_cmd_edid_cea_amd_vsdb { 3087 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 3088 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 3089 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 3090 uint16_t min_frame_rate; /**< Maximum frame rate */ 3091 uint16_t max_frame_rate; /**< Minimum frame rate */ 3092 }; 3093 3094 /** 3095 * Result of sending a CEA chunk 3096 */ 3097 struct dmub_cmd_edid_cea_ack { 3098 uint16_t offset; /**< offset of the chunk into the CEA block */ 3099 uint8_t success; /**< 1 if this sending of chunk succeeded */ 3100 uint8_t pad; /**< padding and for future expansion */ 3101 }; 3102 3103 /** 3104 * Specify whether the result is an ACK/NACK or the parsing has finished 3105 */ 3106 enum dmub_cmd_edid_cea_reply_type { 3107 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 3108 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 3109 }; 3110 3111 /** 3112 * Definition of a DMUB_CMD__EDID_CEA command. 3113 */ 3114 struct dmub_rb_cmd_edid_cea { 3115 struct dmub_cmd_header header; /**< Command header */ 3116 union dmub_cmd_edid_cea_data { 3117 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 3118 struct dmub_cmd_edid_cea_output { /**< output with results */ 3119 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 3120 union { 3121 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 3122 struct dmub_cmd_edid_cea_ack ack; 3123 }; 3124 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 3125 } data; /**< Command data */ 3126 3127 }; 3128 3129 /** 3130 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 3131 */ 3132 struct dmub_cmd_cable_id_input { 3133 uint8_t phy_inst; /**< phy inst for cable id data */ 3134 }; 3135 3136 /** 3137 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 3138 */ 3139 struct dmub_cmd_cable_id_output { 3140 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 3141 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 3142 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 3143 uint8_t RESERVED :2; /**< reserved means not defined */ 3144 }; 3145 3146 /** 3147 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 3148 */ 3149 struct dmub_rb_cmd_get_usbc_cable_id { 3150 struct dmub_cmd_header header; /**< Command header */ 3151 /** 3152 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 3153 */ 3154 union dmub_cmd_cable_id_data { 3155 struct dmub_cmd_cable_id_input input; /**< Input */ 3156 struct dmub_cmd_cable_id_output output; /**< Output */ 3157 uint8_t output_raw; /**< Raw data output */ 3158 } data; 3159 }; 3160 3161 /** 3162 * Command type of a DMUB_CMD__SECURE_DISPLAY command 3163 */ 3164 enum dmub_cmd_secure_display_type { 3165 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 3166 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 3167 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY 3168 }; 3169 3170 /** 3171 * Definition of a DMUB_CMD__SECURE_DISPLAY command 3172 */ 3173 struct dmub_rb_cmd_secure_display { 3174 struct dmub_cmd_header header; 3175 /** 3176 * Data passed from driver to dmub firmware. 3177 */ 3178 struct dmub_cmd_roi_info { 3179 uint16_t x_start; 3180 uint16_t x_end; 3181 uint16_t y_start; 3182 uint16_t y_end; 3183 uint8_t otg_id; 3184 uint8_t phy_id; 3185 } roi_info; 3186 }; 3187 3188 /** 3189 * union dmub_rb_cmd - DMUB inbox command. 3190 */ 3191 union dmub_rb_cmd { 3192 /** 3193 * Elements shared with all commands. 3194 */ 3195 struct dmub_rb_cmd_common cmd_common; 3196 /** 3197 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 3198 */ 3199 struct dmub_rb_cmd_read_modify_write read_modify_write; 3200 /** 3201 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 3202 */ 3203 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 3204 /** 3205 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 3206 */ 3207 struct dmub_rb_cmd_burst_write burst_write; 3208 /** 3209 * Definition of a DMUB_CMD__REG_REG_WAIT command. 3210 */ 3211 struct dmub_rb_cmd_reg_wait reg_wait; 3212 /** 3213 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 3214 */ 3215 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 3216 /** 3217 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 3218 */ 3219 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 3220 /** 3221 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 3222 */ 3223 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 3224 /** 3225 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 3226 */ 3227 struct dmub_rb_cmd_dpphy_init dpphy_init; 3228 /** 3229 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 3230 */ 3231 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 3232 /** 3233 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3234 */ 3235 struct dmub_rb_cmd_psr_set_version psr_set_version; 3236 /** 3237 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3238 */ 3239 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 3240 /** 3241 * Definition of a DMUB_CMD__PSR_ENABLE command. 3242 */ 3243 struct dmub_rb_cmd_psr_enable psr_enable; 3244 /** 3245 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3246 */ 3247 struct dmub_rb_cmd_psr_set_level psr_set_level; 3248 /** 3249 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3250 */ 3251 struct dmub_rb_cmd_psr_force_static psr_force_static; 3252 /** 3253 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3254 */ 3255 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 3256 /** 3257 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3258 */ 3259 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 3260 /** 3261 * Definition of a DMUB_CMD__HW_LOCK command. 3262 * Command is used by driver and FW. 3263 */ 3264 struct dmub_rb_cmd_lock_hw lock_hw; 3265 /** 3266 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3267 */ 3268 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 3269 /** 3270 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3271 */ 3272 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 3273 /** 3274 * Definition of a DMUB_CMD__PLAT_54186_WA command. 3275 */ 3276 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 3277 /** 3278 * Definition of a DMUB_CMD__MALL command. 3279 */ 3280 struct dmub_rb_cmd_mall mall; 3281 /** 3282 * Definition of a DMUB_CMD__CAB command. 3283 */ 3284 struct dmub_rb_cmd_cab_for_ss cab; 3285 3286 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 3287 3288 /** 3289 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 3290 */ 3291 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 3292 3293 /** 3294 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 3295 */ 3296 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 3297 3298 /** 3299 * Definition of DMUB_CMD__PANEL_CNTL commands. 3300 */ 3301 struct dmub_rb_cmd_panel_cntl panel_cntl; 3302 /** 3303 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 3304 */ 3305 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 3306 3307 /** 3308 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 3309 */ 3310 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 3311 3312 /** 3313 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 3314 */ 3315 struct dmub_rb_cmd_abm_set_level abm_set_level; 3316 3317 /** 3318 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 3319 */ 3320 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 3321 3322 /** 3323 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 3324 */ 3325 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 3326 3327 /** 3328 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 3329 */ 3330 struct dmub_rb_cmd_abm_init_config abm_init_config; 3331 3332 /** 3333 * Definition of a DMUB_CMD__ABM_PAUSE command. 3334 */ 3335 struct dmub_rb_cmd_abm_pause abm_pause; 3336 3337 /** 3338 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 3339 */ 3340 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 3341 3342 /** 3343 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 3344 */ 3345 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 3346 3347 /** 3348 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 3349 */ 3350 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 3351 3352 /** 3353 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 3354 */ 3355 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 3356 struct dmub_rb_cmd_drr_update drr_update; 3357 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 3358 3359 /** 3360 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 3361 */ 3362 struct dmub_rb_cmd_lvtma_control lvtma_control; 3363 /** 3364 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 3365 */ 3366 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 3367 /** 3368 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 3369 */ 3370 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 3371 /** 3372 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 3373 */ 3374 struct dmub_rb_cmd_set_config_access set_config_access; 3375 /** 3376 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 3377 */ 3378 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 3379 /** 3380 * Definition of a DMUB_CMD__EDID_CEA command. 3381 */ 3382 struct dmub_rb_cmd_edid_cea edid_cea; 3383 /** 3384 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 3385 */ 3386 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 3387 3388 /** 3389 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3390 */ 3391 struct dmub_rb_cmd_query_hpd_state query_hpd; 3392 /** 3393 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 3394 */ 3395 struct dmub_rb_cmd_secure_display secure_display; 3396 3397 /** 3398 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 3399 */ 3400 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 3401 }; 3402 3403 /** 3404 * union dmub_rb_out_cmd - Outbox command 3405 */ 3406 union dmub_rb_out_cmd { 3407 /** 3408 * Parameters common to every command. 3409 */ 3410 struct dmub_rb_cmd_common cmd_common; 3411 /** 3412 * AUX reply command. 3413 */ 3414 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 3415 /** 3416 * HPD notify command. 3417 */ 3418 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 3419 /** 3420 * SET_CONFIG reply command. 3421 */ 3422 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 3423 }; 3424 #pragma pack(pop) 3425 3426 3427 //============================================================================== 3428 //</DMUB_CMD>=================================================================== 3429 //============================================================================== 3430 //< DMUB_RB>==================================================================== 3431 //============================================================================== 3432 3433 #if defined(__cplusplus) 3434 extern "C" { 3435 #endif 3436 3437 /** 3438 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 3439 */ 3440 struct dmub_rb_init_params { 3441 void *ctx; /**< Caller provided context pointer */ 3442 void *base_address; /**< CPU base address for ring's data */ 3443 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3444 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 3445 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 3446 }; 3447 3448 /** 3449 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 3450 */ 3451 struct dmub_rb { 3452 void *base_address; /**< CPU address for the ring's data */ 3453 uint32_t rptr; /**< Read pointer for consumer in bytes */ 3454 uint32_t wrpt; /**< Write pointer for producer in bytes */ 3455 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 3456 3457 void *ctx; /**< Caller provided context pointer */ 3458 void *dmub; /**< Pointer to the DMUB interface */ 3459 }; 3460 3461 /** 3462 * @brief Checks if the ringbuffer is empty. 3463 * 3464 * @param rb DMUB Ringbuffer 3465 * @return true if empty 3466 * @return false otherwise 3467 */ 3468 static inline bool dmub_rb_empty(struct dmub_rb *rb) 3469 { 3470 return (rb->wrpt == rb->rptr); 3471 } 3472 3473 /** 3474 * @brief Checks if the ringbuffer is full 3475 * 3476 * @param rb DMUB Ringbuffer 3477 * @return true if full 3478 * @return false otherwise 3479 */ 3480 static inline bool dmub_rb_full(struct dmub_rb *rb) 3481 { 3482 uint32_t data_count; 3483 3484 if (rb->wrpt >= rb->rptr) 3485 data_count = rb->wrpt - rb->rptr; 3486 else 3487 data_count = rb->capacity - (rb->rptr - rb->wrpt); 3488 3489 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 3490 } 3491 3492 /** 3493 * @brief Pushes a command into the ringbuffer 3494 * 3495 * @param rb DMUB ringbuffer 3496 * @param cmd The command to push 3497 * @return true if the ringbuffer was not full 3498 * @return false otherwise 3499 */ 3500 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 3501 const union dmub_rb_cmd *cmd) 3502 { 3503 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 3504 const uint64_t *src = (const uint64_t *)cmd; 3505 uint8_t i; 3506 3507 if (dmub_rb_full(rb)) 3508 return false; 3509 3510 // copying data 3511 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3512 *dst++ = *src++; 3513 3514 rb->wrpt += DMUB_RB_CMD_SIZE; 3515 3516 if (rb->wrpt >= rb->capacity) 3517 rb->wrpt %= rb->capacity; 3518 3519 return true; 3520 } 3521 3522 /** 3523 * @brief Pushes a command into the DMUB outbox ringbuffer 3524 * 3525 * @param rb DMUB outbox ringbuffer 3526 * @param cmd Outbox command 3527 * @return true if not full 3528 * @return false otherwise 3529 */ 3530 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 3531 const union dmub_rb_out_cmd *cmd) 3532 { 3533 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 3534 const uint8_t *src = (const uint8_t *)cmd; 3535 3536 if (dmub_rb_full(rb)) 3537 return false; 3538 3539 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 3540 3541 rb->wrpt += DMUB_RB_CMD_SIZE; 3542 3543 if (rb->wrpt >= rb->capacity) 3544 rb->wrpt %= rb->capacity; 3545 3546 return true; 3547 } 3548 3549 /** 3550 * @brief Returns the next unprocessed command in the ringbuffer. 3551 * 3552 * @param rb DMUB ringbuffer 3553 * @param cmd The command to return 3554 * @return true if not empty 3555 * @return false otherwise 3556 */ 3557 static inline bool dmub_rb_front(struct dmub_rb *rb, 3558 union dmub_rb_cmd **cmd) 3559 { 3560 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 3561 3562 if (dmub_rb_empty(rb)) 3563 return false; 3564 3565 *cmd = (union dmub_rb_cmd *)rb_cmd; 3566 3567 return true; 3568 } 3569 3570 /** 3571 * @brief Determines the next ringbuffer offset. 3572 * 3573 * @param rb DMUB inbox ringbuffer 3574 * @param num_cmds Number of commands 3575 * @param next_rptr The next offset in the ringbuffer 3576 */ 3577 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 3578 uint32_t num_cmds, 3579 uint32_t *next_rptr) 3580 { 3581 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 3582 3583 if (*next_rptr >= rb->capacity) 3584 *next_rptr %= rb->capacity; 3585 } 3586 3587 /** 3588 * @brief Returns a pointer to a command in the inbox. 3589 * 3590 * @param rb DMUB inbox ringbuffer 3591 * @param cmd The inbox command to return 3592 * @param rptr The ringbuffer offset 3593 * @return true if not empty 3594 * @return false otherwise 3595 */ 3596 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 3597 union dmub_rb_cmd **cmd, 3598 uint32_t rptr) 3599 { 3600 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 3601 3602 if (dmub_rb_empty(rb)) 3603 return false; 3604 3605 *cmd = (union dmub_rb_cmd *)rb_cmd; 3606 3607 return true; 3608 } 3609 3610 /** 3611 * @brief Returns the next unprocessed command in the outbox. 3612 * 3613 * @param rb DMUB outbox ringbuffer 3614 * @param cmd The outbox command to return 3615 * @return true if not empty 3616 * @return false otherwise 3617 */ 3618 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 3619 union dmub_rb_out_cmd *cmd) 3620 { 3621 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 3622 uint64_t *dst = (uint64_t *)cmd; 3623 uint8_t i; 3624 3625 if (dmub_rb_empty(rb)) 3626 return false; 3627 3628 // copying data 3629 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3630 *dst++ = *src++; 3631 3632 return true; 3633 } 3634 3635 /** 3636 * @brief Removes the front entry in the ringbuffer. 3637 * 3638 * @param rb DMUB ringbuffer 3639 * @return true if the command was removed 3640 * @return false if there were no commands 3641 */ 3642 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 3643 { 3644 if (dmub_rb_empty(rb)) 3645 return false; 3646 3647 rb->rptr += DMUB_RB_CMD_SIZE; 3648 3649 if (rb->rptr >= rb->capacity) 3650 rb->rptr %= rb->capacity; 3651 3652 return true; 3653 } 3654 3655 /** 3656 * @brief Flushes commands in the ringbuffer to framebuffer memory. 3657 * 3658 * Avoids a race condition where DMCUB accesses memory while 3659 * there are still writes in flight to framebuffer. 3660 * 3661 * @param rb DMUB ringbuffer 3662 */ 3663 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 3664 { 3665 uint32_t rptr = rb->rptr; 3666 uint32_t wptr = rb->wrpt; 3667 3668 while (rptr != wptr) { 3669 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 3670 uint8_t i; 3671 3672 /* Don't remove this. 3673 * The contents need to actually be read from the ring buffer 3674 * for this function to be effective. 3675 */ 3676 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 3677 (void)READ_ONCE(*data++); 3678 3679 rptr += DMUB_RB_CMD_SIZE; 3680 if (rptr >= rb->capacity) 3681 rptr %= rb->capacity; 3682 } 3683 } 3684 3685 /** 3686 * @brief Initializes a DMCUB ringbuffer 3687 * 3688 * @param rb DMUB ringbuffer 3689 * @param init_params initial configuration for the ringbuffer 3690 */ 3691 static inline void dmub_rb_init(struct dmub_rb *rb, 3692 struct dmub_rb_init_params *init_params) 3693 { 3694 rb->base_address = init_params->base_address; 3695 rb->capacity = init_params->capacity; 3696 rb->rptr = init_params->read_ptr; 3697 rb->wrpt = init_params->write_ptr; 3698 } 3699 3700 /** 3701 * @brief Copies output data from in/out commands into the given command. 3702 * 3703 * @param rb DMUB ringbuffer 3704 * @param cmd Command to copy data into 3705 */ 3706 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 3707 union dmub_rb_cmd *cmd) 3708 { 3709 // Copy rb entry back into command 3710 uint8_t *rd_ptr = (rb->rptr == 0) ? 3711 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 3712 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 3713 3714 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 3715 } 3716 3717 #if defined(__cplusplus) 3718 } 3719 #endif 3720 3721 //============================================================================== 3722 //</DMUB_RB>==================================================================== 3723 //============================================================================== 3724 3725 #endif /* _DMUB_CMD_H_ */ 3726