1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 #define DMUB_IPS1_ALLOW_MASK 0x00000001 794 #define DMUB_IPS2_ALLOW_MASK 0x00000002 795 #define DMUB_IPS1_COMMIT_MASK 0x00000004 796 #define DMUB_IPS2_COMMIT_MASK 0x00000008 797 798 /** 799 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 800 */ 801 union dmub_fw_boot_options { 802 struct { 803 uint32_t pemu_env : 1; /**< 1 if PEMU */ 804 uint32_t fpga_env : 1; /**< 1 if FPGA */ 805 uint32_t optimized_init : 1; /**< 1 if optimized init */ 806 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 807 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 808 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 809 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 810 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 811 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 812 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 813 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 814 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 815 uint32_t power_optimization: 1; 816 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 817 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 818 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 819 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 820 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 821 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 822 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 823 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 824 uint32_t ips_disable: 3; /* options to disable ips support*/ 825 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 826 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 827 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 828 uint32_t reserved : 6; /**< reserved */ 829 } bits; /**< boot bits */ 830 uint32_t all; /**< 32-bit access to bits */ 831 }; 832 833 enum dmub_fw_boot_options_bit { 834 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 835 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 836 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 837 }; 838 839 //============================================================================== 840 //< DMUB_SHARED_STATE>========================================================== 841 //============================================================================== 842 843 /** 844 * Shared firmware state between driver and firmware for lockless communication 845 * in situations where the inbox/outbox may be unavailable. 846 * 847 * Each structure *must* be at most 256-bytes in size. The layout allocation is 848 * described below: 849 * 850 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 851 */ 852 853 /** 854 * enum dmub_shared_state_feature_id - List of shared state features. 855 */ 856 enum dmub_shared_state_feature_id { 857 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 858 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 859 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 860 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 861 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 862 }; 863 864 /** 865 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 866 */ 867 union dmub_shared_state_ips_fw_signals { 868 struct { 869 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 870 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 871 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 872 uint32_t detection_required : 1; /**< 1 if detection is required */ 873 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 874 uint32_t reserved_bits : 27; /**< Reversed */ 875 } bits; 876 uint32_t all; 877 }; 878 879 /** 880 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 881 */ 882 union dmub_shared_state_ips_driver_signals { 883 struct { 884 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 885 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 886 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 887 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 888 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 889 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 890 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 891 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 892 uint32_t reserved_bits : 24; /**< Reversed bits */ 893 } bits; 894 uint32_t all; 895 }; 896 897 /** 898 * IPS FW Version 899 */ 900 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 901 902 struct dmub_shared_state_debug_setup { 903 union { 904 struct { 905 uint32_t exclude_points[62]; 906 } profile_mode; 907 }; 908 }; 909 910 /** 911 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 912 */ 913 struct dmub_shared_state_ips_fw { 914 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 915 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 916 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 917 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 918 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 919 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 920 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 921 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 922 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 923 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 924 }; /* 248-bytes, fixed */ 925 926 /** 927 * IPS Driver Version 928 */ 929 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 930 931 /** 932 * struct dmub_shared_state_ips_driver - Driver state for IPS. 933 */ 934 struct dmub_shared_state_ips_driver { 935 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 936 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 937 }; /* 248-bytes, fixed */ 938 939 /** 940 * enum dmub_shared_state_feature_common - Generic payload. 941 */ 942 struct dmub_shared_state_feature_common { 943 uint32_t padding[62]; 944 }; /* 248-bytes, fixed */ 945 946 /** 947 * enum dmub_shared_state_feature_header - Feature description. 948 */ 949 struct dmub_shared_state_feature_header { 950 uint16_t id; /**< Feature ID */ 951 uint16_t version; /**< Feature version */ 952 uint32_t reserved; /**< Reserved bytes. */ 953 }; /* 8 bytes, fixed */ 954 955 /** 956 * struct dmub_shared_state_feature_block - Feature block. 957 */ 958 struct dmub_shared_state_feature_block { 959 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 960 union dmub_shared_feature_state_union { 961 struct dmub_shared_state_feature_common common; /**< Generic data */ 962 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 963 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 964 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 965 } data; /**< Shared state data. */ 966 }; /* 256-bytes, fixed */ 967 968 /** 969 * Shared state size in bytes. 970 */ 971 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 972 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 973 974 //============================================================================== 975 //</DMUB_STATUS>================================================================ 976 //============================================================================== 977 //< DMUB_VBIOS>================================================================= 978 //============================================================================== 979 980 /* 981 * enum dmub_cmd_vbios_type - VBIOS commands. 982 * 983 * Command IDs should be treated as stable ABI. 984 * Do not reuse or modify IDs. 985 */ 986 enum dmub_cmd_vbios_type { 987 /** 988 * Configures the DIG encoder. 989 */ 990 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 991 /** 992 * Controls the PHY. 993 */ 994 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 995 /** 996 * Sets the pixel clock/symbol clock. 997 */ 998 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 999 /** 1000 * Enables or disables power gating. 1001 */ 1002 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1003 /** 1004 * Controls embedded panels. 1005 */ 1006 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1007 /** 1008 * Query DP alt status on a transmitter. 1009 */ 1010 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1011 /** 1012 * Control PHY FSM 1013 */ 1014 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1015 /** 1016 * Controls domain power gating 1017 */ 1018 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1019 }; 1020 1021 //============================================================================== 1022 //</DMUB_VBIOS>================================================================= 1023 //============================================================================== 1024 //< DMUB_GPINT>================================================================= 1025 //============================================================================== 1026 1027 /** 1028 * The shifts and masks below may alternatively be used to format and read 1029 * the command register bits. 1030 */ 1031 1032 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1033 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1034 1035 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1036 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1037 1038 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1039 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1040 1041 /** 1042 * Command responses. 1043 */ 1044 1045 /** 1046 * Return response for DMUB_GPINT__STOP_FW command. 1047 */ 1048 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1049 1050 /** 1051 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1052 */ 1053 union dmub_gpint_data_register { 1054 struct { 1055 uint32_t param : 16; /**< 16-bit parameter */ 1056 uint32_t command_code : 12; /**< GPINT command */ 1057 uint32_t status : 4; /**< Command status bit */ 1058 } bits; /**< GPINT bit access */ 1059 uint32_t all; /**< GPINT 32-bit access */ 1060 }; 1061 1062 /* 1063 * enum dmub_gpint_command - GPINT command to DMCUB FW 1064 * 1065 * Command IDs should be treated as stable ABI. 1066 * Do not reuse or modify IDs. 1067 */ 1068 enum dmub_gpint_command { 1069 /** 1070 * Invalid command, ignored. 1071 */ 1072 DMUB_GPINT__INVALID_COMMAND = 0, 1073 /** 1074 * DESC: Queries the firmware version. 1075 * RETURN: Firmware version. 1076 */ 1077 DMUB_GPINT__GET_FW_VERSION = 1, 1078 /** 1079 * DESC: Halts the firmware. 1080 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1081 */ 1082 DMUB_GPINT__STOP_FW = 2, 1083 /** 1084 * DESC: Get PSR state from FW. 1085 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1086 */ 1087 DMUB_GPINT__GET_PSR_STATE = 7, 1088 /** 1089 * DESC: Notifies DMCUB of the currently active streams. 1090 * ARGS: Stream mask, 1 bit per active stream index. 1091 */ 1092 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1093 /** 1094 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1095 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1096 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1097 * RETURN: PSR residency in milli-percent. 1098 */ 1099 DMUB_GPINT__PSR_RESIDENCY = 9, 1100 1101 /** 1102 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1103 */ 1104 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1105 1106 /** 1107 * DESC: Get REPLAY state from FW. 1108 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1109 */ 1110 DMUB_GPINT__GET_REPLAY_STATE = 13, 1111 1112 /** 1113 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1114 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1115 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1116 * RETURN: REPLAY residency in milli-percent. 1117 */ 1118 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1119 1120 /** 1121 * DESC: Copy bounding box to the host. 1122 * ARGS: Version of bounding box to copy 1123 * RETURN: Result of copying bounding box 1124 */ 1125 DMUB_GPINT__BB_COPY = 96, 1126 1127 /** 1128 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1129 * ARGS: The word3 for the 64 bit address 1130 */ 1131 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1132 1133 /** 1134 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1135 * ARGS: The word2 for the 64 bit address 1136 */ 1137 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1138 1139 /** 1140 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1141 * ARGS: The word1 for the 64 bit address 1142 */ 1143 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1144 1145 /** 1146 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1147 * ARGS: The word0 for the 64 bit address 1148 */ 1149 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1150 1151 /** 1152 * DESC: Updates the trace buffer lower 32-bit mask. 1153 * ARGS: The new mask 1154 * RETURN: Lower 32-bit mask. 1155 */ 1156 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1157 1158 /** 1159 * DESC: Updates the trace buffer mask bit0~bit15. 1160 * ARGS: The new mask 1161 * RETURN: Lower 32-bit mask. 1162 */ 1163 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1164 1165 /** 1166 * DESC: Updates the trace buffer mask bit16~bit31. 1167 * ARGS: The new mask 1168 * RETURN: Lower 32-bit mask. 1169 */ 1170 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1171 1172 /** 1173 * DESC: Updates the trace buffer mask bit32~bit47. 1174 * ARGS: The new mask 1175 * RETURN: Lower 32-bit mask. 1176 */ 1177 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1178 1179 /** 1180 * DESC: Updates the trace buffer mask bit48~bit63. 1181 * ARGS: The new mask 1182 * RETURN: Lower 32-bit mask. 1183 */ 1184 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1185 1186 /** 1187 * DESC: Read the trace buffer mask bi0~bit15. 1188 */ 1189 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1190 1191 /** 1192 * DESC: Read the trace buffer mask bit16~bit31. 1193 */ 1194 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1195 1196 /** 1197 * DESC: Read the trace buffer mask bi32~bit47. 1198 */ 1199 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1200 1201 /** 1202 * DESC: Updates the trace buffer mask bit32~bit63. 1203 */ 1204 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1205 1206 /** 1207 * DESC: Set IPS residency measurement 1208 * ARGS: 0 - Disable ips measurement 1209 * 1 - Enable ips measurement 1210 */ 1211 DMUB_GPINT__IPS_RESIDENCY = 121, 1212 1213 /** 1214 * DESC: Enable measurements for various task duration 1215 * ARGS: 0 - Disable measurement 1216 * 1 - Enable measurement 1217 */ 1218 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1219 1220 /** 1221 * DESC: Gets IPS residency in microseconds 1222 * ARGS: 0 - Return IPS1 residency 1223 * 1 - Return IPS2 residency 1224 * 2 - Return IPS1_RCG residency 1225 * 3 - Return IPS1_ONO2_ON residency 1226 * RETURN: Total residency in microseconds - lower 32 bits 1227 */ 1228 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1229 1230 /** 1231 * DESC: Gets IPS1 histogram counts 1232 * ARGS: Bucket index 1233 * RETURN: Total count for the bucket 1234 */ 1235 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1236 1237 /** 1238 * DESC: Gets IPS2 histogram counts 1239 * ARGS: Bucket index 1240 * RETURN: Total count for the bucket 1241 */ 1242 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1243 1244 /** 1245 * DESC: Gets IPS residency 1246 * ARGS: 0 - Return IPS1 residency 1247 * 1 - Return IPS2 residency 1248 * 2 - Return IPS1_RCG residency 1249 * 3 - Return IPS1_ONO2_ON residency 1250 * RETURN: Total residency in milli-percent. 1251 */ 1252 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1253 1254 /** 1255 * DESC: Gets IPS1_RCG histogram counts 1256 * ARGS: Bucket index 1257 * RETURN: Total count for the bucket 1258 */ 1259 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1260 1261 /** 1262 * DESC: Gets IPS1_ONO2_ON histogram counts 1263 * ARGS: Bucket index 1264 * RETURN: Total count for the bucket 1265 */ 1266 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1267 1268 /** 1269 * DESC: Gets IPS entry counter during residency measurement 1270 * ARGS: 0 - Return IPS1 entry counts 1271 * 1 - Return IPS2 entry counts 1272 * 2 - Return IPS1_RCG entry counts 1273 * 3 - Return IPS2_ONO2_ON entry counts 1274 * RETURN: Entry counter for selected IPS mode 1275 */ 1276 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1277 1278 /** 1279 * DESC: Gets IPS inactive residency in microseconds 1280 * ARGS: 0 - Return IPS1_MAX residency 1281 * 1 - Return IPS2 residency 1282 * 2 - Return IPS1_RCG residency 1283 * 3 - Return IPS1_ONO2_ON residency 1284 * RETURN: Total inactive residency in microseconds - lower 32 bits 1285 */ 1286 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1287 1288 /** 1289 * DESC: Gets IPS inactive residency in microseconds 1290 * ARGS: 0 - Return IPS1_MAX residency 1291 * 1 - Return IPS2 residency 1292 * 2 - Return IPS1_RCG residency 1293 * 3 - Return IPS1_ONO2_ON residency 1294 * RETURN: Total inactive residency in microseconds - upper 32 bits 1295 */ 1296 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1297 1298 /** 1299 * DESC: Gets IPS residency in microseconds 1300 * ARGS: 0 - Return IPS1 residency 1301 * 1 - Return IPS2 residency 1302 * 2 - Return IPS1_RCG residency 1303 * 3 - Return IPS1_ONO2_ON residency 1304 * RETURN: Total residency in microseconds - upper 32 bits 1305 */ 1306 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1307 /** 1308 * DESC: Setup debug configs. 1309 */ 1310 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1311 /** 1312 * DESC: Initiates IPS wake sequence. 1313 */ 1314 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1315 }; 1316 1317 /** 1318 * INBOX0 generic command definition 1319 */ 1320 union dmub_inbox0_cmd_common { 1321 struct { 1322 uint32_t command_code: 8; /**< INBOX0 command code */ 1323 uint32_t param: 24; /**< 24-bit parameter */ 1324 } bits; 1325 uint32_t all; 1326 }; 1327 1328 /** 1329 * INBOX0 hw_lock command definition 1330 */ 1331 union dmub_inbox0_cmd_lock_hw { 1332 struct { 1333 uint32_t command_code: 8; 1334 1335 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1336 uint32_t hw_lock_client: 2; 1337 1338 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1339 uint32_t otg_inst: 3; 1340 uint32_t opp_inst: 3; 1341 uint32_t dig_inst: 3; 1342 1343 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1344 uint32_t lock_pipe: 1; 1345 uint32_t lock_cursor: 1; 1346 uint32_t lock_dig: 1; 1347 uint32_t triple_buffer_lock: 1; 1348 1349 uint32_t lock: 1; /**< Lock */ 1350 uint32_t should_release: 1; /**< Release */ 1351 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1352 } bits; 1353 uint32_t all; 1354 }; 1355 1356 union dmub_inbox0_data_register { 1357 union dmub_inbox0_cmd_common inbox0_cmd_common; 1358 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1359 }; 1360 1361 enum dmub_inbox0_command { 1362 /** 1363 * DESC: Invalid command, ignored. 1364 */ 1365 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1366 /** 1367 * DESC: Notification to acquire/release HW lock 1368 * ARGS: 1369 */ 1370 DMUB_INBOX0_CMD__HW_LOCK = 1, 1371 }; 1372 //============================================================================== 1373 //</DMUB_GPINT>================================================================= 1374 //============================================================================== 1375 //< DMUB_CMD>=================================================================== 1376 //============================================================================== 1377 1378 /** 1379 * Size in bytes of each DMUB command. 1380 */ 1381 #define DMUB_RB_CMD_SIZE 64 1382 1383 /** 1384 * Maximum number of items in the DMUB ringbuffer. 1385 */ 1386 #define DMUB_RB_MAX_ENTRY 128 1387 1388 /** 1389 * Ringbuffer size in bytes. 1390 */ 1391 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1392 1393 /** 1394 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1395 */ 1396 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1397 1398 /** 1399 * Ringbuffer size in bytes. 1400 */ 1401 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1402 1403 /** 1404 * REG_SET mask for reg offload. 1405 */ 1406 #define REG_SET_MASK 0xFFFF 1407 1408 /* 1409 * enum dmub_cmd_type - DMUB inbox command. 1410 * 1411 * Command IDs should be treated as stable ABI. 1412 * Do not reuse or modify IDs. 1413 */ 1414 enum dmub_cmd_type { 1415 /** 1416 * Invalid command. 1417 */ 1418 DMUB_CMD__NULL = 0, 1419 /** 1420 * Read modify write register sequence offload. 1421 */ 1422 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1423 /** 1424 * Field update register sequence offload. 1425 */ 1426 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1427 /** 1428 * Burst write sequence offload. 1429 */ 1430 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1431 /** 1432 * Reg wait sequence offload. 1433 */ 1434 DMUB_CMD__REG_REG_WAIT = 4, 1435 /** 1436 * Workaround to avoid HUBP underflow during NV12 playback. 1437 */ 1438 DMUB_CMD__PLAT_54186_WA = 5, 1439 /** 1440 * Command type used to query FW feature caps. 1441 */ 1442 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1443 /** 1444 * Command type used to get visual confirm color. 1445 */ 1446 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1447 /** 1448 * Command type used for all PSR commands. 1449 */ 1450 DMUB_CMD__PSR = 64, 1451 /** 1452 * Command type used for all MALL commands. 1453 */ 1454 DMUB_CMD__MALL = 65, 1455 /** 1456 * Command type used for all ABM commands. 1457 */ 1458 DMUB_CMD__ABM = 66, 1459 /** 1460 * Command type used to update dirty rects in FW. 1461 */ 1462 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1463 /** 1464 * Command type used to update cursor info in FW. 1465 */ 1466 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1467 /** 1468 * Command type used for HW locking in FW. 1469 */ 1470 DMUB_CMD__HW_LOCK = 69, 1471 /** 1472 * Command type used to access DP AUX. 1473 */ 1474 DMUB_CMD__DP_AUX_ACCESS = 70, 1475 /** 1476 * Command type used for OUTBOX1 notification enable 1477 */ 1478 DMUB_CMD__OUTBOX1_ENABLE = 71, 1479 1480 /** 1481 * Command type used for all idle optimization commands. 1482 */ 1483 DMUB_CMD__IDLE_OPT = 72, 1484 /** 1485 * Command type used for all clock manager commands. 1486 */ 1487 DMUB_CMD__CLK_MGR = 73, 1488 /** 1489 * Command type used for all panel control commands. 1490 */ 1491 DMUB_CMD__PANEL_CNTL = 74, 1492 1493 /** 1494 * Command type used for all CAB commands. 1495 */ 1496 DMUB_CMD__CAB_FOR_SS = 75, 1497 1498 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1499 1500 /** 1501 * Command type used for interfacing with DPIA. 1502 */ 1503 DMUB_CMD__DPIA = 77, 1504 /** 1505 * Command type used for EDID CEA parsing 1506 */ 1507 DMUB_CMD__EDID_CEA = 79, 1508 /** 1509 * Command type used for getting usbc cable ID 1510 */ 1511 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1512 /** 1513 * Command type used to query HPD state. 1514 */ 1515 DMUB_CMD__QUERY_HPD_STATE = 82, 1516 /** 1517 * Command type used for all VBIOS interface commands. 1518 */ 1519 /** 1520 * Command type used for all REPLAY commands. 1521 */ 1522 DMUB_CMD__REPLAY = 83, 1523 1524 /** 1525 * Command type used for all SECURE_DISPLAY commands. 1526 */ 1527 DMUB_CMD__SECURE_DISPLAY = 85, 1528 1529 /** 1530 * Command type used to set DPIA HPD interrupt state 1531 */ 1532 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1533 1534 /** 1535 * Command type used for all PSP commands. 1536 */ 1537 DMUB_CMD__PSP = 88, 1538 1539 /** 1540 * Command type used for all Fused IO commands. 1541 */ 1542 DMUB_CMD__FUSED_IO = 89, 1543 1544 /** 1545 * Command type used for all LSDMA commands. 1546 */ 1547 DMUB_CMD__LSDMA = 90, 1548 1549 DMUB_CMD__VBIOS = 128, 1550 }; 1551 1552 /** 1553 * enum dmub_out_cmd_type - DMUB outbox commands. 1554 */ 1555 enum dmub_out_cmd_type { 1556 /** 1557 * Invalid outbox command, ignored. 1558 */ 1559 DMUB_OUT_CMD__NULL = 0, 1560 /** 1561 * Command type used for DP AUX Reply data notification 1562 */ 1563 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1564 /** 1565 * Command type used for DP HPD event notification 1566 */ 1567 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1568 /** 1569 * Command type used for SET_CONFIG Reply notification 1570 */ 1571 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1572 /** 1573 * Command type used for USB4 DPIA notification 1574 */ 1575 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1576 /** 1577 * Command type used for HPD redetect notification 1578 */ 1579 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1580 /** 1581 * Command type used for Fused IO notification 1582 */ 1583 DMUB_OUT_CMD__FUSED_IO = 7, 1584 }; 1585 1586 /* DMUB_CMD__DPIA command sub-types. */ 1587 enum dmub_cmd_dpia_type { 1588 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1589 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1590 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1591 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1592 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1593 }; 1594 1595 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1596 enum dmub_cmd_dpia_notification_type { 1597 DPIA_NOTIFY__BW_ALLOCATION = 0, 1598 }; 1599 1600 #pragma pack(push, 1) 1601 1602 /** 1603 * struct dmub_cmd_header - Common command header fields. 1604 */ 1605 struct dmub_cmd_header { 1606 unsigned int type : 8; /**< command type */ 1607 unsigned int sub_type : 8; /**< command sub type */ 1608 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1609 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1610 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1611 unsigned int reserved0 : 5; /**< reserved bits */ 1612 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1613 unsigned int reserved1 : 2; /**< reserved bits */ 1614 }; 1615 1616 /* 1617 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1618 * 1619 * 60 payload bytes can hold up to 5 sets of read modify writes, 1620 * each take 3 dwords. 1621 * 1622 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1623 * 1624 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1625 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1626 */ 1627 struct dmub_cmd_read_modify_write_sequence { 1628 uint32_t addr; /**< register address */ 1629 uint32_t modify_mask; /**< modify mask */ 1630 uint32_t modify_value; /**< modify value */ 1631 }; 1632 1633 /** 1634 * Maximum number of ops in read modify write sequence. 1635 */ 1636 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1637 1638 /** 1639 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1640 */ 1641 struct dmub_rb_cmd_read_modify_write { 1642 struct dmub_cmd_header header; /**< command header */ 1643 /** 1644 * Read modify write sequence. 1645 */ 1646 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1647 }; 1648 1649 /* 1650 * Update a register with specified masks and values sequeunce 1651 * 1652 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1653 * 1654 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1655 * 1656 * 1657 * USE CASE: 1658 * 1. auto-increment register where additional read would update pointer and produce wrong result 1659 * 2. toggle a bit without read in the middle 1660 */ 1661 1662 struct dmub_cmd_reg_field_update_sequence { 1663 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1664 uint32_t modify_value; /**< value to update with */ 1665 }; 1666 1667 /** 1668 * Maximum number of ops in field update sequence. 1669 */ 1670 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1671 1672 /** 1673 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1674 */ 1675 struct dmub_rb_cmd_reg_field_update_sequence { 1676 struct dmub_cmd_header header; /**< command header */ 1677 uint32_t addr; /**< register address */ 1678 /** 1679 * Field update sequence. 1680 */ 1681 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1682 }; 1683 1684 1685 /** 1686 * Maximum number of burst write values. 1687 */ 1688 #define DMUB_BURST_WRITE_VALUES__MAX 14 1689 1690 /* 1691 * struct dmub_rb_cmd_burst_write - Burst write 1692 * 1693 * support use case such as writing out LUTs. 1694 * 1695 * 60 payload bytes can hold up to 14 values to write to given address 1696 * 1697 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1698 */ 1699 struct dmub_rb_cmd_burst_write { 1700 struct dmub_cmd_header header; /**< command header */ 1701 uint32_t addr; /**< register start address */ 1702 /** 1703 * Burst write register values. 1704 */ 1705 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1706 }; 1707 1708 /** 1709 * struct dmub_rb_cmd_common - Common command header 1710 */ 1711 struct dmub_rb_cmd_common { 1712 struct dmub_cmd_header header; /**< command header */ 1713 /** 1714 * Padding to RB_CMD_SIZE 1715 */ 1716 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1717 }; 1718 1719 /** 1720 * struct dmub_cmd_reg_wait_data - Register wait data 1721 */ 1722 struct dmub_cmd_reg_wait_data { 1723 uint32_t addr; /**< Register address */ 1724 uint32_t mask; /**< Mask for register bits */ 1725 uint32_t condition_field_value; /**< Value to wait for */ 1726 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1727 }; 1728 1729 /** 1730 * struct dmub_rb_cmd_reg_wait - Register wait command 1731 */ 1732 struct dmub_rb_cmd_reg_wait { 1733 struct dmub_cmd_header header; /**< Command header */ 1734 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1735 }; 1736 1737 /** 1738 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1739 * 1740 * Reprograms surface parameters to avoid underflow. 1741 */ 1742 struct dmub_cmd_PLAT_54186_wa { 1743 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1744 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1745 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1746 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1747 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1748 struct { 1749 uint32_t hubp_inst : 4; /**< HUBP instance */ 1750 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1751 uint32_t immediate :1; /**< Immediate flip */ 1752 uint32_t vmid : 4; /**< VMID */ 1753 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1754 uint32_t reserved : 21; /**< Reserved */ 1755 } flip_params; /**< Pageflip parameters */ 1756 uint32_t reserved[9]; /**< Reserved bits */ 1757 }; 1758 1759 /** 1760 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1761 */ 1762 struct dmub_rb_cmd_PLAT_54186_wa { 1763 struct dmub_cmd_header header; /**< Command header */ 1764 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1765 }; 1766 1767 /** 1768 * enum dmub_cmd_mall_type - MALL commands 1769 */ 1770 enum dmub_cmd_mall_type { 1771 /** 1772 * Allows display refresh from MALL. 1773 */ 1774 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1775 /** 1776 * Disallows display refresh from MALL. 1777 */ 1778 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1779 /** 1780 * Cursor copy for MALL. 1781 */ 1782 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1783 /** 1784 * Controls DF requests. 1785 */ 1786 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1787 }; 1788 1789 /** 1790 * struct dmub_rb_cmd_mall - MALL command data. 1791 */ 1792 struct dmub_rb_cmd_mall { 1793 struct dmub_cmd_header header; /**< Common command header */ 1794 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1795 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1796 uint32_t tmr_delay; /**< Timer delay */ 1797 uint32_t tmr_scale; /**< Timer scale */ 1798 uint16_t cursor_width; /**< Cursor width in pixels */ 1799 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1800 uint16_t cursor_height; /**< Cursor height in pixels */ 1801 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1802 uint8_t debug_bits; /**< Debug bits */ 1803 1804 uint8_t reserved1; /**< Reserved bits */ 1805 uint8_t reserved2; /**< Reserved bits */ 1806 }; 1807 1808 /** 1809 * enum dmub_cmd_cab_type - CAB command data. 1810 */ 1811 enum dmub_cmd_cab_type { 1812 /** 1813 * No idle optimizations (i.e. no CAB) 1814 */ 1815 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1816 /** 1817 * No DCN requests for memory 1818 */ 1819 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1820 /** 1821 * Fit surfaces in CAB (i.e. CAB enable) 1822 */ 1823 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1824 /** 1825 * Do not fit surfaces in CAB (i.e. no CAB) 1826 */ 1827 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1828 }; 1829 1830 /** 1831 * struct dmub_rb_cmd_cab - CAB command data. 1832 */ 1833 struct dmub_rb_cmd_cab_for_ss { 1834 struct dmub_cmd_header header; 1835 uint8_t cab_alloc_ways; /* total number of ways */ 1836 uint8_t debug_bits; /* debug bits */ 1837 }; 1838 1839 /** 1840 * Enum for indicating which MCLK switch mode per pipe 1841 */ 1842 enum mclk_switch_mode { 1843 NONE = 0, 1844 FPO = 1, 1845 SUBVP = 2, 1846 VBLANK = 3, 1847 }; 1848 1849 /* Per pipe struct which stores the MCLK switch mode 1850 * data to be sent to DMUB. 1851 * Named "v2" for now -- once FPO and SUBVP are fully merged 1852 * the type name can be updated 1853 */ 1854 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1855 union { 1856 struct { 1857 uint32_t pix_clk_100hz; 1858 uint16_t main_vblank_start; 1859 uint16_t main_vblank_end; 1860 uint16_t mall_region_lines; 1861 uint16_t prefetch_lines; 1862 uint16_t prefetch_to_mall_start_lines; 1863 uint16_t processing_delay_lines; 1864 uint16_t htotal; // required to calculate line time for multi-display cases 1865 uint16_t vtotal; 1866 uint8_t main_pipe_index; 1867 uint8_t phantom_pipe_index; 1868 /* Since the microschedule is calculated in terms of OTG lines, 1869 * include any scaling factors to make sure when we get accurate 1870 * conversion when programming MALL_START_LINE (which is in terms 1871 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1872 * is 1/2 (numerator = 1, denominator = 2). 1873 */ 1874 uint8_t scale_factor_numerator; 1875 uint8_t scale_factor_denominator; 1876 uint8_t is_drr; 1877 uint8_t main_split_pipe_index; 1878 uint8_t phantom_split_pipe_index; 1879 } subvp_data; 1880 1881 struct { 1882 uint32_t pix_clk_100hz; 1883 uint16_t vblank_start; 1884 uint16_t vblank_end; 1885 uint16_t vstartup_start; 1886 uint16_t vtotal; 1887 uint16_t htotal; 1888 uint8_t vblank_pipe_index; 1889 uint8_t padding[1]; 1890 struct { 1891 uint8_t drr_in_use; 1892 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1893 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1894 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1895 uint8_t use_ramping; // Use ramping or not 1896 uint8_t drr_vblank_start_margin; 1897 } drr_info; // DRR considered as part of SubVP + VBLANK case 1898 } vblank_data; 1899 } pipe_config; 1900 1901 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1902 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1903 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1904 */ 1905 uint8_t mode; // enum mclk_switch_mode 1906 }; 1907 1908 /** 1909 * Config data for Sub-VP and FPO 1910 * Named "v2" for now -- once FPO and SUBVP are fully merged 1911 * the type name can be updated 1912 */ 1913 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1914 uint16_t watermark_a_cache; 1915 uint8_t vertical_int_margin_us; 1916 uint8_t pstate_allow_width_us; 1917 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1918 }; 1919 1920 /** 1921 * DMUB rb command definition for Sub-VP and FPO 1922 * Named "v2" for now -- once FPO and SUBVP are fully merged 1923 * the type name can be updated 1924 */ 1925 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1926 struct dmub_cmd_header header; 1927 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1928 }; 1929 1930 struct dmub_flip_addr_info { 1931 uint32_t surf_addr_lo; 1932 uint32_t surf_addr_c_lo; 1933 uint32_t meta_addr_lo; 1934 uint32_t meta_addr_c_lo; 1935 uint16_t surf_addr_hi; 1936 uint16_t surf_addr_c_hi; 1937 uint16_t meta_addr_hi; 1938 uint16_t meta_addr_c_hi; 1939 }; 1940 1941 struct dmub_fams2_flip_info { 1942 union { 1943 struct { 1944 uint8_t is_immediate: 1; 1945 } bits; 1946 uint8_t all; 1947 } config; 1948 uint8_t otg_inst; 1949 uint8_t pipe_mask; 1950 uint8_t pad; 1951 struct dmub_flip_addr_info addr_info; 1952 }; 1953 1954 struct dmub_rb_cmd_fams2_flip { 1955 struct dmub_cmd_header header; 1956 struct dmub_fams2_flip_info flip_info; 1957 }; 1958 1959 struct dmub_cmd_lsdma_data { 1960 union { 1961 struct lsdma_init_data { 1962 union dmub_addr gpu_addr_base; 1963 uint32_t ring_size; 1964 } init_data; 1965 struct lsdma_tiled_copy_data { 1966 uint32_t src_addr_lo; 1967 uint32_t src_addr_hi; 1968 uint32_t dst_addr_lo; 1969 uint32_t dst_addr_hi; 1970 1971 uint32_t src_x : 16; 1972 uint32_t src_y : 16; 1973 1974 uint32_t src_width : 16; 1975 uint32_t src_height : 16; 1976 1977 uint32_t dst_x : 16; 1978 uint32_t dst_y : 16; 1979 1980 uint32_t dst_width : 16; 1981 uint32_t dst_height : 16; 1982 1983 uint32_t rect_x : 16; 1984 uint32_t rect_y : 16; 1985 1986 uint32_t src_swizzle_mode : 5; 1987 uint32_t src_mip_max : 5; 1988 uint32_t src_mip_id : 5; 1989 uint32_t dst_mip_max : 5; 1990 uint32_t dst_swizzle_mode : 5; 1991 uint32_t dst_mip_id : 5; 1992 uint32_t tmz : 1; 1993 uint32_t dcc : 1; 1994 1995 uint32_t data_format : 6; 1996 uint32_t padding1 : 4; 1997 uint32_t dst_element_size : 3; 1998 uint32_t num_type : 3; 1999 uint32_t src_element_size : 3; 2000 uint32_t write_compress : 2; 2001 uint32_t cache_policy_dst : 2; 2002 uint32_t cache_policy_src : 2; 2003 uint32_t read_compress : 2; 2004 uint32_t src_dim : 2; 2005 uint32_t dst_dim : 2; 2006 uint32_t max_uncom : 1; 2007 2008 uint32_t max_com : 2; 2009 uint32_t padding : 30; 2010 } tiled_copy_data; 2011 struct lsdma_linear_copy_data { 2012 uint32_t count : 30; 2013 uint32_t cache_policy_dst : 2; 2014 2015 uint32_t tmz : 1; 2016 uint32_t cache_policy_src : 2; 2017 uint32_t padding : 29; 2018 2019 uint32_t src_lo; 2020 uint32_t src_hi; 2021 uint32_t dst_lo; 2022 uint32_t dst_hi; 2023 } linear_copy_data; 2024 struct lsdma_reg_write_data { 2025 uint32_t reg_addr; 2026 uint32_t reg_data; 2027 } reg_write_data; 2028 struct lsdma_pio_copy_data { 2029 union { 2030 struct { 2031 uint32_t byte_count : 26; 2032 uint32_t src_loc : 1; 2033 uint32_t dst_loc : 1; 2034 uint32_t src_addr_inc : 1; 2035 uint32_t dst_addr_inc : 1; 2036 uint32_t overlap_disable : 1; 2037 uint32_t constant_fill : 1; 2038 } fields; 2039 uint32_t raw; 2040 } packet; 2041 uint32_t src_lo; 2042 uint32_t src_hi; 2043 uint32_t dst_lo; 2044 uint32_t dst_hi; 2045 } pio_copy_data; 2046 struct lsdma_pio_constfill_data { 2047 union { 2048 struct { 2049 uint32_t byte_count : 26; 2050 uint32_t src_loc : 1; 2051 uint32_t dst_loc : 1; 2052 uint32_t src_addr_inc : 1; 2053 uint32_t dst_addr_inc : 1; 2054 uint32_t overlap_disable : 1; 2055 uint32_t constant_fill : 1; 2056 } fields; 2057 uint32_t raw; 2058 } packet; 2059 uint32_t dst_lo; 2060 uint32_t dst_hi; 2061 uint32_t data; 2062 } pio_constfill_data; 2063 2064 uint32_t all[14]; 2065 } u; 2066 2067 }; 2068 2069 struct dmub_rb_cmd_lsdma { 2070 struct dmub_cmd_header header; 2071 struct dmub_cmd_lsdma_data lsdma_data; 2072 }; 2073 2074 struct dmub_optc_state_v2 { 2075 uint32_t v_total_min; 2076 uint32_t v_total_max; 2077 uint32_t v_total_mid; 2078 uint32_t v_total_mid_frame_num; 2079 uint8_t program_manual_trigger; 2080 uint8_t tg_inst; 2081 uint8_t pad[2]; 2082 }; 2083 2084 struct dmub_optc_position { 2085 uint32_t vpos; 2086 uint32_t hpos; 2087 uint32_t frame; 2088 }; 2089 2090 struct dmub_rb_cmd_fams2_drr_update { 2091 struct dmub_cmd_header header; 2092 struct dmub_optc_state_v2 dmub_optc_state_req; 2093 }; 2094 2095 /* HW and FW global configuration data for FAMS2 */ 2096 /* FAMS2 types and structs */ 2097 enum fams2_stream_type { 2098 FAMS2_STREAM_TYPE_NONE = 0, 2099 FAMS2_STREAM_TYPE_VBLANK = 1, 2100 FAMS2_STREAM_TYPE_VACTIVE = 2, 2101 FAMS2_STREAM_TYPE_DRR = 3, 2102 FAMS2_STREAM_TYPE_SUBVP = 4, 2103 }; 2104 2105 struct dmub_rect16 { 2106 /** 2107 * Dirty rect x offset. 2108 */ 2109 uint16_t x; 2110 2111 /** 2112 * Dirty rect y offset. 2113 */ 2114 uint16_t y; 2115 2116 /** 2117 * Dirty rect width. 2118 */ 2119 uint16_t width; 2120 2121 /** 2122 * Dirty rect height. 2123 */ 2124 uint16_t height; 2125 }; 2126 2127 /* static stream state */ 2128 struct dmub_fams2_legacy_stream_static_state { 2129 uint8_t vactive_det_fill_delay_otg_vlines; 2130 uint8_t programming_delay_otg_vlines; 2131 }; //v0 2132 2133 struct dmub_fams2_subvp_stream_static_state { 2134 uint16_t vratio_numerator; 2135 uint16_t vratio_denominator; 2136 uint16_t phantom_vtotal; 2137 uint16_t phantom_vactive; 2138 union { 2139 struct { 2140 uint8_t is_multi_planar : 1; 2141 uint8_t is_yuv420 : 1; 2142 } bits; 2143 uint8_t all; 2144 } config; 2145 uint8_t programming_delay_otg_vlines; 2146 uint8_t prefetch_to_mall_otg_vlines; 2147 uint8_t phantom_otg_inst; 2148 uint8_t phantom_pipe_mask; 2149 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2150 }; //v0 2151 2152 struct dmub_fams2_drr_stream_static_state { 2153 uint16_t nom_stretched_vtotal; 2154 uint8_t programming_delay_otg_vlines; 2155 uint8_t only_stretch_if_required; 2156 uint8_t pad[2]; 2157 }; //v0 2158 2159 struct dmub_fams2_cmd_legacy_stream_static_state { 2160 uint16_t vactive_det_fill_delay_otg_vlines; 2161 uint16_t programming_delay_otg_vlines; 2162 }; //v1 2163 2164 struct dmub_fams2_cmd_subvp_stream_static_state { 2165 uint16_t vratio_numerator; 2166 uint16_t vratio_denominator; 2167 uint16_t phantom_vtotal; 2168 uint16_t phantom_vactive; 2169 uint16_t programming_delay_otg_vlines; 2170 uint16_t prefetch_to_mall_otg_vlines; 2171 union { 2172 struct { 2173 uint8_t is_multi_planar : 1; 2174 uint8_t is_yuv420 : 1; 2175 } bits; 2176 uint8_t all; 2177 } config; 2178 uint8_t phantom_otg_inst; 2179 uint8_t phantom_pipe_mask; 2180 uint8_t pad0; 2181 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2182 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2183 }; //v1 2184 2185 struct dmub_fams2_cmd_drr_stream_static_state { 2186 uint16_t nom_stretched_vtotal; 2187 uint16_t programming_delay_otg_vlines; 2188 uint8_t only_stretch_if_required; 2189 uint8_t pad[3]; 2190 }; //v1 2191 2192 union dmub_fams2_stream_static_sub_state { 2193 struct dmub_fams2_legacy_stream_static_state legacy; 2194 struct dmub_fams2_subvp_stream_static_state subvp; 2195 struct dmub_fams2_drr_stream_static_state drr; 2196 }; //v0 2197 2198 union dmub_fams2_cmd_stream_static_sub_state { 2199 COMMON_STREAM_STATIC_SUB_STATE 2200 }; //v1 2201 2202 union dmub_fams2_stream_static_sub_state_v2 { 2203 COMMON_STREAM_STATIC_SUB_STATE 2204 }; //v2 2205 2206 struct dmub_fams2_stream_static_state { 2207 enum fams2_stream_type type; 2208 uint32_t otg_vline_time_ns; 2209 uint32_t otg_vline_time_ticks; 2210 uint16_t htotal; 2211 uint16_t vtotal; // nominal vtotal 2212 uint16_t vblank_start; 2213 uint16_t vblank_end; 2214 uint16_t max_vtotal; 2215 uint16_t allow_start_otg_vline; 2216 uint16_t allow_end_otg_vline; 2217 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2218 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2219 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2220 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2221 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2222 union { 2223 struct { 2224 uint8_t is_drr: 1; // stream is DRR enabled 2225 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2226 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2227 } bits; 2228 uint8_t all; 2229 } config; 2230 uint8_t otg_inst; 2231 uint8_t pipe_mask; // pipe mask for the whole config 2232 uint8_t num_planes; 2233 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2234 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2235 union dmub_fams2_stream_static_sub_state sub_state; 2236 }; //v0 2237 2238 struct dmub_fams2_cmd_stream_static_base_state { 2239 enum fams2_stream_type type; 2240 uint32_t otg_vline_time_ns; 2241 uint32_t otg_vline_time_ticks; 2242 uint16_t htotal; 2243 uint16_t vtotal; // nominal vtotal 2244 uint16_t vblank_start; 2245 uint16_t vblank_end; 2246 uint16_t max_vtotal; 2247 uint16_t allow_start_otg_vline; 2248 uint16_t allow_end_otg_vline; 2249 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2250 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2251 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2252 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2253 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2254 union { 2255 struct { 2256 uint8_t is_drr : 1; // stream is DRR enabled 2257 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2258 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2259 } bits; 2260 uint8_t all; 2261 } config; 2262 uint8_t otg_inst; 2263 uint8_t pipe_mask; // pipe mask for the whole config 2264 uint8_t num_planes; 2265 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2266 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2267 }; //v1 2268 2269 struct dmub_fams2_stream_static_state_v1 { 2270 struct dmub_fams2_cmd_stream_static_base_state base; 2271 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2272 }; //v1 2273 2274 /** 2275 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2276 * p-state request to allow latency 2277 */ 2278 enum dmub_fams2_allow_delay_check_mode { 2279 /* No check for request to allow delay */ 2280 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2281 /* Check for request to allow delay */ 2282 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2283 /* Check for prepare to allow delay */ 2284 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2285 }; 2286 2287 union dmub_fams2_global_feature_config { 2288 struct { 2289 uint32_t enable: 1; 2290 uint32_t enable_ppt_check: 1; 2291 uint32_t enable_stall_recovery: 1; 2292 uint32_t enable_debug: 1; 2293 uint32_t enable_offload_flip: 1; 2294 uint32_t enable_visual_confirm: 1; 2295 uint32_t allow_delay_check_mode: 2; 2296 uint32_t reserved: 24; 2297 } bits; 2298 uint32_t all; 2299 }; 2300 2301 struct dmub_cmd_fams2_global_config { 2302 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2303 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2304 uint32_t num_streams; 2305 union dmub_fams2_global_feature_config features; 2306 uint32_t recovery_timeout_us; 2307 uint32_t hwfq_flip_programming_delay_us; 2308 }; 2309 2310 union dmub_cmd_fams2_config { 2311 struct dmub_cmd_fams2_global_config global; 2312 struct dmub_fams2_stream_static_state stream; //v0 2313 union { 2314 struct dmub_fams2_cmd_stream_static_base_state base; 2315 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2316 } stream_v1; //v1 2317 }; 2318 2319 struct dmub_fams2_config_v2 { 2320 struct dmub_cmd_fams2_global_config global; 2321 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2322 }; 2323 2324 /** 2325 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2326 */ 2327 struct dmub_rb_cmd_fams2 { 2328 struct dmub_cmd_header header; 2329 union dmub_cmd_fams2_config config; 2330 }; 2331 2332 /** 2333 * Indirect buffer descriptor 2334 */ 2335 struct dmub_ib_data { 2336 union dmub_addr src; // location of indirect buffer in memory 2337 uint16_t size; // indirect buffer size in bytes 2338 }; 2339 2340 /** 2341 * DMUB rb command definition for commands passed over indirect buffer 2342 */ 2343 struct dmub_rb_cmd_ib { 2344 struct dmub_cmd_header header; 2345 struct dmub_ib_data ib_data; 2346 }; 2347 2348 /** 2349 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2350 */ 2351 enum dmub_cmd_idle_opt_type { 2352 /** 2353 * DCN hardware restore. 2354 */ 2355 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2356 2357 /** 2358 * DCN hardware save. 2359 */ 2360 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2361 2362 /** 2363 * DCN hardware notify idle. 2364 */ 2365 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2366 2367 /** 2368 * DCN hardware notify power state. 2369 */ 2370 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2371 2372 /** 2373 * DCN notify to release HW. 2374 */ 2375 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2376 }; 2377 2378 /** 2379 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2380 */ 2381 struct dmub_rb_cmd_idle_opt_dcn_restore { 2382 struct dmub_cmd_header header; /**< header */ 2383 }; 2384 2385 /** 2386 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2387 */ 2388 struct dmub_dcn_notify_idle_cntl_data { 2389 uint8_t driver_idle; 2390 uint8_t skip_otg_disable; 2391 uint8_t reserved[58]; 2392 }; 2393 2394 /** 2395 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2396 */ 2397 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2398 struct dmub_cmd_header header; /**< header */ 2399 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2400 }; 2401 2402 /** 2403 * enum dmub_idle_opt_dc_power_state - DC power states. 2404 */ 2405 enum dmub_idle_opt_dc_power_state { 2406 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2407 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2408 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2409 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2410 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2411 }; 2412 2413 /** 2414 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2415 */ 2416 struct dmub_idle_opt_set_dc_power_state_data { 2417 uint8_t power_state; /**< power state */ 2418 uint8_t pad[3]; /**< padding */ 2419 }; 2420 2421 /** 2422 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2423 */ 2424 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2425 struct dmub_cmd_header header; /**< header */ 2426 struct dmub_idle_opt_set_dc_power_state_data data; 2427 }; 2428 2429 /** 2430 * struct dmub_clocks - Clock update notification. 2431 */ 2432 struct dmub_clocks { 2433 uint32_t dispclk_khz; /**< dispclk kHz */ 2434 uint32_t dppclk_khz; /**< dppclk kHz */ 2435 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2436 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2437 }; 2438 2439 /** 2440 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2441 */ 2442 enum dmub_cmd_clk_mgr_type { 2443 /** 2444 * Notify DMCUB of clock update. 2445 */ 2446 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2447 }; 2448 2449 /** 2450 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2451 */ 2452 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2453 struct dmub_cmd_header header; /**< header */ 2454 struct dmub_clocks clocks; /**< clock data */ 2455 }; 2456 2457 /** 2458 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2459 */ 2460 struct dmub_cmd_digx_encoder_control_data { 2461 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2462 }; 2463 2464 /** 2465 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2466 */ 2467 struct dmub_rb_cmd_digx_encoder_control { 2468 struct dmub_cmd_header header; /**< header */ 2469 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2470 }; 2471 2472 /** 2473 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2474 */ 2475 struct dmub_cmd_set_pixel_clock_data { 2476 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2477 }; 2478 2479 /** 2480 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2481 */ 2482 struct dmub_rb_cmd_set_pixel_clock { 2483 struct dmub_cmd_header header; /**< header */ 2484 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2485 }; 2486 2487 /** 2488 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2489 */ 2490 struct dmub_cmd_enable_disp_power_gating_data { 2491 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2492 }; 2493 2494 /** 2495 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2496 */ 2497 struct dmub_rb_cmd_enable_disp_power_gating { 2498 struct dmub_cmd_header header; /**< header */ 2499 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2500 }; 2501 2502 /** 2503 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2504 */ 2505 struct dmub_dig_transmitter_control_data_v1_7 { 2506 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2507 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2508 union { 2509 uint8_t digmode; /**< enum atom_encode_mode_def */ 2510 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2511 } mode_laneset; 2512 uint8_t lanenum; /**< Number of lanes */ 2513 union { 2514 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2515 } symclk_units; 2516 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2517 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2518 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2519 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2520 uint8_t reserved1; /**< For future use */ 2521 uint8_t skip_phy_ssc_reduction; 2522 uint8_t reserved2[2]; /**< For future use */ 2523 uint32_t reserved3[11]; /**< For future use */ 2524 }; 2525 2526 /** 2527 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2528 */ 2529 union dmub_cmd_dig1_transmitter_control_data { 2530 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2531 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2532 }; 2533 2534 /** 2535 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2536 */ 2537 struct dmub_rb_cmd_dig1_transmitter_control { 2538 struct dmub_cmd_header header; /**< header */ 2539 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2540 }; 2541 2542 /** 2543 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2544 */ 2545 struct dmub_rb_cmd_domain_control_data { 2546 uint8_t inst : 6; /**< DOMAIN instance to control */ 2547 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2548 uint8_t reserved[3]; /**< Reserved for future use */ 2549 }; 2550 2551 /** 2552 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2553 */ 2554 struct dmub_rb_cmd_domain_control { 2555 struct dmub_cmd_header header; /**< header */ 2556 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2557 }; 2558 2559 /** 2560 * DPIA tunnel command parameters. 2561 */ 2562 struct dmub_cmd_dig_dpia_control_data { 2563 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2564 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2565 union { 2566 uint8_t digmode; /** enum atom_encode_mode_def */ 2567 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2568 } mode_laneset; 2569 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2570 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2571 uint8_t hpdsel; /** =0: HPD is not assigned */ 2572 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2573 uint8_t dpia_id; /** Index of DPIA */ 2574 uint8_t fec_rdy : 1; 2575 uint8_t reserved : 7; 2576 uint32_t reserved1; 2577 }; 2578 2579 /** 2580 * DMUB command for DPIA tunnel control. 2581 */ 2582 struct dmub_rb_cmd_dig1_dpia_control { 2583 struct dmub_cmd_header header; 2584 struct dmub_cmd_dig_dpia_control_data dpia_control; 2585 }; 2586 2587 /** 2588 * SET_CONFIG Command Payload (deprecated) 2589 */ 2590 struct set_config_cmd_payload { 2591 uint8_t msg_type; /* set config message type */ 2592 uint8_t msg_data; /* set config message data */ 2593 }; 2594 2595 /** 2596 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2597 */ 2598 struct dmub_cmd_set_config_control_data { 2599 struct set_config_cmd_payload cmd_pkt; 2600 uint8_t instance; /* DPIA instance */ 2601 uint8_t immed_status; /* Immediate status returned in case of error */ 2602 }; 2603 2604 /** 2605 * SET_CONFIG Request Command Payload 2606 */ 2607 struct set_config_request_cmd_payload { 2608 uint8_t instance; /* DPIA instance */ 2609 uint8_t immed_status; /* Immediate status returned in case of error */ 2610 uint8_t msg_type; /* set config message type */ 2611 uint8_t reserved; 2612 uint32_t msg_data; /* set config message data */ 2613 }; 2614 2615 /** 2616 * DMUB command structure for SET_CONFIG command. 2617 */ 2618 struct dmub_rb_cmd_set_config_access { 2619 struct dmub_cmd_header header; /* header */ 2620 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2621 }; 2622 2623 /** 2624 * DMUB command structure for SET_CONFIG request command. 2625 */ 2626 struct dmub_rb_cmd_set_config_request { 2627 struct dmub_cmd_header header; /* header */ 2628 struct set_config_request_cmd_payload payload; /* set config request payload */ 2629 }; 2630 2631 /** 2632 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2633 */ 2634 struct dmub_cmd_mst_alloc_slots_control_data { 2635 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2636 uint8_t instance; /* DPIA instance */ 2637 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2638 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2639 }; 2640 2641 /** 2642 * DMUB command structure for SET_ command. 2643 */ 2644 struct dmub_rb_cmd_set_mst_alloc_slots { 2645 struct dmub_cmd_header header; /* header */ 2646 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2647 }; 2648 2649 /** 2650 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2651 */ 2652 struct dmub_cmd_tps_notification_data { 2653 uint8_t instance; /* DPIA instance */ 2654 uint8_t tps; /* requested training pattern */ 2655 uint8_t reserved1; 2656 uint8_t reserved2; 2657 }; 2658 2659 /** 2660 * DMUB command structure for SET_TPS_NOTIFICATION command. 2661 */ 2662 struct dmub_rb_cmd_set_tps_notification { 2663 struct dmub_cmd_header header; /* header */ 2664 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2665 }; 2666 2667 /** 2668 * DMUB command structure for DPIA HPD int enable control. 2669 */ 2670 struct dmub_rb_cmd_dpia_hpd_int_enable { 2671 struct dmub_cmd_header header; /* header */ 2672 uint32_t enable; /* dpia hpd interrupt enable */ 2673 }; 2674 2675 /** 2676 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2677 */ 2678 struct dmub_rb_cmd_dpphy_init { 2679 struct dmub_cmd_header header; /**< header */ 2680 uint8_t reserved[60]; /**< reserved bits */ 2681 }; 2682 2683 /** 2684 * enum dp_aux_request_action - DP AUX request command listing. 2685 * 2686 * 4 AUX request command bits are shifted to high nibble. 2687 */ 2688 enum dp_aux_request_action { 2689 /** I2C-over-AUX write request */ 2690 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2691 /** I2C-over-AUX read request */ 2692 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2693 /** I2C-over-AUX write status request */ 2694 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2695 /** I2C-over-AUX write request with MOT=1 */ 2696 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2697 /** I2C-over-AUX read request with MOT=1 */ 2698 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2699 /** I2C-over-AUX write status request with MOT=1 */ 2700 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2701 /** Native AUX write request */ 2702 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2703 /** Native AUX read request */ 2704 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2705 }; 2706 2707 /** 2708 * enum aux_return_code_type - DP AUX process return code listing. 2709 */ 2710 enum aux_return_code_type { 2711 /** AUX process succeeded */ 2712 AUX_RET_SUCCESS = 0, 2713 /** AUX process failed with unknown reason */ 2714 AUX_RET_ERROR_UNKNOWN, 2715 /** AUX process completed with invalid reply */ 2716 AUX_RET_ERROR_INVALID_REPLY, 2717 /** AUX process timed out */ 2718 AUX_RET_ERROR_TIMEOUT, 2719 /** HPD was low during AUX process */ 2720 AUX_RET_ERROR_HPD_DISCON, 2721 /** Failed to acquire AUX engine */ 2722 AUX_RET_ERROR_ENGINE_ACQUIRE, 2723 /** AUX request not supported */ 2724 AUX_RET_ERROR_INVALID_OPERATION, 2725 /** AUX process not available */ 2726 AUX_RET_ERROR_PROTOCOL_ERROR, 2727 }; 2728 2729 /** 2730 * enum aux_channel_type - DP AUX channel type listing. 2731 */ 2732 enum aux_channel_type { 2733 /** AUX thru Legacy DP AUX */ 2734 AUX_CHANNEL_LEGACY_DDC, 2735 /** AUX thru DPIA DP tunneling */ 2736 AUX_CHANNEL_DPIA 2737 }; 2738 2739 /** 2740 * struct aux_transaction_parameters - DP AUX request transaction data 2741 */ 2742 struct aux_transaction_parameters { 2743 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2744 uint8_t action; /**< enum dp_aux_request_action */ 2745 uint8_t length; /**< DP AUX request data length */ 2746 uint8_t reserved; /**< For future use */ 2747 uint32_t address; /**< DP AUX address */ 2748 uint8_t data[16]; /**< DP AUX write data */ 2749 }; 2750 2751 /** 2752 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2753 */ 2754 struct dmub_cmd_dp_aux_control_data { 2755 uint8_t instance; /**< AUX instance or DPIA instance */ 2756 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2757 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2758 uint8_t reserved0; /**< For future use */ 2759 uint16_t timeout; /**< timeout time in us */ 2760 uint16_t reserved1; /**< For future use */ 2761 enum aux_channel_type type; /**< enum aux_channel_type */ 2762 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2763 }; 2764 2765 /** 2766 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2767 */ 2768 struct dmub_rb_cmd_dp_aux_access { 2769 /** 2770 * Command header. 2771 */ 2772 struct dmub_cmd_header header; 2773 /** 2774 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2775 */ 2776 struct dmub_cmd_dp_aux_control_data aux_control; 2777 }; 2778 2779 /** 2780 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2781 */ 2782 struct dmub_rb_cmd_outbox1_enable { 2783 /** 2784 * Command header. 2785 */ 2786 struct dmub_cmd_header header; 2787 /** 2788 * enable: 0x0 -> disable outbox1 notification (default value) 2789 * 0x1 -> enable outbox1 notification 2790 */ 2791 uint32_t enable; 2792 }; 2793 2794 /* DP AUX Reply command - OutBox Cmd */ 2795 /** 2796 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2797 */ 2798 struct aux_reply_data { 2799 /** 2800 * Aux cmd 2801 */ 2802 uint8_t command; 2803 /** 2804 * Aux reply data length (max: 16 bytes) 2805 */ 2806 uint8_t length; 2807 /** 2808 * Alignment only 2809 */ 2810 uint8_t pad[2]; 2811 /** 2812 * Aux reply data 2813 */ 2814 uint8_t data[16]; 2815 }; 2816 2817 /** 2818 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2819 */ 2820 struct aux_reply_control_data { 2821 /** 2822 * Reserved for future use 2823 */ 2824 uint32_t handle; 2825 /** 2826 * Aux Instance 2827 */ 2828 uint8_t instance; 2829 /** 2830 * Aux transaction result: definition in enum aux_return_code_type 2831 */ 2832 uint8_t result; 2833 /** 2834 * Alignment only 2835 */ 2836 uint16_t pad; 2837 }; 2838 2839 /** 2840 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2841 */ 2842 struct dmub_rb_cmd_dp_aux_reply { 2843 /** 2844 * Command header. 2845 */ 2846 struct dmub_cmd_header header; 2847 /** 2848 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2849 */ 2850 struct aux_reply_control_data control; 2851 /** 2852 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2853 */ 2854 struct aux_reply_data reply_data; 2855 }; 2856 2857 /* DP HPD Notify command - OutBox Cmd */ 2858 /** 2859 * DP HPD Type 2860 */ 2861 enum dp_hpd_type { 2862 /** 2863 * Normal DP HPD 2864 */ 2865 DP_HPD = 0, 2866 /** 2867 * DP HPD short pulse 2868 */ 2869 DP_IRQ = 1, 2870 /** 2871 * Failure to acquire DP HPD state 2872 */ 2873 DP_NONE_HPD = 2 2874 }; 2875 2876 /** 2877 * DP HPD Status 2878 */ 2879 enum dp_hpd_status { 2880 /** 2881 * DP_HPD status low 2882 */ 2883 DP_HPD_UNPLUG = 0, 2884 /** 2885 * DP_HPD status high 2886 */ 2887 DP_HPD_PLUG 2888 }; 2889 2890 /** 2891 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2892 */ 2893 struct dp_hpd_data { 2894 /** 2895 * DP HPD instance 2896 */ 2897 uint8_t instance; 2898 /** 2899 * HPD type 2900 */ 2901 uint8_t hpd_type; 2902 /** 2903 * HPD status: only for type: DP_HPD to indicate status 2904 */ 2905 uint8_t hpd_status; 2906 /** 2907 * Alignment only 2908 */ 2909 uint8_t pad; 2910 }; 2911 2912 /** 2913 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2914 */ 2915 struct dmub_rb_cmd_dp_hpd_notify { 2916 /** 2917 * Command header. 2918 */ 2919 struct dmub_cmd_header header; 2920 /** 2921 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2922 */ 2923 struct dp_hpd_data hpd_data; 2924 }; 2925 2926 /** 2927 * Definition of a SET_CONFIG reply from DPOA. 2928 */ 2929 enum set_config_status { 2930 SET_CONFIG_PENDING = 0, 2931 SET_CONFIG_ACK_RECEIVED, 2932 SET_CONFIG_RX_TIMEOUT, 2933 SET_CONFIG_UNKNOWN_ERROR, 2934 }; 2935 2936 /** 2937 * Definition of a set_config reply 2938 */ 2939 struct set_config_reply_control_data { 2940 uint8_t instance; /* DPIA Instance */ 2941 uint8_t status; /* Set Config reply */ 2942 uint16_t pad; /* Alignment */ 2943 }; 2944 2945 /** 2946 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2947 */ 2948 struct dmub_rb_cmd_dp_set_config_reply { 2949 struct dmub_cmd_header header; 2950 struct set_config_reply_control_data set_config_reply_control; 2951 }; 2952 2953 /** 2954 * Definition of a DPIA notification header 2955 */ 2956 struct dpia_notification_header { 2957 uint8_t instance; /**< DPIA Instance */ 2958 uint8_t reserved[3]; 2959 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2960 }; 2961 2962 /** 2963 * Definition of the common data struct of DPIA notification 2964 */ 2965 struct dpia_notification_common { 2966 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2967 - sizeof(struct dpia_notification_header)]; 2968 }; 2969 2970 /** 2971 * Definition of a DPIA notification data 2972 */ 2973 struct dpia_bw_allocation_notify_data { 2974 union { 2975 struct { 2976 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2977 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2978 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2979 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2980 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2981 uint16_t reserved: 11; /**< Reserved */ 2982 } bits; 2983 2984 uint16_t flags; 2985 }; 2986 2987 uint8_t cm_id; /**< CM ID */ 2988 uint8_t group_id; /**< Group ID */ 2989 uint8_t granularity; /**< BW Allocation Granularity */ 2990 uint8_t estimated_bw; /**< Estimated_BW */ 2991 uint8_t allocated_bw; /**< Allocated_BW */ 2992 uint8_t reserved; 2993 }; 2994 2995 /** 2996 * union dpia_notify_data_type - DPIA Notification in Outbox command 2997 */ 2998 union dpia_notification_data { 2999 /** 3000 * DPIA Notification for common data struct 3001 */ 3002 struct dpia_notification_common common_data; 3003 3004 /** 3005 * DPIA Notification for DP BW Allocation support 3006 */ 3007 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3008 }; 3009 3010 /** 3011 * Definition of a DPIA notification payload 3012 */ 3013 struct dpia_notification_payload { 3014 struct dpia_notification_header header; 3015 union dpia_notification_data data; /**< DPIA notification payload data */ 3016 }; 3017 3018 /** 3019 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3020 */ 3021 struct dmub_rb_cmd_dpia_notification { 3022 struct dmub_cmd_header header; /**< DPIA notification header */ 3023 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3024 }; 3025 3026 /** 3027 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3028 */ 3029 struct dmub_cmd_hpd_state_query_data { 3030 uint8_t instance; /**< HPD instance or DPIA instance */ 3031 uint8_t result; /**< For returning HPD state */ 3032 uint16_t pad; /** < Alignment */ 3033 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3034 enum aux_return_code_type status; /**< for returning the status of command */ 3035 }; 3036 3037 /** 3038 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3039 */ 3040 struct dmub_rb_cmd_query_hpd_state { 3041 /** 3042 * Command header. 3043 */ 3044 struct dmub_cmd_header header; 3045 /** 3046 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3047 */ 3048 struct dmub_cmd_hpd_state_query_data data; 3049 }; 3050 3051 /** 3052 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3053 */ 3054 struct dmub_rb_cmd_hpd_sense_notify_data { 3055 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3056 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3057 }; 3058 3059 /** 3060 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3061 */ 3062 struct dmub_rb_cmd_hpd_sense_notify { 3063 struct dmub_cmd_header header; /**< header */ 3064 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3065 }; 3066 3067 /* 3068 * Command IDs should be treated as stable ABI. 3069 * Do not reuse or modify IDs. 3070 */ 3071 3072 /** 3073 * PSR command sub-types. 3074 */ 3075 enum dmub_cmd_psr_type { 3076 /** 3077 * Set PSR version support. 3078 */ 3079 DMUB_CMD__PSR_SET_VERSION = 0, 3080 /** 3081 * Copy driver-calculated parameters to PSR state. 3082 */ 3083 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3084 /** 3085 * Enable PSR. 3086 */ 3087 DMUB_CMD__PSR_ENABLE = 2, 3088 3089 /** 3090 * Disable PSR. 3091 */ 3092 DMUB_CMD__PSR_DISABLE = 3, 3093 3094 /** 3095 * Set PSR level. 3096 * PSR level is a 16-bit value dicated by driver that 3097 * will enable/disable different functionality. 3098 */ 3099 DMUB_CMD__PSR_SET_LEVEL = 4, 3100 3101 /** 3102 * Forces PSR enabled until an explicit PSR disable call. 3103 */ 3104 DMUB_CMD__PSR_FORCE_STATIC = 5, 3105 /** 3106 * Set vtotal in psr active for FreeSync PSR. 3107 */ 3108 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3109 /** 3110 * Set PSR power option 3111 */ 3112 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3113 }; 3114 3115 /** 3116 * Different PSR residency modes. 3117 * Different modes change the definition of PSR residency. 3118 */ 3119 enum psr_residency_mode { 3120 PSR_RESIDENCY_MODE_PHY = 0, 3121 PSR_RESIDENCY_MODE_ALPM, 3122 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3123 /* Do not add below. */ 3124 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3125 }; 3126 3127 enum dmub_cmd_fams_type { 3128 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3129 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3130 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3131 /** 3132 * For SubVP set manual trigger in FW because it 3133 * triggers DRR_UPDATE_PENDING which SubVP relies 3134 * on (for any SubVP cases that use a DRR display) 3135 */ 3136 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3137 DMUB_CMD__FAMS2_CONFIG = 4, 3138 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3139 DMUB_CMD__FAMS2_FLIP = 6, 3140 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3141 }; 3142 3143 /** 3144 * PSR versions. 3145 */ 3146 enum psr_version { 3147 /** 3148 * PSR version 1. 3149 */ 3150 PSR_VERSION_1 = 0, 3151 /** 3152 * Freesync PSR SU. 3153 */ 3154 PSR_VERSION_SU_1 = 1, 3155 /** 3156 * PSR not supported. 3157 */ 3158 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3159 }; 3160 3161 /** 3162 * PHY Link rate for DP. 3163 */ 3164 enum phy_link_rate { 3165 /** 3166 * not supported. 3167 */ 3168 PHY_RATE_UNKNOWN = 0, 3169 /** 3170 * Rate_1 (RBR) - 1.62 Gbps/Lane 3171 */ 3172 PHY_RATE_162 = 1, 3173 /** 3174 * Rate_2 - 2.16 Gbps/Lane 3175 */ 3176 PHY_RATE_216 = 2, 3177 /** 3178 * Rate_3 - 2.43 Gbps/Lane 3179 */ 3180 PHY_RATE_243 = 3, 3181 /** 3182 * Rate_4 (HBR) - 2.70 Gbps/Lane 3183 */ 3184 PHY_RATE_270 = 4, 3185 /** 3186 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3187 */ 3188 PHY_RATE_324 = 5, 3189 /** 3190 * Rate_6 - 4.32 Gbps/Lane 3191 */ 3192 PHY_RATE_432 = 6, 3193 /** 3194 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3195 */ 3196 PHY_RATE_540 = 7, 3197 /** 3198 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3199 */ 3200 PHY_RATE_810 = 8, 3201 /** 3202 * UHBR10 - 10.0 Gbps/Lane 3203 */ 3204 PHY_RATE_1000 = 9, 3205 /** 3206 * UHBR13.5 - 13.5 Gbps/Lane 3207 */ 3208 PHY_RATE_1350 = 10, 3209 /** 3210 * UHBR10 - 20.0 Gbps/Lane 3211 */ 3212 PHY_RATE_2000 = 11, 3213 3214 PHY_RATE_675 = 12, 3215 /** 3216 * Rate 12 - 6.75 Gbps/Lane 3217 */ 3218 }; 3219 3220 /** 3221 * enum dmub_phy_fsm_state - PHY FSM states. 3222 * PHY FSM state to transit to during PSR enable/disable. 3223 */ 3224 enum dmub_phy_fsm_state { 3225 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3226 DMUB_PHY_FSM_RESET, 3227 DMUB_PHY_FSM_RESET_RELEASED, 3228 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3229 DMUB_PHY_FSM_INITIALIZED, 3230 DMUB_PHY_FSM_CALIBRATED, 3231 DMUB_PHY_FSM_CALIBRATED_LP, 3232 DMUB_PHY_FSM_CALIBRATED_PG, 3233 DMUB_PHY_FSM_POWER_DOWN, 3234 DMUB_PHY_FSM_PLL_EN, 3235 DMUB_PHY_FSM_TX_EN, 3236 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3237 DMUB_PHY_FSM_FAST_LP, 3238 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3239 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3240 DMUB_PHY_FSM_P2_PLL_OFF, 3241 DMUB_PHY_FSM_P2_PLL_ON, 3242 }; 3243 3244 /** 3245 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3246 */ 3247 struct dmub_cmd_psr_copy_settings_data { 3248 /** 3249 * Flags that can be set by driver to change some PSR behaviour. 3250 */ 3251 union dmub_psr_debug_flags debug; 3252 /** 3253 * 16-bit value dicated by driver that will enable/disable different functionality. 3254 */ 3255 uint16_t psr_level; 3256 /** 3257 * DPP HW instance. 3258 */ 3259 uint8_t dpp_inst; 3260 /** 3261 * MPCC HW instance. 3262 * Not used in dmub fw, 3263 * dmub fw will get active opp by reading odm registers. 3264 */ 3265 uint8_t mpcc_inst; 3266 /** 3267 * OPP HW instance. 3268 * Not used in dmub fw, 3269 * dmub fw will get active opp by reading odm registers. 3270 */ 3271 uint8_t opp_inst; 3272 /** 3273 * OTG HW instance. 3274 */ 3275 uint8_t otg_inst; 3276 /** 3277 * DIG FE HW instance. 3278 */ 3279 uint8_t digfe_inst; 3280 /** 3281 * DIG BE HW instance. 3282 */ 3283 uint8_t digbe_inst; 3284 /** 3285 * DP PHY HW instance. 3286 */ 3287 uint8_t dpphy_inst; 3288 /** 3289 * AUX HW instance. 3290 */ 3291 uint8_t aux_inst; 3292 /** 3293 * Determines if SMU optimzations are enabled/disabled. 3294 */ 3295 uint8_t smu_optimizations_en; 3296 /** 3297 * Unused. 3298 * TODO: Remove. 3299 */ 3300 uint8_t frame_delay; 3301 /** 3302 * If RFB setup time is greater than the total VBLANK time, 3303 * it is not possible for the sink to capture the video frame 3304 * in the same frame the SDP is sent. In this case, 3305 * the frame capture indication bit should be set and an extra 3306 * static frame should be transmitted to the sink. 3307 */ 3308 uint8_t frame_cap_ind; 3309 /** 3310 * Granularity of Y offset supported by sink. 3311 */ 3312 uint8_t su_y_granularity; 3313 /** 3314 * Indicates whether sink should start capturing 3315 * immediately following active scan line, 3316 * or starting with the 2nd active scan line. 3317 */ 3318 uint8_t line_capture_indication; 3319 /** 3320 * Multi-display optimizations are implemented on certain ASICs. 3321 */ 3322 uint8_t multi_disp_optimizations_en; 3323 /** 3324 * The last possible line SDP may be transmitted without violating 3325 * the RFB setup time or entering the active video frame. 3326 */ 3327 uint16_t init_sdp_deadline; 3328 /** 3329 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3330 */ 3331 uint8_t rate_control_caps ; 3332 /* 3333 * Force PSRSU always doing full frame update 3334 */ 3335 uint8_t force_ffu_mode; 3336 /** 3337 * Length of each horizontal line in us. 3338 */ 3339 uint32_t line_time_in_us; 3340 /** 3341 * FEC enable status in driver 3342 */ 3343 uint8_t fec_enable_status; 3344 /** 3345 * FEC re-enable delay when PSR exit. 3346 * unit is 100us, range form 0~255(0xFF). 3347 */ 3348 uint8_t fec_enable_delay_in100us; 3349 /** 3350 * PSR control version. 3351 */ 3352 uint8_t cmd_version; 3353 /** 3354 * Panel Instance. 3355 * Panel instance to identify which psr_state to use 3356 * Currently the support is only for 0 or 1 3357 */ 3358 uint8_t panel_inst; 3359 /* 3360 * DSC enable status in driver 3361 */ 3362 uint8_t dsc_enable_status; 3363 /* 3364 * Use FSM state for PSR power up/down 3365 */ 3366 uint8_t use_phy_fsm; 3367 /** 3368 * frame delay for frame re-lock 3369 */ 3370 uint8_t relock_delay_frame_cnt; 3371 /** 3372 * esd recovery indicate. 3373 */ 3374 uint8_t esd_recovery; 3375 /** 3376 * DSC Slice height. 3377 */ 3378 uint16_t dsc_slice_height; 3379 /** 3380 * Some panels request main link off before xth vertical line 3381 */ 3382 uint16_t poweroff_before_vertical_line; 3383 /** 3384 * Some panels cannot handle idle pattern during PSR entry. 3385 * To power down phy before disable stream to avoid sending 3386 * idle pattern. 3387 */ 3388 uint8_t power_down_phy_before_disable_stream; 3389 }; 3390 3391 /** 3392 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3393 */ 3394 struct dmub_rb_cmd_psr_copy_settings { 3395 /** 3396 * Command header. 3397 */ 3398 struct dmub_cmd_header header; 3399 /** 3400 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3401 */ 3402 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3403 }; 3404 3405 /** 3406 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3407 */ 3408 struct dmub_cmd_psr_set_level_data { 3409 /** 3410 * 16-bit value dicated by driver that will enable/disable different functionality. 3411 */ 3412 uint16_t psr_level; 3413 /** 3414 * PSR control version. 3415 */ 3416 uint8_t cmd_version; 3417 /** 3418 * Panel Instance. 3419 * Panel instance to identify which psr_state to use 3420 * Currently the support is only for 0 or 1 3421 */ 3422 uint8_t panel_inst; 3423 }; 3424 3425 /** 3426 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3427 */ 3428 struct dmub_rb_cmd_psr_set_level { 3429 /** 3430 * Command header. 3431 */ 3432 struct dmub_cmd_header header; 3433 /** 3434 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3435 */ 3436 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3437 }; 3438 3439 struct dmub_rb_cmd_psr_enable_data { 3440 /** 3441 * PSR control version. 3442 */ 3443 uint8_t cmd_version; 3444 /** 3445 * Panel Instance. 3446 * Panel instance to identify which psr_state to use 3447 * Currently the support is only for 0 or 1 3448 */ 3449 uint8_t panel_inst; 3450 /** 3451 * Phy state to enter. 3452 * Values to use are defined in dmub_phy_fsm_state 3453 */ 3454 uint8_t phy_fsm_state; 3455 /** 3456 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3457 * Set this using enum phy_link_rate. 3458 * This does not support HDMI/DP2 for now. 3459 */ 3460 uint8_t phy_rate; 3461 }; 3462 3463 /** 3464 * Definition of a DMUB_CMD__PSR_ENABLE command. 3465 * PSR enable/disable is controlled using the sub_type. 3466 */ 3467 struct dmub_rb_cmd_psr_enable { 3468 /** 3469 * Command header. 3470 */ 3471 struct dmub_cmd_header header; 3472 3473 struct dmub_rb_cmd_psr_enable_data data; 3474 }; 3475 3476 /** 3477 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3478 */ 3479 struct dmub_cmd_psr_set_version_data { 3480 /** 3481 * PSR version that FW should implement. 3482 */ 3483 enum psr_version version; 3484 /** 3485 * PSR control version. 3486 */ 3487 uint8_t cmd_version; 3488 /** 3489 * Panel Instance. 3490 * Panel instance to identify which psr_state to use 3491 * Currently the support is only for 0 or 1 3492 */ 3493 uint8_t panel_inst; 3494 /** 3495 * Explicit padding to 4 byte boundary. 3496 */ 3497 uint8_t pad[2]; 3498 }; 3499 3500 /** 3501 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3502 */ 3503 struct dmub_rb_cmd_psr_set_version { 3504 /** 3505 * Command header. 3506 */ 3507 struct dmub_cmd_header header; 3508 /** 3509 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3510 */ 3511 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3512 }; 3513 3514 struct dmub_cmd_psr_force_static_data { 3515 /** 3516 * PSR control version. 3517 */ 3518 uint8_t cmd_version; 3519 /** 3520 * Panel Instance. 3521 * Panel instance to identify which psr_state to use 3522 * Currently the support is only for 0 or 1 3523 */ 3524 uint8_t panel_inst; 3525 /** 3526 * Explicit padding to 4 byte boundary. 3527 */ 3528 uint8_t pad[2]; 3529 }; 3530 3531 /** 3532 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3533 */ 3534 struct dmub_rb_cmd_psr_force_static { 3535 /** 3536 * Command header. 3537 */ 3538 struct dmub_cmd_header header; 3539 /** 3540 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3541 */ 3542 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3543 }; 3544 3545 /** 3546 * PSR SU debug flags. 3547 */ 3548 union dmub_psr_su_debug_flags { 3549 /** 3550 * PSR SU debug flags. 3551 */ 3552 struct { 3553 /** 3554 * Update dirty rect in SW only. 3555 */ 3556 uint8_t update_dirty_rect_only : 1; 3557 /** 3558 * Reset the cursor/plane state before processing the call. 3559 */ 3560 uint8_t reset_state : 1; 3561 } bitfields; 3562 3563 /** 3564 * Union for debug flags. 3565 */ 3566 uint32_t u32All; 3567 }; 3568 3569 /** 3570 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3571 * This triggers a selective update for PSR SU. 3572 */ 3573 struct dmub_cmd_update_dirty_rect_data { 3574 /** 3575 * Dirty rects from OS. 3576 */ 3577 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3578 /** 3579 * PSR SU debug flags. 3580 */ 3581 union dmub_psr_su_debug_flags debug_flags; 3582 /** 3583 * OTG HW instance. 3584 */ 3585 uint8_t pipe_idx; 3586 /** 3587 * Number of dirty rects. 3588 */ 3589 uint8_t dirty_rect_count; 3590 /** 3591 * PSR control version. 3592 */ 3593 uint8_t cmd_version; 3594 /** 3595 * Panel Instance. 3596 * Panel instance to identify which psr_state to use 3597 * Currently the support is only for 0 or 1 3598 */ 3599 uint8_t panel_inst; 3600 }; 3601 3602 /** 3603 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3604 */ 3605 struct dmub_rb_cmd_update_dirty_rect { 3606 /** 3607 * Command header. 3608 */ 3609 struct dmub_cmd_header header; 3610 /** 3611 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3612 */ 3613 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3614 }; 3615 3616 /** 3617 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3618 */ 3619 union dmub_reg_cursor_control_cfg { 3620 struct { 3621 uint32_t cur_enable: 1; 3622 uint32_t reser0: 3; 3623 uint32_t cur_2x_magnify: 1; 3624 uint32_t reser1: 3; 3625 uint32_t mode: 3; 3626 uint32_t reser2: 5; 3627 uint32_t pitch: 2; 3628 uint32_t reser3: 6; 3629 uint32_t line_per_chunk: 5; 3630 uint32_t reser4: 3; 3631 } bits; 3632 uint32_t raw; 3633 }; 3634 struct dmub_cursor_position_cache_hubp { 3635 union dmub_reg_cursor_control_cfg cur_ctl; 3636 union dmub_reg_position_cfg { 3637 struct { 3638 uint32_t cur_x_pos: 16; 3639 uint32_t cur_y_pos: 16; 3640 } bits; 3641 uint32_t raw; 3642 } position; 3643 union dmub_reg_hot_spot_cfg { 3644 struct { 3645 uint32_t hot_x: 16; 3646 uint32_t hot_y: 16; 3647 } bits; 3648 uint32_t raw; 3649 } hot_spot; 3650 union dmub_reg_dst_offset_cfg { 3651 struct { 3652 uint32_t dst_x_offset: 13; 3653 uint32_t reserved: 19; 3654 } bits; 3655 uint32_t raw; 3656 } dst_offset; 3657 }; 3658 3659 union dmub_reg_cur0_control_cfg { 3660 struct { 3661 uint32_t cur0_enable: 1; 3662 uint32_t expansion_mode: 1; 3663 uint32_t reser0: 1; 3664 uint32_t cur0_rom_en: 1; 3665 uint32_t mode: 3; 3666 uint32_t reserved: 25; 3667 } bits; 3668 uint32_t raw; 3669 }; 3670 struct dmub_cursor_position_cache_dpp { 3671 union dmub_reg_cur0_control_cfg cur0_ctl; 3672 }; 3673 struct dmub_cursor_position_cfg { 3674 struct dmub_cursor_position_cache_hubp pHubp; 3675 struct dmub_cursor_position_cache_dpp pDpp; 3676 uint8_t pipe_idx; 3677 /* 3678 * Padding is required. To be 4 Bytes Aligned. 3679 */ 3680 uint8_t padding[3]; 3681 }; 3682 3683 struct dmub_cursor_attribute_cache_hubp { 3684 uint32_t SURFACE_ADDR_HIGH; 3685 uint32_t SURFACE_ADDR; 3686 union dmub_reg_cursor_control_cfg cur_ctl; 3687 union dmub_reg_cursor_size_cfg { 3688 struct { 3689 uint32_t width: 16; 3690 uint32_t height: 16; 3691 } bits; 3692 uint32_t raw; 3693 } size; 3694 union dmub_reg_cursor_settings_cfg { 3695 struct { 3696 uint32_t dst_y_offset: 8; 3697 uint32_t chunk_hdl_adjust: 2; 3698 uint32_t reserved: 22; 3699 } bits; 3700 uint32_t raw; 3701 } settings; 3702 }; 3703 struct dmub_cursor_attribute_cache_dpp { 3704 union dmub_reg_cur0_control_cfg cur0_ctl; 3705 }; 3706 struct dmub_cursor_attributes_cfg { 3707 struct dmub_cursor_attribute_cache_hubp aHubp; 3708 struct dmub_cursor_attribute_cache_dpp aDpp; 3709 }; 3710 3711 struct dmub_cmd_update_cursor_payload0 { 3712 /** 3713 * Cursor dirty rects. 3714 */ 3715 struct dmub_rect cursor_rect; 3716 /** 3717 * PSR SU debug flags. 3718 */ 3719 union dmub_psr_su_debug_flags debug_flags; 3720 /** 3721 * Cursor enable/disable. 3722 */ 3723 uint8_t enable; 3724 /** 3725 * OTG HW instance. 3726 */ 3727 uint8_t pipe_idx; 3728 /** 3729 * PSR control version. 3730 */ 3731 uint8_t cmd_version; 3732 /** 3733 * Panel Instance. 3734 * Panel instance to identify which psr_state to use 3735 * Currently the support is only for 0 or 1 3736 */ 3737 uint8_t panel_inst; 3738 /** 3739 * Cursor Position Register. 3740 * Registers contains Hubp & Dpp modules 3741 */ 3742 struct dmub_cursor_position_cfg position_cfg; 3743 }; 3744 3745 struct dmub_cmd_update_cursor_payload1 { 3746 struct dmub_cursor_attributes_cfg attribute_cfg; 3747 }; 3748 3749 union dmub_cmd_update_cursor_info_data { 3750 struct dmub_cmd_update_cursor_payload0 payload0; 3751 struct dmub_cmd_update_cursor_payload1 payload1; 3752 }; 3753 /** 3754 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3755 */ 3756 struct dmub_rb_cmd_update_cursor_info { 3757 /** 3758 * Command header. 3759 */ 3760 struct dmub_cmd_header header; 3761 /** 3762 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3763 */ 3764 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3765 }; 3766 3767 /** 3768 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3769 */ 3770 struct dmub_cmd_psr_set_vtotal_data { 3771 /** 3772 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3773 */ 3774 uint16_t psr_vtotal_idle; 3775 /** 3776 * PSR control version. 3777 */ 3778 uint8_t cmd_version; 3779 /** 3780 * Panel Instance. 3781 * Panel instance to identify which psr_state to use 3782 * Currently the support is only for 0 or 1 3783 */ 3784 uint8_t panel_inst; 3785 /* 3786 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3787 */ 3788 uint16_t psr_vtotal_su; 3789 /** 3790 * Explicit padding to 4 byte boundary. 3791 */ 3792 uint8_t pad2[2]; 3793 }; 3794 3795 /** 3796 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3797 */ 3798 struct dmub_rb_cmd_psr_set_vtotal { 3799 /** 3800 * Command header. 3801 */ 3802 struct dmub_cmd_header header; 3803 /** 3804 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3805 */ 3806 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3807 }; 3808 3809 /** 3810 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3811 */ 3812 struct dmub_cmd_psr_set_power_opt_data { 3813 /** 3814 * PSR control version. 3815 */ 3816 uint8_t cmd_version; 3817 /** 3818 * Panel Instance. 3819 * Panel instance to identify which psr_state to use 3820 * Currently the support is only for 0 or 1 3821 */ 3822 uint8_t panel_inst; 3823 /** 3824 * Explicit padding to 4 byte boundary. 3825 */ 3826 uint8_t pad[2]; 3827 /** 3828 * PSR power option 3829 */ 3830 uint32_t power_opt; 3831 }; 3832 3833 /** 3834 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3835 */ 3836 struct dmub_rb_cmd_psr_set_power_opt { 3837 /** 3838 * Command header. 3839 */ 3840 struct dmub_cmd_header header; 3841 /** 3842 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3843 */ 3844 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3845 }; 3846 3847 enum dmub_alpm_mode { 3848 ALPM_AUXWAKE = 0, 3849 ALPM_AUXLESS = 1, 3850 ALPM_UNSUPPORTED = 2, 3851 }; 3852 3853 /** 3854 * Definition of Replay Residency GPINT command. 3855 * Bit[0] - Residency mode for Revision 0 3856 * Bit[1] - Enable/Disable state 3857 * Bit[2-3] - Revision number 3858 * Bit[4-7] - Residency mode for Revision 1 3859 * Bit[8] - Panel instance 3860 * Bit[9-15] - Reserved 3861 */ 3862 3863 enum pr_residency_mode { 3864 PR_RESIDENCY_MODE_PHY = 0x0, 3865 PR_RESIDENCY_MODE_ALPM, 3866 PR_RESIDENCY_MODE_IPS2, 3867 PR_RESIDENCY_MODE_FRAME_CNT, 3868 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3869 }; 3870 3871 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3872 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3873 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3874 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3875 3876 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3877 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3878 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3879 3880 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3881 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3882 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3883 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3884 3885 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3886 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3887 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3888 3889 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3890 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3891 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3892 3893 /** 3894 * Definition of a replay_state. 3895 */ 3896 enum replay_state { 3897 REPLAY_STATE_0 = 0x0, 3898 REPLAY_STATE_1 = 0x10, 3899 REPLAY_STATE_1A = 0x11, 3900 REPLAY_STATE_2 = 0x20, 3901 REPLAY_STATE_2A = 0x21, 3902 REPLAY_STATE_3 = 0x30, 3903 REPLAY_STATE_3INIT = 0x31, 3904 REPLAY_STATE_4 = 0x40, 3905 REPLAY_STATE_4A = 0x41, 3906 REPLAY_STATE_4B = 0x42, 3907 REPLAY_STATE_4C = 0x43, 3908 REPLAY_STATE_4D = 0x44, 3909 REPLAY_STATE_4E = 0x45, 3910 REPLAY_STATE_4B_LOCKED = 0x4A, 3911 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3912 REPLAY_STATE_5 = 0x50, 3913 REPLAY_STATE_5A = 0x51, 3914 REPLAY_STATE_5B = 0x52, 3915 REPLAY_STATE_5A_LOCKED = 0x5A, 3916 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3917 REPLAY_STATE_6 = 0x60, 3918 REPLAY_STATE_6A = 0x61, 3919 REPLAY_STATE_6B = 0x62, 3920 REPLAY_STATE_INVALID = 0xFF, 3921 }; 3922 3923 /** 3924 * Replay command sub-types. 3925 */ 3926 enum dmub_cmd_replay_type { 3927 /** 3928 * Copy driver-calculated parameters to REPLAY state. 3929 */ 3930 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3931 /** 3932 * Enable REPLAY. 3933 */ 3934 DMUB_CMD__REPLAY_ENABLE = 1, 3935 /** 3936 * Set Replay power option. 3937 */ 3938 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3939 /** 3940 * Set coasting vtotal. 3941 */ 3942 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3943 /** 3944 * Set power opt and coasting vtotal. 3945 */ 3946 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3947 /** 3948 * Set disabled iiming sync. 3949 */ 3950 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3951 /** 3952 * Set Residency Frameupdate Timer. 3953 */ 3954 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3955 /** 3956 * Set pseudo vtotal 3957 */ 3958 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3959 /** 3960 * Set adaptive sync sdp enabled 3961 */ 3962 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3963 /** 3964 * Set Replay General command. 3965 */ 3966 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3967 }; 3968 3969 /** 3970 * Replay general command sub-types. 3971 */ 3972 enum dmub_cmd_replay_general_subtype { 3973 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3974 /** 3975 * TODO: For backward compatible, allow new command only. 3976 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3977 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3978 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3979 */ 3980 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3981 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3982 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3983 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3984 }; 3985 3986 struct dmub_alpm_auxless_data { 3987 uint16_t lfps_setup_ns; 3988 uint16_t lfps_period_ns; 3989 uint16_t lfps_silence_ns; 3990 uint16_t lfps_t1_t2_override_us; 3991 short lfps_t1_t2_offset_us; 3992 uint8_t lttpr_count; 3993 }; 3994 3995 /** 3996 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3997 */ 3998 struct dmub_cmd_replay_copy_settings_data { 3999 /** 4000 * Flags that can be set by driver to change some replay behaviour. 4001 */ 4002 union replay_debug_flags debug; 4003 4004 /** 4005 * @flags: Flags used to determine feature functionality. 4006 */ 4007 union replay_hw_flags flags; 4008 4009 /** 4010 * DPP HW instance. 4011 */ 4012 uint8_t dpp_inst; 4013 /** 4014 * OTG HW instance. 4015 */ 4016 uint8_t otg_inst; 4017 /** 4018 * DIG FE HW instance. 4019 */ 4020 uint8_t digfe_inst; 4021 /** 4022 * DIG BE HW instance. 4023 */ 4024 uint8_t digbe_inst; 4025 /** 4026 * AUX HW instance. 4027 */ 4028 uint8_t aux_inst; 4029 /** 4030 * Panel Instance. 4031 * Panel isntance to identify which psr_state to use 4032 * Currently the support is only for 0 or 1 4033 */ 4034 uint8_t panel_inst; 4035 /** 4036 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4037 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4038 */ 4039 uint8_t pixel_deviation_per_line; 4040 /** 4041 * @max_deviation_line: The max number of deviation line that can keep the timing 4042 * synchronized between the Source and Sink during Replay normal sleep mode. 4043 */ 4044 uint8_t max_deviation_line; 4045 /** 4046 * Length of each horizontal line in ns. 4047 */ 4048 uint32_t line_time_in_ns; 4049 /** 4050 * PHY instance. 4051 */ 4052 uint8_t dpphy_inst; 4053 /** 4054 * Determines if SMU optimzations are enabled/disabled. 4055 */ 4056 uint8_t smu_optimizations_en; 4057 /** 4058 * Determines if timing sync are enabled/disabled. 4059 */ 4060 uint8_t replay_timing_sync_supported; 4061 /* 4062 * Use FSM state for Replay power up/down 4063 */ 4064 uint8_t use_phy_fsm; 4065 /** 4066 * Use for AUX-less ALPM LFPS wake operation 4067 */ 4068 struct dmub_alpm_auxless_data auxless_alpm_data; 4069 }; 4070 4071 /** 4072 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4073 */ 4074 struct dmub_rb_cmd_replay_copy_settings { 4075 /** 4076 * Command header. 4077 */ 4078 struct dmub_cmd_header header; 4079 /** 4080 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4081 */ 4082 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4083 }; 4084 4085 /** 4086 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4087 */ 4088 enum replay_enable { 4089 /** 4090 * Disable REPLAY. 4091 */ 4092 REPLAY_DISABLE = 0, 4093 /** 4094 * Enable REPLAY. 4095 */ 4096 REPLAY_ENABLE = 1, 4097 }; 4098 4099 /** 4100 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4101 */ 4102 struct dmub_rb_cmd_replay_enable_data { 4103 /** 4104 * Replay enable or disable. 4105 */ 4106 uint8_t enable; 4107 /** 4108 * Panel Instance. 4109 * Panel isntance to identify which replay_state to use 4110 * Currently the support is only for 0 or 1 4111 */ 4112 uint8_t panel_inst; 4113 /** 4114 * Phy state to enter. 4115 * Values to use are defined in dmub_phy_fsm_state 4116 */ 4117 uint8_t phy_fsm_state; 4118 /** 4119 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4120 * Set this using enum phy_link_rate. 4121 * This does not support HDMI/DP2 for now. 4122 */ 4123 uint8_t phy_rate; 4124 }; 4125 4126 /** 4127 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4128 * Replay enable/disable is controlled using action in data. 4129 */ 4130 struct dmub_rb_cmd_replay_enable { 4131 /** 4132 * Command header. 4133 */ 4134 struct dmub_cmd_header header; 4135 4136 struct dmub_rb_cmd_replay_enable_data data; 4137 }; 4138 4139 /** 4140 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4141 */ 4142 struct dmub_cmd_replay_set_power_opt_data { 4143 /** 4144 * Panel Instance. 4145 * Panel isntance to identify which replay_state to use 4146 * Currently the support is only for 0 or 1 4147 */ 4148 uint8_t panel_inst; 4149 /** 4150 * Explicit padding to 4 byte boundary. 4151 */ 4152 uint8_t pad[3]; 4153 /** 4154 * REPLAY power option 4155 */ 4156 uint32_t power_opt; 4157 }; 4158 4159 /** 4160 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4161 */ 4162 struct dmub_cmd_replay_set_timing_sync_data { 4163 /** 4164 * Panel Instance. 4165 * Panel isntance to identify which replay_state to use 4166 * Currently the support is only for 0 or 1 4167 */ 4168 uint8_t panel_inst; 4169 /** 4170 * REPLAY set_timing_sync 4171 */ 4172 uint8_t timing_sync_supported; 4173 /** 4174 * Explicit padding to 4 byte boundary. 4175 */ 4176 uint8_t pad[2]; 4177 }; 4178 4179 /** 4180 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4181 */ 4182 struct dmub_cmd_replay_set_pseudo_vtotal { 4183 /** 4184 * Panel Instance. 4185 * Panel isntance to identify which replay_state to use 4186 * Currently the support is only for 0 or 1 4187 */ 4188 uint8_t panel_inst; 4189 /** 4190 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4191 */ 4192 uint16_t vtotal; 4193 /** 4194 * Explicit padding to 4 byte boundary. 4195 */ 4196 uint8_t pad; 4197 }; 4198 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4199 /** 4200 * Panel Instance. 4201 * Panel isntance to identify which replay_state to use 4202 * Currently the support is only for 0 or 1 4203 */ 4204 uint8_t panel_inst; 4205 /** 4206 * enabled: set adaptive sync sdp enabled 4207 */ 4208 uint8_t force_disabled; 4209 4210 uint8_t pad[2]; 4211 }; 4212 struct dmub_cmd_replay_set_general_cmd_data { 4213 /** 4214 * Panel Instance. 4215 * Panel isntance to identify which replay_state to use 4216 * Currently the support is only for 0 or 1 4217 */ 4218 uint8_t panel_inst; 4219 /** 4220 * subtype: replay general cmd sub type 4221 */ 4222 uint8_t subtype; 4223 4224 uint8_t pad[2]; 4225 /** 4226 * config data with param1 and param2 4227 */ 4228 uint32_t param1; 4229 4230 uint32_t param2; 4231 }; 4232 4233 /** 4234 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4235 */ 4236 struct dmub_rb_cmd_replay_set_power_opt { 4237 /** 4238 * Command header. 4239 */ 4240 struct dmub_cmd_header header; 4241 /** 4242 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4243 */ 4244 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4245 }; 4246 4247 /** 4248 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4249 */ 4250 struct dmub_cmd_replay_set_coasting_vtotal_data { 4251 /** 4252 * 16-bit value dicated by driver that indicates the coasting vtotal. 4253 */ 4254 uint16_t coasting_vtotal; 4255 /** 4256 * REPLAY control version. 4257 */ 4258 uint8_t cmd_version; 4259 /** 4260 * Panel Instance. 4261 * Panel isntance to identify which replay_state to use 4262 * Currently the support is only for 0 or 1 4263 */ 4264 uint8_t panel_inst; 4265 /** 4266 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4267 */ 4268 uint16_t coasting_vtotal_high; 4269 /** 4270 * Explicit padding to 4 byte boundary. 4271 */ 4272 uint8_t pad[2]; 4273 }; 4274 4275 /** 4276 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4277 */ 4278 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4279 /** 4280 * Command header. 4281 */ 4282 struct dmub_cmd_header header; 4283 /** 4284 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4285 */ 4286 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4287 }; 4288 4289 /** 4290 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4291 */ 4292 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4293 /** 4294 * Command header. 4295 */ 4296 struct dmub_cmd_header header; 4297 /** 4298 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4299 */ 4300 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4301 /** 4302 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4303 */ 4304 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4305 }; 4306 4307 /** 4308 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4309 */ 4310 struct dmub_rb_cmd_replay_set_timing_sync { 4311 /** 4312 * Command header. 4313 */ 4314 struct dmub_cmd_header header; 4315 /** 4316 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4317 */ 4318 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4319 }; 4320 4321 /** 4322 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4323 */ 4324 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4325 /** 4326 * Command header. 4327 */ 4328 struct dmub_cmd_header header; 4329 /** 4330 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4331 */ 4332 struct dmub_cmd_replay_set_pseudo_vtotal data; 4333 }; 4334 4335 /** 4336 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4337 */ 4338 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4339 /** 4340 * Command header. 4341 */ 4342 struct dmub_cmd_header header; 4343 /** 4344 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4345 */ 4346 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4347 }; 4348 4349 /** 4350 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4351 */ 4352 struct dmub_rb_cmd_replay_set_general_cmd { 4353 /** 4354 * Command header. 4355 */ 4356 struct dmub_cmd_header header; 4357 /** 4358 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4359 */ 4360 struct dmub_cmd_replay_set_general_cmd_data data; 4361 }; 4362 4363 /** 4364 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4365 */ 4366 struct dmub_cmd_replay_frameupdate_timer_data { 4367 /** 4368 * Panel Instance. 4369 * Panel isntance to identify which replay_state to use 4370 * Currently the support is only for 0 or 1 4371 */ 4372 uint8_t panel_inst; 4373 /** 4374 * Replay Frameupdate Timer Enable or not 4375 */ 4376 uint8_t enable; 4377 /** 4378 * REPLAY force reflash frame update number 4379 */ 4380 uint16_t frameupdate_count; 4381 }; 4382 /** 4383 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4384 */ 4385 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4386 /** 4387 * Command header. 4388 */ 4389 struct dmub_cmd_header header; 4390 /** 4391 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4392 */ 4393 struct dmub_cmd_replay_frameupdate_timer_data data; 4394 }; 4395 4396 /** 4397 * Definition union of replay command set 4398 */ 4399 union dmub_replay_cmd_set { 4400 /** 4401 * Panel Instance. 4402 * Panel isntance to identify which replay_state to use 4403 * Currently the support is only for 0 or 1 4404 */ 4405 uint8_t panel_inst; 4406 /** 4407 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4408 */ 4409 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4410 /** 4411 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4412 */ 4413 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4414 /** 4415 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4416 */ 4417 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4418 /** 4419 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4420 */ 4421 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4422 /** 4423 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4424 */ 4425 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4426 }; 4427 4428 /** 4429 * Set of HW components that can be locked. 4430 * 4431 * Note: If updating with more HW components, fields 4432 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4433 */ 4434 union dmub_hw_lock_flags { 4435 /** 4436 * Set of HW components that can be locked. 4437 */ 4438 struct { 4439 /** 4440 * Lock/unlock OTG master update lock. 4441 */ 4442 uint8_t lock_pipe : 1; 4443 /** 4444 * Lock/unlock cursor. 4445 */ 4446 uint8_t lock_cursor : 1; 4447 /** 4448 * Lock/unlock global update lock. 4449 */ 4450 uint8_t lock_dig : 1; 4451 /** 4452 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4453 */ 4454 uint8_t triple_buffer_lock : 1; 4455 } bits; 4456 4457 /** 4458 * Union for HW Lock flags. 4459 */ 4460 uint8_t u8All; 4461 }; 4462 4463 /** 4464 * Instances of HW to be locked. 4465 * 4466 * Note: If updating with more HW components, fields 4467 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4468 */ 4469 struct dmub_hw_lock_inst_flags { 4470 /** 4471 * OTG HW instance for OTG master update lock. 4472 */ 4473 uint8_t otg_inst; 4474 /** 4475 * OPP instance for cursor lock. 4476 */ 4477 uint8_t opp_inst; 4478 /** 4479 * OTG HW instance for global update lock. 4480 * TODO: Remove, and re-use otg_inst. 4481 */ 4482 uint8_t dig_inst; 4483 /** 4484 * Explicit pad to 4 byte boundary. 4485 */ 4486 uint8_t pad; 4487 }; 4488 4489 /** 4490 * Clients that can acquire the HW Lock Manager. 4491 * 4492 * Note: If updating with more clients, fields in 4493 * dmub_inbox0_cmd_lock_hw must be updated to match. 4494 */ 4495 enum hw_lock_client { 4496 /** 4497 * Driver is the client of HW Lock Manager. 4498 */ 4499 HW_LOCK_CLIENT_DRIVER = 0, 4500 /** 4501 * PSR SU is the client of HW Lock Manager. 4502 */ 4503 HW_LOCK_CLIENT_PSR_SU = 1, 4504 HW_LOCK_CLIENT_SUBVP = 3, 4505 /** 4506 * Replay is the client of HW Lock Manager. 4507 */ 4508 HW_LOCK_CLIENT_REPLAY = 4, 4509 HW_LOCK_CLIENT_FAMS2 = 5, 4510 /** 4511 * Invalid client. 4512 */ 4513 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4514 }; 4515 4516 /** 4517 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4518 */ 4519 struct dmub_cmd_lock_hw_data { 4520 /** 4521 * Specifies the client accessing HW Lock Manager. 4522 */ 4523 enum hw_lock_client client; 4524 /** 4525 * HW instances to be locked. 4526 */ 4527 struct dmub_hw_lock_inst_flags inst_flags; 4528 /** 4529 * Which components to be locked. 4530 */ 4531 union dmub_hw_lock_flags hw_locks; 4532 /** 4533 * Specifies lock/unlock. 4534 */ 4535 uint8_t lock; 4536 /** 4537 * HW can be unlocked separately from releasing the HW Lock Mgr. 4538 * This flag is set if the client wishes to release the object. 4539 */ 4540 uint8_t should_release; 4541 /** 4542 * Explicit padding to 4 byte boundary. 4543 */ 4544 uint8_t pad; 4545 }; 4546 4547 /** 4548 * Definition of a DMUB_CMD__HW_LOCK command. 4549 * Command is used by driver and FW. 4550 */ 4551 struct dmub_rb_cmd_lock_hw { 4552 /** 4553 * Command header. 4554 */ 4555 struct dmub_cmd_header header; 4556 /** 4557 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4558 */ 4559 struct dmub_cmd_lock_hw_data lock_hw_data; 4560 }; 4561 4562 /** 4563 * ABM command sub-types. 4564 */ 4565 enum dmub_cmd_abm_type { 4566 /** 4567 * Initialize parameters for ABM algorithm. 4568 * Data is passed through an indirect buffer. 4569 */ 4570 DMUB_CMD__ABM_INIT_CONFIG = 0, 4571 /** 4572 * Set OTG and panel HW instance. 4573 */ 4574 DMUB_CMD__ABM_SET_PIPE = 1, 4575 /** 4576 * Set user requested backklight level. 4577 */ 4578 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4579 /** 4580 * Set ABM operating/aggression level. 4581 */ 4582 DMUB_CMD__ABM_SET_LEVEL = 3, 4583 /** 4584 * Set ambient light level. 4585 */ 4586 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4587 /** 4588 * Enable/disable fractional duty cycle for backlight PWM. 4589 */ 4590 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4591 4592 /** 4593 * unregister vertical interrupt after steady state is reached 4594 */ 4595 DMUB_CMD__ABM_PAUSE = 6, 4596 4597 /** 4598 * Save and Restore ABM state. On save we save parameters, and 4599 * on restore we update state with passed in data. 4600 */ 4601 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4602 4603 /** 4604 * Query ABM caps. 4605 */ 4606 DMUB_CMD__ABM_QUERY_CAPS = 8, 4607 4608 /** 4609 * Set ABM Events 4610 */ 4611 DMUB_CMD__ABM_SET_EVENT = 9, 4612 4613 /** 4614 * Get the current ACE curve. 4615 */ 4616 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4617 4618 /** 4619 * Get current histogram data 4620 */ 4621 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4622 }; 4623 4624 /** 4625 * LSDMA command sub-types. 4626 */ 4627 enum dmub_cmd_lsdma_type { 4628 /** 4629 * Initialize parameters for LSDMA. 4630 * Ring buffer is mapped to the ring buffer 4631 */ 4632 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4633 /** 4634 * LSDMA copies data from source to destination linearly 4635 */ 4636 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4637 /** 4638 * Send the tiled-to-tiled copy command 4639 */ 4640 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4641 /** 4642 * Send the poll reg write command 4643 */ 4644 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4645 /** 4646 * Send the pio copy command 4647 */ 4648 DMUB_CMD__LSDMA_PIO_COPY = 4, 4649 /** 4650 * Send the pio constfill command 4651 */ 4652 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4653 }; 4654 4655 struct abm_ace_curve { 4656 /** 4657 * @offsets: ACE curve offsets. 4658 */ 4659 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4660 4661 /** 4662 * @thresholds: ACE curve thresholds. 4663 */ 4664 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4665 4666 /** 4667 * @slopes: ACE curve slopes. 4668 */ 4669 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4670 }; 4671 4672 struct fixed_pt_format { 4673 /** 4674 * @sign_bit: Indicates whether one bit is reserved for the sign. 4675 */ 4676 bool sign_bit; 4677 4678 /** 4679 * @num_int_bits: Number of bits used for integer part. 4680 */ 4681 uint8_t num_int_bits; 4682 4683 /** 4684 * @num_frac_bits: Number of bits used for fractional part. 4685 */ 4686 uint8_t num_frac_bits; 4687 4688 /** 4689 * @pad: Explicit padding to 4 byte boundary. 4690 */ 4691 uint8_t pad; 4692 }; 4693 4694 struct abm_caps { 4695 /** 4696 * @num_hg_bins: Number of histogram bins. 4697 */ 4698 uint8_t num_hg_bins; 4699 4700 /** 4701 * @num_ace_segments: Number of ACE curve segments. 4702 */ 4703 uint8_t num_ace_segments; 4704 4705 /** 4706 * @pad: Explicit padding to 4 byte boundary. 4707 */ 4708 uint8_t pad[2]; 4709 4710 /** 4711 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4712 */ 4713 struct fixed_pt_format ace_thresholds_format; 4714 4715 /** 4716 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4717 */ 4718 struct fixed_pt_format ace_offsets_format; 4719 4720 /** 4721 * @ace_slopes_format: Format of the ACE slopes. 4722 */ 4723 struct fixed_pt_format ace_slopes_format; 4724 }; 4725 4726 /** 4727 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4728 * Requirements: 4729 * - Padded explicitly to 32-bit boundary. 4730 * - Must ensure this structure matches the one on driver-side, 4731 * otherwise it won't be aligned. 4732 */ 4733 struct abm_config_table { 4734 /** 4735 * Gamma curve thresholds, used for crgb conversion. 4736 */ 4737 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4738 /** 4739 * Gamma curve offsets, used for crgb conversion. 4740 */ 4741 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4742 /** 4743 * Gamma curve slopes, used for crgb conversion. 4744 */ 4745 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4746 /** 4747 * Custom backlight curve thresholds. 4748 */ 4749 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4750 /** 4751 * Custom backlight curve offsets. 4752 */ 4753 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4754 /** 4755 * Ambient light thresholds. 4756 */ 4757 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4758 /** 4759 * Minimum programmable backlight. 4760 */ 4761 uint16_t min_abm_backlight; // 122B 4762 /** 4763 * Minimum reduction values. 4764 */ 4765 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4766 /** 4767 * Maximum reduction values. 4768 */ 4769 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4770 /** 4771 * Bright positive gain. 4772 */ 4773 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4774 /** 4775 * Dark negative gain. 4776 */ 4777 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4778 /** 4779 * Hybrid factor. 4780 */ 4781 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4782 /** 4783 * Contrast factor. 4784 */ 4785 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4786 /** 4787 * Deviation gain. 4788 */ 4789 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4790 /** 4791 * Minimum knee. 4792 */ 4793 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4794 /** 4795 * Maximum knee. 4796 */ 4797 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4798 /** 4799 * Unused. 4800 */ 4801 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4802 /** 4803 * Explicit padding to 4 byte boundary. 4804 */ 4805 uint8_t pad3[3]; // 229B 4806 /** 4807 * Backlight ramp reduction. 4808 */ 4809 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4810 /** 4811 * Backlight ramp start. 4812 */ 4813 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4814 }; 4815 4816 /** 4817 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4818 */ 4819 struct dmub_cmd_abm_set_pipe_data { 4820 /** 4821 * OTG HW instance. 4822 */ 4823 uint8_t otg_inst; 4824 4825 /** 4826 * Panel Control HW instance. 4827 */ 4828 uint8_t panel_inst; 4829 4830 /** 4831 * Controls how ABM will interpret a set pipe or set level command. 4832 */ 4833 uint8_t set_pipe_option; 4834 4835 /** 4836 * Unused. 4837 * TODO: Remove. 4838 */ 4839 uint8_t ramping_boundary; 4840 4841 /** 4842 * PwrSeq HW Instance. 4843 */ 4844 uint8_t pwrseq_inst; 4845 4846 /** 4847 * Explicit padding to 4 byte boundary. 4848 */ 4849 uint8_t pad[3]; 4850 }; 4851 4852 /** 4853 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4854 */ 4855 struct dmub_rb_cmd_abm_set_pipe { 4856 /** 4857 * Command header. 4858 */ 4859 struct dmub_cmd_header header; 4860 4861 /** 4862 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4863 */ 4864 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4865 }; 4866 4867 /** 4868 * Type of backlight control method to be used by ABM module 4869 */ 4870 enum dmub_backlight_control_type { 4871 /** 4872 * PWM Backlight control 4873 */ 4874 DMU_BACKLIGHT_CONTROL_PWM = 0, 4875 /** 4876 * VESA Aux-based backlight control 4877 */ 4878 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4879 /** 4880 * AMD DPCD Aux-based backlight control 4881 */ 4882 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4883 }; 4884 4885 /** 4886 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4887 */ 4888 struct dmub_cmd_abm_set_backlight_data { 4889 /** 4890 * Number of frames to ramp to backlight user level. 4891 */ 4892 uint32_t frame_ramp; 4893 4894 /** 4895 * Requested backlight level from user. 4896 */ 4897 uint32_t backlight_user_level; 4898 4899 /** 4900 * ABM control version. 4901 */ 4902 uint8_t version; 4903 4904 /** 4905 * Panel Control HW instance mask. 4906 * Bit 0 is Panel Control HW instance 0. 4907 * Bit 1 is Panel Control HW instance 1. 4908 */ 4909 uint8_t panel_mask; 4910 4911 /** 4912 * AUX HW Instance. 4913 */ 4914 uint8_t aux_inst; 4915 4916 /** 4917 * Explicit padding to 4 byte boundary. 4918 */ 4919 uint8_t pad[1]; 4920 4921 /** 4922 * Backlight control type. 4923 * Value 0 is PWM backlight control. 4924 * Value 1 is VAUX backlight control. 4925 * Value 2 is AMD DPCD AUX backlight control. 4926 */ 4927 enum dmub_backlight_control_type backlight_control_type; 4928 4929 /** 4930 * Minimum luminance in nits. 4931 */ 4932 uint32_t min_luminance; 4933 4934 /** 4935 * Maximum luminance in nits. 4936 */ 4937 uint32_t max_luminance; 4938 4939 /** 4940 * Minimum backlight in pwm. 4941 */ 4942 uint32_t min_backlight_pwm; 4943 4944 /** 4945 * Maximum backlight in pwm. 4946 */ 4947 uint32_t max_backlight_pwm; 4948 }; 4949 4950 /** 4951 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4952 */ 4953 struct dmub_rb_cmd_abm_set_backlight { 4954 /** 4955 * Command header. 4956 */ 4957 struct dmub_cmd_header header; 4958 4959 /** 4960 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4961 */ 4962 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4963 }; 4964 4965 /** 4966 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4967 */ 4968 struct dmub_cmd_abm_set_level_data { 4969 /** 4970 * Set current ABM operating/aggression level. 4971 */ 4972 uint32_t level; 4973 4974 /** 4975 * ABM control version. 4976 */ 4977 uint8_t version; 4978 4979 /** 4980 * Panel Control HW instance mask. 4981 * Bit 0 is Panel Control HW instance 0. 4982 * Bit 1 is Panel Control HW instance 1. 4983 */ 4984 uint8_t panel_mask; 4985 4986 /** 4987 * Explicit padding to 4 byte boundary. 4988 */ 4989 uint8_t pad[2]; 4990 }; 4991 4992 /** 4993 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4994 */ 4995 struct dmub_rb_cmd_abm_set_level { 4996 /** 4997 * Command header. 4998 */ 4999 struct dmub_cmd_header header; 5000 5001 /** 5002 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5003 */ 5004 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5005 }; 5006 5007 /** 5008 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5009 */ 5010 struct dmub_cmd_abm_set_ambient_level_data { 5011 /** 5012 * Ambient light sensor reading from OS. 5013 */ 5014 uint32_t ambient_lux; 5015 5016 /** 5017 * ABM control version. 5018 */ 5019 uint8_t version; 5020 5021 /** 5022 * Panel Control HW instance mask. 5023 * Bit 0 is Panel Control HW instance 0. 5024 * Bit 1 is Panel Control HW instance 1. 5025 */ 5026 uint8_t panel_mask; 5027 5028 /** 5029 * Explicit padding to 4 byte boundary. 5030 */ 5031 uint8_t pad[2]; 5032 }; 5033 5034 /** 5035 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5036 */ 5037 struct dmub_rb_cmd_abm_set_ambient_level { 5038 /** 5039 * Command header. 5040 */ 5041 struct dmub_cmd_header header; 5042 5043 /** 5044 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5045 */ 5046 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5047 }; 5048 5049 /** 5050 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5051 */ 5052 struct dmub_cmd_abm_set_pwm_frac_data { 5053 /** 5054 * Enable/disable fractional duty cycle for backlight PWM. 5055 * TODO: Convert to uint8_t. 5056 */ 5057 uint32_t fractional_pwm; 5058 5059 /** 5060 * ABM control version. 5061 */ 5062 uint8_t version; 5063 5064 /** 5065 * Panel Control HW instance mask. 5066 * Bit 0 is Panel Control HW instance 0. 5067 * Bit 1 is Panel Control HW instance 1. 5068 */ 5069 uint8_t panel_mask; 5070 5071 /** 5072 * Explicit padding to 4 byte boundary. 5073 */ 5074 uint8_t pad[2]; 5075 }; 5076 5077 /** 5078 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5079 */ 5080 struct dmub_rb_cmd_abm_set_pwm_frac { 5081 /** 5082 * Command header. 5083 */ 5084 struct dmub_cmd_header header; 5085 5086 /** 5087 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5088 */ 5089 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5090 }; 5091 5092 /** 5093 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5094 */ 5095 struct dmub_cmd_abm_init_config_data { 5096 /** 5097 * Location of indirect buffer used to pass init data to ABM. 5098 */ 5099 union dmub_addr src; 5100 5101 /** 5102 * Indirect buffer length. 5103 */ 5104 uint16_t bytes; 5105 5106 5107 /** 5108 * ABM control version. 5109 */ 5110 uint8_t version; 5111 5112 /** 5113 * Panel Control HW instance mask. 5114 * Bit 0 is Panel Control HW instance 0. 5115 * Bit 1 is Panel Control HW instance 1. 5116 */ 5117 uint8_t panel_mask; 5118 5119 /** 5120 * Explicit padding to 4 byte boundary. 5121 */ 5122 uint8_t pad[2]; 5123 }; 5124 5125 /** 5126 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5127 */ 5128 struct dmub_rb_cmd_abm_init_config { 5129 /** 5130 * Command header. 5131 */ 5132 struct dmub_cmd_header header; 5133 5134 /** 5135 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5136 */ 5137 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5138 }; 5139 5140 /** 5141 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5142 */ 5143 5144 struct dmub_cmd_abm_pause_data { 5145 5146 /** 5147 * Panel Control HW instance mask. 5148 * Bit 0 is Panel Control HW instance 0. 5149 * Bit 1 is Panel Control HW instance 1. 5150 */ 5151 uint8_t panel_mask; 5152 5153 /** 5154 * OTG hw instance 5155 */ 5156 uint8_t otg_inst; 5157 5158 /** 5159 * Enable or disable ABM pause 5160 */ 5161 uint8_t enable; 5162 5163 /** 5164 * Explicit padding to 4 byte boundary. 5165 */ 5166 uint8_t pad[1]; 5167 }; 5168 5169 /** 5170 * Definition of a DMUB_CMD__ABM_PAUSE command. 5171 */ 5172 struct dmub_rb_cmd_abm_pause { 5173 /** 5174 * Command header. 5175 */ 5176 struct dmub_cmd_header header; 5177 5178 /** 5179 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5180 */ 5181 struct dmub_cmd_abm_pause_data abm_pause_data; 5182 }; 5183 5184 /** 5185 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5186 */ 5187 struct dmub_cmd_abm_query_caps_in { 5188 /** 5189 * Panel instance. 5190 */ 5191 uint8_t panel_inst; 5192 5193 /** 5194 * Explicit padding to 4 byte boundary. 5195 */ 5196 uint8_t pad[3]; 5197 }; 5198 5199 /** 5200 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5201 */ 5202 struct dmub_cmd_abm_query_caps_out { 5203 /** 5204 * SW Algorithm caps. 5205 */ 5206 struct abm_caps sw_caps; 5207 5208 /** 5209 * ABM HW caps. 5210 */ 5211 struct abm_caps hw_caps; 5212 }; 5213 5214 /** 5215 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5216 */ 5217 struct dmub_rb_cmd_abm_query_caps { 5218 /** 5219 * Command header. 5220 */ 5221 struct dmub_cmd_header header; 5222 5223 /** 5224 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5225 */ 5226 union { 5227 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5228 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5229 } data; 5230 }; 5231 5232 /** 5233 * enum dmub_abm_ace_curve_type - ACE curve type. 5234 */ 5235 enum dmub_abm_ace_curve_type { 5236 /** 5237 * ACE curve as defined by the SW layer. 5238 */ 5239 ABM_ACE_CURVE_TYPE__SW = 0, 5240 /** 5241 * ACE curve as defined by the SW to HW translation interface layer. 5242 */ 5243 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5244 }; 5245 5246 /** 5247 * enum dmub_abm_histogram_type - Histogram type. 5248 */ 5249 enum dmub_abm_histogram_type { 5250 /** 5251 * ACE curve as defined by the SW layer. 5252 */ 5253 ABM_HISTOGRAM_TYPE__SW = 0, 5254 /** 5255 * ACE curve as defined by the SW to HW translation interface layer. 5256 */ 5257 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5258 }; 5259 5260 /** 5261 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5262 */ 5263 struct dmub_rb_cmd_abm_get_ace_curve { 5264 /** 5265 * Command header. 5266 */ 5267 struct dmub_cmd_header header; 5268 5269 /** 5270 * Address where ACE curve should be copied. 5271 */ 5272 union dmub_addr dest; 5273 5274 /** 5275 * Type of ACE curve being queried. 5276 */ 5277 enum dmub_abm_ace_curve_type ace_type; 5278 5279 /** 5280 * Indirect buffer length. 5281 */ 5282 uint16_t bytes; 5283 5284 /** 5285 * eDP panel instance. 5286 */ 5287 uint8_t panel_inst; 5288 5289 /** 5290 * Explicit padding to 4 byte boundary. 5291 */ 5292 uint8_t pad; 5293 }; 5294 5295 /** 5296 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5297 */ 5298 struct dmub_rb_cmd_abm_get_histogram { 5299 /** 5300 * Command header. 5301 */ 5302 struct dmub_cmd_header header; 5303 5304 /** 5305 * Address where Histogram should be copied. 5306 */ 5307 union dmub_addr dest; 5308 5309 /** 5310 * Type of Histogram being queried. 5311 */ 5312 enum dmub_abm_histogram_type histogram_type; 5313 5314 /** 5315 * Indirect buffer length. 5316 */ 5317 uint16_t bytes; 5318 5319 /** 5320 * eDP panel instance. 5321 */ 5322 uint8_t panel_inst; 5323 5324 /** 5325 * Explicit padding to 4 byte boundary. 5326 */ 5327 uint8_t pad; 5328 }; 5329 5330 /** 5331 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5332 */ 5333 struct dmub_rb_cmd_abm_save_restore { 5334 /** 5335 * Command header. 5336 */ 5337 struct dmub_cmd_header header; 5338 5339 /** 5340 * OTG hw instance 5341 */ 5342 uint8_t otg_inst; 5343 5344 /** 5345 * Enable or disable ABM pause 5346 */ 5347 uint8_t freeze; 5348 5349 /** 5350 * Explicit padding to 4 byte boundary. 5351 */ 5352 uint8_t debug; 5353 5354 /** 5355 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5356 */ 5357 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5358 }; 5359 5360 /** 5361 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5362 */ 5363 5364 struct dmub_cmd_abm_set_event_data { 5365 5366 /** 5367 * VB Scaling Init. Strength Mapping 5368 * Byte 0: 0~255 for VB level 0 5369 * Byte 1: 0~255 for VB level 1 5370 * Byte 2: 0~255 for VB level 2 5371 * Byte 3: 0~255 for VB level 3 5372 */ 5373 uint32_t vb_scaling_strength_mapping; 5374 /** 5375 * VariBright Scaling Enable 5376 */ 5377 uint8_t vb_scaling_enable; 5378 /** 5379 * Panel Control HW instance mask. 5380 * Bit 0 is Panel Control HW instance 0. 5381 * Bit 1 is Panel Control HW instance 1. 5382 */ 5383 uint8_t panel_mask; 5384 5385 /** 5386 * Explicit padding to 4 byte boundary. 5387 */ 5388 uint8_t pad[2]; 5389 }; 5390 5391 /** 5392 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5393 */ 5394 struct dmub_rb_cmd_abm_set_event { 5395 /** 5396 * Command header. 5397 */ 5398 struct dmub_cmd_header header; 5399 5400 /** 5401 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5402 */ 5403 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5404 }; 5405 5406 /** 5407 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5408 */ 5409 struct dmub_cmd_query_feature_caps_data { 5410 /** 5411 * DMUB feature capabilities. 5412 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5413 */ 5414 struct dmub_feature_caps feature_caps; 5415 }; 5416 5417 /** 5418 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5419 */ 5420 struct dmub_rb_cmd_query_feature_caps { 5421 /** 5422 * Command header. 5423 */ 5424 struct dmub_cmd_header header; 5425 /** 5426 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5427 */ 5428 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5429 }; 5430 5431 /** 5432 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5433 */ 5434 struct dmub_cmd_visual_confirm_color_data { 5435 /** 5436 * DMUB visual confirm color 5437 */ 5438 struct dmub_visual_confirm_color visual_confirm_color; 5439 }; 5440 5441 /** 5442 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5443 */ 5444 struct dmub_rb_cmd_get_visual_confirm_color { 5445 /** 5446 * Command header. 5447 */ 5448 struct dmub_cmd_header header; 5449 /** 5450 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5451 */ 5452 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5453 }; 5454 5455 /** 5456 * enum dmub_cmd_panel_cntl_type - Panel control command. 5457 */ 5458 enum dmub_cmd_panel_cntl_type { 5459 /** 5460 * Initializes embedded panel hardware blocks. 5461 */ 5462 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5463 /** 5464 * Queries backlight info for the embedded panel. 5465 */ 5466 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5467 /** 5468 * Sets the PWM Freq as per user's requirement. 5469 */ 5470 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5471 }; 5472 5473 /** 5474 * struct dmub_cmd_panel_cntl_data - Panel control data. 5475 */ 5476 struct dmub_cmd_panel_cntl_data { 5477 uint32_t pwrseq_inst; /**< pwrseq instance */ 5478 uint32_t current_backlight; /* in/out */ 5479 uint32_t bl_pwm_cntl; /* in/out */ 5480 uint32_t bl_pwm_period_cntl; /* in/out */ 5481 uint32_t bl_pwm_ref_div1; /* in/out */ 5482 uint8_t is_backlight_on : 1; /* in/out */ 5483 uint8_t is_powered_on : 1; /* in/out */ 5484 uint8_t padding[3]; 5485 uint32_t bl_pwm_ref_div2; /* in/out */ 5486 uint8_t reserved[4]; 5487 }; 5488 5489 /** 5490 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5491 */ 5492 struct dmub_rb_cmd_panel_cntl { 5493 struct dmub_cmd_header header; /**< header */ 5494 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5495 }; 5496 5497 struct dmub_optc_state { 5498 uint32_t v_total_max; 5499 uint32_t v_total_min; 5500 uint32_t tg_inst; 5501 }; 5502 5503 struct dmub_rb_cmd_drr_update { 5504 struct dmub_cmd_header header; 5505 struct dmub_optc_state dmub_optc_state_req; 5506 }; 5507 5508 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5509 uint32_t pix_clk_100hz; 5510 uint8_t max_ramp_step; 5511 uint8_t pipes; 5512 uint8_t min_refresh_in_hz; 5513 uint8_t pipe_count; 5514 uint8_t pipe_index[4]; 5515 }; 5516 5517 struct dmub_cmd_fw_assisted_mclk_switch_config { 5518 uint8_t fams_enabled; 5519 uint8_t visual_confirm_enabled; 5520 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5521 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5522 }; 5523 5524 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5525 struct dmub_cmd_header header; 5526 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5527 }; 5528 5529 /** 5530 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5531 */ 5532 struct dmub_cmd_lvtma_control_data { 5533 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5534 uint8_t bypass_panel_control_wait; 5535 uint8_t reserved_0[2]; /**< For future use */ 5536 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5537 uint8_t reserved_1[3]; /**< For future use */ 5538 }; 5539 5540 /** 5541 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5542 */ 5543 struct dmub_rb_cmd_lvtma_control { 5544 /** 5545 * Command header. 5546 */ 5547 struct dmub_cmd_header header; 5548 /** 5549 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5550 */ 5551 struct dmub_cmd_lvtma_control_data data; 5552 }; 5553 5554 /** 5555 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5556 */ 5557 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5558 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5559 uint8_t is_usb; /**< is phy is usb */ 5560 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5561 uint8_t is_dp4; /**< is dp in 4 lane */ 5562 }; 5563 5564 /** 5565 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5566 */ 5567 struct dmub_rb_cmd_transmitter_query_dp_alt { 5568 struct dmub_cmd_header header; /**< header */ 5569 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5570 }; 5571 5572 struct phy_test_mode { 5573 uint8_t mode; 5574 uint8_t pat0; 5575 uint8_t pad[2]; 5576 }; 5577 5578 /** 5579 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5580 */ 5581 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5582 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5583 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5584 uint8_t lane_num; /**< Number of lanes */ 5585 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5586 struct phy_test_mode test_mode; 5587 enum dmub_phy_fsm_state state; 5588 uint32_t status; 5589 uint8_t pad; 5590 }; 5591 5592 /** 5593 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5594 */ 5595 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5596 struct dmub_cmd_header header; /**< header */ 5597 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5598 }; 5599 5600 /** 5601 * Maximum number of bytes a chunk sent to DMUB for parsing 5602 */ 5603 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5604 5605 /** 5606 * Represent a chunk of CEA blocks sent to DMUB for parsing 5607 */ 5608 struct dmub_cmd_send_edid_cea { 5609 uint16_t offset; /**< offset into the CEA block */ 5610 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5611 uint16_t cea_total_length; /**< total length of the CEA block */ 5612 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5613 uint8_t pad[3]; /**< padding and for future expansion */ 5614 }; 5615 5616 /** 5617 * Result of VSDB parsing from CEA block 5618 */ 5619 struct dmub_cmd_edid_cea_amd_vsdb { 5620 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5621 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5622 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5623 uint16_t min_frame_rate; /**< Maximum frame rate */ 5624 uint16_t max_frame_rate; /**< Minimum frame rate */ 5625 }; 5626 5627 /** 5628 * Result of sending a CEA chunk 5629 */ 5630 struct dmub_cmd_edid_cea_ack { 5631 uint16_t offset; /**< offset of the chunk into the CEA block */ 5632 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5633 uint8_t pad; /**< padding and for future expansion */ 5634 }; 5635 5636 /** 5637 * Specify whether the result is an ACK/NACK or the parsing has finished 5638 */ 5639 enum dmub_cmd_edid_cea_reply_type { 5640 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5641 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5642 }; 5643 5644 /** 5645 * Definition of a DMUB_CMD__EDID_CEA command. 5646 */ 5647 struct dmub_rb_cmd_edid_cea { 5648 struct dmub_cmd_header header; /**< Command header */ 5649 union dmub_cmd_edid_cea_data { 5650 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5651 struct dmub_cmd_edid_cea_output { /**< output with results */ 5652 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5653 union { 5654 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5655 struct dmub_cmd_edid_cea_ack ack; 5656 }; 5657 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5658 } data; /**< Command data */ 5659 5660 }; 5661 5662 /** 5663 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5664 */ 5665 struct dmub_cmd_cable_id_input { 5666 uint8_t phy_inst; /**< phy inst for cable id data */ 5667 }; 5668 5669 /** 5670 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5671 */ 5672 struct dmub_cmd_cable_id_output { 5673 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5674 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5675 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5676 uint8_t RESERVED :2; /**< reserved means not defined */ 5677 }; 5678 5679 /** 5680 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5681 */ 5682 struct dmub_rb_cmd_get_usbc_cable_id { 5683 struct dmub_cmd_header header; /**< Command header */ 5684 /** 5685 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5686 */ 5687 union dmub_cmd_cable_id_data { 5688 struct dmub_cmd_cable_id_input input; /**< Input */ 5689 struct dmub_cmd_cable_id_output output; /**< Output */ 5690 uint8_t output_raw; /**< Raw data output */ 5691 } data; 5692 }; 5693 5694 enum dmub_cmd_fused_io_sub_type { 5695 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5696 DMUB_CMD__FUSED_IO_ABORT = 1, 5697 }; 5698 5699 enum dmub_cmd_fused_request_type { 5700 FUSED_REQUEST_READ, 5701 FUSED_REQUEST_WRITE, 5702 FUSED_REQUEST_POLL, 5703 }; 5704 5705 enum dmub_cmd_fused_request_status { 5706 FUSED_REQUEST_STATUS_SUCCESS, 5707 FUSED_REQUEST_STATUS_BEGIN, 5708 FUSED_REQUEST_STATUS_SUBMIT, 5709 FUSED_REQUEST_STATUS_REPLY, 5710 FUSED_REQUEST_STATUS_POLL, 5711 FUSED_REQUEST_STATUS_ABORTED, 5712 FUSED_REQUEST_STATUS_FAILED = 0x80, 5713 FUSED_REQUEST_STATUS_INVALID, 5714 FUSED_REQUEST_STATUS_BUSY, 5715 FUSED_REQUEST_STATUS_TIMEOUT, 5716 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5717 }; 5718 5719 struct dmub_cmd_fused_request { 5720 uint8_t status; 5721 uint8_t type : 2; 5722 uint8_t _reserved0 : 3; 5723 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5724 uint8_t identifier; 5725 uint8_t _reserved1; 5726 uint32_t timeout_us; 5727 union dmub_cmd_fused_request_location { 5728 struct dmub_cmd_fused_request_location_i2c { 5729 uint8_t is_aux : 1; // False 5730 uint8_t ddc_line : 3; 5731 uint8_t over_aux : 1; 5732 uint8_t _reserved0 : 3; 5733 uint8_t address; 5734 uint8_t offset; 5735 uint8_t length; 5736 } i2c; 5737 struct dmub_cmd_fused_request_location_aux { 5738 uint32_t is_aux : 1; // True 5739 uint32_t ddc_line : 3; 5740 uint32_t address : 20; 5741 uint32_t length : 8; // Automatically split into 16B transactions 5742 } aux; 5743 } u; 5744 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5745 }; 5746 5747 struct dmub_rb_cmd_fused_io { 5748 struct dmub_cmd_header header; 5749 struct dmub_cmd_fused_request request; 5750 }; 5751 5752 /** 5753 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5754 */ 5755 enum dmub_cmd_secure_display_type { 5756 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5757 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5758 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5759 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5760 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5761 }; 5762 5763 #define MAX_ROI_NUM 2 5764 5765 struct dmub_cmd_roi_info { 5766 uint16_t x_start; 5767 uint16_t x_end; 5768 uint16_t y_start; 5769 uint16_t y_end; 5770 uint8_t otg_id; 5771 uint8_t phy_id; 5772 }; 5773 5774 struct dmub_cmd_roi_window_ctl { 5775 uint16_t x_start; 5776 uint16_t x_end; 5777 uint16_t y_start; 5778 uint16_t y_end; 5779 bool enable; 5780 }; 5781 5782 struct dmub_cmd_roi_ctl_info { 5783 uint8_t otg_id; 5784 uint8_t phy_id; 5785 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5786 }; 5787 5788 /** 5789 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5790 */ 5791 struct dmub_rb_cmd_secure_display { 5792 struct dmub_cmd_header header; 5793 /** 5794 * Data passed from driver to dmub firmware. 5795 */ 5796 struct dmub_cmd_roi_info roi_info; 5797 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5798 }; 5799 5800 /** 5801 * Command type of a DMUB_CMD__PSP command 5802 */ 5803 enum dmub_cmd_psp_type { 5804 DMUB_CMD__PSP_ASSR_ENABLE = 0 5805 }; 5806 5807 /** 5808 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5809 */ 5810 struct dmub_cmd_assr_enable_data { 5811 /** 5812 * ASSR enable or disable. 5813 */ 5814 uint8_t enable; 5815 /** 5816 * PHY port type. 5817 * Indicates eDP / non-eDP port type 5818 */ 5819 uint8_t phy_port_type; 5820 /** 5821 * PHY port ID. 5822 */ 5823 uint8_t phy_port_id; 5824 /** 5825 * Link encoder index. 5826 */ 5827 uint8_t link_enc_index; 5828 /** 5829 * HPO mode. 5830 */ 5831 uint8_t hpo_mode; 5832 5833 /** 5834 * Reserved field. 5835 */ 5836 uint8_t reserved[7]; 5837 }; 5838 5839 /** 5840 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5841 */ 5842 struct dmub_rb_cmd_assr_enable { 5843 /** 5844 * Command header. 5845 */ 5846 struct dmub_cmd_header header; 5847 5848 /** 5849 * Assr data. 5850 */ 5851 struct dmub_cmd_assr_enable_data assr_data; 5852 5853 /** 5854 * Reserved field. 5855 */ 5856 uint32_t reserved[3]; 5857 }; 5858 5859 /** 5860 * union dmub_rb_cmd - DMUB inbox command. 5861 */ 5862 union dmub_rb_cmd { 5863 /** 5864 * Elements shared with all commands. 5865 */ 5866 struct dmub_rb_cmd_common cmd_common; 5867 /** 5868 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5869 */ 5870 struct dmub_rb_cmd_read_modify_write read_modify_write; 5871 /** 5872 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5873 */ 5874 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5875 /** 5876 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5877 */ 5878 struct dmub_rb_cmd_burst_write burst_write; 5879 /** 5880 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5881 */ 5882 struct dmub_rb_cmd_reg_wait reg_wait; 5883 /** 5884 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5885 */ 5886 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5887 /** 5888 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5889 */ 5890 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5891 /** 5892 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5893 */ 5894 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5895 /** 5896 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5897 */ 5898 struct dmub_rb_cmd_dpphy_init dpphy_init; 5899 /** 5900 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5901 */ 5902 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5903 /** 5904 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5905 */ 5906 struct dmub_rb_cmd_domain_control domain_control; 5907 /** 5908 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5909 */ 5910 struct dmub_rb_cmd_psr_set_version psr_set_version; 5911 /** 5912 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5913 */ 5914 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5915 /** 5916 * Definition of a DMUB_CMD__PSR_ENABLE command. 5917 */ 5918 struct dmub_rb_cmd_psr_enable psr_enable; 5919 /** 5920 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5921 */ 5922 struct dmub_rb_cmd_psr_set_level psr_set_level; 5923 /** 5924 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5925 */ 5926 struct dmub_rb_cmd_psr_force_static psr_force_static; 5927 /** 5928 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5929 */ 5930 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5931 /** 5932 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5933 */ 5934 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5935 /** 5936 * Definition of a DMUB_CMD__HW_LOCK command. 5937 * Command is used by driver and FW. 5938 */ 5939 struct dmub_rb_cmd_lock_hw lock_hw; 5940 /** 5941 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5942 */ 5943 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5944 /** 5945 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5946 */ 5947 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5948 /** 5949 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5950 */ 5951 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5952 /** 5953 * Definition of a DMUB_CMD__MALL command. 5954 */ 5955 struct dmub_rb_cmd_mall mall; 5956 5957 /** 5958 * Definition of a DMUB_CMD__CAB command. 5959 */ 5960 struct dmub_rb_cmd_cab_for_ss cab; 5961 5962 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5963 5964 /** 5965 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5966 */ 5967 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5968 5969 /** 5970 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5971 */ 5972 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5973 5974 /** 5975 * Definition of DMUB_CMD__PANEL_CNTL commands. 5976 */ 5977 struct dmub_rb_cmd_panel_cntl panel_cntl; 5978 5979 /** 5980 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5981 */ 5982 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5983 5984 /** 5985 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5986 */ 5987 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5988 5989 /** 5990 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5991 */ 5992 struct dmub_rb_cmd_abm_set_level abm_set_level; 5993 5994 /** 5995 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5996 */ 5997 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5998 5999 /** 6000 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6001 */ 6002 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6003 6004 /** 6005 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6006 */ 6007 struct dmub_rb_cmd_abm_init_config abm_init_config; 6008 6009 /** 6010 * Definition of a DMUB_CMD__ABM_PAUSE command. 6011 */ 6012 struct dmub_rb_cmd_abm_pause abm_pause; 6013 6014 /** 6015 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6016 */ 6017 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6018 6019 /** 6020 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6021 */ 6022 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6023 6024 /** 6025 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6026 */ 6027 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6028 6029 /** 6030 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6031 */ 6032 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6033 6034 /** 6035 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6036 */ 6037 struct dmub_rb_cmd_abm_set_event abm_set_event; 6038 6039 /** 6040 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6041 */ 6042 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6043 6044 /** 6045 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6046 */ 6047 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6048 6049 /** 6050 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6051 */ 6052 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6053 6054 /** 6055 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6056 */ 6057 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6058 struct dmub_rb_cmd_drr_update drr_update; 6059 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6060 6061 /** 6062 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6063 */ 6064 struct dmub_rb_cmd_lvtma_control lvtma_control; 6065 /** 6066 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6067 */ 6068 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6069 /** 6070 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6071 */ 6072 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6073 /** 6074 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6075 */ 6076 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6077 /** 6078 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6079 */ 6080 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6081 /** 6082 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6083 */ 6084 struct dmub_rb_cmd_set_config_request set_config_request; 6085 /** 6086 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6087 */ 6088 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6089 /** 6090 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6091 */ 6092 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6093 /** 6094 * Definition of a DMUB_CMD__EDID_CEA command. 6095 */ 6096 struct dmub_rb_cmd_edid_cea edid_cea; 6097 /** 6098 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6099 */ 6100 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6101 6102 /** 6103 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6104 */ 6105 struct dmub_rb_cmd_query_hpd_state query_hpd; 6106 /** 6107 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6108 */ 6109 struct dmub_rb_cmd_secure_display secure_display; 6110 6111 /** 6112 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6113 */ 6114 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6115 /** 6116 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6117 */ 6118 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6119 /** 6120 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6121 */ 6122 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6123 /* 6124 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6125 */ 6126 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6127 /** 6128 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6129 */ 6130 struct dmub_rb_cmd_replay_enable replay_enable; 6131 /** 6132 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6133 */ 6134 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6135 /** 6136 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6137 */ 6138 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6139 /** 6140 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6141 */ 6142 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6143 6144 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6145 /** 6146 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6147 */ 6148 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6149 /** 6150 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6151 */ 6152 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6153 /** 6154 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6155 */ 6156 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6157 /** 6158 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6159 */ 6160 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6161 /** 6162 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6163 */ 6164 struct dmub_rb_cmd_assr_enable assr_enable; 6165 6166 struct dmub_rb_cmd_fams2 fams2_config; 6167 6168 struct dmub_rb_cmd_ib ib_fams2_config; 6169 6170 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6171 6172 struct dmub_rb_cmd_fams2_flip fams2_flip; 6173 6174 struct dmub_rb_cmd_fused_io fused_io; 6175 6176 /** 6177 * Definition of a DMUB_CMD__LSDMA command. 6178 */ 6179 struct dmub_rb_cmd_lsdma lsdma; 6180 }; 6181 6182 /** 6183 * union dmub_rb_out_cmd - Outbox command 6184 */ 6185 union dmub_rb_out_cmd { 6186 /** 6187 * Parameters common to every command. 6188 */ 6189 struct dmub_rb_cmd_common cmd_common; 6190 /** 6191 * AUX reply command. 6192 */ 6193 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6194 /** 6195 * HPD notify command. 6196 */ 6197 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6198 /** 6199 * SET_CONFIG reply command. 6200 */ 6201 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6202 /** 6203 * DPIA notification command. 6204 */ 6205 struct dmub_rb_cmd_dpia_notification dpia_notification; 6206 /** 6207 * HPD sense notification command. 6208 */ 6209 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6210 struct dmub_rb_cmd_fused_io fused_io; 6211 }; 6212 #pragma pack(pop) 6213 6214 6215 //============================================================================== 6216 //</DMUB_CMD>=================================================================== 6217 //============================================================================== 6218 //< DMUB_RB>==================================================================== 6219 //============================================================================== 6220 6221 /** 6222 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6223 */ 6224 struct dmub_rb_init_params { 6225 void *ctx; /**< Caller provided context pointer */ 6226 void *base_address; /**< CPU base address for ring's data */ 6227 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6228 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6229 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6230 }; 6231 6232 /** 6233 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6234 */ 6235 struct dmub_rb { 6236 void *base_address; /**< CPU address for the ring's data */ 6237 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6238 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6239 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6240 6241 void *ctx; /**< Caller provided context pointer */ 6242 void *dmub; /**< Pointer to the DMUB interface */ 6243 }; 6244 6245 /** 6246 * @brief Checks if the ringbuffer is empty. 6247 * 6248 * @param rb DMUB Ringbuffer 6249 * @return true if empty 6250 * @return false otherwise 6251 */ 6252 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6253 { 6254 return (rb->wrpt == rb->rptr); 6255 } 6256 6257 /** 6258 * @brief gets number of outstanding requests in the RB 6259 * 6260 * @param rb DMUB Ringbuffer 6261 * @return true if full 6262 */ 6263 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6264 { 6265 uint32_t data_count; 6266 6267 if (rb->wrpt >= rb->rptr) 6268 data_count = rb->wrpt - rb->rptr; 6269 else 6270 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6271 6272 return data_count / DMUB_RB_CMD_SIZE; 6273 } 6274 6275 /** 6276 * @brief gets number of free buffers in the RB 6277 * 6278 * @param rb DMUB Ringbuffer 6279 * @return true if full 6280 */ 6281 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6282 { 6283 uint32_t data_count; 6284 6285 if (rb->wrpt >= rb->rptr) 6286 data_count = rb->wrpt - rb->rptr; 6287 else 6288 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6289 6290 /* +1 because 1 entry is always unusable */ 6291 data_count += DMUB_RB_CMD_SIZE; 6292 6293 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6294 } 6295 6296 /** 6297 * @brief Checks if the ringbuffer is full 6298 * 6299 * @param rb DMUB Ringbuffer 6300 * @return true if full 6301 * @return false otherwise 6302 */ 6303 static inline bool dmub_rb_full(struct dmub_rb *rb) 6304 { 6305 uint32_t data_count; 6306 6307 if (rb->wrpt >= rb->rptr) 6308 data_count = rb->wrpt - rb->rptr; 6309 else 6310 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6311 6312 /* -1 because 1 entry is always unusable */ 6313 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6314 } 6315 6316 /** 6317 * @brief Pushes a command into the ringbuffer 6318 * 6319 * @param rb DMUB ringbuffer 6320 * @param cmd The command to push 6321 * @return true if the ringbuffer was not full 6322 * @return false otherwise 6323 */ 6324 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6325 const union dmub_rb_cmd *cmd) 6326 { 6327 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6328 const uint64_t *src = (const uint64_t *)cmd; 6329 uint8_t i; 6330 6331 if (dmub_rb_full(rb)) 6332 return false; 6333 6334 // copying data 6335 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6336 *dst++ = *src++; 6337 6338 rb->wrpt += DMUB_RB_CMD_SIZE; 6339 6340 if (rb->wrpt >= rb->capacity) 6341 rb->wrpt %= rb->capacity; 6342 6343 return true; 6344 } 6345 6346 /** 6347 * @brief Pushes a command into the DMUB outbox ringbuffer 6348 * 6349 * @param rb DMUB outbox ringbuffer 6350 * @param cmd Outbox command 6351 * @return true if not full 6352 * @return false otherwise 6353 */ 6354 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6355 const union dmub_rb_out_cmd *cmd) 6356 { 6357 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6358 const uint8_t *src = (const uint8_t *)cmd; 6359 6360 if (dmub_rb_full(rb)) 6361 return false; 6362 6363 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6364 6365 rb->wrpt += DMUB_RB_CMD_SIZE; 6366 6367 if (rb->wrpt >= rb->capacity) 6368 rb->wrpt %= rb->capacity; 6369 6370 return true; 6371 } 6372 6373 /** 6374 * @brief Returns the next unprocessed command in the ringbuffer. 6375 * 6376 * @param rb DMUB ringbuffer 6377 * @param cmd The command to return 6378 * @return true if not empty 6379 * @return false otherwise 6380 */ 6381 static inline bool dmub_rb_front(struct dmub_rb *rb, 6382 union dmub_rb_cmd **cmd) 6383 { 6384 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6385 6386 if (dmub_rb_empty(rb)) 6387 return false; 6388 6389 *cmd = (union dmub_rb_cmd *)rb_cmd; 6390 6391 return true; 6392 } 6393 6394 /** 6395 * @brief Determines the next ringbuffer offset. 6396 * 6397 * @param rb DMUB inbox ringbuffer 6398 * @param num_cmds Number of commands 6399 * @param next_rptr The next offset in the ringbuffer 6400 */ 6401 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6402 uint32_t num_cmds, 6403 uint32_t *next_rptr) 6404 { 6405 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6406 6407 if (*next_rptr >= rb->capacity) 6408 *next_rptr %= rb->capacity; 6409 } 6410 6411 /** 6412 * @brief Returns a pointer to a command in the inbox. 6413 * 6414 * @param rb DMUB inbox ringbuffer 6415 * @param cmd The inbox command to return 6416 * @param rptr The ringbuffer offset 6417 * @return true if not empty 6418 * @return false otherwise 6419 */ 6420 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6421 union dmub_rb_cmd **cmd, 6422 uint32_t rptr) 6423 { 6424 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6425 6426 if (dmub_rb_empty(rb)) 6427 return false; 6428 6429 *cmd = (union dmub_rb_cmd *)rb_cmd; 6430 6431 return true; 6432 } 6433 6434 /** 6435 * @brief Returns the next unprocessed command in the outbox. 6436 * 6437 * @param rb DMUB outbox ringbuffer 6438 * @param cmd The outbox command to return 6439 * @return true if not empty 6440 * @return false otherwise 6441 */ 6442 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6443 union dmub_rb_out_cmd *cmd) 6444 { 6445 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6446 uint64_t *dst = (uint64_t *)cmd; 6447 uint8_t i; 6448 6449 if (dmub_rb_empty(rb)) 6450 return false; 6451 6452 // copying data 6453 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6454 *dst++ = *src++; 6455 6456 return true; 6457 } 6458 6459 /** 6460 * @brief Removes the front entry in the ringbuffer. 6461 * 6462 * @param rb DMUB ringbuffer 6463 * @return true if the command was removed 6464 * @return false if there were no commands 6465 */ 6466 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6467 { 6468 if (dmub_rb_empty(rb)) 6469 return false; 6470 6471 rb->rptr += DMUB_RB_CMD_SIZE; 6472 6473 if (rb->rptr >= rb->capacity) 6474 rb->rptr %= rb->capacity; 6475 6476 return true; 6477 } 6478 6479 /** 6480 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6481 * 6482 * Avoids a race condition where DMCUB accesses memory while 6483 * there are still writes in flight to framebuffer. 6484 * 6485 * @param rb DMUB ringbuffer 6486 */ 6487 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6488 { 6489 uint32_t rptr = rb->rptr; 6490 uint32_t wptr = rb->wrpt; 6491 6492 while (rptr != wptr) { 6493 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6494 uint8_t i; 6495 6496 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6497 (void)READ_ONCE(*data++); 6498 6499 rptr += DMUB_RB_CMD_SIZE; 6500 if (rptr >= rb->capacity) 6501 rptr %= rb->capacity; 6502 } 6503 } 6504 6505 /** 6506 * @brief Initializes a DMCUB ringbuffer 6507 * 6508 * @param rb DMUB ringbuffer 6509 * @param init_params initial configuration for the ringbuffer 6510 */ 6511 static inline void dmub_rb_init(struct dmub_rb *rb, 6512 struct dmub_rb_init_params *init_params) 6513 { 6514 rb->base_address = init_params->base_address; 6515 rb->capacity = init_params->capacity; 6516 rb->rptr = init_params->read_ptr; 6517 rb->wrpt = init_params->write_ptr; 6518 } 6519 6520 /** 6521 * @brief Copies output data from in/out commands into the given command. 6522 * 6523 * @param rb DMUB ringbuffer 6524 * @param cmd Command to copy data into 6525 */ 6526 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6527 union dmub_rb_cmd *cmd) 6528 { 6529 // Copy rb entry back into command 6530 uint8_t *rd_ptr = (rb->rptr == 0) ? 6531 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6532 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6533 6534 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6535 } 6536 6537 //============================================================================== 6538 //</DMUB_RB>==================================================================== 6539 //============================================================================== 6540 #endif /* _DMUB_CMD_H_ */ 6541