1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Maximum number of streams on any ASIC. */ 108 #define DMUB_MAX_STREAMS 6 109 110 /* Maximum number of planes on any ASIC. */ 111 #define DMUB_MAX_PLANES 6 112 113 /* Maximum number of phantom planes on any ASIC */ 114 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 115 116 /* Trace buffer offset for entry */ 117 #define TRACE_BUFFER_ENTRY_OFFSET 16 118 119 /** 120 * Maximum number of dirty rects supported by FW. 121 */ 122 #define DMUB_MAX_DIRTY_RECTS 3 123 124 /** 125 * 126 * PSR control version legacy 127 */ 128 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 129 /** 130 * PSR control version with multi edp support 131 */ 132 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 133 134 135 /** 136 * ABM control version legacy 137 */ 138 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 139 140 /** 141 * ABM control version with multi edp support 142 */ 143 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 144 145 /** 146 * Physical framebuffer address location, 64-bit. 147 */ 148 #ifndef PHYSICAL_ADDRESS_LOC 149 #define PHYSICAL_ADDRESS_LOC union large_integer 150 #endif 151 152 /** 153 * OS/FW agnostic memcpy 154 */ 155 #ifndef dmub_memcpy 156 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 157 #endif 158 159 /** 160 * OS/FW agnostic memset 161 */ 162 #ifndef dmub_memset 163 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 164 #endif 165 166 /** 167 * OS/FW agnostic memcmp 168 */ 169 #ifndef dmub_memcmp 170 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 171 #endif 172 173 /** 174 * OS/FW agnostic udelay 175 */ 176 #ifndef dmub_udelay 177 #define dmub_udelay(microseconds) udelay(microseconds) 178 #endif 179 180 #pragma pack(push, 1) 181 #define ABM_NUM_OF_ACE_SEGMENTS 5 182 183 /** 184 * Debug FW state offset 185 */ 186 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 187 188 union abm_flags { 189 struct { 190 /** 191 * @abm_enabled: Indicates if ABM is enabled. 192 */ 193 unsigned int abm_enabled : 1; 194 195 /** 196 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 197 */ 198 unsigned int disable_abm_requested : 1; 199 200 /** 201 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 202 */ 203 unsigned int disable_abm_immediately : 1; 204 205 /** 206 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 207 * to be disabled immediately and keep gain. 208 */ 209 unsigned int disable_abm_immediate_keep_gain : 1; 210 211 /** 212 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 213 */ 214 unsigned int fractional_pwm : 1; 215 216 /** 217 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 218 * of user backlight level. 219 */ 220 unsigned int abm_gradual_bl_change : 1; 221 222 /** 223 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 224 */ 225 unsigned int abm_new_frame : 1; 226 227 /** 228 * @vb_scaling_enabled: Indicates variBright Scaling Enable 229 */ 230 unsigned int vb_scaling_enabled : 1; 231 } bitfields; 232 233 unsigned int u32All; 234 }; 235 236 struct abm_save_restore { 237 /** 238 * @flags: Misc. ABM flags. 239 */ 240 union abm_flags flags; 241 242 /** 243 * @pause: true: pause ABM and get state 244 * false: unpause ABM after setting state 245 */ 246 uint32_t pause; 247 248 /** 249 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 250 */ 251 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 252 253 /** 254 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 255 */ 256 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 257 258 /** 259 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 260 */ 261 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 262 263 264 /** 265 * @knee_threshold: Current x-position of ACE knee (u0.16). 266 */ 267 uint32_t knee_threshold; 268 /** 269 * @current_gain: Current backlight reduction (u16.16). 270 */ 271 uint32_t current_gain; 272 /** 273 * @curr_bl_level: Current actual backlight level converging to target backlight level. 274 */ 275 uint16_t curr_bl_level; 276 277 /** 278 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 279 */ 280 uint16_t curr_user_bl_level; 281 282 }; 283 284 /** 285 * union dmub_addr - DMUB physical/virtual 64-bit address. 286 */ 287 union dmub_addr { 288 struct { 289 uint32_t low_part; /**< Lower 32 bits */ 290 uint32_t high_part; /**< Upper 32 bits */ 291 } u; /*<< Low/high bit access */ 292 uint64_t quad_part; /*<< 64 bit address */ 293 }; 294 #pragma pack(pop) 295 296 /** 297 * Dirty rect definition. 298 */ 299 struct dmub_rect { 300 /** 301 * Dirty rect x offset. 302 */ 303 uint32_t x; 304 305 /** 306 * Dirty rect y offset. 307 */ 308 uint32_t y; 309 310 /** 311 * Dirty rect width. 312 */ 313 uint32_t width; 314 315 /** 316 * Dirty rect height. 317 */ 318 uint32_t height; 319 }; 320 321 /** 322 * Flags that can be set by driver to change some PSR behaviour. 323 */ 324 union dmub_psr_debug_flags { 325 /** 326 * Debug flags. 327 */ 328 struct { 329 /** 330 * Enable visual confirm in FW. 331 */ 332 uint32_t visual_confirm : 1; 333 334 /** 335 * Force all selective updates to bw full frame updates. 336 */ 337 uint32_t force_full_frame_update : 1; 338 339 /** 340 * Use HW Lock Mgr object to do HW locking in FW. 341 */ 342 uint32_t use_hw_lock_mgr : 1; 343 344 /** 345 * Use TPS3 signal when restore main link. 346 */ 347 uint32_t force_wakeup_by_tps3 : 1; 348 349 /** 350 * Back to back flip, therefore cannot power down PHY 351 */ 352 uint32_t back_to_back_flip : 1; 353 354 /** 355 * Enable visual confirm for IPS 356 */ 357 uint32_t enable_ips_visual_confirm : 1; 358 } bitfields; 359 360 /** 361 * Union for debug flags. 362 */ 363 uint32_t u32All; 364 }; 365 366 /** 367 * Flags that can be set by driver to change some Replay behaviour. 368 */ 369 union replay_debug_flags { 370 struct { 371 /** 372 * 0x1 (bit 0) 373 * Enable visual confirm in FW. 374 */ 375 uint32_t visual_confirm : 1; 376 377 /** 378 * 0x2 (bit 1) 379 * @skip_crc: Set if need to skip CRC. 380 */ 381 uint32_t skip_crc : 1; 382 383 /** 384 * 0x4 (bit 2) 385 * @force_link_power_on: Force disable ALPM control 386 */ 387 uint32_t force_link_power_on : 1; 388 389 /** 390 * 0x8 (bit 3) 391 * @force_phy_power_on: Force phy power on 392 */ 393 uint32_t force_phy_power_on : 1; 394 395 /** 396 * 0x10 (bit 4) 397 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 398 */ 399 uint32_t timing_resync_disabled : 1; 400 401 /** 402 * 0x20 (bit 5) 403 * @skip_crtc_disabled: CRTC disable skipped 404 */ 405 uint32_t skip_crtc_disabled : 1; 406 407 /** 408 * 0x40 (bit 6) 409 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 410 */ 411 uint32_t force_defer_one_frame_update : 1; 412 413 /** 414 * 0x80 (bit 7) 415 * @disable_delay_alpm_on: Force disable delay alpm on 416 */ 417 uint32_t disable_delay_alpm_on : 1; 418 419 /** 420 * 0x100 (bit 8) 421 * @disable_desync_error_check: Force disable desync error check 422 */ 423 uint32_t disable_desync_error_check : 1; 424 425 /** 426 * 0x200 (bit 9) 427 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 428 */ 429 uint32_t force_self_update_when_abm_non_steady : 1; 430 431 /** 432 * 0x400 (bit 10) 433 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 434 * If we enter IPS2, the Visual confirm bar will change to yellow 435 */ 436 uint32_t enable_ips_visual_confirm : 1; 437 438 /** 439 * 0x800 (bit 11) 440 * @enable_ips_residency_profiling: Enable IPS residency profiling 441 */ 442 uint32_t enable_ips_residency_profiling : 1; 443 444 /** 445 * 0x1000 (bit 12) 446 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 447 */ 448 uint32_t enable_coasting_vtotal_check : 1; 449 /** 450 * 0x2000 (bit 13) 451 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 452 */ 453 uint32_t enable_visual_confirm_debug : 1; 454 455 uint32_t reserved : 18; 456 } bitfields; 457 458 uint32_t u32All; 459 }; 460 461 /** 462 * Flags record error state. 463 */ 464 union replay_visual_confirm_error_state_flags { 465 struct { 466 /** 467 * 0x1 (bit 0) - Desync Error flag. 468 */ 469 uint32_t desync_error : 1; 470 471 /** 472 * 0x2 (bit 1) - State Transition Error flag. 473 */ 474 uint32_t state_transition_error : 1; 475 476 /** 477 * 0x4 (bit 2) - Crc Error flag 478 */ 479 uint32_t crc_error : 1; 480 481 /** 482 * 0x8 (bit 3) - Reserved 483 */ 484 uint32_t reserved_3 : 1; 485 486 /** 487 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 488 * Added new debug flag to control DPCD. 489 */ 490 uint32_t incorrect_vtotal_in_static_screen : 1; 491 492 /** 493 * 0x20 (bit 5) - No doubled Refresh Rate. 494 */ 495 uint32_t no_double_rr : 1; 496 497 /** 498 * Reserved bit 6-7 499 */ 500 uint32_t reserved_6_7 : 2; 501 502 /** 503 * Reserved bit 9-31 504 */ 505 uint32_t reserved_9_31 : 24; 506 } bitfields; 507 508 uint32_t u32All; 509 }; 510 511 union replay_hw_flags { 512 struct { 513 /** 514 * @allow_alpm_fw_standby_mode: To indicate whether the 515 * ALPM FW standby mode is allowed 516 */ 517 uint32_t allow_alpm_fw_standby_mode : 1; 518 519 /* 520 * @dsc_enable_status: DSC enable status in driver 521 */ 522 uint32_t dsc_enable_status : 1; 523 524 /** 525 * @fec_enable_status: receive fec enable/disable status from driver 526 */ 527 uint32_t fec_enable_status : 1; 528 529 /* 530 * @smu_optimizations_en: SMU power optimization. 531 * Only when active display is Replay capable and display enters Replay. 532 * Trigger interrupt to SMU to powerup/down. 533 */ 534 uint32_t smu_optimizations_en : 1; 535 536 /** 537 * @phy_power_state: Indicates current phy power state 538 */ 539 uint32_t phy_power_state : 1; 540 541 /** 542 * @link_power_state: Indicates current link power state 543 */ 544 uint32_t link_power_state : 1; 545 /** 546 * Use TPS3 signal when restore main link. 547 */ 548 uint32_t force_wakeup_by_tps3 : 1; 549 /** 550 * @is_alpm_initialized: Indicates whether ALPM is initialized 551 */ 552 uint32_t is_alpm_initialized : 1; 553 } bitfields; 554 555 uint32_t u32All; 556 }; 557 558 union fw_assisted_mclk_switch_version { 559 struct { 560 uint8_t minor : 5; 561 uint8_t major : 3; 562 }; 563 uint8_t ver; 564 }; 565 566 /** 567 * DMUB feature capabilities. 568 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 569 */ 570 struct dmub_feature_caps { 571 /** 572 * Max PSR version supported by FW. 573 */ 574 uint8_t psr; 575 uint8_t fw_assisted_mclk_switch_ver; 576 uint8_t reserved[4]; 577 uint8_t subvp_psr_support; 578 uint8_t gecc_enable; 579 uint8_t replay_supported; 580 uint8_t replay_reserved[3]; 581 uint8_t abm_aux_backlight_support; 582 }; 583 584 struct dmub_visual_confirm_color { 585 /** 586 * Maximum 10 bits color value 587 */ 588 uint16_t color_r_cr; 589 uint16_t color_g_y; 590 uint16_t color_b_cb; 591 uint16_t panel_inst; 592 }; 593 594 //============================================================================== 595 //</DMUB_TYPES>================================================================= 596 //============================================================================== 597 //< DMUB_META>================================================================== 598 //============================================================================== 599 #pragma pack(push, 1) 600 601 /* Magic value for identifying dmub_fw_meta_info */ 602 #define DMUB_FW_META_MAGIC 0x444D5542 603 604 /* Offset from the end of the file to the dmub_fw_meta_info */ 605 #define DMUB_FW_META_OFFSET 0x24 606 607 /** 608 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 609 */ 610 union dmub_fw_meta_feature_bits { 611 struct { 612 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 613 uint32_t reserved : 31; 614 } bits; /**< status bits */ 615 uint32_t all; /**< 32-bit access to status bits */ 616 }; 617 618 /** 619 * struct dmub_fw_meta_info - metadata associated with fw binary 620 * 621 * NOTE: This should be considered a stable API. Fields should 622 * not be repurposed or reordered. New fields should be 623 * added instead to extend the structure. 624 * 625 * @magic_value: magic value identifying DMUB firmware meta info 626 * @fw_region_size: size of the firmware state region 627 * @trace_buffer_size: size of the tracebuffer region 628 * @fw_version: the firmware version information 629 * @dal_fw: 1 if the firmware is DAL 630 * @shared_state_size: size of the shared state region in bytes 631 * @shared_state_features: number of shared state features 632 */ 633 struct dmub_fw_meta_info { 634 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 635 uint32_t fw_region_size; /**< size of the firmware state region */ 636 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 637 uint32_t fw_version; /**< the firmware version information */ 638 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 639 uint8_t reserved[3]; /**< padding bits */ 640 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 641 uint16_t shared_state_features; /**< number of shared state features */ 642 uint16_t reserved2; /**< padding bytes */ 643 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 644 }; 645 646 /** 647 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 648 */ 649 union dmub_fw_meta { 650 struct dmub_fw_meta_info info; /**< metadata info */ 651 uint8_t reserved[64]; /**< padding bits */ 652 }; 653 654 #pragma pack(pop) 655 656 //============================================================================== 657 //< DMUB Trace Buffer>================================================================ 658 //============================================================================== 659 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 660 /** 661 * dmub_trace_code_t - firmware trace code, 32-bits 662 */ 663 typedef uint32_t dmub_trace_code_t; 664 665 /** 666 * struct dmcub_trace_buf_entry - Firmware trace entry 667 */ 668 struct dmcub_trace_buf_entry { 669 dmub_trace_code_t trace_code; /**< trace code for the event */ 670 uint32_t tick_count; /**< the tick count at time of trace */ 671 uint32_t param0; /**< trace defined parameter 0 */ 672 uint32_t param1; /**< trace defined parameter 1 */ 673 }; 674 #endif 675 676 //============================================================================== 677 //< DMUB_STATUS>================================================================ 678 //============================================================================== 679 680 /** 681 * DMCUB scratch registers can be used to determine firmware status. 682 * Current scratch register usage is as follows: 683 * 684 * SCRATCH0: FW Boot Status register 685 * SCRATCH5: LVTMA Status Register 686 * SCRATCH15: FW Boot Options register 687 */ 688 689 /** 690 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 691 */ 692 union dmub_fw_boot_status { 693 struct { 694 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 695 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 696 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 697 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 698 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 699 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 700 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 701 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 702 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 703 } bits; /**< status bits */ 704 uint32_t all; /**< 32-bit access to status bits */ 705 }; 706 707 /** 708 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 709 */ 710 enum dmub_fw_boot_status_bit { 711 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 712 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 713 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 714 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 715 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 716 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 717 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 718 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 719 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 720 }; 721 722 /* Register bit definition for SCRATCH5 */ 723 union dmub_lvtma_status { 724 struct { 725 uint32_t psp_ok : 1; 726 uint32_t edp_on : 1; 727 uint32_t reserved : 30; 728 } bits; 729 uint32_t all; 730 }; 731 732 enum dmub_lvtma_status_bit { 733 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 734 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 735 }; 736 737 enum dmub_ips_disable_type { 738 DMUB_IPS_ENABLE = 0, 739 DMUB_IPS_DISABLE_ALL = 1, 740 DMUB_IPS_DISABLE_IPS1 = 2, 741 DMUB_IPS_DISABLE_IPS2 = 3, 742 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 743 DMUB_IPS_DISABLE_DYNAMIC = 5, 744 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 745 }; 746 747 #define DMUB_IPS1_ALLOW_MASK 0x00000001 748 #define DMUB_IPS2_ALLOW_MASK 0x00000002 749 #define DMUB_IPS1_COMMIT_MASK 0x00000004 750 #define DMUB_IPS2_COMMIT_MASK 0x00000008 751 752 /** 753 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 754 */ 755 union dmub_fw_boot_options { 756 struct { 757 uint32_t pemu_env : 1; /**< 1 if PEMU */ 758 uint32_t fpga_env : 1; /**< 1 if FPGA */ 759 uint32_t optimized_init : 1; /**< 1 if optimized init */ 760 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 761 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 762 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 763 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 764 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 765 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 766 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 767 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 768 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 769 uint32_t power_optimization: 1; 770 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 771 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 772 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 773 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 774 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 775 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 776 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 777 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 778 uint32_t ips_disable: 3; /* options to disable ips support*/ 779 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 780 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 781 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 782 uint32_t reserved : 6; /**< reserved */ 783 } bits; /**< boot bits */ 784 uint32_t all; /**< 32-bit access to bits */ 785 }; 786 787 enum dmub_fw_boot_options_bit { 788 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 789 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 790 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 791 }; 792 793 //============================================================================== 794 //< DMUB_SHARED_STATE>========================================================== 795 //============================================================================== 796 797 /** 798 * Shared firmware state between driver and firmware for lockless communication 799 * in situations where the inbox/outbox may be unavailable. 800 * 801 * Each structure *must* be at most 256-bytes in size. The layout allocation is 802 * described below: 803 * 804 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 805 */ 806 807 /** 808 * enum dmub_shared_state_feature_id - List of shared state features. 809 */ 810 enum dmub_shared_state_feature_id { 811 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 812 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 813 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 814 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 815 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 816 }; 817 818 /** 819 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 820 */ 821 union dmub_shared_state_ips_fw_signals { 822 struct { 823 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ 824 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 825 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 826 uint32_t detection_required : 1; /**< 1 if detection is required */ 827 uint32_t reserved_bits : 28; /**< Reversed */ 828 } bits; 829 uint32_t all; 830 }; 831 832 /** 833 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 834 */ 835 union dmub_shared_state_ips_driver_signals { 836 struct { 837 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 838 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 839 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 840 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 841 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 842 uint32_t reserved_bits : 27; /**< Reversed bits */ 843 } bits; 844 uint32_t all; 845 }; 846 847 /** 848 * IPS FW Version 849 */ 850 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 851 852 struct dmub_shared_state_debug_setup { 853 union { 854 struct { 855 uint32_t exclude_points[62]; 856 } profile_mode; 857 }; 858 }; 859 860 /** 861 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 862 */ 863 struct dmub_shared_state_ips_fw { 864 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 865 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 866 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 867 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 868 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 869 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 870 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 871 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */ 872 }; /* 248-bytes, fixed */ 873 874 /** 875 * IPS Driver Version 876 */ 877 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 878 879 /** 880 * struct dmub_shared_state_ips_driver - Driver state for IPS. 881 */ 882 struct dmub_shared_state_ips_driver { 883 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 884 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 885 }; /* 248-bytes, fixed */ 886 887 /** 888 * enum dmub_shared_state_feature_common - Generic payload. 889 */ 890 struct dmub_shared_state_feature_common { 891 uint32_t padding[62]; 892 }; /* 248-bytes, fixed */ 893 894 /** 895 * enum dmub_shared_state_feature_header - Feature description. 896 */ 897 struct dmub_shared_state_feature_header { 898 uint16_t id; /**< Feature ID */ 899 uint16_t version; /**< Feature version */ 900 uint32_t reserved; /**< Reserved bytes. */ 901 }; /* 8 bytes, fixed */ 902 903 /** 904 * struct dmub_shared_state_feature_block - Feature block. 905 */ 906 struct dmub_shared_state_feature_block { 907 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 908 union dmub_shared_feature_state_union { 909 struct dmub_shared_state_feature_common common; /**< Generic data */ 910 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 911 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 912 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 913 } data; /**< Shared state data. */ 914 }; /* 256-bytes, fixed */ 915 916 /** 917 * Shared state size in bytes. 918 */ 919 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 920 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 921 922 //============================================================================== 923 //</DMUB_STATUS>================================================================ 924 //============================================================================== 925 //< DMUB_VBIOS>================================================================= 926 //============================================================================== 927 928 /* 929 * enum dmub_cmd_vbios_type - VBIOS commands. 930 * 931 * Command IDs should be treated as stable ABI. 932 * Do not reuse or modify IDs. 933 */ 934 enum dmub_cmd_vbios_type { 935 /** 936 * Configures the DIG encoder. 937 */ 938 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 939 /** 940 * Controls the PHY. 941 */ 942 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 943 /** 944 * Sets the pixel clock/symbol clock. 945 */ 946 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 947 /** 948 * Enables or disables power gating. 949 */ 950 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 951 /** 952 * Controls embedded panels. 953 */ 954 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 955 /** 956 * Query DP alt status on a transmitter. 957 */ 958 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 959 /** 960 * Control PHY FSM 961 */ 962 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 963 /** 964 * Controls domain power gating 965 */ 966 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 967 }; 968 969 //============================================================================== 970 //</DMUB_VBIOS>================================================================= 971 //============================================================================== 972 //< DMUB_GPINT>================================================================= 973 //============================================================================== 974 975 /** 976 * The shifts and masks below may alternatively be used to format and read 977 * the command register bits. 978 */ 979 980 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 981 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 982 983 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 984 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 985 986 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 987 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 988 989 /** 990 * Command responses. 991 */ 992 993 /** 994 * Return response for DMUB_GPINT__STOP_FW command. 995 */ 996 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 997 998 /** 999 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1000 */ 1001 union dmub_gpint_data_register { 1002 struct { 1003 uint32_t param : 16; /**< 16-bit parameter */ 1004 uint32_t command_code : 12; /**< GPINT command */ 1005 uint32_t status : 4; /**< Command status bit */ 1006 } bits; /**< GPINT bit access */ 1007 uint32_t all; /**< GPINT 32-bit access */ 1008 }; 1009 1010 /* 1011 * enum dmub_gpint_command - GPINT command to DMCUB FW 1012 * 1013 * Command IDs should be treated as stable ABI. 1014 * Do not reuse or modify IDs. 1015 */ 1016 enum dmub_gpint_command { 1017 /** 1018 * Invalid command, ignored. 1019 */ 1020 DMUB_GPINT__INVALID_COMMAND = 0, 1021 /** 1022 * DESC: Queries the firmware version. 1023 * RETURN: Firmware version. 1024 */ 1025 DMUB_GPINT__GET_FW_VERSION = 1, 1026 /** 1027 * DESC: Halts the firmware. 1028 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1029 */ 1030 DMUB_GPINT__STOP_FW = 2, 1031 /** 1032 * DESC: Get PSR state from FW. 1033 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1034 */ 1035 DMUB_GPINT__GET_PSR_STATE = 7, 1036 /** 1037 * DESC: Notifies DMCUB of the currently active streams. 1038 * ARGS: Stream mask, 1 bit per active stream index. 1039 */ 1040 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1041 /** 1042 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1043 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1044 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1045 * RETURN: PSR residency in milli-percent. 1046 */ 1047 DMUB_GPINT__PSR_RESIDENCY = 9, 1048 1049 /** 1050 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1051 */ 1052 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1053 1054 /** 1055 * DESC: Get REPLAY state from FW. 1056 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1057 */ 1058 DMUB_GPINT__GET_REPLAY_STATE = 13, 1059 1060 /** 1061 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1062 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1063 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1064 * RETURN: REPLAY residency in milli-percent. 1065 */ 1066 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1067 1068 /** 1069 * DESC: Copy bounding box to the host. 1070 * ARGS: Version of bounding box to copy 1071 * RETURN: Result of copying bounding box 1072 */ 1073 DMUB_GPINT__BB_COPY = 96, 1074 1075 /** 1076 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1077 * ARGS: The word3 for the 64 bit address 1078 */ 1079 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1080 1081 /** 1082 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1083 * ARGS: The word2 for the 64 bit address 1084 */ 1085 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1086 1087 /** 1088 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1089 * ARGS: The word1 for the 64 bit address 1090 */ 1091 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1092 1093 /** 1094 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1095 * ARGS: The word0 for the 64 bit address 1096 */ 1097 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1098 1099 /** 1100 * DESC: Updates the trace buffer lower 32-bit mask. 1101 * ARGS: The new mask 1102 * RETURN: Lower 32-bit mask. 1103 */ 1104 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1105 1106 /** 1107 * DESC: Updates the trace buffer mask bit0~bit15. 1108 * ARGS: The new mask 1109 * RETURN: Lower 32-bit mask. 1110 */ 1111 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1112 1113 /** 1114 * DESC: Updates the trace buffer mask bit16~bit31. 1115 * ARGS: The new mask 1116 * RETURN: Lower 32-bit mask. 1117 */ 1118 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1119 1120 /** 1121 * DESC: Updates the trace buffer mask bit32~bit47. 1122 * ARGS: The new mask 1123 * RETURN: Lower 32-bit mask. 1124 */ 1125 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1126 1127 /** 1128 * DESC: Updates the trace buffer mask bit48~bit63. 1129 * ARGS: The new mask 1130 * RETURN: Lower 32-bit mask. 1131 */ 1132 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1133 1134 /** 1135 * DESC: Read the trace buffer mask bi0~bit15. 1136 */ 1137 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1138 1139 /** 1140 * DESC: Read the trace buffer mask bit16~bit31. 1141 */ 1142 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1143 1144 /** 1145 * DESC: Read the trace buffer mask bi32~bit47. 1146 */ 1147 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1148 1149 /** 1150 * DESC: Updates the trace buffer mask bit32~bit63. 1151 */ 1152 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1153 1154 /** 1155 * DESC: Set IPS residency measurement 1156 * ARGS: 0 - Disable ips measurement 1157 * 1 - Enable ips measurement 1158 */ 1159 DMUB_GPINT__IPS_RESIDENCY = 121, 1160 1161 /** 1162 * DESC: Enable measurements for various task duration 1163 * ARGS: 0 - Disable measurement 1164 * 1 - Enable measurement 1165 */ 1166 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1167 1168 /** 1169 * DESC: Gets IPS residency in microseconds 1170 * ARGS: 0 - Return IPS1 residency 1171 * 1 - Return IPS2 residency 1172 * 2 - Return IPS1_RCG residency 1173 * 3 - Return IPS1_ONO2_ON residency 1174 * RETURN: Total residency in microseconds - lower 32 bits 1175 */ 1176 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1177 1178 /** 1179 * DESC: Gets IPS1 histogram counts 1180 * ARGS: Bucket index 1181 * RETURN: Total count for the bucket 1182 */ 1183 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1184 1185 /** 1186 * DESC: Gets IPS2 histogram counts 1187 * ARGS: Bucket index 1188 * RETURN: Total count for the bucket 1189 */ 1190 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1191 1192 /** 1193 * DESC: Gets IPS residency 1194 * ARGS: 0 - Return IPS1 residency 1195 * 1 - Return IPS2 residency 1196 * 2 - Return IPS1_RCG residency 1197 * 3 - Return IPS1_ONO2_ON residency 1198 * RETURN: Total residency in milli-percent. 1199 */ 1200 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1201 1202 /** 1203 * DESC: Gets IPS1_RCG histogram counts 1204 * ARGS: Bucket index 1205 * RETURN: Total count for the bucket 1206 */ 1207 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1208 1209 /** 1210 * DESC: Gets IPS1_ONO2_ON histogram counts 1211 * ARGS: Bucket index 1212 * RETURN: Total count for the bucket 1213 */ 1214 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1215 1216 /** 1217 * DESC: Gets IPS entry counter during residency measurement 1218 * ARGS: 0 - Return IPS1 entry counts 1219 * 1 - Return IPS2 entry counts 1220 * 2 - Return IPS1_RCG entry counts 1221 * 3 - Return IPS2_ONO2_ON entry counts 1222 * RETURN: Entry counter for selected IPS mode 1223 */ 1224 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1225 1226 /** 1227 * DESC: Gets IPS inactive residency in microseconds 1228 * ARGS: 0 - Return IPS1_MAX residency 1229 * 1 - Return IPS2 residency 1230 * 2 - Return IPS1_RCG residency 1231 * 3 - Return IPS1_ONO2_ON residency 1232 * RETURN: Total inactive residency in microseconds - lower 32 bits 1233 */ 1234 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1235 1236 /** 1237 * DESC: Gets IPS inactive residency in microseconds 1238 * ARGS: 0 - Return IPS1_MAX residency 1239 * 1 - Return IPS2 residency 1240 * 2 - Return IPS1_RCG residency 1241 * 3 - Return IPS1_ONO2_ON residency 1242 * RETURN: Total inactive residency in microseconds - upper 32 bits 1243 */ 1244 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1245 1246 /** 1247 * DESC: Gets IPS residency in microseconds 1248 * ARGS: 0 - Return IPS1 residency 1249 * 1 - Return IPS2 residency 1250 * 2 - Return IPS1_RCG residency 1251 * 3 - Return IPS1_ONO2_ON residency 1252 * RETURN: Total residency in microseconds - upper 32 bits 1253 */ 1254 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1255 /** 1256 * DESC: Setup debug configs. 1257 */ 1258 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1259 }; 1260 1261 /** 1262 * INBOX0 generic command definition 1263 */ 1264 union dmub_inbox0_cmd_common { 1265 struct { 1266 uint32_t command_code: 8; /**< INBOX0 command code */ 1267 uint32_t param: 24; /**< 24-bit parameter */ 1268 } bits; 1269 uint32_t all; 1270 }; 1271 1272 /** 1273 * INBOX0 hw_lock command definition 1274 */ 1275 union dmub_inbox0_cmd_lock_hw { 1276 struct { 1277 uint32_t command_code: 8; 1278 1279 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1280 uint32_t hw_lock_client: 2; 1281 1282 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1283 uint32_t otg_inst: 3; 1284 uint32_t opp_inst: 3; 1285 uint32_t dig_inst: 3; 1286 1287 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1288 uint32_t lock_pipe: 1; 1289 uint32_t lock_cursor: 1; 1290 uint32_t lock_dig: 1; 1291 uint32_t triple_buffer_lock: 1; 1292 1293 uint32_t lock: 1; /**< Lock */ 1294 uint32_t should_release: 1; /**< Release */ 1295 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1296 } bits; 1297 uint32_t all; 1298 }; 1299 1300 union dmub_inbox0_data_register { 1301 union dmub_inbox0_cmd_common inbox0_cmd_common; 1302 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1303 }; 1304 1305 enum dmub_inbox0_command { 1306 /** 1307 * DESC: Invalid command, ignored. 1308 */ 1309 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1310 /** 1311 * DESC: Notification to acquire/release HW lock 1312 * ARGS: 1313 */ 1314 DMUB_INBOX0_CMD__HW_LOCK = 1, 1315 }; 1316 //============================================================================== 1317 //</DMUB_GPINT>================================================================= 1318 //============================================================================== 1319 //< DMUB_CMD>=================================================================== 1320 //============================================================================== 1321 1322 /** 1323 * Size in bytes of each DMUB command. 1324 */ 1325 #define DMUB_RB_CMD_SIZE 64 1326 1327 /** 1328 * Maximum number of items in the DMUB ringbuffer. 1329 */ 1330 #define DMUB_RB_MAX_ENTRY 128 1331 1332 /** 1333 * Ringbuffer size in bytes. 1334 */ 1335 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1336 1337 /** 1338 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1339 */ 1340 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1341 1342 /** 1343 * Ringbuffer size in bytes. 1344 */ 1345 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1346 1347 /** 1348 * REG_SET mask for reg offload. 1349 */ 1350 #define REG_SET_MASK 0xFFFF 1351 1352 /* 1353 * enum dmub_cmd_type - DMUB inbox command. 1354 * 1355 * Command IDs should be treated as stable ABI. 1356 * Do not reuse or modify IDs. 1357 */ 1358 enum dmub_cmd_type { 1359 /** 1360 * Invalid command. 1361 */ 1362 DMUB_CMD__NULL = 0, 1363 /** 1364 * Read modify write register sequence offload. 1365 */ 1366 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1367 /** 1368 * Field update register sequence offload. 1369 */ 1370 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1371 /** 1372 * Burst write sequence offload. 1373 */ 1374 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1375 /** 1376 * Reg wait sequence offload. 1377 */ 1378 DMUB_CMD__REG_REG_WAIT = 4, 1379 /** 1380 * Workaround to avoid HUBP underflow during NV12 playback. 1381 */ 1382 DMUB_CMD__PLAT_54186_WA = 5, 1383 /** 1384 * Command type used to query FW feature caps. 1385 */ 1386 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1387 /** 1388 * Command type used to get visual confirm color. 1389 */ 1390 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1391 /** 1392 * Command type used for all PSR commands. 1393 */ 1394 DMUB_CMD__PSR = 64, 1395 /** 1396 * Command type used for all MALL commands. 1397 */ 1398 DMUB_CMD__MALL = 65, 1399 /** 1400 * Command type used for all ABM commands. 1401 */ 1402 DMUB_CMD__ABM = 66, 1403 /** 1404 * Command type used to update dirty rects in FW. 1405 */ 1406 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1407 /** 1408 * Command type used to update cursor info in FW. 1409 */ 1410 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1411 /** 1412 * Command type used for HW locking in FW. 1413 */ 1414 DMUB_CMD__HW_LOCK = 69, 1415 /** 1416 * Command type used to access DP AUX. 1417 */ 1418 DMUB_CMD__DP_AUX_ACCESS = 70, 1419 /** 1420 * Command type used for OUTBOX1 notification enable 1421 */ 1422 DMUB_CMD__OUTBOX1_ENABLE = 71, 1423 1424 /** 1425 * Command type used for all idle optimization commands. 1426 */ 1427 DMUB_CMD__IDLE_OPT = 72, 1428 /** 1429 * Command type used for all clock manager commands. 1430 */ 1431 DMUB_CMD__CLK_MGR = 73, 1432 /** 1433 * Command type used for all panel control commands. 1434 */ 1435 DMUB_CMD__PANEL_CNTL = 74, 1436 1437 /** 1438 * Command type used for all CAB commands. 1439 */ 1440 DMUB_CMD__CAB_FOR_SS = 75, 1441 1442 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1443 1444 /** 1445 * Command type used for interfacing with DPIA. 1446 */ 1447 DMUB_CMD__DPIA = 77, 1448 /** 1449 * Command type used for EDID CEA parsing 1450 */ 1451 DMUB_CMD__EDID_CEA = 79, 1452 /** 1453 * Command type used for getting usbc cable ID 1454 */ 1455 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1456 /** 1457 * Command type used to query HPD state. 1458 */ 1459 DMUB_CMD__QUERY_HPD_STATE = 82, 1460 /** 1461 * Command type used for all VBIOS interface commands. 1462 */ 1463 /** 1464 * Command type used for all REPLAY commands. 1465 */ 1466 DMUB_CMD__REPLAY = 83, 1467 1468 /** 1469 * Command type used for all SECURE_DISPLAY commands. 1470 */ 1471 DMUB_CMD__SECURE_DISPLAY = 85, 1472 1473 /** 1474 * Command type used to set DPIA HPD interrupt state 1475 */ 1476 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1477 1478 /** 1479 * Command type used for all PSP commands. 1480 */ 1481 DMUB_CMD__PSP = 88, 1482 1483 /** 1484 * Command type used for all Fused IO commands. 1485 */ 1486 DMUB_CMD__FUSED_IO = 89, 1487 1488 DMUB_CMD__VBIOS = 128, 1489 }; 1490 1491 /** 1492 * enum dmub_out_cmd_type - DMUB outbox commands. 1493 */ 1494 enum dmub_out_cmd_type { 1495 /** 1496 * Invalid outbox command, ignored. 1497 */ 1498 DMUB_OUT_CMD__NULL = 0, 1499 /** 1500 * Command type used for DP AUX Reply data notification 1501 */ 1502 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1503 /** 1504 * Command type used for DP HPD event notification 1505 */ 1506 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1507 /** 1508 * Command type used for SET_CONFIG Reply notification 1509 */ 1510 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1511 /** 1512 * Command type used for USB4 DPIA notification 1513 */ 1514 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1515 /** 1516 * Command type used for HPD redetect notification 1517 */ 1518 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1519 /** 1520 * Command type used for Fused IO notification 1521 */ 1522 DMUB_OUT_CMD__FUSED_IO = 7, 1523 }; 1524 1525 /* DMUB_CMD__DPIA command sub-types. */ 1526 enum dmub_cmd_dpia_type { 1527 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1528 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1529 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1530 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1531 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1532 }; 1533 1534 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1535 enum dmub_cmd_dpia_notification_type { 1536 DPIA_NOTIFY__BW_ALLOCATION = 0, 1537 }; 1538 1539 #pragma pack(push, 1) 1540 1541 /** 1542 * struct dmub_cmd_header - Common command header fields. 1543 */ 1544 struct dmub_cmd_header { 1545 unsigned int type : 8; /**< command type */ 1546 unsigned int sub_type : 8; /**< command sub type */ 1547 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1548 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1549 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1550 unsigned int reserved0 : 5; /**< reserved bits */ 1551 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1552 unsigned int reserved1 : 2; /**< reserved bits */ 1553 }; 1554 1555 /* 1556 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1557 * 1558 * 60 payload bytes can hold up to 5 sets of read modify writes, 1559 * each take 3 dwords. 1560 * 1561 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1562 * 1563 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1564 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1565 */ 1566 struct dmub_cmd_read_modify_write_sequence { 1567 uint32_t addr; /**< register address */ 1568 uint32_t modify_mask; /**< modify mask */ 1569 uint32_t modify_value; /**< modify value */ 1570 }; 1571 1572 /** 1573 * Maximum number of ops in read modify write sequence. 1574 */ 1575 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1576 1577 /** 1578 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1579 */ 1580 struct dmub_rb_cmd_read_modify_write { 1581 struct dmub_cmd_header header; /**< command header */ 1582 /** 1583 * Read modify write sequence. 1584 */ 1585 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1586 }; 1587 1588 /* 1589 * Update a register with specified masks and values sequeunce 1590 * 1591 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1592 * 1593 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1594 * 1595 * 1596 * USE CASE: 1597 * 1. auto-increment register where additional read would update pointer and produce wrong result 1598 * 2. toggle a bit without read in the middle 1599 */ 1600 1601 struct dmub_cmd_reg_field_update_sequence { 1602 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1603 uint32_t modify_value; /**< value to update with */ 1604 }; 1605 1606 /** 1607 * Maximum number of ops in field update sequence. 1608 */ 1609 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1610 1611 /** 1612 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1613 */ 1614 struct dmub_rb_cmd_reg_field_update_sequence { 1615 struct dmub_cmd_header header; /**< command header */ 1616 uint32_t addr; /**< register address */ 1617 /** 1618 * Field update sequence. 1619 */ 1620 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1621 }; 1622 1623 1624 /** 1625 * Maximum number of burst write values. 1626 */ 1627 #define DMUB_BURST_WRITE_VALUES__MAX 14 1628 1629 /* 1630 * struct dmub_rb_cmd_burst_write - Burst write 1631 * 1632 * support use case such as writing out LUTs. 1633 * 1634 * 60 payload bytes can hold up to 14 values to write to given address 1635 * 1636 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1637 */ 1638 struct dmub_rb_cmd_burst_write { 1639 struct dmub_cmd_header header; /**< command header */ 1640 uint32_t addr; /**< register start address */ 1641 /** 1642 * Burst write register values. 1643 */ 1644 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1645 }; 1646 1647 /** 1648 * struct dmub_rb_cmd_common - Common command header 1649 */ 1650 struct dmub_rb_cmd_common { 1651 struct dmub_cmd_header header; /**< command header */ 1652 /** 1653 * Padding to RB_CMD_SIZE 1654 */ 1655 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1656 }; 1657 1658 /** 1659 * struct dmub_cmd_reg_wait_data - Register wait data 1660 */ 1661 struct dmub_cmd_reg_wait_data { 1662 uint32_t addr; /**< Register address */ 1663 uint32_t mask; /**< Mask for register bits */ 1664 uint32_t condition_field_value; /**< Value to wait for */ 1665 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1666 }; 1667 1668 /** 1669 * struct dmub_rb_cmd_reg_wait - Register wait command 1670 */ 1671 struct dmub_rb_cmd_reg_wait { 1672 struct dmub_cmd_header header; /**< Command header */ 1673 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1674 }; 1675 1676 /** 1677 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1678 * 1679 * Reprograms surface parameters to avoid underflow. 1680 */ 1681 struct dmub_cmd_PLAT_54186_wa { 1682 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1683 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1684 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1685 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1686 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1687 struct { 1688 uint32_t hubp_inst : 4; /**< HUBP instance */ 1689 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1690 uint32_t immediate :1; /**< Immediate flip */ 1691 uint32_t vmid : 4; /**< VMID */ 1692 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1693 uint32_t reserved : 21; /**< Reserved */ 1694 } flip_params; /**< Pageflip parameters */ 1695 uint32_t reserved[9]; /**< Reserved bits */ 1696 }; 1697 1698 /** 1699 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1700 */ 1701 struct dmub_rb_cmd_PLAT_54186_wa { 1702 struct dmub_cmd_header header; /**< Command header */ 1703 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1704 }; 1705 1706 /** 1707 * enum dmub_cmd_mall_type - MALL commands 1708 */ 1709 enum dmub_cmd_mall_type { 1710 /** 1711 * Allows display refresh from MALL. 1712 */ 1713 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1714 /** 1715 * Disallows display refresh from MALL. 1716 */ 1717 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1718 /** 1719 * Cursor copy for MALL. 1720 */ 1721 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1722 /** 1723 * Controls DF requests. 1724 */ 1725 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1726 }; 1727 1728 /** 1729 * struct dmub_rb_cmd_mall - MALL command data. 1730 */ 1731 struct dmub_rb_cmd_mall { 1732 struct dmub_cmd_header header; /**< Common command header */ 1733 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1734 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1735 uint32_t tmr_delay; /**< Timer delay */ 1736 uint32_t tmr_scale; /**< Timer scale */ 1737 uint16_t cursor_width; /**< Cursor width in pixels */ 1738 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1739 uint16_t cursor_height; /**< Cursor height in pixels */ 1740 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1741 uint8_t debug_bits; /**< Debug bits */ 1742 1743 uint8_t reserved1; /**< Reserved bits */ 1744 uint8_t reserved2; /**< Reserved bits */ 1745 }; 1746 1747 /** 1748 * enum dmub_cmd_cab_type - CAB command data. 1749 */ 1750 enum dmub_cmd_cab_type { 1751 /** 1752 * No idle optimizations (i.e. no CAB) 1753 */ 1754 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1755 /** 1756 * No DCN requests for memory 1757 */ 1758 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1759 /** 1760 * Fit surfaces in CAB (i.e. CAB enable) 1761 */ 1762 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1763 /** 1764 * Do not fit surfaces in CAB (i.e. no CAB) 1765 */ 1766 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1767 }; 1768 1769 /** 1770 * struct dmub_rb_cmd_cab - CAB command data. 1771 */ 1772 struct dmub_rb_cmd_cab_for_ss { 1773 struct dmub_cmd_header header; 1774 uint8_t cab_alloc_ways; /* total number of ways */ 1775 uint8_t debug_bits; /* debug bits */ 1776 }; 1777 1778 /** 1779 * Enum for indicating which MCLK switch mode per pipe 1780 */ 1781 enum mclk_switch_mode { 1782 NONE = 0, 1783 FPO = 1, 1784 SUBVP = 2, 1785 VBLANK = 3, 1786 }; 1787 1788 /* Per pipe struct which stores the MCLK switch mode 1789 * data to be sent to DMUB. 1790 * Named "v2" for now -- once FPO and SUBVP are fully merged 1791 * the type name can be updated 1792 */ 1793 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1794 union { 1795 struct { 1796 uint32_t pix_clk_100hz; 1797 uint16_t main_vblank_start; 1798 uint16_t main_vblank_end; 1799 uint16_t mall_region_lines; 1800 uint16_t prefetch_lines; 1801 uint16_t prefetch_to_mall_start_lines; 1802 uint16_t processing_delay_lines; 1803 uint16_t htotal; // required to calculate line time for multi-display cases 1804 uint16_t vtotal; 1805 uint8_t main_pipe_index; 1806 uint8_t phantom_pipe_index; 1807 /* Since the microschedule is calculated in terms of OTG lines, 1808 * include any scaling factors to make sure when we get accurate 1809 * conversion when programming MALL_START_LINE (which is in terms 1810 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1811 * is 1/2 (numerator = 1, denominator = 2). 1812 */ 1813 uint8_t scale_factor_numerator; 1814 uint8_t scale_factor_denominator; 1815 uint8_t is_drr; 1816 uint8_t main_split_pipe_index; 1817 uint8_t phantom_split_pipe_index; 1818 } subvp_data; 1819 1820 struct { 1821 uint32_t pix_clk_100hz; 1822 uint16_t vblank_start; 1823 uint16_t vblank_end; 1824 uint16_t vstartup_start; 1825 uint16_t vtotal; 1826 uint16_t htotal; 1827 uint8_t vblank_pipe_index; 1828 uint8_t padding[1]; 1829 struct { 1830 uint8_t drr_in_use; 1831 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1832 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1833 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1834 uint8_t use_ramping; // Use ramping or not 1835 uint8_t drr_vblank_start_margin; 1836 } drr_info; // DRR considered as part of SubVP + VBLANK case 1837 } vblank_data; 1838 } pipe_config; 1839 1840 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1841 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1842 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1843 */ 1844 uint8_t mode; // enum mclk_switch_mode 1845 }; 1846 1847 /** 1848 * Config data for Sub-VP and FPO 1849 * Named "v2" for now -- once FPO and SUBVP are fully merged 1850 * the type name can be updated 1851 */ 1852 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1853 uint16_t watermark_a_cache; 1854 uint8_t vertical_int_margin_us; 1855 uint8_t pstate_allow_width_us; 1856 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1857 }; 1858 1859 /** 1860 * DMUB rb command definition for Sub-VP and FPO 1861 * Named "v2" for now -- once FPO and SUBVP are fully merged 1862 * the type name can be updated 1863 */ 1864 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1865 struct dmub_cmd_header header; 1866 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1867 }; 1868 1869 struct dmub_flip_addr_info { 1870 uint32_t surf_addr_lo; 1871 uint32_t surf_addr_c_lo; 1872 uint32_t meta_addr_lo; 1873 uint32_t meta_addr_c_lo; 1874 uint16_t surf_addr_hi; 1875 uint16_t surf_addr_c_hi; 1876 uint16_t meta_addr_hi; 1877 uint16_t meta_addr_c_hi; 1878 }; 1879 1880 struct dmub_fams2_flip_info { 1881 union { 1882 struct { 1883 uint8_t is_immediate: 1; 1884 } bits; 1885 uint8_t all; 1886 } config; 1887 uint8_t otg_inst; 1888 uint8_t pipe_mask; 1889 uint8_t pad; 1890 struct dmub_flip_addr_info addr_info; 1891 }; 1892 1893 struct dmub_rb_cmd_fams2_flip { 1894 struct dmub_cmd_header header; 1895 struct dmub_fams2_flip_info flip_info; 1896 }; 1897 1898 struct dmub_optc_state_v2 { 1899 uint32_t v_total_min; 1900 uint32_t v_total_max; 1901 uint32_t v_total_mid; 1902 uint32_t v_total_mid_frame_num; 1903 uint8_t program_manual_trigger; 1904 uint8_t tg_inst; 1905 uint8_t pad[2]; 1906 }; 1907 1908 struct dmub_optc_position { 1909 uint32_t vpos; 1910 uint32_t hpos; 1911 uint32_t frame; 1912 }; 1913 1914 struct dmub_rb_cmd_fams2_drr_update { 1915 struct dmub_cmd_header header; 1916 struct dmub_optc_state_v2 dmub_optc_state_req; 1917 }; 1918 1919 /* HW and FW global configuration data for FAMS2 */ 1920 /* FAMS2 types and structs */ 1921 enum fams2_stream_type { 1922 FAMS2_STREAM_TYPE_NONE = 0, 1923 FAMS2_STREAM_TYPE_VBLANK = 1, 1924 FAMS2_STREAM_TYPE_VACTIVE = 2, 1925 FAMS2_STREAM_TYPE_DRR = 3, 1926 FAMS2_STREAM_TYPE_SUBVP = 4, 1927 }; 1928 1929 /* static stream state */ 1930 struct dmub_fams2_legacy_stream_static_state { 1931 uint8_t vactive_det_fill_delay_otg_vlines; 1932 uint8_t programming_delay_otg_vlines; 1933 }; //v0 1934 1935 struct dmub_fams2_subvp_stream_static_state { 1936 uint16_t vratio_numerator; 1937 uint16_t vratio_denominator; 1938 uint16_t phantom_vtotal; 1939 uint16_t phantom_vactive; 1940 union { 1941 struct { 1942 uint8_t is_multi_planar : 1; 1943 uint8_t is_yuv420 : 1; 1944 } bits; 1945 uint8_t all; 1946 } config; 1947 uint8_t programming_delay_otg_vlines; 1948 uint8_t prefetch_to_mall_otg_vlines; 1949 uint8_t phantom_otg_inst; 1950 uint8_t phantom_pipe_mask; 1951 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1952 }; //v0 1953 1954 struct dmub_fams2_drr_stream_static_state { 1955 uint16_t nom_stretched_vtotal; 1956 uint8_t programming_delay_otg_vlines; 1957 uint8_t only_stretch_if_required; 1958 uint8_t pad[2]; 1959 }; //v0 1960 1961 struct dmub_fams2_cmd_legacy_stream_static_state { 1962 uint16_t vactive_det_fill_delay_otg_vlines; 1963 uint16_t programming_delay_otg_vlines; 1964 }; //v1 1965 1966 struct dmub_fams2_cmd_subvp_stream_static_state { 1967 uint16_t vratio_numerator; 1968 uint16_t vratio_denominator; 1969 uint16_t phantom_vtotal; 1970 uint16_t phantom_vactive; 1971 uint16_t programming_delay_otg_vlines; 1972 uint16_t prefetch_to_mall_otg_vlines; 1973 union { 1974 struct { 1975 uint8_t is_multi_planar : 1; 1976 uint8_t is_yuv420 : 1; 1977 } bits; 1978 uint8_t all; 1979 } config; 1980 uint8_t phantom_otg_inst; 1981 uint8_t phantom_pipe_mask; 1982 uint8_t pad0; 1983 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 1984 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 1985 }; //v1 1986 1987 struct dmub_fams2_cmd_drr_stream_static_state { 1988 uint16_t nom_stretched_vtotal; 1989 uint16_t programming_delay_otg_vlines; 1990 uint8_t only_stretch_if_required; 1991 uint8_t pad[3]; 1992 }; //v1 1993 1994 union dmub_fams2_stream_static_sub_state { 1995 struct dmub_fams2_legacy_stream_static_state legacy; 1996 struct dmub_fams2_subvp_stream_static_state subvp; 1997 struct dmub_fams2_drr_stream_static_state drr; 1998 }; //v0 1999 2000 union dmub_fams2_cmd_stream_static_sub_state { 2001 struct dmub_fams2_cmd_legacy_stream_static_state legacy; 2002 struct dmub_fams2_cmd_subvp_stream_static_state subvp; 2003 struct dmub_fams2_cmd_drr_stream_static_state drr; 2004 }; //v1 2005 2006 struct dmub_fams2_stream_static_state { 2007 enum fams2_stream_type type; 2008 uint32_t otg_vline_time_ns; 2009 uint32_t otg_vline_time_ticks; 2010 uint16_t htotal; 2011 uint16_t vtotal; // nominal vtotal 2012 uint16_t vblank_start; 2013 uint16_t vblank_end; 2014 uint16_t max_vtotal; 2015 uint16_t allow_start_otg_vline; 2016 uint16_t allow_end_otg_vline; 2017 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2018 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2019 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2020 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2021 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2022 union { 2023 struct { 2024 uint8_t is_drr: 1; // stream is DRR enabled 2025 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2026 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2027 } bits; 2028 uint8_t all; 2029 } config; 2030 uint8_t otg_inst; 2031 uint8_t pipe_mask; // pipe mask for the whole config 2032 uint8_t num_planes; 2033 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2034 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2035 union dmub_fams2_stream_static_sub_state sub_state; 2036 }; //v0 2037 2038 struct dmub_fams2_cmd_stream_static_base_state { 2039 enum fams2_stream_type type; 2040 uint32_t otg_vline_time_ns; 2041 uint32_t otg_vline_time_ticks; 2042 uint16_t htotal; 2043 uint16_t vtotal; // nominal vtotal 2044 uint16_t vblank_start; 2045 uint16_t vblank_end; 2046 uint16_t max_vtotal; 2047 uint16_t allow_start_otg_vline; 2048 uint16_t allow_end_otg_vline; 2049 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2050 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2051 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2052 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2053 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2054 union { 2055 struct { 2056 uint8_t is_drr : 1; // stream is DRR enabled 2057 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2058 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2059 } bits; 2060 uint8_t all; 2061 } config; 2062 uint8_t otg_inst; 2063 uint8_t pipe_mask; // pipe mask for the whole config 2064 uint8_t num_planes; 2065 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2066 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2067 }; //v1 2068 2069 struct dmub_fams2_stream_static_state_v1 { 2070 struct dmub_fams2_cmd_stream_static_base_state base; 2071 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2072 }; //v1 2073 2074 /** 2075 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2076 * p-state request to allow latency 2077 */ 2078 enum dmub_fams2_allow_delay_check_mode { 2079 /* No check for request to allow delay */ 2080 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2081 /* Check for request to allow delay */ 2082 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2083 /* Check for prepare to allow delay */ 2084 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2085 }; 2086 2087 union dmub_fams2_global_feature_config { 2088 struct { 2089 uint32_t enable: 1; 2090 uint32_t enable_ppt_check: 1; 2091 uint32_t enable_stall_recovery: 1; 2092 uint32_t enable_debug: 1; 2093 uint32_t enable_offload_flip: 1; 2094 uint32_t enable_visual_confirm: 1; 2095 uint32_t allow_delay_check_mode: 2; 2096 uint32_t reserved: 24; 2097 } bits; 2098 uint32_t all; 2099 }; 2100 2101 struct dmub_cmd_fams2_global_config { 2102 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2103 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2104 uint32_t num_streams; 2105 union dmub_fams2_global_feature_config features; 2106 uint32_t recovery_timeout_us; 2107 uint32_t hwfq_flip_programming_delay_us; 2108 }; 2109 2110 union dmub_cmd_fams2_config { 2111 struct dmub_cmd_fams2_global_config global; 2112 struct dmub_fams2_stream_static_state stream; //v0 2113 union { 2114 struct dmub_fams2_cmd_stream_static_base_state base; 2115 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2116 } stream_v1; //v1 2117 }; 2118 2119 /** 2120 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2121 */ 2122 struct dmub_rb_cmd_fams2 { 2123 struct dmub_cmd_header header; 2124 union dmub_cmd_fams2_config config; 2125 }; 2126 2127 /** 2128 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2129 */ 2130 enum dmub_cmd_idle_opt_type { 2131 /** 2132 * DCN hardware restore. 2133 */ 2134 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2135 2136 /** 2137 * DCN hardware save. 2138 */ 2139 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2140 2141 /** 2142 * DCN hardware notify idle. 2143 */ 2144 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2145 2146 /** 2147 * DCN hardware notify power state. 2148 */ 2149 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2150 }; 2151 2152 /** 2153 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2154 */ 2155 struct dmub_rb_cmd_idle_opt_dcn_restore { 2156 struct dmub_cmd_header header; /**< header */ 2157 }; 2158 2159 /** 2160 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2161 */ 2162 struct dmub_dcn_notify_idle_cntl_data { 2163 uint8_t driver_idle; 2164 uint8_t skip_otg_disable; 2165 uint8_t reserved[58]; 2166 }; 2167 2168 /** 2169 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2170 */ 2171 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2172 struct dmub_cmd_header header; /**< header */ 2173 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2174 }; 2175 2176 /** 2177 * enum dmub_idle_opt_dc_power_state - DC power states. 2178 */ 2179 enum dmub_idle_opt_dc_power_state { 2180 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2181 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2182 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2183 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2184 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2185 }; 2186 2187 /** 2188 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2189 */ 2190 struct dmub_idle_opt_set_dc_power_state_data { 2191 uint8_t power_state; /**< power state */ 2192 uint8_t pad[3]; /**< padding */ 2193 }; 2194 2195 /** 2196 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2197 */ 2198 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2199 struct dmub_cmd_header header; /**< header */ 2200 struct dmub_idle_opt_set_dc_power_state_data data; 2201 }; 2202 2203 /** 2204 * struct dmub_clocks - Clock update notification. 2205 */ 2206 struct dmub_clocks { 2207 uint32_t dispclk_khz; /**< dispclk kHz */ 2208 uint32_t dppclk_khz; /**< dppclk kHz */ 2209 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2210 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2211 }; 2212 2213 /** 2214 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2215 */ 2216 enum dmub_cmd_clk_mgr_type { 2217 /** 2218 * Notify DMCUB of clock update. 2219 */ 2220 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2221 }; 2222 2223 /** 2224 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2225 */ 2226 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2227 struct dmub_cmd_header header; /**< header */ 2228 struct dmub_clocks clocks; /**< clock data */ 2229 }; 2230 2231 /** 2232 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2233 */ 2234 struct dmub_cmd_digx_encoder_control_data { 2235 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2236 }; 2237 2238 /** 2239 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2240 */ 2241 struct dmub_rb_cmd_digx_encoder_control { 2242 struct dmub_cmd_header header; /**< header */ 2243 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2244 }; 2245 2246 /** 2247 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2248 */ 2249 struct dmub_cmd_set_pixel_clock_data { 2250 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2251 }; 2252 2253 /** 2254 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2255 */ 2256 struct dmub_rb_cmd_set_pixel_clock { 2257 struct dmub_cmd_header header; /**< header */ 2258 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2259 }; 2260 2261 /** 2262 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2263 */ 2264 struct dmub_cmd_enable_disp_power_gating_data { 2265 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2266 }; 2267 2268 /** 2269 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2270 */ 2271 struct dmub_rb_cmd_enable_disp_power_gating { 2272 struct dmub_cmd_header header; /**< header */ 2273 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2274 }; 2275 2276 /** 2277 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2278 */ 2279 struct dmub_dig_transmitter_control_data_v1_7 { 2280 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2281 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2282 union { 2283 uint8_t digmode; /**< enum atom_encode_mode_def */ 2284 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2285 } mode_laneset; 2286 uint8_t lanenum; /**< Number of lanes */ 2287 union { 2288 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2289 } symclk_units; 2290 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2291 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2292 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2293 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2294 uint8_t reserved1; /**< For future use */ 2295 uint8_t reserved2[3]; /**< For future use */ 2296 uint32_t reserved3[11]; /**< For future use */ 2297 }; 2298 2299 /** 2300 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2301 */ 2302 union dmub_cmd_dig1_transmitter_control_data { 2303 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2304 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2305 }; 2306 2307 /** 2308 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2309 */ 2310 struct dmub_rb_cmd_dig1_transmitter_control { 2311 struct dmub_cmd_header header; /**< header */ 2312 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2313 }; 2314 2315 /** 2316 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2317 */ 2318 struct dmub_rb_cmd_domain_control_data { 2319 uint8_t inst : 6; /**< DOMAIN instance to control */ 2320 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2321 uint8_t reserved[3]; /**< Reserved for future use */ 2322 }; 2323 2324 /** 2325 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2326 */ 2327 struct dmub_rb_cmd_domain_control { 2328 struct dmub_cmd_header header; /**< header */ 2329 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2330 }; 2331 2332 /** 2333 * DPIA tunnel command parameters. 2334 */ 2335 struct dmub_cmd_dig_dpia_control_data { 2336 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2337 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2338 union { 2339 uint8_t digmode; /** enum atom_encode_mode_def */ 2340 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2341 } mode_laneset; 2342 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2343 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2344 uint8_t hpdsel; /** =0: HPD is not assigned */ 2345 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2346 uint8_t dpia_id; /** Index of DPIA */ 2347 uint8_t fec_rdy : 1; 2348 uint8_t reserved : 7; 2349 uint32_t reserved1; 2350 }; 2351 2352 /** 2353 * DMUB command for DPIA tunnel control. 2354 */ 2355 struct dmub_rb_cmd_dig1_dpia_control { 2356 struct dmub_cmd_header header; 2357 struct dmub_cmd_dig_dpia_control_data dpia_control; 2358 }; 2359 2360 /** 2361 * SET_CONFIG Command Payload (deprecated) 2362 */ 2363 struct set_config_cmd_payload { 2364 uint8_t msg_type; /* set config message type */ 2365 uint8_t msg_data; /* set config message data */ 2366 }; 2367 2368 /** 2369 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2370 */ 2371 struct dmub_cmd_set_config_control_data { 2372 struct set_config_cmd_payload cmd_pkt; 2373 uint8_t instance; /* DPIA instance */ 2374 uint8_t immed_status; /* Immediate status returned in case of error */ 2375 }; 2376 2377 /** 2378 * SET_CONFIG Request Command Payload 2379 */ 2380 struct set_config_request_cmd_payload { 2381 uint8_t instance; /* DPIA instance */ 2382 uint8_t immed_status; /* Immediate status returned in case of error */ 2383 uint8_t msg_type; /* set config message type */ 2384 uint8_t reserved; 2385 uint32_t msg_data; /* set config message data */ 2386 }; 2387 2388 /** 2389 * DMUB command structure for SET_CONFIG command. 2390 */ 2391 struct dmub_rb_cmd_set_config_access { 2392 struct dmub_cmd_header header; /* header */ 2393 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2394 }; 2395 2396 /** 2397 * DMUB command structure for SET_CONFIG request command. 2398 */ 2399 struct dmub_rb_cmd_set_config_request { 2400 struct dmub_cmd_header header; /* header */ 2401 struct set_config_request_cmd_payload payload; /* set config request payload */ 2402 }; 2403 2404 /** 2405 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2406 */ 2407 struct dmub_cmd_mst_alloc_slots_control_data { 2408 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2409 uint8_t instance; /* DPIA instance */ 2410 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2411 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2412 }; 2413 2414 /** 2415 * DMUB command structure for SET_ command. 2416 */ 2417 struct dmub_rb_cmd_set_mst_alloc_slots { 2418 struct dmub_cmd_header header; /* header */ 2419 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2420 }; 2421 2422 /** 2423 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2424 */ 2425 struct dmub_cmd_tps_notification_data { 2426 uint8_t instance; /* DPIA instance */ 2427 uint8_t tps; /* requested training pattern */ 2428 uint8_t reserved1; 2429 uint8_t reserved2; 2430 }; 2431 2432 /** 2433 * DMUB command structure for SET_TPS_NOTIFICATION command. 2434 */ 2435 struct dmub_rb_cmd_set_tps_notification { 2436 struct dmub_cmd_header header; /* header */ 2437 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2438 }; 2439 2440 /** 2441 * DMUB command structure for DPIA HPD int enable control. 2442 */ 2443 struct dmub_rb_cmd_dpia_hpd_int_enable { 2444 struct dmub_cmd_header header; /* header */ 2445 uint32_t enable; /* dpia hpd interrupt enable */ 2446 }; 2447 2448 /** 2449 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2450 */ 2451 struct dmub_rb_cmd_dpphy_init { 2452 struct dmub_cmd_header header; /**< header */ 2453 uint8_t reserved[60]; /**< reserved bits */ 2454 }; 2455 2456 /** 2457 * enum dp_aux_request_action - DP AUX request command listing. 2458 * 2459 * 4 AUX request command bits are shifted to high nibble. 2460 */ 2461 enum dp_aux_request_action { 2462 /** I2C-over-AUX write request */ 2463 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2464 /** I2C-over-AUX read request */ 2465 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2466 /** I2C-over-AUX write status request */ 2467 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2468 /** I2C-over-AUX write request with MOT=1 */ 2469 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2470 /** I2C-over-AUX read request with MOT=1 */ 2471 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2472 /** I2C-over-AUX write status request with MOT=1 */ 2473 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2474 /** Native AUX write request */ 2475 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2476 /** Native AUX read request */ 2477 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2478 }; 2479 2480 /** 2481 * enum aux_return_code_type - DP AUX process return code listing. 2482 */ 2483 enum aux_return_code_type { 2484 /** AUX process succeeded */ 2485 AUX_RET_SUCCESS = 0, 2486 /** AUX process failed with unknown reason */ 2487 AUX_RET_ERROR_UNKNOWN, 2488 /** AUX process completed with invalid reply */ 2489 AUX_RET_ERROR_INVALID_REPLY, 2490 /** AUX process timed out */ 2491 AUX_RET_ERROR_TIMEOUT, 2492 /** HPD was low during AUX process */ 2493 AUX_RET_ERROR_HPD_DISCON, 2494 /** Failed to acquire AUX engine */ 2495 AUX_RET_ERROR_ENGINE_ACQUIRE, 2496 /** AUX request not supported */ 2497 AUX_RET_ERROR_INVALID_OPERATION, 2498 /** AUX process not available */ 2499 AUX_RET_ERROR_PROTOCOL_ERROR, 2500 }; 2501 2502 /** 2503 * enum aux_channel_type - DP AUX channel type listing. 2504 */ 2505 enum aux_channel_type { 2506 /** AUX thru Legacy DP AUX */ 2507 AUX_CHANNEL_LEGACY_DDC, 2508 /** AUX thru DPIA DP tunneling */ 2509 AUX_CHANNEL_DPIA 2510 }; 2511 2512 /** 2513 * struct aux_transaction_parameters - DP AUX request transaction data 2514 */ 2515 struct aux_transaction_parameters { 2516 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2517 uint8_t action; /**< enum dp_aux_request_action */ 2518 uint8_t length; /**< DP AUX request data length */ 2519 uint8_t reserved; /**< For future use */ 2520 uint32_t address; /**< DP AUX address */ 2521 uint8_t data[16]; /**< DP AUX write data */ 2522 }; 2523 2524 /** 2525 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2526 */ 2527 struct dmub_cmd_dp_aux_control_data { 2528 uint8_t instance; /**< AUX instance or DPIA instance */ 2529 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2530 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2531 uint8_t reserved0; /**< For future use */ 2532 uint16_t timeout; /**< timeout time in us */ 2533 uint16_t reserved1; /**< For future use */ 2534 enum aux_channel_type type; /**< enum aux_channel_type */ 2535 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2536 }; 2537 2538 /** 2539 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2540 */ 2541 struct dmub_rb_cmd_dp_aux_access { 2542 /** 2543 * Command header. 2544 */ 2545 struct dmub_cmd_header header; 2546 /** 2547 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2548 */ 2549 struct dmub_cmd_dp_aux_control_data aux_control; 2550 }; 2551 2552 /** 2553 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2554 */ 2555 struct dmub_rb_cmd_outbox1_enable { 2556 /** 2557 * Command header. 2558 */ 2559 struct dmub_cmd_header header; 2560 /** 2561 * enable: 0x0 -> disable outbox1 notification (default value) 2562 * 0x1 -> enable outbox1 notification 2563 */ 2564 uint32_t enable; 2565 }; 2566 2567 /* DP AUX Reply command - OutBox Cmd */ 2568 /** 2569 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2570 */ 2571 struct aux_reply_data { 2572 /** 2573 * Aux cmd 2574 */ 2575 uint8_t command; 2576 /** 2577 * Aux reply data length (max: 16 bytes) 2578 */ 2579 uint8_t length; 2580 /** 2581 * Alignment only 2582 */ 2583 uint8_t pad[2]; 2584 /** 2585 * Aux reply data 2586 */ 2587 uint8_t data[16]; 2588 }; 2589 2590 /** 2591 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2592 */ 2593 struct aux_reply_control_data { 2594 /** 2595 * Reserved for future use 2596 */ 2597 uint32_t handle; 2598 /** 2599 * Aux Instance 2600 */ 2601 uint8_t instance; 2602 /** 2603 * Aux transaction result: definition in enum aux_return_code_type 2604 */ 2605 uint8_t result; 2606 /** 2607 * Alignment only 2608 */ 2609 uint16_t pad; 2610 }; 2611 2612 /** 2613 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2614 */ 2615 struct dmub_rb_cmd_dp_aux_reply { 2616 /** 2617 * Command header. 2618 */ 2619 struct dmub_cmd_header header; 2620 /** 2621 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2622 */ 2623 struct aux_reply_control_data control; 2624 /** 2625 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2626 */ 2627 struct aux_reply_data reply_data; 2628 }; 2629 2630 /* DP HPD Notify command - OutBox Cmd */ 2631 /** 2632 * DP HPD Type 2633 */ 2634 enum dp_hpd_type { 2635 /** 2636 * Normal DP HPD 2637 */ 2638 DP_HPD = 0, 2639 /** 2640 * DP HPD short pulse 2641 */ 2642 DP_IRQ = 1, 2643 /** 2644 * Failure to acquire DP HPD state 2645 */ 2646 DP_NONE_HPD = 2 2647 }; 2648 2649 /** 2650 * DP HPD Status 2651 */ 2652 enum dp_hpd_status { 2653 /** 2654 * DP_HPD status low 2655 */ 2656 DP_HPD_UNPLUG = 0, 2657 /** 2658 * DP_HPD status high 2659 */ 2660 DP_HPD_PLUG 2661 }; 2662 2663 /** 2664 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2665 */ 2666 struct dp_hpd_data { 2667 /** 2668 * DP HPD instance 2669 */ 2670 uint8_t instance; 2671 /** 2672 * HPD type 2673 */ 2674 uint8_t hpd_type; 2675 /** 2676 * HPD status: only for type: DP_HPD to indicate status 2677 */ 2678 uint8_t hpd_status; 2679 /** 2680 * Alignment only 2681 */ 2682 uint8_t pad; 2683 }; 2684 2685 /** 2686 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2687 */ 2688 struct dmub_rb_cmd_dp_hpd_notify { 2689 /** 2690 * Command header. 2691 */ 2692 struct dmub_cmd_header header; 2693 /** 2694 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2695 */ 2696 struct dp_hpd_data hpd_data; 2697 }; 2698 2699 /** 2700 * Definition of a SET_CONFIG reply from DPOA. 2701 */ 2702 enum set_config_status { 2703 SET_CONFIG_PENDING = 0, 2704 SET_CONFIG_ACK_RECEIVED, 2705 SET_CONFIG_RX_TIMEOUT, 2706 SET_CONFIG_UNKNOWN_ERROR, 2707 }; 2708 2709 /** 2710 * Definition of a set_config reply 2711 */ 2712 struct set_config_reply_control_data { 2713 uint8_t instance; /* DPIA Instance */ 2714 uint8_t status; /* Set Config reply */ 2715 uint16_t pad; /* Alignment */ 2716 }; 2717 2718 /** 2719 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2720 */ 2721 struct dmub_rb_cmd_dp_set_config_reply { 2722 struct dmub_cmd_header header; 2723 struct set_config_reply_control_data set_config_reply_control; 2724 }; 2725 2726 /** 2727 * Definition of a DPIA notification header 2728 */ 2729 struct dpia_notification_header { 2730 uint8_t instance; /**< DPIA Instance */ 2731 uint8_t reserved[3]; 2732 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2733 }; 2734 2735 /** 2736 * Definition of the common data struct of DPIA notification 2737 */ 2738 struct dpia_notification_common { 2739 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2740 - sizeof(struct dpia_notification_header)]; 2741 }; 2742 2743 /** 2744 * Definition of a DPIA notification data 2745 */ 2746 struct dpia_bw_allocation_notify_data { 2747 union { 2748 struct { 2749 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2750 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2751 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2752 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2753 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2754 uint16_t reserved: 11; /**< Reserved */ 2755 } bits; 2756 2757 uint16_t flags; 2758 }; 2759 2760 uint8_t cm_id; /**< CM ID */ 2761 uint8_t group_id; /**< Group ID */ 2762 uint8_t granularity; /**< BW Allocation Granularity */ 2763 uint8_t estimated_bw; /**< Estimated_BW */ 2764 uint8_t allocated_bw; /**< Allocated_BW */ 2765 uint8_t reserved; 2766 }; 2767 2768 /** 2769 * union dpia_notify_data_type - DPIA Notification in Outbox command 2770 */ 2771 union dpia_notification_data { 2772 /** 2773 * DPIA Notification for common data struct 2774 */ 2775 struct dpia_notification_common common_data; 2776 2777 /** 2778 * DPIA Notification for DP BW Allocation support 2779 */ 2780 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2781 }; 2782 2783 /** 2784 * Definition of a DPIA notification payload 2785 */ 2786 struct dpia_notification_payload { 2787 struct dpia_notification_header header; 2788 union dpia_notification_data data; /**< DPIA notification payload data */ 2789 }; 2790 2791 /** 2792 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2793 */ 2794 struct dmub_rb_cmd_dpia_notification { 2795 struct dmub_cmd_header header; /**< DPIA notification header */ 2796 struct dpia_notification_payload payload; /**< DPIA notification payload */ 2797 }; 2798 2799 /** 2800 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2801 */ 2802 struct dmub_cmd_hpd_state_query_data { 2803 uint8_t instance; /**< HPD instance or DPIA instance */ 2804 uint8_t result; /**< For returning HPD state */ 2805 uint16_t pad; /** < Alignment */ 2806 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 2807 enum aux_return_code_type status; /**< for returning the status of command */ 2808 }; 2809 2810 /** 2811 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 2812 */ 2813 struct dmub_rb_cmd_query_hpd_state { 2814 /** 2815 * Command header. 2816 */ 2817 struct dmub_cmd_header header; 2818 /** 2819 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 2820 */ 2821 struct dmub_cmd_hpd_state_query_data data; 2822 }; 2823 2824 /** 2825 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 2826 */ 2827 struct dmub_rb_cmd_hpd_sense_notify_data { 2828 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 2829 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 2830 }; 2831 2832 /** 2833 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 2834 */ 2835 struct dmub_rb_cmd_hpd_sense_notify { 2836 struct dmub_cmd_header header; /**< header */ 2837 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 2838 }; 2839 2840 /* 2841 * Command IDs should be treated as stable ABI. 2842 * Do not reuse or modify IDs. 2843 */ 2844 2845 /** 2846 * PSR command sub-types. 2847 */ 2848 enum dmub_cmd_psr_type { 2849 /** 2850 * Set PSR version support. 2851 */ 2852 DMUB_CMD__PSR_SET_VERSION = 0, 2853 /** 2854 * Copy driver-calculated parameters to PSR state. 2855 */ 2856 DMUB_CMD__PSR_COPY_SETTINGS = 1, 2857 /** 2858 * Enable PSR. 2859 */ 2860 DMUB_CMD__PSR_ENABLE = 2, 2861 2862 /** 2863 * Disable PSR. 2864 */ 2865 DMUB_CMD__PSR_DISABLE = 3, 2866 2867 /** 2868 * Set PSR level. 2869 * PSR level is a 16-bit value dicated by driver that 2870 * will enable/disable different functionality. 2871 */ 2872 DMUB_CMD__PSR_SET_LEVEL = 4, 2873 2874 /** 2875 * Forces PSR enabled until an explicit PSR disable call. 2876 */ 2877 DMUB_CMD__PSR_FORCE_STATIC = 5, 2878 /** 2879 * Set vtotal in psr active for FreeSync PSR. 2880 */ 2881 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 2882 /** 2883 * Set PSR power option 2884 */ 2885 DMUB_CMD__SET_PSR_POWER_OPT = 7, 2886 }; 2887 2888 /** 2889 * Different PSR residency modes. 2890 * Different modes change the definition of PSR residency. 2891 */ 2892 enum psr_residency_mode { 2893 PSR_RESIDENCY_MODE_PHY = 0, 2894 PSR_RESIDENCY_MODE_ALPM, 2895 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 2896 /* Do not add below. */ 2897 PSR_RESIDENCY_MODE_LAST_ELEMENT, 2898 }; 2899 2900 enum dmub_cmd_fams_type { 2901 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 2902 DMUB_CMD__FAMS_DRR_UPDATE = 1, 2903 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 2904 /** 2905 * For SubVP set manual trigger in FW because it 2906 * triggers DRR_UPDATE_PENDING which SubVP relies 2907 * on (for any SubVP cases that use a DRR display) 2908 */ 2909 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 2910 DMUB_CMD__FAMS2_CONFIG = 4, 2911 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 2912 DMUB_CMD__FAMS2_FLIP = 6, 2913 }; 2914 2915 /** 2916 * PSR versions. 2917 */ 2918 enum psr_version { 2919 /** 2920 * PSR version 1. 2921 */ 2922 PSR_VERSION_1 = 0, 2923 /** 2924 * Freesync PSR SU. 2925 */ 2926 PSR_VERSION_SU_1 = 1, 2927 /** 2928 * PSR not supported. 2929 */ 2930 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 2931 }; 2932 2933 /** 2934 * PHY Link rate for DP. 2935 */ 2936 enum phy_link_rate { 2937 /** 2938 * not supported. 2939 */ 2940 PHY_RATE_UNKNOWN = 0, 2941 /** 2942 * Rate_1 (RBR) - 1.62 Gbps/Lane 2943 */ 2944 PHY_RATE_162 = 1, 2945 /** 2946 * Rate_2 - 2.16 Gbps/Lane 2947 */ 2948 PHY_RATE_216 = 2, 2949 /** 2950 * Rate_3 - 2.43 Gbps/Lane 2951 */ 2952 PHY_RATE_243 = 3, 2953 /** 2954 * Rate_4 (HBR) - 2.70 Gbps/Lane 2955 */ 2956 PHY_RATE_270 = 4, 2957 /** 2958 * Rate_5 (RBR2)- 3.24 Gbps/Lane 2959 */ 2960 PHY_RATE_324 = 5, 2961 /** 2962 * Rate_6 - 4.32 Gbps/Lane 2963 */ 2964 PHY_RATE_432 = 6, 2965 /** 2966 * Rate_7 (HBR2)- 5.40 Gbps/Lane 2967 */ 2968 PHY_RATE_540 = 7, 2969 /** 2970 * Rate_8 (HBR3)- 8.10 Gbps/Lane 2971 */ 2972 PHY_RATE_810 = 8, 2973 /** 2974 * UHBR10 - 10.0 Gbps/Lane 2975 */ 2976 PHY_RATE_1000 = 9, 2977 /** 2978 * UHBR13.5 - 13.5 Gbps/Lane 2979 */ 2980 PHY_RATE_1350 = 10, 2981 /** 2982 * UHBR10 - 20.0 Gbps/Lane 2983 */ 2984 PHY_RATE_2000 = 11, 2985 2986 PHY_RATE_675 = 12, 2987 /** 2988 * Rate 12 - 6.75 Gbps/Lane 2989 */ 2990 }; 2991 2992 /** 2993 * enum dmub_phy_fsm_state - PHY FSM states. 2994 * PHY FSM state to transit to during PSR enable/disable. 2995 */ 2996 enum dmub_phy_fsm_state { 2997 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 2998 DMUB_PHY_FSM_RESET, 2999 DMUB_PHY_FSM_RESET_RELEASED, 3000 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3001 DMUB_PHY_FSM_INITIALIZED, 3002 DMUB_PHY_FSM_CALIBRATED, 3003 DMUB_PHY_FSM_CALIBRATED_LP, 3004 DMUB_PHY_FSM_CALIBRATED_PG, 3005 DMUB_PHY_FSM_POWER_DOWN, 3006 DMUB_PHY_FSM_PLL_EN, 3007 DMUB_PHY_FSM_TX_EN, 3008 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3009 DMUB_PHY_FSM_FAST_LP, 3010 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3011 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3012 DMUB_PHY_FSM_P2_PLL_OFF, 3013 DMUB_PHY_FSM_P2_PLL_ON, 3014 }; 3015 3016 /** 3017 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3018 */ 3019 struct dmub_cmd_psr_copy_settings_data { 3020 /** 3021 * Flags that can be set by driver to change some PSR behaviour. 3022 */ 3023 union dmub_psr_debug_flags debug; 3024 /** 3025 * 16-bit value dicated by driver that will enable/disable different functionality. 3026 */ 3027 uint16_t psr_level; 3028 /** 3029 * DPP HW instance. 3030 */ 3031 uint8_t dpp_inst; 3032 /** 3033 * MPCC HW instance. 3034 * Not used in dmub fw, 3035 * dmub fw will get active opp by reading odm registers. 3036 */ 3037 uint8_t mpcc_inst; 3038 /** 3039 * OPP HW instance. 3040 * Not used in dmub fw, 3041 * dmub fw will get active opp by reading odm registers. 3042 */ 3043 uint8_t opp_inst; 3044 /** 3045 * OTG HW instance. 3046 */ 3047 uint8_t otg_inst; 3048 /** 3049 * DIG FE HW instance. 3050 */ 3051 uint8_t digfe_inst; 3052 /** 3053 * DIG BE HW instance. 3054 */ 3055 uint8_t digbe_inst; 3056 /** 3057 * DP PHY HW instance. 3058 */ 3059 uint8_t dpphy_inst; 3060 /** 3061 * AUX HW instance. 3062 */ 3063 uint8_t aux_inst; 3064 /** 3065 * Determines if SMU optimzations are enabled/disabled. 3066 */ 3067 uint8_t smu_optimizations_en; 3068 /** 3069 * Unused. 3070 * TODO: Remove. 3071 */ 3072 uint8_t frame_delay; 3073 /** 3074 * If RFB setup time is greater than the total VBLANK time, 3075 * it is not possible for the sink to capture the video frame 3076 * in the same frame the SDP is sent. In this case, 3077 * the frame capture indication bit should be set and an extra 3078 * static frame should be transmitted to the sink. 3079 */ 3080 uint8_t frame_cap_ind; 3081 /** 3082 * Granularity of Y offset supported by sink. 3083 */ 3084 uint8_t su_y_granularity; 3085 /** 3086 * Indicates whether sink should start capturing 3087 * immediately following active scan line, 3088 * or starting with the 2nd active scan line. 3089 */ 3090 uint8_t line_capture_indication; 3091 /** 3092 * Multi-display optimizations are implemented on certain ASICs. 3093 */ 3094 uint8_t multi_disp_optimizations_en; 3095 /** 3096 * The last possible line SDP may be transmitted without violating 3097 * the RFB setup time or entering the active video frame. 3098 */ 3099 uint16_t init_sdp_deadline; 3100 /** 3101 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3102 */ 3103 uint8_t rate_control_caps ; 3104 /* 3105 * Force PSRSU always doing full frame update 3106 */ 3107 uint8_t force_ffu_mode; 3108 /** 3109 * Length of each horizontal line in us. 3110 */ 3111 uint32_t line_time_in_us; 3112 /** 3113 * FEC enable status in driver 3114 */ 3115 uint8_t fec_enable_status; 3116 /** 3117 * FEC re-enable delay when PSR exit. 3118 * unit is 100us, range form 0~255(0xFF). 3119 */ 3120 uint8_t fec_enable_delay_in100us; 3121 /** 3122 * PSR control version. 3123 */ 3124 uint8_t cmd_version; 3125 /** 3126 * Panel Instance. 3127 * Panel instance to identify which psr_state to use 3128 * Currently the support is only for 0 or 1 3129 */ 3130 uint8_t panel_inst; 3131 /* 3132 * DSC enable status in driver 3133 */ 3134 uint8_t dsc_enable_status; 3135 /* 3136 * Use FSM state for PSR power up/down 3137 */ 3138 uint8_t use_phy_fsm; 3139 /** 3140 * frame delay for frame re-lock 3141 */ 3142 uint8_t relock_delay_frame_cnt; 3143 /** 3144 * esd recovery indicate. 3145 */ 3146 uint8_t esd_recovery; 3147 /** 3148 * DSC Slice height. 3149 */ 3150 uint16_t dsc_slice_height; 3151 /** 3152 * Some panels request main link off before xth vertical line 3153 */ 3154 uint16_t poweroff_before_vertical_line; 3155 /** 3156 * Some panels cannot handle idle pattern during PSR entry. 3157 * To power down phy before disable stream to avoid sending 3158 * idle pattern. 3159 */ 3160 uint8_t power_down_phy_before_disable_stream; 3161 }; 3162 3163 /** 3164 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3165 */ 3166 struct dmub_rb_cmd_psr_copy_settings { 3167 /** 3168 * Command header. 3169 */ 3170 struct dmub_cmd_header header; 3171 /** 3172 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3173 */ 3174 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3175 }; 3176 3177 /** 3178 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3179 */ 3180 struct dmub_cmd_psr_set_level_data { 3181 /** 3182 * 16-bit value dicated by driver that will enable/disable different functionality. 3183 */ 3184 uint16_t psr_level; 3185 /** 3186 * PSR control version. 3187 */ 3188 uint8_t cmd_version; 3189 /** 3190 * Panel Instance. 3191 * Panel instance to identify which psr_state to use 3192 * Currently the support is only for 0 or 1 3193 */ 3194 uint8_t panel_inst; 3195 }; 3196 3197 /** 3198 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3199 */ 3200 struct dmub_rb_cmd_psr_set_level { 3201 /** 3202 * Command header. 3203 */ 3204 struct dmub_cmd_header header; 3205 /** 3206 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3207 */ 3208 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3209 }; 3210 3211 struct dmub_rb_cmd_psr_enable_data { 3212 /** 3213 * PSR control version. 3214 */ 3215 uint8_t cmd_version; 3216 /** 3217 * Panel Instance. 3218 * Panel instance to identify which psr_state to use 3219 * Currently the support is only for 0 or 1 3220 */ 3221 uint8_t panel_inst; 3222 /** 3223 * Phy state to enter. 3224 * Values to use are defined in dmub_phy_fsm_state 3225 */ 3226 uint8_t phy_fsm_state; 3227 /** 3228 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3229 * Set this using enum phy_link_rate. 3230 * This does not support HDMI/DP2 for now. 3231 */ 3232 uint8_t phy_rate; 3233 }; 3234 3235 /** 3236 * Definition of a DMUB_CMD__PSR_ENABLE command. 3237 * PSR enable/disable is controlled using the sub_type. 3238 */ 3239 struct dmub_rb_cmd_psr_enable { 3240 /** 3241 * Command header. 3242 */ 3243 struct dmub_cmd_header header; 3244 3245 struct dmub_rb_cmd_psr_enable_data data; 3246 }; 3247 3248 /** 3249 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3250 */ 3251 struct dmub_cmd_psr_set_version_data { 3252 /** 3253 * PSR version that FW should implement. 3254 */ 3255 enum psr_version version; 3256 /** 3257 * PSR control version. 3258 */ 3259 uint8_t cmd_version; 3260 /** 3261 * Panel Instance. 3262 * Panel instance to identify which psr_state to use 3263 * Currently the support is only for 0 or 1 3264 */ 3265 uint8_t panel_inst; 3266 /** 3267 * Explicit padding to 4 byte boundary. 3268 */ 3269 uint8_t pad[2]; 3270 }; 3271 3272 /** 3273 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3274 */ 3275 struct dmub_rb_cmd_psr_set_version { 3276 /** 3277 * Command header. 3278 */ 3279 struct dmub_cmd_header header; 3280 /** 3281 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3282 */ 3283 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3284 }; 3285 3286 struct dmub_cmd_psr_force_static_data { 3287 /** 3288 * PSR control version. 3289 */ 3290 uint8_t cmd_version; 3291 /** 3292 * Panel Instance. 3293 * Panel instance to identify which psr_state to use 3294 * Currently the support is only for 0 or 1 3295 */ 3296 uint8_t panel_inst; 3297 /** 3298 * Explicit padding to 4 byte boundary. 3299 */ 3300 uint8_t pad[2]; 3301 }; 3302 3303 /** 3304 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3305 */ 3306 struct dmub_rb_cmd_psr_force_static { 3307 /** 3308 * Command header. 3309 */ 3310 struct dmub_cmd_header header; 3311 /** 3312 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3313 */ 3314 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3315 }; 3316 3317 /** 3318 * PSR SU debug flags. 3319 */ 3320 union dmub_psr_su_debug_flags { 3321 /** 3322 * PSR SU debug flags. 3323 */ 3324 struct { 3325 /** 3326 * Update dirty rect in SW only. 3327 */ 3328 uint8_t update_dirty_rect_only : 1; 3329 /** 3330 * Reset the cursor/plane state before processing the call. 3331 */ 3332 uint8_t reset_state : 1; 3333 } bitfields; 3334 3335 /** 3336 * Union for debug flags. 3337 */ 3338 uint32_t u32All; 3339 }; 3340 3341 /** 3342 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3343 * This triggers a selective update for PSR SU. 3344 */ 3345 struct dmub_cmd_update_dirty_rect_data { 3346 /** 3347 * Dirty rects from OS. 3348 */ 3349 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3350 /** 3351 * PSR SU debug flags. 3352 */ 3353 union dmub_psr_su_debug_flags debug_flags; 3354 /** 3355 * OTG HW instance. 3356 */ 3357 uint8_t pipe_idx; 3358 /** 3359 * Number of dirty rects. 3360 */ 3361 uint8_t dirty_rect_count; 3362 /** 3363 * PSR control version. 3364 */ 3365 uint8_t cmd_version; 3366 /** 3367 * Panel Instance. 3368 * Panel instance to identify which psr_state to use 3369 * Currently the support is only for 0 or 1 3370 */ 3371 uint8_t panel_inst; 3372 }; 3373 3374 /** 3375 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3376 */ 3377 struct dmub_rb_cmd_update_dirty_rect { 3378 /** 3379 * Command header. 3380 */ 3381 struct dmub_cmd_header header; 3382 /** 3383 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3384 */ 3385 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3386 }; 3387 3388 /** 3389 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3390 */ 3391 union dmub_reg_cursor_control_cfg { 3392 struct { 3393 uint32_t cur_enable: 1; 3394 uint32_t reser0: 3; 3395 uint32_t cur_2x_magnify: 1; 3396 uint32_t reser1: 3; 3397 uint32_t mode: 3; 3398 uint32_t reser2: 5; 3399 uint32_t pitch: 2; 3400 uint32_t reser3: 6; 3401 uint32_t line_per_chunk: 5; 3402 uint32_t reser4: 3; 3403 } bits; 3404 uint32_t raw; 3405 }; 3406 struct dmub_cursor_position_cache_hubp { 3407 union dmub_reg_cursor_control_cfg cur_ctl; 3408 union dmub_reg_position_cfg { 3409 struct { 3410 uint32_t cur_x_pos: 16; 3411 uint32_t cur_y_pos: 16; 3412 } bits; 3413 uint32_t raw; 3414 } position; 3415 union dmub_reg_hot_spot_cfg { 3416 struct { 3417 uint32_t hot_x: 16; 3418 uint32_t hot_y: 16; 3419 } bits; 3420 uint32_t raw; 3421 } hot_spot; 3422 union dmub_reg_dst_offset_cfg { 3423 struct { 3424 uint32_t dst_x_offset: 13; 3425 uint32_t reserved: 19; 3426 } bits; 3427 uint32_t raw; 3428 } dst_offset; 3429 }; 3430 3431 union dmub_reg_cur0_control_cfg { 3432 struct { 3433 uint32_t cur0_enable: 1; 3434 uint32_t expansion_mode: 1; 3435 uint32_t reser0: 1; 3436 uint32_t cur0_rom_en: 1; 3437 uint32_t mode: 3; 3438 uint32_t reserved: 25; 3439 } bits; 3440 uint32_t raw; 3441 }; 3442 struct dmub_cursor_position_cache_dpp { 3443 union dmub_reg_cur0_control_cfg cur0_ctl; 3444 }; 3445 struct dmub_cursor_position_cfg { 3446 struct dmub_cursor_position_cache_hubp pHubp; 3447 struct dmub_cursor_position_cache_dpp pDpp; 3448 uint8_t pipe_idx; 3449 /* 3450 * Padding is required. To be 4 Bytes Aligned. 3451 */ 3452 uint8_t padding[3]; 3453 }; 3454 3455 struct dmub_cursor_attribute_cache_hubp { 3456 uint32_t SURFACE_ADDR_HIGH; 3457 uint32_t SURFACE_ADDR; 3458 union dmub_reg_cursor_control_cfg cur_ctl; 3459 union dmub_reg_cursor_size_cfg { 3460 struct { 3461 uint32_t width: 16; 3462 uint32_t height: 16; 3463 } bits; 3464 uint32_t raw; 3465 } size; 3466 union dmub_reg_cursor_settings_cfg { 3467 struct { 3468 uint32_t dst_y_offset: 8; 3469 uint32_t chunk_hdl_adjust: 2; 3470 uint32_t reserved: 22; 3471 } bits; 3472 uint32_t raw; 3473 } settings; 3474 }; 3475 struct dmub_cursor_attribute_cache_dpp { 3476 union dmub_reg_cur0_control_cfg cur0_ctl; 3477 }; 3478 struct dmub_cursor_attributes_cfg { 3479 struct dmub_cursor_attribute_cache_hubp aHubp; 3480 struct dmub_cursor_attribute_cache_dpp aDpp; 3481 }; 3482 3483 struct dmub_cmd_update_cursor_payload0 { 3484 /** 3485 * Cursor dirty rects. 3486 */ 3487 struct dmub_rect cursor_rect; 3488 /** 3489 * PSR SU debug flags. 3490 */ 3491 union dmub_psr_su_debug_flags debug_flags; 3492 /** 3493 * Cursor enable/disable. 3494 */ 3495 uint8_t enable; 3496 /** 3497 * OTG HW instance. 3498 */ 3499 uint8_t pipe_idx; 3500 /** 3501 * PSR control version. 3502 */ 3503 uint8_t cmd_version; 3504 /** 3505 * Panel Instance. 3506 * Panel instance to identify which psr_state to use 3507 * Currently the support is only for 0 or 1 3508 */ 3509 uint8_t panel_inst; 3510 /** 3511 * Cursor Position Register. 3512 * Registers contains Hubp & Dpp modules 3513 */ 3514 struct dmub_cursor_position_cfg position_cfg; 3515 }; 3516 3517 struct dmub_cmd_update_cursor_payload1 { 3518 struct dmub_cursor_attributes_cfg attribute_cfg; 3519 }; 3520 3521 union dmub_cmd_update_cursor_info_data { 3522 struct dmub_cmd_update_cursor_payload0 payload0; 3523 struct dmub_cmd_update_cursor_payload1 payload1; 3524 }; 3525 /** 3526 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3527 */ 3528 struct dmub_rb_cmd_update_cursor_info { 3529 /** 3530 * Command header. 3531 */ 3532 struct dmub_cmd_header header; 3533 /** 3534 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3535 */ 3536 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3537 }; 3538 3539 /** 3540 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3541 */ 3542 struct dmub_cmd_psr_set_vtotal_data { 3543 /** 3544 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3545 */ 3546 uint16_t psr_vtotal_idle; 3547 /** 3548 * PSR control version. 3549 */ 3550 uint8_t cmd_version; 3551 /** 3552 * Panel Instance. 3553 * Panel instance to identify which psr_state to use 3554 * Currently the support is only for 0 or 1 3555 */ 3556 uint8_t panel_inst; 3557 /* 3558 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3559 */ 3560 uint16_t psr_vtotal_su; 3561 /** 3562 * Explicit padding to 4 byte boundary. 3563 */ 3564 uint8_t pad2[2]; 3565 }; 3566 3567 /** 3568 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3569 */ 3570 struct dmub_rb_cmd_psr_set_vtotal { 3571 /** 3572 * Command header. 3573 */ 3574 struct dmub_cmd_header header; 3575 /** 3576 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3577 */ 3578 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3579 }; 3580 3581 /** 3582 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3583 */ 3584 struct dmub_cmd_psr_set_power_opt_data { 3585 /** 3586 * PSR control version. 3587 */ 3588 uint8_t cmd_version; 3589 /** 3590 * Panel Instance. 3591 * Panel instance to identify which psr_state to use 3592 * Currently the support is only for 0 or 1 3593 */ 3594 uint8_t panel_inst; 3595 /** 3596 * Explicit padding to 4 byte boundary. 3597 */ 3598 uint8_t pad[2]; 3599 /** 3600 * PSR power option 3601 */ 3602 uint32_t power_opt; 3603 }; 3604 3605 /** 3606 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3607 */ 3608 struct dmub_rb_cmd_psr_set_power_opt { 3609 /** 3610 * Command header. 3611 */ 3612 struct dmub_cmd_header header; 3613 /** 3614 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3615 */ 3616 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3617 }; 3618 3619 /** 3620 * Definition of Replay Residency GPINT command. 3621 * Bit[0] - Residency mode for Revision 0 3622 * Bit[1] - Enable/Disable state 3623 * Bit[2-3] - Revision number 3624 * Bit[4-7] - Residency mode for Revision 1 3625 * Bit[8] - Panel instance 3626 * Bit[9-15] - Reserved 3627 */ 3628 3629 enum pr_residency_mode { 3630 PR_RESIDENCY_MODE_PHY = 0x0, 3631 PR_RESIDENCY_MODE_ALPM, 3632 PR_RESIDENCY_MODE_IPS2, 3633 PR_RESIDENCY_MODE_FRAME_CNT, 3634 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3635 }; 3636 3637 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3638 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3639 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3640 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3641 3642 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3643 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3644 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3645 3646 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3647 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3648 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3649 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3650 3651 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3652 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3653 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3654 3655 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3656 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3657 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3658 3659 /** 3660 * Definition of a replay_state. 3661 */ 3662 enum replay_state { 3663 REPLAY_STATE_0 = 0x0, 3664 REPLAY_STATE_1 = 0x10, 3665 REPLAY_STATE_1A = 0x11, 3666 REPLAY_STATE_2 = 0x20, 3667 REPLAY_STATE_2A = 0x21, 3668 REPLAY_STATE_3 = 0x30, 3669 REPLAY_STATE_3INIT = 0x31, 3670 REPLAY_STATE_4 = 0x40, 3671 REPLAY_STATE_4A = 0x41, 3672 REPLAY_STATE_4B = 0x42, 3673 REPLAY_STATE_4C = 0x43, 3674 REPLAY_STATE_4D = 0x44, 3675 REPLAY_STATE_4E = 0x45, 3676 REPLAY_STATE_4B_LOCKED = 0x4A, 3677 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3678 REPLAY_STATE_5 = 0x50, 3679 REPLAY_STATE_5A = 0x51, 3680 REPLAY_STATE_5B = 0x52, 3681 REPLAY_STATE_5A_LOCKED = 0x5A, 3682 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3683 REPLAY_STATE_6 = 0x60, 3684 REPLAY_STATE_6A = 0x61, 3685 REPLAY_STATE_6B = 0x62, 3686 REPLAY_STATE_INVALID = 0xFF, 3687 }; 3688 3689 /** 3690 * Replay command sub-types. 3691 */ 3692 enum dmub_cmd_replay_type { 3693 /** 3694 * Copy driver-calculated parameters to REPLAY state. 3695 */ 3696 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3697 /** 3698 * Enable REPLAY. 3699 */ 3700 DMUB_CMD__REPLAY_ENABLE = 1, 3701 /** 3702 * Set Replay power option. 3703 */ 3704 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3705 /** 3706 * Set coasting vtotal. 3707 */ 3708 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3709 /** 3710 * Set power opt and coasting vtotal. 3711 */ 3712 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3713 /** 3714 * Set disabled iiming sync. 3715 */ 3716 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3717 /** 3718 * Set Residency Frameupdate Timer. 3719 */ 3720 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3721 /** 3722 * Set pseudo vtotal 3723 */ 3724 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3725 /** 3726 * Set adaptive sync sdp enabled 3727 */ 3728 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3729 /** 3730 * Set Replay General command. 3731 */ 3732 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3733 }; 3734 3735 /** 3736 * Replay general command sub-types. 3737 */ 3738 enum dmub_cmd_replay_general_subtype { 3739 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3740 /** 3741 * TODO: For backward compatible, allow new command only. 3742 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3743 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3744 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3745 */ 3746 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3747 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3748 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3749 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3750 }; 3751 3752 /** 3753 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3754 */ 3755 struct dmub_cmd_replay_copy_settings_data { 3756 /** 3757 * Flags that can be set by driver to change some replay behaviour. 3758 */ 3759 union replay_debug_flags debug; 3760 3761 /** 3762 * @flags: Flags used to determine feature functionality. 3763 */ 3764 union replay_hw_flags flags; 3765 3766 /** 3767 * DPP HW instance. 3768 */ 3769 uint8_t dpp_inst; 3770 /** 3771 * OTG HW instance. 3772 */ 3773 uint8_t otg_inst; 3774 /** 3775 * DIG FE HW instance. 3776 */ 3777 uint8_t digfe_inst; 3778 /** 3779 * DIG BE HW instance. 3780 */ 3781 uint8_t digbe_inst; 3782 /** 3783 * AUX HW instance. 3784 */ 3785 uint8_t aux_inst; 3786 /** 3787 * Panel Instance. 3788 * Panel isntance to identify which psr_state to use 3789 * Currently the support is only for 0 or 1 3790 */ 3791 uint8_t panel_inst; 3792 /** 3793 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 3794 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 3795 */ 3796 uint8_t pixel_deviation_per_line; 3797 /** 3798 * @max_deviation_line: The max number of deviation line that can keep the timing 3799 * synchronized between the Source and Sink during Replay normal sleep mode. 3800 */ 3801 uint8_t max_deviation_line; 3802 /** 3803 * Length of each horizontal line in ns. 3804 */ 3805 uint32_t line_time_in_ns; 3806 /** 3807 * PHY instance. 3808 */ 3809 uint8_t dpphy_inst; 3810 /** 3811 * Determines if SMU optimzations are enabled/disabled. 3812 */ 3813 uint8_t smu_optimizations_en; 3814 /** 3815 * Determines if timing sync are enabled/disabled. 3816 */ 3817 uint8_t replay_timing_sync_supported; 3818 /* 3819 * Use FSM state for Replay power up/down 3820 */ 3821 uint8_t use_phy_fsm; 3822 }; 3823 3824 /** 3825 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3826 */ 3827 struct dmub_rb_cmd_replay_copy_settings { 3828 /** 3829 * Command header. 3830 */ 3831 struct dmub_cmd_header header; 3832 /** 3833 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3834 */ 3835 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 3836 }; 3837 3838 /** 3839 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 3840 */ 3841 enum replay_enable { 3842 /** 3843 * Disable REPLAY. 3844 */ 3845 REPLAY_DISABLE = 0, 3846 /** 3847 * Enable REPLAY. 3848 */ 3849 REPLAY_ENABLE = 1, 3850 }; 3851 3852 /** 3853 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 3854 */ 3855 struct dmub_rb_cmd_replay_enable_data { 3856 /** 3857 * Replay enable or disable. 3858 */ 3859 uint8_t enable; 3860 /** 3861 * Panel Instance. 3862 * Panel isntance to identify which replay_state to use 3863 * Currently the support is only for 0 or 1 3864 */ 3865 uint8_t panel_inst; 3866 /** 3867 * Phy state to enter. 3868 * Values to use are defined in dmub_phy_fsm_state 3869 */ 3870 uint8_t phy_fsm_state; 3871 /** 3872 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3873 * Set this using enum phy_link_rate. 3874 * This does not support HDMI/DP2 for now. 3875 */ 3876 uint8_t phy_rate; 3877 }; 3878 3879 /** 3880 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 3881 * Replay enable/disable is controlled using action in data. 3882 */ 3883 struct dmub_rb_cmd_replay_enable { 3884 /** 3885 * Command header. 3886 */ 3887 struct dmub_cmd_header header; 3888 3889 struct dmub_rb_cmd_replay_enable_data data; 3890 }; 3891 3892 /** 3893 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3894 */ 3895 struct dmub_cmd_replay_set_power_opt_data { 3896 /** 3897 * Panel Instance. 3898 * Panel isntance to identify which replay_state to use 3899 * Currently the support is only for 0 or 1 3900 */ 3901 uint8_t panel_inst; 3902 /** 3903 * Explicit padding to 4 byte boundary. 3904 */ 3905 uint8_t pad[3]; 3906 /** 3907 * REPLAY power option 3908 */ 3909 uint32_t power_opt; 3910 }; 3911 3912 /** 3913 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 3914 */ 3915 struct dmub_cmd_replay_set_timing_sync_data { 3916 /** 3917 * Panel Instance. 3918 * Panel isntance to identify which replay_state to use 3919 * Currently the support is only for 0 or 1 3920 */ 3921 uint8_t panel_inst; 3922 /** 3923 * REPLAY set_timing_sync 3924 */ 3925 uint8_t timing_sync_supported; 3926 /** 3927 * Explicit padding to 4 byte boundary. 3928 */ 3929 uint8_t pad[2]; 3930 }; 3931 3932 /** 3933 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 3934 */ 3935 struct dmub_cmd_replay_set_pseudo_vtotal { 3936 /** 3937 * Panel Instance. 3938 * Panel isntance to identify which replay_state to use 3939 * Currently the support is only for 0 or 1 3940 */ 3941 uint8_t panel_inst; 3942 /** 3943 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 3944 */ 3945 uint16_t vtotal; 3946 /** 3947 * Explicit padding to 4 byte boundary. 3948 */ 3949 uint8_t pad; 3950 }; 3951 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 3952 /** 3953 * Panel Instance. 3954 * Panel isntance to identify which replay_state to use 3955 * Currently the support is only for 0 or 1 3956 */ 3957 uint8_t panel_inst; 3958 /** 3959 * enabled: set adaptive sync sdp enabled 3960 */ 3961 uint8_t force_disabled; 3962 3963 uint8_t pad[2]; 3964 }; 3965 struct dmub_cmd_replay_set_general_cmd_data { 3966 /** 3967 * Panel Instance. 3968 * Panel isntance to identify which replay_state to use 3969 * Currently the support is only for 0 or 1 3970 */ 3971 uint8_t panel_inst; 3972 /** 3973 * subtype: replay general cmd sub type 3974 */ 3975 uint8_t subtype; 3976 3977 uint8_t pad[2]; 3978 /** 3979 * config data with param1 and param2 3980 */ 3981 uint32_t param1; 3982 3983 uint32_t param2; 3984 }; 3985 3986 /** 3987 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3988 */ 3989 struct dmub_rb_cmd_replay_set_power_opt { 3990 /** 3991 * Command header. 3992 */ 3993 struct dmub_cmd_header header; 3994 /** 3995 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 3996 */ 3997 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 3998 }; 3999 4000 /** 4001 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4002 */ 4003 struct dmub_cmd_replay_set_coasting_vtotal_data { 4004 /** 4005 * 16-bit value dicated by driver that indicates the coasting vtotal. 4006 */ 4007 uint16_t coasting_vtotal; 4008 /** 4009 * REPLAY control version. 4010 */ 4011 uint8_t cmd_version; 4012 /** 4013 * Panel Instance. 4014 * Panel isntance to identify which replay_state to use 4015 * Currently the support is only for 0 or 1 4016 */ 4017 uint8_t panel_inst; 4018 /** 4019 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4020 */ 4021 uint16_t coasting_vtotal_high; 4022 /** 4023 * Explicit padding to 4 byte boundary. 4024 */ 4025 uint8_t pad[2]; 4026 }; 4027 4028 /** 4029 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4030 */ 4031 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4032 /** 4033 * Command header. 4034 */ 4035 struct dmub_cmd_header header; 4036 /** 4037 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4038 */ 4039 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4040 }; 4041 4042 /** 4043 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4044 */ 4045 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4046 /** 4047 * Command header. 4048 */ 4049 struct dmub_cmd_header header; 4050 /** 4051 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4052 */ 4053 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4054 /** 4055 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4056 */ 4057 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4058 }; 4059 4060 /** 4061 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4062 */ 4063 struct dmub_rb_cmd_replay_set_timing_sync { 4064 /** 4065 * Command header. 4066 */ 4067 struct dmub_cmd_header header; 4068 /** 4069 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4070 */ 4071 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4072 }; 4073 4074 /** 4075 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4076 */ 4077 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4078 /** 4079 * Command header. 4080 */ 4081 struct dmub_cmd_header header; 4082 /** 4083 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4084 */ 4085 struct dmub_cmd_replay_set_pseudo_vtotal data; 4086 }; 4087 4088 /** 4089 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4090 */ 4091 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4092 /** 4093 * Command header. 4094 */ 4095 struct dmub_cmd_header header; 4096 /** 4097 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4098 */ 4099 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4100 }; 4101 4102 /** 4103 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4104 */ 4105 struct dmub_rb_cmd_replay_set_general_cmd { 4106 /** 4107 * Command header. 4108 */ 4109 struct dmub_cmd_header header; 4110 /** 4111 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4112 */ 4113 struct dmub_cmd_replay_set_general_cmd_data data; 4114 }; 4115 4116 /** 4117 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4118 */ 4119 struct dmub_cmd_replay_frameupdate_timer_data { 4120 /** 4121 * Panel Instance. 4122 * Panel isntance to identify which replay_state to use 4123 * Currently the support is only for 0 or 1 4124 */ 4125 uint8_t panel_inst; 4126 /** 4127 * Replay Frameupdate Timer Enable or not 4128 */ 4129 uint8_t enable; 4130 /** 4131 * REPLAY force reflash frame update number 4132 */ 4133 uint16_t frameupdate_count; 4134 }; 4135 /** 4136 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4137 */ 4138 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4139 /** 4140 * Command header. 4141 */ 4142 struct dmub_cmd_header header; 4143 /** 4144 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4145 */ 4146 struct dmub_cmd_replay_frameupdate_timer_data data; 4147 }; 4148 4149 /** 4150 * Definition union of replay command set 4151 */ 4152 union dmub_replay_cmd_set { 4153 /** 4154 * Panel Instance. 4155 * Panel isntance to identify which replay_state to use 4156 * Currently the support is only for 0 or 1 4157 */ 4158 uint8_t panel_inst; 4159 /** 4160 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4161 */ 4162 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4163 /** 4164 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4165 */ 4166 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4167 /** 4168 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4169 */ 4170 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4171 /** 4172 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4173 */ 4174 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4175 /** 4176 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4177 */ 4178 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4179 }; 4180 4181 /** 4182 * Set of HW components that can be locked. 4183 * 4184 * Note: If updating with more HW components, fields 4185 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4186 */ 4187 union dmub_hw_lock_flags { 4188 /** 4189 * Set of HW components that can be locked. 4190 */ 4191 struct { 4192 /** 4193 * Lock/unlock OTG master update lock. 4194 */ 4195 uint8_t lock_pipe : 1; 4196 /** 4197 * Lock/unlock cursor. 4198 */ 4199 uint8_t lock_cursor : 1; 4200 /** 4201 * Lock/unlock global update lock. 4202 */ 4203 uint8_t lock_dig : 1; 4204 /** 4205 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4206 */ 4207 uint8_t triple_buffer_lock : 1; 4208 } bits; 4209 4210 /** 4211 * Union for HW Lock flags. 4212 */ 4213 uint8_t u8All; 4214 }; 4215 4216 /** 4217 * Instances of HW to be locked. 4218 * 4219 * Note: If updating with more HW components, fields 4220 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4221 */ 4222 struct dmub_hw_lock_inst_flags { 4223 /** 4224 * OTG HW instance for OTG master update lock. 4225 */ 4226 uint8_t otg_inst; 4227 /** 4228 * OPP instance for cursor lock. 4229 */ 4230 uint8_t opp_inst; 4231 /** 4232 * OTG HW instance for global update lock. 4233 * TODO: Remove, and re-use otg_inst. 4234 */ 4235 uint8_t dig_inst; 4236 /** 4237 * Explicit pad to 4 byte boundary. 4238 */ 4239 uint8_t pad; 4240 }; 4241 4242 /** 4243 * Clients that can acquire the HW Lock Manager. 4244 * 4245 * Note: If updating with more clients, fields in 4246 * dmub_inbox0_cmd_lock_hw must be updated to match. 4247 */ 4248 enum hw_lock_client { 4249 /** 4250 * Driver is the client of HW Lock Manager. 4251 */ 4252 HW_LOCK_CLIENT_DRIVER = 0, 4253 /** 4254 * PSR SU is the client of HW Lock Manager. 4255 */ 4256 HW_LOCK_CLIENT_PSR_SU = 1, 4257 HW_LOCK_CLIENT_SUBVP = 3, 4258 /** 4259 * Replay is the client of HW Lock Manager. 4260 */ 4261 HW_LOCK_CLIENT_REPLAY = 4, 4262 HW_LOCK_CLIENT_FAMS2 = 5, 4263 /** 4264 * Invalid client. 4265 */ 4266 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4267 }; 4268 4269 /** 4270 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4271 */ 4272 struct dmub_cmd_lock_hw_data { 4273 /** 4274 * Specifies the client accessing HW Lock Manager. 4275 */ 4276 enum hw_lock_client client; 4277 /** 4278 * HW instances to be locked. 4279 */ 4280 struct dmub_hw_lock_inst_flags inst_flags; 4281 /** 4282 * Which components to be locked. 4283 */ 4284 union dmub_hw_lock_flags hw_locks; 4285 /** 4286 * Specifies lock/unlock. 4287 */ 4288 uint8_t lock; 4289 /** 4290 * HW can be unlocked separately from releasing the HW Lock Mgr. 4291 * This flag is set if the client wishes to release the object. 4292 */ 4293 uint8_t should_release; 4294 /** 4295 * Explicit padding to 4 byte boundary. 4296 */ 4297 uint8_t pad; 4298 }; 4299 4300 /** 4301 * Definition of a DMUB_CMD__HW_LOCK command. 4302 * Command is used by driver and FW. 4303 */ 4304 struct dmub_rb_cmd_lock_hw { 4305 /** 4306 * Command header. 4307 */ 4308 struct dmub_cmd_header header; 4309 /** 4310 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4311 */ 4312 struct dmub_cmd_lock_hw_data lock_hw_data; 4313 }; 4314 4315 /** 4316 * ABM command sub-types. 4317 */ 4318 enum dmub_cmd_abm_type { 4319 /** 4320 * Initialize parameters for ABM algorithm. 4321 * Data is passed through an indirect buffer. 4322 */ 4323 DMUB_CMD__ABM_INIT_CONFIG = 0, 4324 /** 4325 * Set OTG and panel HW instance. 4326 */ 4327 DMUB_CMD__ABM_SET_PIPE = 1, 4328 /** 4329 * Set user requested backklight level. 4330 */ 4331 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4332 /** 4333 * Set ABM operating/aggression level. 4334 */ 4335 DMUB_CMD__ABM_SET_LEVEL = 3, 4336 /** 4337 * Set ambient light level. 4338 */ 4339 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4340 /** 4341 * Enable/disable fractional duty cycle for backlight PWM. 4342 */ 4343 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4344 4345 /** 4346 * unregister vertical interrupt after steady state is reached 4347 */ 4348 DMUB_CMD__ABM_PAUSE = 6, 4349 4350 /** 4351 * Save and Restore ABM state. On save we save parameters, and 4352 * on restore we update state with passed in data. 4353 */ 4354 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4355 4356 /** 4357 * Query ABM caps. 4358 */ 4359 DMUB_CMD__ABM_QUERY_CAPS = 8, 4360 4361 /** 4362 * Set ABM Events 4363 */ 4364 DMUB_CMD__ABM_SET_EVENT = 9, 4365 4366 /** 4367 * Get the current ACE curve. 4368 */ 4369 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4370 4371 /** 4372 * Get current histogram data 4373 */ 4374 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4375 }; 4376 4377 struct abm_ace_curve { 4378 /** 4379 * @offsets: ACE curve offsets. 4380 */ 4381 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4382 4383 /** 4384 * @thresholds: ACE curve thresholds. 4385 */ 4386 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4387 4388 /** 4389 * @slopes: ACE curve slopes. 4390 */ 4391 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4392 }; 4393 4394 struct fixed_pt_format { 4395 /** 4396 * @sign_bit: Indicates whether one bit is reserved for the sign. 4397 */ 4398 bool sign_bit; 4399 4400 /** 4401 * @num_int_bits: Number of bits used for integer part. 4402 */ 4403 uint8_t num_int_bits; 4404 4405 /** 4406 * @num_frac_bits: Number of bits used for fractional part. 4407 */ 4408 uint8_t num_frac_bits; 4409 4410 /** 4411 * @pad: Explicit padding to 4 byte boundary. 4412 */ 4413 uint8_t pad; 4414 }; 4415 4416 struct abm_caps { 4417 /** 4418 * @num_hg_bins: Number of histogram bins. 4419 */ 4420 uint8_t num_hg_bins; 4421 4422 /** 4423 * @num_ace_segments: Number of ACE curve segments. 4424 */ 4425 uint8_t num_ace_segments; 4426 4427 /** 4428 * @pad: Explicit padding to 4 byte boundary. 4429 */ 4430 uint8_t pad[2]; 4431 4432 /** 4433 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4434 */ 4435 struct fixed_pt_format ace_thresholds_format; 4436 4437 /** 4438 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4439 */ 4440 struct fixed_pt_format ace_offsets_format; 4441 4442 /** 4443 * @ace_slopes_format: Format of the ACE slopes. 4444 */ 4445 struct fixed_pt_format ace_slopes_format; 4446 }; 4447 4448 /** 4449 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4450 * Requirements: 4451 * - Padded explicitly to 32-bit boundary. 4452 * - Must ensure this structure matches the one on driver-side, 4453 * otherwise it won't be aligned. 4454 */ 4455 struct abm_config_table { 4456 /** 4457 * Gamma curve thresholds, used for crgb conversion. 4458 */ 4459 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4460 /** 4461 * Gamma curve offsets, used for crgb conversion. 4462 */ 4463 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4464 /** 4465 * Gamma curve slopes, used for crgb conversion. 4466 */ 4467 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4468 /** 4469 * Custom backlight curve thresholds. 4470 */ 4471 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4472 /** 4473 * Custom backlight curve offsets. 4474 */ 4475 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4476 /** 4477 * Ambient light thresholds. 4478 */ 4479 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4480 /** 4481 * Minimum programmable backlight. 4482 */ 4483 uint16_t min_abm_backlight; // 122B 4484 /** 4485 * Minimum reduction values. 4486 */ 4487 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4488 /** 4489 * Maximum reduction values. 4490 */ 4491 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4492 /** 4493 * Bright positive gain. 4494 */ 4495 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4496 /** 4497 * Dark negative gain. 4498 */ 4499 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4500 /** 4501 * Hybrid factor. 4502 */ 4503 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4504 /** 4505 * Contrast factor. 4506 */ 4507 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4508 /** 4509 * Deviation gain. 4510 */ 4511 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4512 /** 4513 * Minimum knee. 4514 */ 4515 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4516 /** 4517 * Maximum knee. 4518 */ 4519 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4520 /** 4521 * Unused. 4522 */ 4523 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4524 /** 4525 * Explicit padding to 4 byte boundary. 4526 */ 4527 uint8_t pad3[3]; // 229B 4528 /** 4529 * Backlight ramp reduction. 4530 */ 4531 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4532 /** 4533 * Backlight ramp start. 4534 */ 4535 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4536 }; 4537 4538 /** 4539 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4540 */ 4541 struct dmub_cmd_abm_set_pipe_data { 4542 /** 4543 * OTG HW instance. 4544 */ 4545 uint8_t otg_inst; 4546 4547 /** 4548 * Panel Control HW instance. 4549 */ 4550 uint8_t panel_inst; 4551 4552 /** 4553 * Controls how ABM will interpret a set pipe or set level command. 4554 */ 4555 uint8_t set_pipe_option; 4556 4557 /** 4558 * Unused. 4559 * TODO: Remove. 4560 */ 4561 uint8_t ramping_boundary; 4562 4563 /** 4564 * PwrSeq HW Instance. 4565 */ 4566 uint8_t pwrseq_inst; 4567 4568 /** 4569 * Explicit padding to 4 byte boundary. 4570 */ 4571 uint8_t pad[3]; 4572 }; 4573 4574 /** 4575 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4576 */ 4577 struct dmub_rb_cmd_abm_set_pipe { 4578 /** 4579 * Command header. 4580 */ 4581 struct dmub_cmd_header header; 4582 4583 /** 4584 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4585 */ 4586 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4587 }; 4588 4589 /** 4590 * Type of backlight control method to be used by ABM module 4591 */ 4592 enum dmub_backlight_control_type { 4593 /** 4594 * PWM Backlight control 4595 */ 4596 DMU_BACKLIGHT_CONTROL_PWM = 0, 4597 /** 4598 * VESA Aux-based backlight control 4599 */ 4600 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4601 /** 4602 * AMD DPCD Aux-based backlight control 4603 */ 4604 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4605 }; 4606 4607 /** 4608 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4609 */ 4610 struct dmub_cmd_abm_set_backlight_data { 4611 /** 4612 * Number of frames to ramp to backlight user level. 4613 */ 4614 uint32_t frame_ramp; 4615 4616 /** 4617 * Requested backlight level from user. 4618 */ 4619 uint32_t backlight_user_level; 4620 4621 /** 4622 * ABM control version. 4623 */ 4624 uint8_t version; 4625 4626 /** 4627 * Panel Control HW instance mask. 4628 * Bit 0 is Panel Control HW instance 0. 4629 * Bit 1 is Panel Control HW instance 1. 4630 */ 4631 uint8_t panel_mask; 4632 4633 /** 4634 * AUX HW Instance. 4635 */ 4636 uint8_t aux_inst; 4637 4638 /** 4639 * Explicit padding to 4 byte boundary. 4640 */ 4641 uint8_t pad[1]; 4642 4643 /** 4644 * Backlight control type. 4645 * Value 0 is PWM backlight control. 4646 * Value 1 is VAUX backlight control. 4647 * Value 2 is AMD DPCD AUX backlight control. 4648 */ 4649 enum dmub_backlight_control_type backlight_control_type; 4650 4651 /** 4652 * Minimum luminance in nits. 4653 */ 4654 uint32_t min_luminance; 4655 4656 /** 4657 * Maximum luminance in nits. 4658 */ 4659 uint32_t max_luminance; 4660 4661 /** 4662 * Minimum backlight in pwm. 4663 */ 4664 uint32_t min_backlight_pwm; 4665 4666 /** 4667 * Maximum backlight in pwm. 4668 */ 4669 uint32_t max_backlight_pwm; 4670 }; 4671 4672 /** 4673 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4674 */ 4675 struct dmub_rb_cmd_abm_set_backlight { 4676 /** 4677 * Command header. 4678 */ 4679 struct dmub_cmd_header header; 4680 4681 /** 4682 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4683 */ 4684 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4685 }; 4686 4687 /** 4688 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4689 */ 4690 struct dmub_cmd_abm_set_level_data { 4691 /** 4692 * Set current ABM operating/aggression level. 4693 */ 4694 uint32_t level; 4695 4696 /** 4697 * ABM control version. 4698 */ 4699 uint8_t version; 4700 4701 /** 4702 * Panel Control HW instance mask. 4703 * Bit 0 is Panel Control HW instance 0. 4704 * Bit 1 is Panel Control HW instance 1. 4705 */ 4706 uint8_t panel_mask; 4707 4708 /** 4709 * Explicit padding to 4 byte boundary. 4710 */ 4711 uint8_t pad[2]; 4712 }; 4713 4714 /** 4715 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4716 */ 4717 struct dmub_rb_cmd_abm_set_level { 4718 /** 4719 * Command header. 4720 */ 4721 struct dmub_cmd_header header; 4722 4723 /** 4724 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4725 */ 4726 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4727 }; 4728 4729 /** 4730 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4731 */ 4732 struct dmub_cmd_abm_set_ambient_level_data { 4733 /** 4734 * Ambient light sensor reading from OS. 4735 */ 4736 uint32_t ambient_lux; 4737 4738 /** 4739 * ABM control version. 4740 */ 4741 uint8_t version; 4742 4743 /** 4744 * Panel Control HW instance mask. 4745 * Bit 0 is Panel Control HW instance 0. 4746 * Bit 1 is Panel Control HW instance 1. 4747 */ 4748 uint8_t panel_mask; 4749 4750 /** 4751 * Explicit padding to 4 byte boundary. 4752 */ 4753 uint8_t pad[2]; 4754 }; 4755 4756 /** 4757 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4758 */ 4759 struct dmub_rb_cmd_abm_set_ambient_level { 4760 /** 4761 * Command header. 4762 */ 4763 struct dmub_cmd_header header; 4764 4765 /** 4766 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4767 */ 4768 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 4769 }; 4770 4771 /** 4772 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4773 */ 4774 struct dmub_cmd_abm_set_pwm_frac_data { 4775 /** 4776 * Enable/disable fractional duty cycle for backlight PWM. 4777 * TODO: Convert to uint8_t. 4778 */ 4779 uint32_t fractional_pwm; 4780 4781 /** 4782 * ABM control version. 4783 */ 4784 uint8_t version; 4785 4786 /** 4787 * Panel Control HW instance mask. 4788 * Bit 0 is Panel Control HW instance 0. 4789 * Bit 1 is Panel Control HW instance 1. 4790 */ 4791 uint8_t panel_mask; 4792 4793 /** 4794 * Explicit padding to 4 byte boundary. 4795 */ 4796 uint8_t pad[2]; 4797 }; 4798 4799 /** 4800 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 4801 */ 4802 struct dmub_rb_cmd_abm_set_pwm_frac { 4803 /** 4804 * Command header. 4805 */ 4806 struct dmub_cmd_header header; 4807 4808 /** 4809 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 4810 */ 4811 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 4812 }; 4813 4814 /** 4815 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4816 */ 4817 struct dmub_cmd_abm_init_config_data { 4818 /** 4819 * Location of indirect buffer used to pass init data to ABM. 4820 */ 4821 union dmub_addr src; 4822 4823 /** 4824 * Indirect buffer length. 4825 */ 4826 uint16_t bytes; 4827 4828 4829 /** 4830 * ABM control version. 4831 */ 4832 uint8_t version; 4833 4834 /** 4835 * Panel Control HW instance mask. 4836 * Bit 0 is Panel Control HW instance 0. 4837 * Bit 1 is Panel Control HW instance 1. 4838 */ 4839 uint8_t panel_mask; 4840 4841 /** 4842 * Explicit padding to 4 byte boundary. 4843 */ 4844 uint8_t pad[2]; 4845 }; 4846 4847 /** 4848 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 4849 */ 4850 struct dmub_rb_cmd_abm_init_config { 4851 /** 4852 * Command header. 4853 */ 4854 struct dmub_cmd_header header; 4855 4856 /** 4857 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 4858 */ 4859 struct dmub_cmd_abm_init_config_data abm_init_config_data; 4860 }; 4861 4862 /** 4863 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4864 */ 4865 4866 struct dmub_cmd_abm_pause_data { 4867 4868 /** 4869 * Panel Control HW instance mask. 4870 * Bit 0 is Panel Control HW instance 0. 4871 * Bit 1 is Panel Control HW instance 1. 4872 */ 4873 uint8_t panel_mask; 4874 4875 /** 4876 * OTG hw instance 4877 */ 4878 uint8_t otg_inst; 4879 4880 /** 4881 * Enable or disable ABM pause 4882 */ 4883 uint8_t enable; 4884 4885 /** 4886 * Explicit padding to 4 byte boundary. 4887 */ 4888 uint8_t pad[1]; 4889 }; 4890 4891 /** 4892 * Definition of a DMUB_CMD__ABM_PAUSE command. 4893 */ 4894 struct dmub_rb_cmd_abm_pause { 4895 /** 4896 * Command header. 4897 */ 4898 struct dmub_cmd_header header; 4899 4900 /** 4901 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 4902 */ 4903 struct dmub_cmd_abm_pause_data abm_pause_data; 4904 }; 4905 4906 /** 4907 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 4908 */ 4909 struct dmub_cmd_abm_query_caps_in { 4910 /** 4911 * Panel instance. 4912 */ 4913 uint8_t panel_inst; 4914 4915 /** 4916 * Explicit padding to 4 byte boundary. 4917 */ 4918 uint8_t pad[3]; 4919 }; 4920 4921 /** 4922 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4923 */ 4924 struct dmub_cmd_abm_query_caps_out { 4925 /** 4926 * SW Algorithm caps. 4927 */ 4928 struct abm_caps sw_caps; 4929 4930 /** 4931 * ABM HW caps. 4932 */ 4933 struct abm_caps hw_caps; 4934 }; 4935 4936 /** 4937 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 4938 */ 4939 struct dmub_rb_cmd_abm_query_caps { 4940 /** 4941 * Command header. 4942 */ 4943 struct dmub_cmd_header header; 4944 4945 /** 4946 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 4947 */ 4948 union { 4949 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 4950 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 4951 } data; 4952 }; 4953 4954 /** 4955 * enum dmub_abm_ace_curve_type - ACE curve type. 4956 */ 4957 enum dmub_abm_ace_curve_type { 4958 /** 4959 * ACE curve as defined by the SW layer. 4960 */ 4961 ABM_ACE_CURVE_TYPE__SW = 0, 4962 /** 4963 * ACE curve as defined by the SW to HW translation interface layer. 4964 */ 4965 ABM_ACE_CURVE_TYPE__SW_IF = 1, 4966 }; 4967 4968 /** 4969 * enum dmub_abm_histogram_type - Histogram type. 4970 */ 4971 enum dmub_abm_histogram_type { 4972 /** 4973 * ACE curve as defined by the SW layer. 4974 */ 4975 ABM_HISTOGRAM_TYPE__SW = 0, 4976 /** 4977 * ACE curve as defined by the SW to HW translation interface layer. 4978 */ 4979 ABM_HISTOGRAM_TYPE__SW_IF = 1, 4980 }; 4981 4982 /** 4983 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 4984 */ 4985 struct dmub_rb_cmd_abm_get_ace_curve { 4986 /** 4987 * Command header. 4988 */ 4989 struct dmub_cmd_header header; 4990 4991 /** 4992 * Address where ACE curve should be copied. 4993 */ 4994 union dmub_addr dest; 4995 4996 /** 4997 * Type of ACE curve being queried. 4998 */ 4999 enum dmub_abm_ace_curve_type ace_type; 5000 5001 /** 5002 * Indirect buffer length. 5003 */ 5004 uint16_t bytes; 5005 5006 /** 5007 * eDP panel instance. 5008 */ 5009 uint8_t panel_inst; 5010 5011 /** 5012 * Explicit padding to 4 byte boundary. 5013 */ 5014 uint8_t pad; 5015 }; 5016 5017 /** 5018 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5019 */ 5020 struct dmub_rb_cmd_abm_get_histogram { 5021 /** 5022 * Command header. 5023 */ 5024 struct dmub_cmd_header header; 5025 5026 /** 5027 * Address where Histogram should be copied. 5028 */ 5029 union dmub_addr dest; 5030 5031 /** 5032 * Type of Histogram being queried. 5033 */ 5034 enum dmub_abm_histogram_type histogram_type; 5035 5036 /** 5037 * Indirect buffer length. 5038 */ 5039 uint16_t bytes; 5040 5041 /** 5042 * eDP panel instance. 5043 */ 5044 uint8_t panel_inst; 5045 5046 /** 5047 * Explicit padding to 4 byte boundary. 5048 */ 5049 uint8_t pad; 5050 }; 5051 5052 /** 5053 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5054 */ 5055 struct dmub_rb_cmd_abm_save_restore { 5056 /** 5057 * Command header. 5058 */ 5059 struct dmub_cmd_header header; 5060 5061 /** 5062 * OTG hw instance 5063 */ 5064 uint8_t otg_inst; 5065 5066 /** 5067 * Enable or disable ABM pause 5068 */ 5069 uint8_t freeze; 5070 5071 /** 5072 * Explicit padding to 4 byte boundary. 5073 */ 5074 uint8_t debug; 5075 5076 /** 5077 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5078 */ 5079 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5080 }; 5081 5082 /** 5083 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5084 */ 5085 5086 struct dmub_cmd_abm_set_event_data { 5087 5088 /** 5089 * VB Scaling Init. Strength Mapping 5090 * Byte 0: 0~255 for VB level 0 5091 * Byte 1: 0~255 for VB level 1 5092 * Byte 2: 0~255 for VB level 2 5093 * Byte 3: 0~255 for VB level 3 5094 */ 5095 uint32_t vb_scaling_strength_mapping; 5096 /** 5097 * VariBright Scaling Enable 5098 */ 5099 uint8_t vb_scaling_enable; 5100 /** 5101 * Panel Control HW instance mask. 5102 * Bit 0 is Panel Control HW instance 0. 5103 * Bit 1 is Panel Control HW instance 1. 5104 */ 5105 uint8_t panel_mask; 5106 5107 /** 5108 * Explicit padding to 4 byte boundary. 5109 */ 5110 uint8_t pad[2]; 5111 }; 5112 5113 /** 5114 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5115 */ 5116 struct dmub_rb_cmd_abm_set_event { 5117 /** 5118 * Command header. 5119 */ 5120 struct dmub_cmd_header header; 5121 5122 /** 5123 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5124 */ 5125 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5126 }; 5127 5128 /** 5129 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5130 */ 5131 struct dmub_cmd_query_feature_caps_data { 5132 /** 5133 * DMUB feature capabilities. 5134 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5135 */ 5136 struct dmub_feature_caps feature_caps; 5137 }; 5138 5139 /** 5140 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5141 */ 5142 struct dmub_rb_cmd_query_feature_caps { 5143 /** 5144 * Command header. 5145 */ 5146 struct dmub_cmd_header header; 5147 /** 5148 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5149 */ 5150 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5151 }; 5152 5153 /** 5154 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5155 */ 5156 struct dmub_cmd_visual_confirm_color_data { 5157 /** 5158 * DMUB visual confirm color 5159 */ 5160 struct dmub_visual_confirm_color visual_confirm_color; 5161 }; 5162 5163 /** 5164 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5165 */ 5166 struct dmub_rb_cmd_get_visual_confirm_color { 5167 /** 5168 * Command header. 5169 */ 5170 struct dmub_cmd_header header; 5171 /** 5172 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5173 */ 5174 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5175 }; 5176 5177 /** 5178 * enum dmub_cmd_panel_cntl_type - Panel control command. 5179 */ 5180 enum dmub_cmd_panel_cntl_type { 5181 /** 5182 * Initializes embedded panel hardware blocks. 5183 */ 5184 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5185 /** 5186 * Queries backlight info for the embedded panel. 5187 */ 5188 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5189 /** 5190 * Sets the PWM Freq as per user's requirement. 5191 */ 5192 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5193 }; 5194 5195 /** 5196 * struct dmub_cmd_panel_cntl_data - Panel control data. 5197 */ 5198 struct dmub_cmd_panel_cntl_data { 5199 uint32_t pwrseq_inst; /**< pwrseq instance */ 5200 uint32_t current_backlight; /* in/out */ 5201 uint32_t bl_pwm_cntl; /* in/out */ 5202 uint32_t bl_pwm_period_cntl; /* in/out */ 5203 uint32_t bl_pwm_ref_div1; /* in/out */ 5204 uint8_t is_backlight_on : 1; /* in/out */ 5205 uint8_t is_powered_on : 1; /* in/out */ 5206 uint8_t padding[3]; 5207 uint32_t bl_pwm_ref_div2; /* in/out */ 5208 uint8_t reserved[4]; 5209 }; 5210 5211 /** 5212 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5213 */ 5214 struct dmub_rb_cmd_panel_cntl { 5215 struct dmub_cmd_header header; /**< header */ 5216 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5217 }; 5218 5219 struct dmub_optc_state { 5220 uint32_t v_total_max; 5221 uint32_t v_total_min; 5222 uint32_t tg_inst; 5223 }; 5224 5225 struct dmub_rb_cmd_drr_update { 5226 struct dmub_cmd_header header; 5227 struct dmub_optc_state dmub_optc_state_req; 5228 }; 5229 5230 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5231 uint32_t pix_clk_100hz; 5232 uint8_t max_ramp_step; 5233 uint8_t pipes; 5234 uint8_t min_refresh_in_hz; 5235 uint8_t pipe_count; 5236 uint8_t pipe_index[4]; 5237 }; 5238 5239 struct dmub_cmd_fw_assisted_mclk_switch_config { 5240 uint8_t fams_enabled; 5241 uint8_t visual_confirm_enabled; 5242 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5243 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5244 }; 5245 5246 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5247 struct dmub_cmd_header header; 5248 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5249 }; 5250 5251 /** 5252 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5253 */ 5254 struct dmub_cmd_lvtma_control_data { 5255 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5256 uint8_t bypass_panel_control_wait; 5257 uint8_t reserved_0[2]; /**< For future use */ 5258 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5259 uint8_t reserved_1[3]; /**< For future use */ 5260 }; 5261 5262 /** 5263 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5264 */ 5265 struct dmub_rb_cmd_lvtma_control { 5266 /** 5267 * Command header. 5268 */ 5269 struct dmub_cmd_header header; 5270 /** 5271 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5272 */ 5273 struct dmub_cmd_lvtma_control_data data; 5274 }; 5275 5276 /** 5277 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5278 */ 5279 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5280 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5281 uint8_t is_usb; /**< is phy is usb */ 5282 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5283 uint8_t is_dp4; /**< is dp in 4 lane */ 5284 }; 5285 5286 /** 5287 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5288 */ 5289 struct dmub_rb_cmd_transmitter_query_dp_alt { 5290 struct dmub_cmd_header header; /**< header */ 5291 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5292 }; 5293 5294 struct phy_test_mode { 5295 uint8_t mode; 5296 uint8_t pat0; 5297 uint8_t pad[2]; 5298 }; 5299 5300 /** 5301 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5302 */ 5303 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5304 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5305 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5306 uint8_t lane_num; /**< Number of lanes */ 5307 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5308 struct phy_test_mode test_mode; 5309 enum dmub_phy_fsm_state state; 5310 uint32_t status; 5311 uint8_t pad; 5312 }; 5313 5314 /** 5315 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5316 */ 5317 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5318 struct dmub_cmd_header header; /**< header */ 5319 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5320 }; 5321 5322 /** 5323 * Maximum number of bytes a chunk sent to DMUB for parsing 5324 */ 5325 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5326 5327 /** 5328 * Represent a chunk of CEA blocks sent to DMUB for parsing 5329 */ 5330 struct dmub_cmd_send_edid_cea { 5331 uint16_t offset; /**< offset into the CEA block */ 5332 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5333 uint16_t cea_total_length; /**< total length of the CEA block */ 5334 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5335 uint8_t pad[3]; /**< padding and for future expansion */ 5336 }; 5337 5338 /** 5339 * Result of VSDB parsing from CEA block 5340 */ 5341 struct dmub_cmd_edid_cea_amd_vsdb { 5342 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5343 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5344 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5345 uint16_t min_frame_rate; /**< Maximum frame rate */ 5346 uint16_t max_frame_rate; /**< Minimum frame rate */ 5347 }; 5348 5349 /** 5350 * Result of sending a CEA chunk 5351 */ 5352 struct dmub_cmd_edid_cea_ack { 5353 uint16_t offset; /**< offset of the chunk into the CEA block */ 5354 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5355 uint8_t pad; /**< padding and for future expansion */ 5356 }; 5357 5358 /** 5359 * Specify whether the result is an ACK/NACK or the parsing has finished 5360 */ 5361 enum dmub_cmd_edid_cea_reply_type { 5362 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5363 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5364 }; 5365 5366 /** 5367 * Definition of a DMUB_CMD__EDID_CEA command. 5368 */ 5369 struct dmub_rb_cmd_edid_cea { 5370 struct dmub_cmd_header header; /**< Command header */ 5371 union dmub_cmd_edid_cea_data { 5372 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5373 struct dmub_cmd_edid_cea_output { /**< output with results */ 5374 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5375 union { 5376 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5377 struct dmub_cmd_edid_cea_ack ack; 5378 }; 5379 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5380 } data; /**< Command data */ 5381 5382 }; 5383 5384 /** 5385 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5386 */ 5387 struct dmub_cmd_cable_id_input { 5388 uint8_t phy_inst; /**< phy inst for cable id data */ 5389 }; 5390 5391 /** 5392 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5393 */ 5394 struct dmub_cmd_cable_id_output { 5395 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5396 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5397 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5398 uint8_t RESERVED :2; /**< reserved means not defined */ 5399 }; 5400 5401 /** 5402 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5403 */ 5404 struct dmub_rb_cmd_get_usbc_cable_id { 5405 struct dmub_cmd_header header; /**< Command header */ 5406 /** 5407 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5408 */ 5409 union dmub_cmd_cable_id_data { 5410 struct dmub_cmd_cable_id_input input; /**< Input */ 5411 struct dmub_cmd_cable_id_output output; /**< Output */ 5412 uint8_t output_raw; /**< Raw data output */ 5413 } data; 5414 }; 5415 5416 enum dmub_cmd_fused_io_sub_type { 5417 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5418 DMUB_CMD__FUSED_IO_ABORT = 1, 5419 }; 5420 5421 enum dmub_cmd_fused_request_type { 5422 FUSED_REQUEST_READ, 5423 FUSED_REQUEST_WRITE, 5424 FUSED_REQUEST_POLL, 5425 }; 5426 5427 enum dmub_cmd_fused_request_status { 5428 FUSED_REQUEST_STATUS_SUCCESS, 5429 FUSED_REQUEST_STATUS_BEGIN, 5430 FUSED_REQUEST_STATUS_SUBMIT, 5431 FUSED_REQUEST_STATUS_REPLY, 5432 FUSED_REQUEST_STATUS_POLL, 5433 FUSED_REQUEST_STATUS_ABORTED, 5434 FUSED_REQUEST_STATUS_FAILED = 0x80, 5435 FUSED_REQUEST_STATUS_INVALID, 5436 FUSED_REQUEST_STATUS_BUSY, 5437 FUSED_REQUEST_STATUS_TIMEOUT, 5438 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5439 }; 5440 5441 struct dmub_cmd_fused_request { 5442 uint8_t status; 5443 uint8_t type : 2; 5444 uint8_t _reserved0 : 3; 5445 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5446 uint8_t identifier; 5447 uint8_t _reserved1; 5448 uint32_t timeout_us; 5449 union dmub_cmd_fused_request_location { 5450 struct dmub_cmd_fused_request_location_i2c { 5451 uint8_t is_aux : 1; // False 5452 uint8_t ddc_line : 3; 5453 uint8_t over_aux : 1; 5454 uint8_t _reserved0 : 3; 5455 uint8_t address; 5456 uint8_t offset; 5457 uint8_t length; 5458 } i2c; 5459 struct dmub_cmd_fused_request_location_aux { 5460 uint32_t is_aux : 1; // True 5461 uint32_t ddc_line : 3; 5462 uint32_t address : 20; 5463 uint32_t length : 8; // Automatically split into 16B transactions 5464 } aux; 5465 } u; 5466 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5467 }; 5468 5469 struct dmub_rb_cmd_fused_io { 5470 struct dmub_cmd_header header; 5471 struct dmub_cmd_fused_request request; 5472 }; 5473 5474 /** 5475 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5476 */ 5477 enum dmub_cmd_secure_display_type { 5478 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5479 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5480 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5481 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5482 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5483 }; 5484 5485 #define MAX_ROI_NUM 2 5486 5487 struct dmub_cmd_roi_info { 5488 uint16_t x_start; 5489 uint16_t x_end; 5490 uint16_t y_start; 5491 uint16_t y_end; 5492 uint8_t otg_id; 5493 uint8_t phy_id; 5494 }; 5495 5496 struct dmub_cmd_roi_window_ctl { 5497 uint16_t x_start; 5498 uint16_t x_end; 5499 uint16_t y_start; 5500 uint16_t y_end; 5501 bool enable; 5502 }; 5503 5504 struct dmub_cmd_roi_ctl_info { 5505 uint8_t otg_id; 5506 uint8_t phy_id; 5507 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5508 }; 5509 5510 /** 5511 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5512 */ 5513 struct dmub_rb_cmd_secure_display { 5514 struct dmub_cmd_header header; 5515 /** 5516 * Data passed from driver to dmub firmware. 5517 */ 5518 struct dmub_cmd_roi_info roi_info; 5519 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5520 }; 5521 5522 /** 5523 * Command type of a DMUB_CMD__PSP command 5524 */ 5525 enum dmub_cmd_psp_type { 5526 DMUB_CMD__PSP_ASSR_ENABLE = 0 5527 }; 5528 5529 /** 5530 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5531 */ 5532 struct dmub_cmd_assr_enable_data { 5533 /** 5534 * ASSR enable or disable. 5535 */ 5536 uint8_t enable; 5537 /** 5538 * PHY port type. 5539 * Indicates eDP / non-eDP port type 5540 */ 5541 uint8_t phy_port_type; 5542 /** 5543 * PHY port ID. 5544 */ 5545 uint8_t phy_port_id; 5546 /** 5547 * Link encoder index. 5548 */ 5549 uint8_t link_enc_index; 5550 /** 5551 * HPO mode. 5552 */ 5553 uint8_t hpo_mode; 5554 5555 /** 5556 * Reserved field. 5557 */ 5558 uint8_t reserved[7]; 5559 }; 5560 5561 /** 5562 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5563 */ 5564 struct dmub_rb_cmd_assr_enable { 5565 /** 5566 * Command header. 5567 */ 5568 struct dmub_cmd_header header; 5569 5570 /** 5571 * Assr data. 5572 */ 5573 struct dmub_cmd_assr_enable_data assr_data; 5574 5575 /** 5576 * Reserved field. 5577 */ 5578 uint32_t reserved[3]; 5579 }; 5580 5581 /** 5582 * union dmub_rb_cmd - DMUB inbox command. 5583 */ 5584 union dmub_rb_cmd { 5585 /** 5586 * Elements shared with all commands. 5587 */ 5588 struct dmub_rb_cmd_common cmd_common; 5589 /** 5590 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5591 */ 5592 struct dmub_rb_cmd_read_modify_write read_modify_write; 5593 /** 5594 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5595 */ 5596 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5597 /** 5598 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5599 */ 5600 struct dmub_rb_cmd_burst_write burst_write; 5601 /** 5602 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5603 */ 5604 struct dmub_rb_cmd_reg_wait reg_wait; 5605 /** 5606 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5607 */ 5608 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5609 /** 5610 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5611 */ 5612 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5613 /** 5614 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5615 */ 5616 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5617 /** 5618 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5619 */ 5620 struct dmub_rb_cmd_dpphy_init dpphy_init; 5621 /** 5622 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5623 */ 5624 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5625 /** 5626 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5627 */ 5628 struct dmub_rb_cmd_domain_control domain_control; 5629 /** 5630 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5631 */ 5632 struct dmub_rb_cmd_psr_set_version psr_set_version; 5633 /** 5634 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5635 */ 5636 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5637 /** 5638 * Definition of a DMUB_CMD__PSR_ENABLE command. 5639 */ 5640 struct dmub_rb_cmd_psr_enable psr_enable; 5641 /** 5642 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5643 */ 5644 struct dmub_rb_cmd_psr_set_level psr_set_level; 5645 /** 5646 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5647 */ 5648 struct dmub_rb_cmd_psr_force_static psr_force_static; 5649 /** 5650 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5651 */ 5652 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5653 /** 5654 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5655 */ 5656 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5657 /** 5658 * Definition of a DMUB_CMD__HW_LOCK command. 5659 * Command is used by driver and FW. 5660 */ 5661 struct dmub_rb_cmd_lock_hw lock_hw; 5662 /** 5663 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5664 */ 5665 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5666 /** 5667 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5668 */ 5669 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5670 /** 5671 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5672 */ 5673 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5674 /** 5675 * Definition of a DMUB_CMD__MALL command. 5676 */ 5677 struct dmub_rb_cmd_mall mall; 5678 5679 /** 5680 * Definition of a DMUB_CMD__CAB command. 5681 */ 5682 struct dmub_rb_cmd_cab_for_ss cab; 5683 5684 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5685 5686 /** 5687 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5688 */ 5689 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5690 5691 /** 5692 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5693 */ 5694 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5695 5696 /** 5697 * Definition of DMUB_CMD__PANEL_CNTL commands. 5698 */ 5699 struct dmub_rb_cmd_panel_cntl panel_cntl; 5700 5701 /** 5702 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5703 */ 5704 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5705 5706 /** 5707 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5708 */ 5709 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5710 5711 /** 5712 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5713 */ 5714 struct dmub_rb_cmd_abm_set_level abm_set_level; 5715 5716 /** 5717 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5718 */ 5719 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5720 5721 /** 5722 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5723 */ 5724 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5725 5726 /** 5727 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5728 */ 5729 struct dmub_rb_cmd_abm_init_config abm_init_config; 5730 5731 /** 5732 * Definition of a DMUB_CMD__ABM_PAUSE command. 5733 */ 5734 struct dmub_rb_cmd_abm_pause abm_pause; 5735 5736 /** 5737 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5738 */ 5739 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5740 5741 /** 5742 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5743 */ 5744 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5745 5746 /** 5747 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5748 */ 5749 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 5750 5751 /** 5752 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5753 */ 5754 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 5755 5756 /** 5757 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5758 */ 5759 struct dmub_rb_cmd_abm_set_event abm_set_event; 5760 5761 /** 5762 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 5763 */ 5764 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 5765 5766 /** 5767 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 5768 */ 5769 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 5770 5771 /** 5772 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5773 */ 5774 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 5775 5776 /** 5777 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5778 */ 5779 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 5780 struct dmub_rb_cmd_drr_update drr_update; 5781 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 5782 5783 /** 5784 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5785 */ 5786 struct dmub_rb_cmd_lvtma_control lvtma_control; 5787 /** 5788 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5789 */ 5790 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 5791 /** 5792 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5793 */ 5794 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 5795 /** 5796 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 5797 */ 5798 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 5799 /** 5800 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5801 */ 5802 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 5803 /** 5804 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 5805 */ 5806 struct dmub_rb_cmd_set_config_request set_config_request; 5807 /** 5808 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 5809 */ 5810 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 5811 /** 5812 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 5813 */ 5814 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 5815 /** 5816 * Definition of a DMUB_CMD__EDID_CEA command. 5817 */ 5818 struct dmub_rb_cmd_edid_cea edid_cea; 5819 /** 5820 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 5821 */ 5822 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 5823 5824 /** 5825 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 5826 */ 5827 struct dmub_rb_cmd_query_hpd_state query_hpd; 5828 /** 5829 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 5830 */ 5831 struct dmub_rb_cmd_secure_display secure_display; 5832 5833 /** 5834 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 5835 */ 5836 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 5837 /** 5838 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 5839 */ 5840 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 5841 /** 5842 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 5843 */ 5844 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 5845 /* 5846 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 5847 */ 5848 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 5849 /** 5850 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 5851 */ 5852 struct dmub_rb_cmd_replay_enable replay_enable; 5853 /** 5854 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 5855 */ 5856 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 5857 /** 5858 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 5859 */ 5860 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 5861 /** 5862 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 5863 */ 5864 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 5865 5866 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 5867 /** 5868 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 5869 */ 5870 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 5871 /** 5872 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 5873 */ 5874 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 5875 /** 5876 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 5877 */ 5878 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 5879 /** 5880 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 5881 */ 5882 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 5883 /** 5884 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5885 */ 5886 struct dmub_rb_cmd_assr_enable assr_enable; 5887 struct dmub_rb_cmd_fams2 fams2_config; 5888 5889 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 5890 5891 struct dmub_rb_cmd_fams2_flip fams2_flip; 5892 5893 struct dmub_rb_cmd_fused_io fused_io; 5894 }; 5895 5896 /** 5897 * union dmub_rb_out_cmd - Outbox command 5898 */ 5899 union dmub_rb_out_cmd { 5900 /** 5901 * Parameters common to every command. 5902 */ 5903 struct dmub_rb_cmd_common cmd_common; 5904 /** 5905 * AUX reply command. 5906 */ 5907 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 5908 /** 5909 * HPD notify command. 5910 */ 5911 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 5912 /** 5913 * SET_CONFIG reply command. 5914 */ 5915 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 5916 /** 5917 * DPIA notification command. 5918 */ 5919 struct dmub_rb_cmd_dpia_notification dpia_notification; 5920 /** 5921 * HPD sense notification command. 5922 */ 5923 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 5924 struct dmub_rb_cmd_fused_io fused_io; 5925 }; 5926 #pragma pack(pop) 5927 5928 5929 //============================================================================== 5930 //</DMUB_CMD>=================================================================== 5931 //============================================================================== 5932 //< DMUB_RB>==================================================================== 5933 //============================================================================== 5934 5935 /** 5936 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 5937 */ 5938 struct dmub_rb_init_params { 5939 void *ctx; /**< Caller provided context pointer */ 5940 void *base_address; /**< CPU base address for ring's data */ 5941 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5942 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 5943 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 5944 }; 5945 5946 /** 5947 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 5948 */ 5949 struct dmub_rb { 5950 void *base_address; /**< CPU address for the ring's data */ 5951 uint32_t rptr; /**< Read pointer for consumer in bytes */ 5952 uint32_t wrpt; /**< Write pointer for producer in bytes */ 5953 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 5954 5955 void *ctx; /**< Caller provided context pointer */ 5956 void *dmub; /**< Pointer to the DMUB interface */ 5957 }; 5958 5959 /** 5960 * @brief Checks if the ringbuffer is empty. 5961 * 5962 * @param rb DMUB Ringbuffer 5963 * @return true if empty 5964 * @return false otherwise 5965 */ 5966 static inline bool dmub_rb_empty(struct dmub_rb *rb) 5967 { 5968 return (rb->wrpt == rb->rptr); 5969 } 5970 5971 /** 5972 * @brief gets number of outstanding requests in the RB 5973 * 5974 * @param rb DMUB Ringbuffer 5975 * @return true if full 5976 */ 5977 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 5978 { 5979 uint32_t data_count; 5980 5981 if (rb->wrpt >= rb->rptr) 5982 data_count = rb->wrpt - rb->rptr; 5983 else 5984 data_count = rb->capacity - (rb->rptr - rb->wrpt); 5985 5986 return data_count / DMUB_RB_CMD_SIZE; 5987 } 5988 5989 /** 5990 * @brief gets number of free buffers in the RB 5991 * 5992 * @param rb DMUB Ringbuffer 5993 * @return true if full 5994 */ 5995 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 5996 { 5997 uint32_t data_count; 5998 5999 if (rb->wrpt >= rb->rptr) 6000 data_count = rb->wrpt - rb->rptr; 6001 else 6002 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6003 6004 /* +1 because 1 entry is always unusable */ 6005 data_count += DMUB_RB_CMD_SIZE; 6006 6007 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6008 } 6009 6010 /** 6011 * @brief Checks if the ringbuffer is full 6012 * 6013 * @param rb DMUB Ringbuffer 6014 * @return true if full 6015 * @return false otherwise 6016 */ 6017 static inline bool dmub_rb_full(struct dmub_rb *rb) 6018 { 6019 uint32_t data_count; 6020 6021 if (rb->wrpt >= rb->rptr) 6022 data_count = rb->wrpt - rb->rptr; 6023 else 6024 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6025 6026 /* -1 because 1 entry is always unusable */ 6027 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6028 } 6029 6030 /** 6031 * @brief Pushes a command into the ringbuffer 6032 * 6033 * @param rb DMUB ringbuffer 6034 * @param cmd The command to push 6035 * @return true if the ringbuffer was not full 6036 * @return false otherwise 6037 */ 6038 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6039 const union dmub_rb_cmd *cmd) 6040 { 6041 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6042 const uint64_t *src = (const uint64_t *)cmd; 6043 uint8_t i; 6044 6045 if (dmub_rb_full(rb)) 6046 return false; 6047 6048 // copying data 6049 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6050 *dst++ = *src++; 6051 6052 rb->wrpt += DMUB_RB_CMD_SIZE; 6053 6054 if (rb->wrpt >= rb->capacity) 6055 rb->wrpt %= rb->capacity; 6056 6057 return true; 6058 } 6059 6060 /** 6061 * @brief Pushes a command into the DMUB outbox ringbuffer 6062 * 6063 * @param rb DMUB outbox ringbuffer 6064 * @param cmd Outbox command 6065 * @return true if not full 6066 * @return false otherwise 6067 */ 6068 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6069 const union dmub_rb_out_cmd *cmd) 6070 { 6071 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6072 const uint8_t *src = (const uint8_t *)cmd; 6073 6074 if (dmub_rb_full(rb)) 6075 return false; 6076 6077 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6078 6079 rb->wrpt += DMUB_RB_CMD_SIZE; 6080 6081 if (rb->wrpt >= rb->capacity) 6082 rb->wrpt %= rb->capacity; 6083 6084 return true; 6085 } 6086 6087 /** 6088 * @brief Returns the next unprocessed command in the ringbuffer. 6089 * 6090 * @param rb DMUB ringbuffer 6091 * @param cmd The command to return 6092 * @return true if not empty 6093 * @return false otherwise 6094 */ 6095 static inline bool dmub_rb_front(struct dmub_rb *rb, 6096 union dmub_rb_cmd **cmd) 6097 { 6098 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6099 6100 if (dmub_rb_empty(rb)) 6101 return false; 6102 6103 *cmd = (union dmub_rb_cmd *)rb_cmd; 6104 6105 return true; 6106 } 6107 6108 /** 6109 * @brief Determines the next ringbuffer offset. 6110 * 6111 * @param rb DMUB inbox ringbuffer 6112 * @param num_cmds Number of commands 6113 * @param next_rptr The next offset in the ringbuffer 6114 */ 6115 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6116 uint32_t num_cmds, 6117 uint32_t *next_rptr) 6118 { 6119 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6120 6121 if (*next_rptr >= rb->capacity) 6122 *next_rptr %= rb->capacity; 6123 } 6124 6125 /** 6126 * @brief Returns a pointer to a command in the inbox. 6127 * 6128 * @param rb DMUB inbox ringbuffer 6129 * @param cmd The inbox command to return 6130 * @param rptr The ringbuffer offset 6131 * @return true if not empty 6132 * @return false otherwise 6133 */ 6134 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6135 union dmub_rb_cmd **cmd, 6136 uint32_t rptr) 6137 { 6138 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6139 6140 if (dmub_rb_empty(rb)) 6141 return false; 6142 6143 *cmd = (union dmub_rb_cmd *)rb_cmd; 6144 6145 return true; 6146 } 6147 6148 /** 6149 * @brief Returns the next unprocessed command in the outbox. 6150 * 6151 * @param rb DMUB outbox ringbuffer 6152 * @param cmd The outbox command to return 6153 * @return true if not empty 6154 * @return false otherwise 6155 */ 6156 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6157 union dmub_rb_out_cmd *cmd) 6158 { 6159 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6160 uint64_t *dst = (uint64_t *)cmd; 6161 uint8_t i; 6162 6163 if (dmub_rb_empty(rb)) 6164 return false; 6165 6166 // copying data 6167 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6168 *dst++ = *src++; 6169 6170 return true; 6171 } 6172 6173 /** 6174 * @brief Removes the front entry in the ringbuffer. 6175 * 6176 * @param rb DMUB ringbuffer 6177 * @return true if the command was removed 6178 * @return false if there were no commands 6179 */ 6180 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6181 { 6182 if (dmub_rb_empty(rb)) 6183 return false; 6184 6185 rb->rptr += DMUB_RB_CMD_SIZE; 6186 6187 if (rb->rptr >= rb->capacity) 6188 rb->rptr %= rb->capacity; 6189 6190 return true; 6191 } 6192 6193 /** 6194 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6195 * 6196 * Avoids a race condition where DMCUB accesses memory while 6197 * there are still writes in flight to framebuffer. 6198 * 6199 * @param rb DMUB ringbuffer 6200 */ 6201 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6202 { 6203 uint32_t rptr = rb->rptr; 6204 uint32_t wptr = rb->wrpt; 6205 6206 while (rptr != wptr) { 6207 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6208 uint8_t i; 6209 6210 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6211 (void)READ_ONCE(*data++); 6212 6213 rptr += DMUB_RB_CMD_SIZE; 6214 if (rptr >= rb->capacity) 6215 rptr %= rb->capacity; 6216 } 6217 } 6218 6219 /** 6220 * @brief Initializes a DMCUB ringbuffer 6221 * 6222 * @param rb DMUB ringbuffer 6223 * @param init_params initial configuration for the ringbuffer 6224 */ 6225 static inline void dmub_rb_init(struct dmub_rb *rb, 6226 struct dmub_rb_init_params *init_params) 6227 { 6228 rb->base_address = init_params->base_address; 6229 rb->capacity = init_params->capacity; 6230 rb->rptr = init_params->read_ptr; 6231 rb->wrpt = init_params->write_ptr; 6232 } 6233 6234 /** 6235 * @brief Copies output data from in/out commands into the given command. 6236 * 6237 * @param rb DMUB ringbuffer 6238 * @param cmd Command to copy data into 6239 */ 6240 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6241 union dmub_rb_cmd *cmd) 6242 { 6243 // Copy rb entry back into command 6244 uint8_t *rd_ptr = (rb->rptr == 0) ? 6245 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6246 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6247 6248 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6249 } 6250 6251 //============================================================================== 6252 //</DMUB_RB>==================================================================== 6253 //============================================================================== 6254 #endif /* _DMUB_CMD_H_ */ 6255