1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 */ 307 struct dmub_soc_bb_params { 308 /* dml2_soc_power_management_parameters */ 309 uint32_t dram_clk_change_blackout_ns; 310 uint32_t dram_clk_change_read_only_ns; 311 uint32_t dram_clk_change_write_only_ns; 312 uint32_t fclk_change_blackout_ns; 313 uint32_t g7_ppt_blackout_ns; 314 uint32_t stutter_enter_plus_exit_latency_ns; 315 uint32_t stutter_exit_latency_ns; 316 uint32_t z8_stutter_enter_plus_exit_latency_ns; 317 uint32_t z8_stutter_exit_latency_ns; 318 uint32_t z8_min_idle_time_ns; 319 uint32_t type_b_dram_clk_change_blackout_ns; 320 uint32_t type_b_ppt_blackout_ns; 321 /* dml2_soc_vmin_clock_limits */ 322 uint32_t vmin_limit_dispclk_khz; 323 uint32_t vmin_limit_dcfclk_khz; 324 }; 325 #pragma pack(pop) 326 327 /** 328 * Dirty rect definition. 329 */ 330 struct dmub_rect { 331 /** 332 * Dirty rect x offset. 333 */ 334 uint32_t x; 335 336 /** 337 * Dirty rect y offset. 338 */ 339 uint32_t y; 340 341 /** 342 * Dirty rect width. 343 */ 344 uint32_t width; 345 346 /** 347 * Dirty rect height. 348 */ 349 uint32_t height; 350 }; 351 352 /** 353 * Flags that can be set by driver to change some PSR behaviour. 354 */ 355 union dmub_psr_debug_flags { 356 /** 357 * Debug flags. 358 */ 359 struct { 360 /** 361 * Enable visual confirm in FW. 362 */ 363 uint32_t visual_confirm : 1; 364 365 /** 366 * Force all selective updates to bw full frame updates. 367 */ 368 uint32_t force_full_frame_update : 1; 369 370 /** 371 * Use HW Lock Mgr object to do HW locking in FW. 372 */ 373 uint32_t use_hw_lock_mgr : 1; 374 375 /** 376 * Use TPS3 signal when restore main link. 377 */ 378 uint32_t force_wakeup_by_tps3 : 1; 379 380 /** 381 * Back to back flip, therefore cannot power down PHY 382 */ 383 uint32_t back_to_back_flip : 1; 384 385 /** 386 * Enable visual confirm for IPS 387 */ 388 uint32_t enable_ips_visual_confirm : 1; 389 } bitfields; 390 391 /** 392 * Union for debug flags. 393 */ 394 uint32_t u32All; 395 }; 396 397 /** 398 * Flags that can be set by driver to change some Replay behaviour. 399 */ 400 union replay_debug_flags { 401 struct { 402 /** 403 * 0x1 (bit 0) 404 * Enable visual confirm in FW. 405 */ 406 uint32_t visual_confirm : 1; 407 408 /** 409 * 0x2 (bit 1) 410 * @skip_crc: Set if need to skip CRC. 411 */ 412 uint32_t skip_crc : 1; 413 414 /** 415 * 0x4 (bit 2) 416 * @force_link_power_on: Force disable ALPM control 417 */ 418 uint32_t force_link_power_on : 1; 419 420 /** 421 * 0x8 (bit 3) 422 * @force_phy_power_on: Force phy power on 423 */ 424 uint32_t force_phy_power_on : 1; 425 426 /** 427 * 0x10 (bit 4) 428 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 429 */ 430 uint32_t timing_resync_disabled : 1; 431 432 /** 433 * 0x20 (bit 5) 434 * @skip_crtc_disabled: CRTC disable skipped 435 */ 436 uint32_t skip_crtc_disabled : 1; 437 438 /** 439 * 0x40 (bit 6) 440 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 441 */ 442 uint32_t force_defer_one_frame_update : 1; 443 444 /** 445 * 0x80 (bit 7) 446 * @disable_delay_alpm_on: Force disable delay alpm on 447 */ 448 uint32_t disable_delay_alpm_on : 1; 449 450 /** 451 * 0x100 (bit 8) 452 * @disable_desync_error_check: Force disable desync error check 453 */ 454 uint32_t disable_desync_error_check : 1; 455 456 /** 457 * 0x200 (bit 9) 458 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 459 */ 460 uint32_t force_self_update_when_abm_non_steady : 1; 461 462 /** 463 * 0x400 (bit 10) 464 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 465 * If we enter IPS2, the Visual confirm bar will change to yellow 466 */ 467 uint32_t enable_ips_visual_confirm : 1; 468 469 /** 470 * 0x800 (bit 11) 471 * @enable_ips_residency_profiling: Enable IPS residency profiling 472 */ 473 uint32_t enable_ips_residency_profiling : 1; 474 475 /** 476 * 0x1000 (bit 12) 477 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 478 */ 479 uint32_t enable_coasting_vtotal_check : 1; 480 /** 481 * 0x2000 (bit 13) 482 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 483 */ 484 uint32_t enable_visual_confirm_debug : 1; 485 486 uint32_t reserved : 18; 487 } bitfields; 488 489 uint32_t u32All; 490 }; 491 492 /** 493 * Flags record error state. 494 */ 495 union replay_visual_confirm_error_state_flags { 496 struct { 497 /** 498 * 0x1 (bit 0) - Desync Error flag. 499 */ 500 uint32_t desync_error : 1; 501 502 /** 503 * 0x2 (bit 1) - State Transition Error flag. 504 */ 505 uint32_t state_transition_error : 1; 506 507 /** 508 * 0x4 (bit 2) - Crc Error flag 509 */ 510 uint32_t crc_error : 1; 511 512 /** 513 * 0x8 (bit 3) - Reserved 514 */ 515 uint32_t reserved_3 : 1; 516 517 /** 518 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 519 * Added new debug flag to control DPCD. 520 */ 521 uint32_t incorrect_vtotal_in_static_screen : 1; 522 523 /** 524 * 0x20 (bit 5) - No doubled Refresh Rate. 525 */ 526 uint32_t no_double_rr : 1; 527 528 /** 529 * Reserved bit 6-7 530 */ 531 uint32_t reserved_6_7 : 2; 532 533 /** 534 * Reserved bit 9-31 535 */ 536 uint32_t reserved_9_31 : 24; 537 } bitfields; 538 539 uint32_t u32All; 540 }; 541 542 union replay_hw_flags { 543 struct { 544 /** 545 * @allow_alpm_fw_standby_mode: To indicate whether the 546 * ALPM FW standby mode is allowed 547 */ 548 uint32_t allow_alpm_fw_standby_mode : 1; 549 550 /* 551 * @dsc_enable_status: DSC enable status in driver 552 */ 553 uint32_t dsc_enable_status : 1; 554 555 /** 556 * @fec_enable_status: receive fec enable/disable status from driver 557 */ 558 uint32_t fec_enable_status : 1; 559 560 /* 561 * @smu_optimizations_en: SMU power optimization. 562 * Only when active display is Replay capable and display enters Replay. 563 * Trigger interrupt to SMU to powerup/down. 564 */ 565 uint32_t smu_optimizations_en : 1; 566 567 /** 568 * @phy_power_state: Indicates current phy power state 569 */ 570 uint32_t phy_power_state : 1; 571 572 /** 573 * @link_power_state: Indicates current link power state 574 */ 575 uint32_t link_power_state : 1; 576 /** 577 * Use TPS3 signal when restore main link. 578 */ 579 uint32_t force_wakeup_by_tps3 : 1; 580 /** 581 * @is_alpm_initialized: Indicates whether ALPM is initialized 582 */ 583 uint32_t is_alpm_initialized : 1; 584 585 /** 586 * @alpm_mode: Indicates ALPM mode selected 587 */ 588 uint32_t alpm_mode : 2; 589 } bitfields; 590 591 uint32_t u32All; 592 }; 593 594 union fw_assisted_mclk_switch_version { 595 struct { 596 uint8_t minor : 5; 597 uint8_t major : 3; 598 }; 599 uint8_t ver; 600 }; 601 602 /** 603 * DMUB feature capabilities. 604 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 605 */ 606 struct dmub_feature_caps { 607 /** 608 * Max PSR version supported by FW. 609 */ 610 uint8_t psr; 611 uint8_t fw_assisted_mclk_switch_ver; 612 uint8_t reserved[4]; 613 uint8_t subvp_psr_support; 614 uint8_t gecc_enable; 615 uint8_t replay_supported; 616 uint8_t replay_reserved[3]; 617 uint8_t abm_aux_backlight_support; 618 }; 619 620 struct dmub_visual_confirm_color { 621 /** 622 * Maximum 10 bits color value 623 */ 624 uint16_t color_r_cr; 625 uint16_t color_g_y; 626 uint16_t color_b_cb; 627 uint16_t panel_inst; 628 }; 629 630 //============================================================================== 631 //</DMUB_TYPES>================================================================= 632 //============================================================================== 633 //< DMUB_META>================================================================== 634 //============================================================================== 635 #pragma pack(push, 1) 636 637 /* Magic value for identifying dmub_fw_meta_info */ 638 #define DMUB_FW_META_MAGIC 0x444D5542 639 640 /* Offset from the end of the file to the dmub_fw_meta_info */ 641 #define DMUB_FW_META_OFFSET 0x24 642 643 /** 644 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 645 */ 646 union dmub_fw_meta_feature_bits { 647 struct { 648 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 649 uint32_t reserved : 31; 650 } bits; /**< status bits */ 651 uint32_t all; /**< 32-bit access to status bits */ 652 }; 653 654 /** 655 * struct dmub_fw_meta_info - metadata associated with fw binary 656 * 657 * NOTE: This should be considered a stable API. Fields should 658 * not be repurposed or reordered. New fields should be 659 * added instead to extend the structure. 660 * 661 * @magic_value: magic value identifying DMUB firmware meta info 662 * @fw_region_size: size of the firmware state region 663 * @trace_buffer_size: size of the tracebuffer region 664 * @fw_version: the firmware version information 665 * @dal_fw: 1 if the firmware is DAL 666 * @shared_state_size: size of the shared state region in bytes 667 * @shared_state_features: number of shared state features 668 */ 669 struct dmub_fw_meta_info { 670 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 671 uint32_t fw_region_size; /**< size of the firmware state region */ 672 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 673 uint32_t fw_version; /**< the firmware version information */ 674 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 675 uint8_t reserved[3]; /**< padding bits */ 676 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 677 uint16_t shared_state_features; /**< number of shared state features */ 678 uint16_t reserved2; /**< padding bytes */ 679 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 680 }; 681 682 /** 683 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 684 */ 685 union dmub_fw_meta { 686 struct dmub_fw_meta_info info; /**< metadata info */ 687 uint8_t reserved[64]; /**< padding bits */ 688 }; 689 690 #pragma pack(pop) 691 692 //============================================================================== 693 //< DMUB Trace Buffer>================================================================ 694 //============================================================================== 695 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 696 /** 697 * dmub_trace_code_t - firmware trace code, 32-bits 698 */ 699 typedef uint32_t dmub_trace_code_t; 700 701 /** 702 * struct dmcub_trace_buf_entry - Firmware trace entry 703 */ 704 struct dmcub_trace_buf_entry { 705 dmub_trace_code_t trace_code; /**< trace code for the event */ 706 uint32_t tick_count; /**< the tick count at time of trace */ 707 uint32_t param0; /**< trace defined parameter 0 */ 708 uint32_t param1; /**< trace defined parameter 1 */ 709 }; 710 #endif 711 712 //============================================================================== 713 //< DMUB_STATUS>================================================================ 714 //============================================================================== 715 716 /** 717 * DMCUB scratch registers can be used to determine firmware status. 718 * Current scratch register usage is as follows: 719 * 720 * SCRATCH0: FW Boot Status register 721 * SCRATCH5: LVTMA Status Register 722 * SCRATCH15: FW Boot Options register 723 */ 724 725 /** 726 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 727 */ 728 union dmub_fw_boot_status { 729 struct { 730 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 731 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 732 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 733 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 734 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 735 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 736 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 737 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 738 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 739 } bits; /**< status bits */ 740 uint32_t all; /**< 32-bit access to status bits */ 741 }; 742 743 /** 744 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 745 */ 746 enum dmub_fw_boot_status_bit { 747 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 748 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 749 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 750 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 751 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 752 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 753 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 754 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 755 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 756 }; 757 758 /* Register bit definition for SCRATCH5 */ 759 union dmub_lvtma_status { 760 struct { 761 uint32_t psp_ok : 1; 762 uint32_t edp_on : 1; 763 uint32_t reserved : 30; 764 } bits; 765 uint32_t all; 766 }; 767 768 enum dmub_lvtma_status_bit { 769 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 770 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 771 }; 772 773 enum dmub_ips_disable_type { 774 DMUB_IPS_ENABLE = 0, 775 DMUB_IPS_DISABLE_ALL = 1, 776 DMUB_IPS_DISABLE_IPS1 = 2, 777 DMUB_IPS_DISABLE_IPS2 = 3, 778 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 779 DMUB_IPS_DISABLE_DYNAMIC = 5, 780 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 781 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 782 }; 783 784 enum dmub_ips_rcg_disable_type { 785 DMUB_IPS_RCG_ENABLE = 0, 786 DMUB_IPS0_RCG_DISABLE = 1, 787 DMUB_IPS1_RCG_DISABLE = 2, 788 DMUB_IPS_RCG_DISABLE = 3 789 }; 790 791 #define DMUB_IPS1_ALLOW_MASK 0x00000001 792 #define DMUB_IPS2_ALLOW_MASK 0x00000002 793 #define DMUB_IPS1_COMMIT_MASK 0x00000004 794 #define DMUB_IPS2_COMMIT_MASK 0x00000008 795 796 /** 797 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 798 */ 799 union dmub_fw_boot_options { 800 struct { 801 uint32_t pemu_env : 1; /**< 1 if PEMU */ 802 uint32_t fpga_env : 1; /**< 1 if FPGA */ 803 uint32_t optimized_init : 1; /**< 1 if optimized init */ 804 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 805 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 806 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 807 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 808 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 809 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 810 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 811 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 812 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 813 uint32_t power_optimization: 1; 814 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 815 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 816 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 817 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 818 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 819 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 820 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 821 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 822 uint32_t ips_disable: 3; /* options to disable ips support*/ 823 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 824 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 825 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 826 uint32_t reserved : 6; /**< reserved */ 827 } bits; /**< boot bits */ 828 uint32_t all; /**< 32-bit access to bits */ 829 }; 830 831 enum dmub_fw_boot_options_bit { 832 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 833 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 834 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 835 }; 836 837 //============================================================================== 838 //< DMUB_SHARED_STATE>========================================================== 839 //============================================================================== 840 841 /** 842 * Shared firmware state between driver and firmware for lockless communication 843 * in situations where the inbox/outbox may be unavailable. 844 * 845 * Each structure *must* be at most 256-bytes in size. The layout allocation is 846 * described below: 847 * 848 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 849 */ 850 851 /** 852 * enum dmub_shared_state_feature_id - List of shared state features. 853 */ 854 enum dmub_shared_state_feature_id { 855 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 856 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 857 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 858 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 859 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 860 }; 861 862 /** 863 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 864 */ 865 union dmub_shared_state_ips_fw_signals { 866 struct { 867 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 868 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 869 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 870 uint32_t detection_required : 1; /**< 1 if detection is required */ 871 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 872 uint32_t reserved_bits : 27; /**< Reversed */ 873 } bits; 874 uint32_t all; 875 }; 876 877 /** 878 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 879 */ 880 union dmub_shared_state_ips_driver_signals { 881 struct { 882 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 883 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 884 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 885 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 886 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 887 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 888 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 889 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 890 uint32_t reserved_bits : 24; /**< Reversed bits */ 891 } bits; 892 uint32_t all; 893 }; 894 895 /** 896 * IPS FW Version 897 */ 898 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 899 900 struct dmub_shared_state_debug_setup { 901 union { 902 struct { 903 uint32_t exclude_points[62]; 904 } profile_mode; 905 }; 906 }; 907 908 /** 909 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 910 */ 911 struct dmub_shared_state_ips_fw { 912 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 913 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 914 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 915 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 916 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 917 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 918 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 919 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 920 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 921 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 922 }; /* 248-bytes, fixed */ 923 924 /** 925 * IPS Driver Version 926 */ 927 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 928 929 /** 930 * struct dmub_shared_state_ips_driver - Driver state for IPS. 931 */ 932 struct dmub_shared_state_ips_driver { 933 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 934 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 935 }; /* 248-bytes, fixed */ 936 937 /** 938 * enum dmub_shared_state_feature_common - Generic payload. 939 */ 940 struct dmub_shared_state_feature_common { 941 uint32_t padding[62]; 942 }; /* 248-bytes, fixed */ 943 944 /** 945 * enum dmub_shared_state_feature_header - Feature description. 946 */ 947 struct dmub_shared_state_feature_header { 948 uint16_t id; /**< Feature ID */ 949 uint16_t version; /**< Feature version */ 950 uint32_t reserved; /**< Reserved bytes. */ 951 }; /* 8 bytes, fixed */ 952 953 /** 954 * struct dmub_shared_state_feature_block - Feature block. 955 */ 956 struct dmub_shared_state_feature_block { 957 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 958 union dmub_shared_feature_state_union { 959 struct dmub_shared_state_feature_common common; /**< Generic data */ 960 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 961 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 962 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 963 } data; /**< Shared state data. */ 964 }; /* 256-bytes, fixed */ 965 966 /** 967 * Shared state size in bytes. 968 */ 969 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 970 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 971 972 //============================================================================== 973 //</DMUB_STATUS>================================================================ 974 //============================================================================== 975 //< DMUB_VBIOS>================================================================= 976 //============================================================================== 977 978 /* 979 * enum dmub_cmd_vbios_type - VBIOS commands. 980 * 981 * Command IDs should be treated as stable ABI. 982 * Do not reuse or modify IDs. 983 */ 984 enum dmub_cmd_vbios_type { 985 /** 986 * Configures the DIG encoder. 987 */ 988 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 989 /** 990 * Controls the PHY. 991 */ 992 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 993 /** 994 * Sets the pixel clock/symbol clock. 995 */ 996 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 997 /** 998 * Enables or disables power gating. 999 */ 1000 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1001 /** 1002 * Controls embedded panels. 1003 */ 1004 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1005 /** 1006 * Query DP alt status on a transmitter. 1007 */ 1008 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1009 /** 1010 * Control PHY FSM 1011 */ 1012 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1013 /** 1014 * Controls domain power gating 1015 */ 1016 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1017 }; 1018 1019 //============================================================================== 1020 //</DMUB_VBIOS>================================================================= 1021 //============================================================================== 1022 //< DMUB_GPINT>================================================================= 1023 //============================================================================== 1024 1025 /** 1026 * The shifts and masks below may alternatively be used to format and read 1027 * the command register bits. 1028 */ 1029 1030 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1031 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1032 1033 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1034 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1035 1036 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1037 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1038 1039 /** 1040 * Command responses. 1041 */ 1042 1043 /** 1044 * Return response for DMUB_GPINT__STOP_FW command. 1045 */ 1046 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1047 1048 /** 1049 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1050 */ 1051 union dmub_gpint_data_register { 1052 struct { 1053 uint32_t param : 16; /**< 16-bit parameter */ 1054 uint32_t command_code : 12; /**< GPINT command */ 1055 uint32_t status : 4; /**< Command status bit */ 1056 } bits; /**< GPINT bit access */ 1057 uint32_t all; /**< GPINT 32-bit access */ 1058 }; 1059 1060 /* 1061 * enum dmub_gpint_command - GPINT command to DMCUB FW 1062 * 1063 * Command IDs should be treated as stable ABI. 1064 * Do not reuse or modify IDs. 1065 */ 1066 enum dmub_gpint_command { 1067 /** 1068 * Invalid command, ignored. 1069 */ 1070 DMUB_GPINT__INVALID_COMMAND = 0, 1071 /** 1072 * DESC: Queries the firmware version. 1073 * RETURN: Firmware version. 1074 */ 1075 DMUB_GPINT__GET_FW_VERSION = 1, 1076 /** 1077 * DESC: Halts the firmware. 1078 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1079 */ 1080 DMUB_GPINT__STOP_FW = 2, 1081 /** 1082 * DESC: Get PSR state from FW. 1083 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1084 */ 1085 DMUB_GPINT__GET_PSR_STATE = 7, 1086 /** 1087 * DESC: Notifies DMCUB of the currently active streams. 1088 * ARGS: Stream mask, 1 bit per active stream index. 1089 */ 1090 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1091 /** 1092 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1093 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1094 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1095 * RETURN: PSR residency in milli-percent. 1096 */ 1097 DMUB_GPINT__PSR_RESIDENCY = 9, 1098 1099 /** 1100 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1101 */ 1102 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1103 1104 /** 1105 * DESC: Get REPLAY state from FW. 1106 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1107 */ 1108 DMUB_GPINT__GET_REPLAY_STATE = 13, 1109 1110 /** 1111 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1112 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1113 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1114 * RETURN: REPLAY residency in milli-percent. 1115 */ 1116 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1117 1118 /** 1119 * DESC: Copy bounding box to the host. 1120 * ARGS: Version of bounding box to copy 1121 * RETURN: Result of copying bounding box 1122 */ 1123 DMUB_GPINT__BB_COPY = 96, 1124 1125 /** 1126 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1127 * ARGS: The word3 for the 64 bit address 1128 */ 1129 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1130 1131 /** 1132 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1133 * ARGS: The word2 for the 64 bit address 1134 */ 1135 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1136 1137 /** 1138 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1139 * ARGS: The word1 for the 64 bit address 1140 */ 1141 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1142 1143 /** 1144 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1145 * ARGS: The word0 for the 64 bit address 1146 */ 1147 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1148 1149 /** 1150 * DESC: Updates the trace buffer lower 32-bit mask. 1151 * ARGS: The new mask 1152 * RETURN: Lower 32-bit mask. 1153 */ 1154 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1155 1156 /** 1157 * DESC: Updates the trace buffer mask bit0~bit15. 1158 * ARGS: The new mask 1159 * RETURN: Lower 32-bit mask. 1160 */ 1161 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1162 1163 /** 1164 * DESC: Updates the trace buffer mask bit16~bit31. 1165 * ARGS: The new mask 1166 * RETURN: Lower 32-bit mask. 1167 */ 1168 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1169 1170 /** 1171 * DESC: Updates the trace buffer mask bit32~bit47. 1172 * ARGS: The new mask 1173 * RETURN: Lower 32-bit mask. 1174 */ 1175 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1176 1177 /** 1178 * DESC: Updates the trace buffer mask bit48~bit63. 1179 * ARGS: The new mask 1180 * RETURN: Lower 32-bit mask. 1181 */ 1182 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1183 1184 /** 1185 * DESC: Read the trace buffer mask bi0~bit15. 1186 */ 1187 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1188 1189 /** 1190 * DESC: Read the trace buffer mask bit16~bit31. 1191 */ 1192 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1193 1194 /** 1195 * DESC: Read the trace buffer mask bi32~bit47. 1196 */ 1197 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1198 1199 /** 1200 * DESC: Updates the trace buffer mask bit32~bit63. 1201 */ 1202 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1203 1204 /** 1205 * DESC: Set IPS residency measurement 1206 * ARGS: 0 - Disable ips measurement 1207 * 1 - Enable ips measurement 1208 */ 1209 DMUB_GPINT__IPS_RESIDENCY = 121, 1210 1211 /** 1212 * DESC: Enable measurements for various task duration 1213 * ARGS: 0 - Disable measurement 1214 * 1 - Enable measurement 1215 */ 1216 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1217 1218 /** 1219 * DESC: Gets IPS residency in microseconds 1220 * ARGS: 0 - Return IPS1 residency 1221 * 1 - Return IPS2 residency 1222 * 2 - Return IPS1_RCG residency 1223 * 3 - Return IPS1_ONO2_ON residency 1224 * RETURN: Total residency in microseconds - lower 32 bits 1225 */ 1226 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1227 1228 /** 1229 * DESC: Gets IPS1 histogram counts 1230 * ARGS: Bucket index 1231 * RETURN: Total count for the bucket 1232 */ 1233 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1234 1235 /** 1236 * DESC: Gets IPS2 histogram counts 1237 * ARGS: Bucket index 1238 * RETURN: Total count for the bucket 1239 */ 1240 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1241 1242 /** 1243 * DESC: Gets IPS residency 1244 * ARGS: 0 - Return IPS1 residency 1245 * 1 - Return IPS2 residency 1246 * 2 - Return IPS1_RCG residency 1247 * 3 - Return IPS1_ONO2_ON residency 1248 * RETURN: Total residency in milli-percent. 1249 */ 1250 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1251 1252 /** 1253 * DESC: Gets IPS1_RCG histogram counts 1254 * ARGS: Bucket index 1255 * RETURN: Total count for the bucket 1256 */ 1257 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1258 1259 /** 1260 * DESC: Gets IPS1_ONO2_ON histogram counts 1261 * ARGS: Bucket index 1262 * RETURN: Total count for the bucket 1263 */ 1264 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1265 1266 /** 1267 * DESC: Gets IPS entry counter during residency measurement 1268 * ARGS: 0 - Return IPS1 entry counts 1269 * 1 - Return IPS2 entry counts 1270 * 2 - Return IPS1_RCG entry counts 1271 * 3 - Return IPS2_ONO2_ON entry counts 1272 * RETURN: Entry counter for selected IPS mode 1273 */ 1274 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1275 1276 /** 1277 * DESC: Gets IPS inactive residency in microseconds 1278 * ARGS: 0 - Return IPS1_MAX residency 1279 * 1 - Return IPS2 residency 1280 * 2 - Return IPS1_RCG residency 1281 * 3 - Return IPS1_ONO2_ON residency 1282 * RETURN: Total inactive residency in microseconds - lower 32 bits 1283 */ 1284 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1285 1286 /** 1287 * DESC: Gets IPS inactive residency in microseconds 1288 * ARGS: 0 - Return IPS1_MAX residency 1289 * 1 - Return IPS2 residency 1290 * 2 - Return IPS1_RCG residency 1291 * 3 - Return IPS1_ONO2_ON residency 1292 * RETURN: Total inactive residency in microseconds - upper 32 bits 1293 */ 1294 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1295 1296 /** 1297 * DESC: Gets IPS residency in microseconds 1298 * ARGS: 0 - Return IPS1 residency 1299 * 1 - Return IPS2 residency 1300 * 2 - Return IPS1_RCG residency 1301 * 3 - Return IPS1_ONO2_ON residency 1302 * RETURN: Total residency in microseconds - upper 32 bits 1303 */ 1304 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1305 /** 1306 * DESC: Setup debug configs. 1307 */ 1308 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1309 /** 1310 * DESC: Initiates IPS wake sequence. 1311 */ 1312 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1313 }; 1314 1315 /** 1316 * INBOX0 generic command definition 1317 */ 1318 union dmub_inbox0_cmd_common { 1319 struct { 1320 uint32_t command_code: 8; /**< INBOX0 command code */ 1321 uint32_t param: 24; /**< 24-bit parameter */ 1322 } bits; 1323 uint32_t all; 1324 }; 1325 1326 /** 1327 * INBOX0 hw_lock command definition 1328 */ 1329 union dmub_inbox0_cmd_lock_hw { 1330 struct { 1331 uint32_t command_code: 8; 1332 1333 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1334 uint32_t hw_lock_client: 2; 1335 1336 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1337 uint32_t otg_inst: 3; 1338 uint32_t opp_inst: 3; 1339 uint32_t dig_inst: 3; 1340 1341 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1342 uint32_t lock_pipe: 1; 1343 uint32_t lock_cursor: 1; 1344 uint32_t lock_dig: 1; 1345 uint32_t triple_buffer_lock: 1; 1346 1347 uint32_t lock: 1; /**< Lock */ 1348 uint32_t should_release: 1; /**< Release */ 1349 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1350 } bits; 1351 uint32_t all; 1352 }; 1353 1354 union dmub_inbox0_data_register { 1355 union dmub_inbox0_cmd_common inbox0_cmd_common; 1356 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1357 }; 1358 1359 enum dmub_inbox0_command { 1360 /** 1361 * DESC: Invalid command, ignored. 1362 */ 1363 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1364 /** 1365 * DESC: Notification to acquire/release HW lock 1366 * ARGS: 1367 */ 1368 DMUB_INBOX0_CMD__HW_LOCK = 1, 1369 }; 1370 //============================================================================== 1371 //</DMUB_GPINT>================================================================= 1372 //============================================================================== 1373 //< DMUB_CMD>=================================================================== 1374 //============================================================================== 1375 1376 /** 1377 * Size in bytes of each DMUB command. 1378 */ 1379 #define DMUB_RB_CMD_SIZE 64 1380 1381 /** 1382 * Maximum number of items in the DMUB ringbuffer. 1383 */ 1384 #define DMUB_RB_MAX_ENTRY 128 1385 1386 /** 1387 * Ringbuffer size in bytes. 1388 */ 1389 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1390 1391 /** 1392 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1393 */ 1394 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1395 1396 /** 1397 * Ringbuffer size in bytes. 1398 */ 1399 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1400 1401 /** 1402 * REG_SET mask for reg offload. 1403 */ 1404 #define REG_SET_MASK 0xFFFF 1405 1406 /* 1407 * enum dmub_cmd_type - DMUB inbox command. 1408 * 1409 * Command IDs should be treated as stable ABI. 1410 * Do not reuse or modify IDs. 1411 */ 1412 enum dmub_cmd_type { 1413 /** 1414 * Invalid command. 1415 */ 1416 DMUB_CMD__NULL = 0, 1417 /** 1418 * Read modify write register sequence offload. 1419 */ 1420 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1421 /** 1422 * Field update register sequence offload. 1423 */ 1424 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1425 /** 1426 * Burst write sequence offload. 1427 */ 1428 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1429 /** 1430 * Reg wait sequence offload. 1431 */ 1432 DMUB_CMD__REG_REG_WAIT = 4, 1433 /** 1434 * Workaround to avoid HUBP underflow during NV12 playback. 1435 */ 1436 DMUB_CMD__PLAT_54186_WA = 5, 1437 /** 1438 * Command type used to query FW feature caps. 1439 */ 1440 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1441 /** 1442 * Command type used to get visual confirm color. 1443 */ 1444 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1445 /** 1446 * Command type used for all PSR commands. 1447 */ 1448 DMUB_CMD__PSR = 64, 1449 /** 1450 * Command type used for all MALL commands. 1451 */ 1452 DMUB_CMD__MALL = 65, 1453 /** 1454 * Command type used for all ABM commands. 1455 */ 1456 DMUB_CMD__ABM = 66, 1457 /** 1458 * Command type used to update dirty rects in FW. 1459 */ 1460 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1461 /** 1462 * Command type used to update cursor info in FW. 1463 */ 1464 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1465 /** 1466 * Command type used for HW locking in FW. 1467 */ 1468 DMUB_CMD__HW_LOCK = 69, 1469 /** 1470 * Command type used to access DP AUX. 1471 */ 1472 DMUB_CMD__DP_AUX_ACCESS = 70, 1473 /** 1474 * Command type used for OUTBOX1 notification enable 1475 */ 1476 DMUB_CMD__OUTBOX1_ENABLE = 71, 1477 1478 /** 1479 * Command type used for all idle optimization commands. 1480 */ 1481 DMUB_CMD__IDLE_OPT = 72, 1482 /** 1483 * Command type used for all clock manager commands. 1484 */ 1485 DMUB_CMD__CLK_MGR = 73, 1486 /** 1487 * Command type used for all panel control commands. 1488 */ 1489 DMUB_CMD__PANEL_CNTL = 74, 1490 1491 /** 1492 * Command type used for all CAB commands. 1493 */ 1494 DMUB_CMD__CAB_FOR_SS = 75, 1495 1496 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1497 1498 /** 1499 * Command type used for interfacing with DPIA. 1500 */ 1501 DMUB_CMD__DPIA = 77, 1502 /** 1503 * Command type used for EDID CEA parsing 1504 */ 1505 DMUB_CMD__EDID_CEA = 79, 1506 /** 1507 * Command type used for getting usbc cable ID 1508 */ 1509 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1510 /** 1511 * Command type used to query HPD state. 1512 */ 1513 DMUB_CMD__QUERY_HPD_STATE = 82, 1514 /** 1515 * Command type used for all VBIOS interface commands. 1516 */ 1517 /** 1518 * Command type used for all REPLAY commands. 1519 */ 1520 DMUB_CMD__REPLAY = 83, 1521 1522 /** 1523 * Command type used for all SECURE_DISPLAY commands. 1524 */ 1525 DMUB_CMD__SECURE_DISPLAY = 85, 1526 1527 /** 1528 * Command type used to set DPIA HPD interrupt state 1529 */ 1530 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1531 1532 /** 1533 * Command type used for all PSP commands. 1534 */ 1535 DMUB_CMD__PSP = 88, 1536 1537 /** 1538 * Command type used for all Fused IO commands. 1539 */ 1540 DMUB_CMD__FUSED_IO = 89, 1541 1542 /** 1543 * Command type used for all LSDMA commands. 1544 */ 1545 DMUB_CMD__LSDMA = 90, 1546 1547 DMUB_CMD__VBIOS = 128, 1548 }; 1549 1550 /** 1551 * enum dmub_out_cmd_type - DMUB outbox commands. 1552 */ 1553 enum dmub_out_cmd_type { 1554 /** 1555 * Invalid outbox command, ignored. 1556 */ 1557 DMUB_OUT_CMD__NULL = 0, 1558 /** 1559 * Command type used for DP AUX Reply data notification 1560 */ 1561 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1562 /** 1563 * Command type used for DP HPD event notification 1564 */ 1565 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1566 /** 1567 * Command type used for SET_CONFIG Reply notification 1568 */ 1569 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1570 /** 1571 * Command type used for USB4 DPIA notification 1572 */ 1573 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1574 /** 1575 * Command type used for HPD redetect notification 1576 */ 1577 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1578 /** 1579 * Command type used for Fused IO notification 1580 */ 1581 DMUB_OUT_CMD__FUSED_IO = 7, 1582 }; 1583 1584 /* DMUB_CMD__DPIA command sub-types. */ 1585 enum dmub_cmd_dpia_type { 1586 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1587 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1588 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1589 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1590 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1591 }; 1592 1593 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1594 enum dmub_cmd_dpia_notification_type { 1595 DPIA_NOTIFY__BW_ALLOCATION = 0, 1596 }; 1597 1598 #pragma pack(push, 1) 1599 1600 /** 1601 * struct dmub_cmd_header - Common command header fields. 1602 */ 1603 struct dmub_cmd_header { 1604 unsigned int type : 8; /**< command type */ 1605 unsigned int sub_type : 8; /**< command sub type */ 1606 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1607 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1608 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1609 unsigned int reserved0 : 5; /**< reserved bits */ 1610 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1611 unsigned int reserved1 : 2; /**< reserved bits */ 1612 }; 1613 1614 /* 1615 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1616 * 1617 * 60 payload bytes can hold up to 5 sets of read modify writes, 1618 * each take 3 dwords. 1619 * 1620 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1621 * 1622 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1623 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1624 */ 1625 struct dmub_cmd_read_modify_write_sequence { 1626 uint32_t addr; /**< register address */ 1627 uint32_t modify_mask; /**< modify mask */ 1628 uint32_t modify_value; /**< modify value */ 1629 }; 1630 1631 /** 1632 * Maximum number of ops in read modify write sequence. 1633 */ 1634 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1635 1636 /** 1637 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1638 */ 1639 struct dmub_rb_cmd_read_modify_write { 1640 struct dmub_cmd_header header; /**< command header */ 1641 /** 1642 * Read modify write sequence. 1643 */ 1644 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1645 }; 1646 1647 /* 1648 * Update a register with specified masks and values sequeunce 1649 * 1650 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1651 * 1652 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1653 * 1654 * 1655 * USE CASE: 1656 * 1. auto-increment register where additional read would update pointer and produce wrong result 1657 * 2. toggle a bit without read in the middle 1658 */ 1659 1660 struct dmub_cmd_reg_field_update_sequence { 1661 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1662 uint32_t modify_value; /**< value to update with */ 1663 }; 1664 1665 /** 1666 * Maximum number of ops in field update sequence. 1667 */ 1668 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1669 1670 /** 1671 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1672 */ 1673 struct dmub_rb_cmd_reg_field_update_sequence { 1674 struct dmub_cmd_header header; /**< command header */ 1675 uint32_t addr; /**< register address */ 1676 /** 1677 * Field update sequence. 1678 */ 1679 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1680 }; 1681 1682 1683 /** 1684 * Maximum number of burst write values. 1685 */ 1686 #define DMUB_BURST_WRITE_VALUES__MAX 14 1687 1688 /* 1689 * struct dmub_rb_cmd_burst_write - Burst write 1690 * 1691 * support use case such as writing out LUTs. 1692 * 1693 * 60 payload bytes can hold up to 14 values to write to given address 1694 * 1695 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1696 */ 1697 struct dmub_rb_cmd_burst_write { 1698 struct dmub_cmd_header header; /**< command header */ 1699 uint32_t addr; /**< register start address */ 1700 /** 1701 * Burst write register values. 1702 */ 1703 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1704 }; 1705 1706 /** 1707 * struct dmub_rb_cmd_common - Common command header 1708 */ 1709 struct dmub_rb_cmd_common { 1710 struct dmub_cmd_header header; /**< command header */ 1711 /** 1712 * Padding to RB_CMD_SIZE 1713 */ 1714 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1715 }; 1716 1717 /** 1718 * struct dmub_cmd_reg_wait_data - Register wait data 1719 */ 1720 struct dmub_cmd_reg_wait_data { 1721 uint32_t addr; /**< Register address */ 1722 uint32_t mask; /**< Mask for register bits */ 1723 uint32_t condition_field_value; /**< Value to wait for */ 1724 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1725 }; 1726 1727 /** 1728 * struct dmub_rb_cmd_reg_wait - Register wait command 1729 */ 1730 struct dmub_rb_cmd_reg_wait { 1731 struct dmub_cmd_header header; /**< Command header */ 1732 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1733 }; 1734 1735 /** 1736 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1737 * 1738 * Reprograms surface parameters to avoid underflow. 1739 */ 1740 struct dmub_cmd_PLAT_54186_wa { 1741 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1742 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1743 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1744 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1745 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1746 struct { 1747 uint32_t hubp_inst : 4; /**< HUBP instance */ 1748 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1749 uint32_t immediate :1; /**< Immediate flip */ 1750 uint32_t vmid : 4; /**< VMID */ 1751 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1752 uint32_t reserved : 21; /**< Reserved */ 1753 } flip_params; /**< Pageflip parameters */ 1754 uint32_t reserved[9]; /**< Reserved bits */ 1755 }; 1756 1757 /** 1758 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1759 */ 1760 struct dmub_rb_cmd_PLAT_54186_wa { 1761 struct dmub_cmd_header header; /**< Command header */ 1762 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1763 }; 1764 1765 /** 1766 * enum dmub_cmd_mall_type - MALL commands 1767 */ 1768 enum dmub_cmd_mall_type { 1769 /** 1770 * Allows display refresh from MALL. 1771 */ 1772 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1773 /** 1774 * Disallows display refresh from MALL. 1775 */ 1776 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1777 /** 1778 * Cursor copy for MALL. 1779 */ 1780 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1781 /** 1782 * Controls DF requests. 1783 */ 1784 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1785 }; 1786 1787 /** 1788 * struct dmub_rb_cmd_mall - MALL command data. 1789 */ 1790 struct dmub_rb_cmd_mall { 1791 struct dmub_cmd_header header; /**< Common command header */ 1792 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1793 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1794 uint32_t tmr_delay; /**< Timer delay */ 1795 uint32_t tmr_scale; /**< Timer scale */ 1796 uint16_t cursor_width; /**< Cursor width in pixels */ 1797 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1798 uint16_t cursor_height; /**< Cursor height in pixels */ 1799 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1800 uint8_t debug_bits; /**< Debug bits */ 1801 1802 uint8_t reserved1; /**< Reserved bits */ 1803 uint8_t reserved2; /**< Reserved bits */ 1804 }; 1805 1806 /** 1807 * enum dmub_cmd_cab_type - CAB command data. 1808 */ 1809 enum dmub_cmd_cab_type { 1810 /** 1811 * No idle optimizations (i.e. no CAB) 1812 */ 1813 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1814 /** 1815 * No DCN requests for memory 1816 */ 1817 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1818 /** 1819 * Fit surfaces in CAB (i.e. CAB enable) 1820 */ 1821 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1822 /** 1823 * Do not fit surfaces in CAB (i.e. no CAB) 1824 */ 1825 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1826 }; 1827 1828 /** 1829 * struct dmub_rb_cmd_cab - CAB command data. 1830 */ 1831 struct dmub_rb_cmd_cab_for_ss { 1832 struct dmub_cmd_header header; 1833 uint8_t cab_alloc_ways; /* total number of ways */ 1834 uint8_t debug_bits; /* debug bits */ 1835 }; 1836 1837 /** 1838 * Enum for indicating which MCLK switch mode per pipe 1839 */ 1840 enum mclk_switch_mode { 1841 NONE = 0, 1842 FPO = 1, 1843 SUBVP = 2, 1844 VBLANK = 3, 1845 }; 1846 1847 /* Per pipe struct which stores the MCLK switch mode 1848 * data to be sent to DMUB. 1849 * Named "v2" for now -- once FPO and SUBVP are fully merged 1850 * the type name can be updated 1851 */ 1852 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1853 union { 1854 struct { 1855 uint32_t pix_clk_100hz; 1856 uint16_t main_vblank_start; 1857 uint16_t main_vblank_end; 1858 uint16_t mall_region_lines; 1859 uint16_t prefetch_lines; 1860 uint16_t prefetch_to_mall_start_lines; 1861 uint16_t processing_delay_lines; 1862 uint16_t htotal; // required to calculate line time for multi-display cases 1863 uint16_t vtotal; 1864 uint8_t main_pipe_index; 1865 uint8_t phantom_pipe_index; 1866 /* Since the microschedule is calculated in terms of OTG lines, 1867 * include any scaling factors to make sure when we get accurate 1868 * conversion when programming MALL_START_LINE (which is in terms 1869 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1870 * is 1/2 (numerator = 1, denominator = 2). 1871 */ 1872 uint8_t scale_factor_numerator; 1873 uint8_t scale_factor_denominator; 1874 uint8_t is_drr; 1875 uint8_t main_split_pipe_index; 1876 uint8_t phantom_split_pipe_index; 1877 } subvp_data; 1878 1879 struct { 1880 uint32_t pix_clk_100hz; 1881 uint16_t vblank_start; 1882 uint16_t vblank_end; 1883 uint16_t vstartup_start; 1884 uint16_t vtotal; 1885 uint16_t htotal; 1886 uint8_t vblank_pipe_index; 1887 uint8_t padding[1]; 1888 struct { 1889 uint8_t drr_in_use; 1890 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1891 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1892 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1893 uint8_t use_ramping; // Use ramping or not 1894 uint8_t drr_vblank_start_margin; 1895 } drr_info; // DRR considered as part of SubVP + VBLANK case 1896 } vblank_data; 1897 } pipe_config; 1898 1899 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1900 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1901 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1902 */ 1903 uint8_t mode; // enum mclk_switch_mode 1904 }; 1905 1906 /** 1907 * Config data for Sub-VP and FPO 1908 * Named "v2" for now -- once FPO and SUBVP are fully merged 1909 * the type name can be updated 1910 */ 1911 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1912 uint16_t watermark_a_cache; 1913 uint8_t vertical_int_margin_us; 1914 uint8_t pstate_allow_width_us; 1915 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1916 }; 1917 1918 /** 1919 * DMUB rb command definition for Sub-VP and FPO 1920 * Named "v2" for now -- once FPO and SUBVP are fully merged 1921 * the type name can be updated 1922 */ 1923 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1924 struct dmub_cmd_header header; 1925 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1926 }; 1927 1928 struct dmub_flip_addr_info { 1929 uint32_t surf_addr_lo; 1930 uint32_t surf_addr_c_lo; 1931 uint32_t meta_addr_lo; 1932 uint32_t meta_addr_c_lo; 1933 uint16_t surf_addr_hi; 1934 uint16_t surf_addr_c_hi; 1935 uint16_t meta_addr_hi; 1936 uint16_t meta_addr_c_hi; 1937 }; 1938 1939 struct dmub_fams2_flip_info { 1940 union { 1941 struct { 1942 uint8_t is_immediate: 1; 1943 } bits; 1944 uint8_t all; 1945 } config; 1946 uint8_t otg_inst; 1947 uint8_t pipe_mask; 1948 uint8_t pad; 1949 struct dmub_flip_addr_info addr_info; 1950 }; 1951 1952 struct dmub_rb_cmd_fams2_flip { 1953 struct dmub_cmd_header header; 1954 struct dmub_fams2_flip_info flip_info; 1955 }; 1956 1957 struct dmub_cmd_lsdma_data { 1958 union { 1959 struct lsdma_init_data { 1960 union dmub_addr gpu_addr_base; 1961 uint32_t ring_size; 1962 } init_data; 1963 struct lsdma_tiled_copy_data { 1964 uint32_t src_addr_lo; 1965 uint32_t src_addr_hi; 1966 uint32_t dst_addr_lo; 1967 uint32_t dst_addr_hi; 1968 1969 uint32_t src_x : 16; 1970 uint32_t src_y : 16; 1971 1972 uint32_t src_width : 16; 1973 uint32_t src_height : 16; 1974 1975 uint32_t dst_x : 16; 1976 uint32_t dst_y : 16; 1977 1978 uint32_t dst_width : 16; 1979 uint32_t dst_height : 16; 1980 1981 uint32_t rect_x : 16; 1982 uint32_t rect_y : 16; 1983 1984 uint32_t src_swizzle_mode : 5; 1985 uint32_t src_mip_max : 5; 1986 uint32_t src_mip_id : 5; 1987 uint32_t dst_mip_max : 5; 1988 uint32_t dst_swizzle_mode : 5; 1989 uint32_t dst_mip_id : 5; 1990 uint32_t tmz : 1; 1991 uint32_t dcc : 1; 1992 1993 uint32_t data_format : 6; 1994 uint32_t padding1 : 4; 1995 uint32_t dst_element_size : 3; 1996 uint32_t num_type : 3; 1997 uint32_t src_element_size : 3; 1998 uint32_t write_compress : 2; 1999 uint32_t cache_policy_dst : 2; 2000 uint32_t cache_policy_src : 2; 2001 uint32_t read_compress : 2; 2002 uint32_t src_dim : 2; 2003 uint32_t dst_dim : 2; 2004 uint32_t max_uncom : 1; 2005 2006 uint32_t max_com : 2; 2007 uint32_t padding : 30; 2008 } tiled_copy_data; 2009 struct lsdma_linear_copy_data { 2010 uint32_t count : 30; 2011 uint32_t cache_policy_dst : 2; 2012 2013 uint32_t tmz : 1; 2014 uint32_t cache_policy_src : 2; 2015 uint32_t padding : 29; 2016 2017 uint32_t src_lo; 2018 uint32_t src_hi; 2019 uint32_t dst_lo; 2020 uint32_t dst_hi; 2021 } linear_copy_data; 2022 struct lsdma_reg_write_data { 2023 uint32_t reg_addr; 2024 uint32_t reg_data; 2025 } reg_write_data; 2026 struct lsdma_pio_copy_data { 2027 union { 2028 struct { 2029 uint32_t byte_count : 26; 2030 uint32_t src_loc : 1; 2031 uint32_t dst_loc : 1; 2032 uint32_t src_addr_inc : 1; 2033 uint32_t dst_addr_inc : 1; 2034 uint32_t overlap_disable : 1; 2035 uint32_t constant_fill : 1; 2036 } fields; 2037 uint32_t raw; 2038 } packet; 2039 uint32_t src_lo; 2040 uint32_t src_hi; 2041 uint32_t dst_lo; 2042 uint32_t dst_hi; 2043 } pio_copy_data; 2044 struct lsdma_pio_constfill_data { 2045 union { 2046 struct { 2047 uint32_t byte_count : 26; 2048 uint32_t src_loc : 1; 2049 uint32_t dst_loc : 1; 2050 uint32_t src_addr_inc : 1; 2051 uint32_t dst_addr_inc : 1; 2052 uint32_t overlap_disable : 1; 2053 uint32_t constant_fill : 1; 2054 } fields; 2055 uint32_t raw; 2056 } packet; 2057 uint32_t dst_lo; 2058 uint32_t dst_hi; 2059 uint32_t data; 2060 } pio_constfill_data; 2061 2062 uint32_t all[14]; 2063 } u; 2064 2065 }; 2066 2067 struct dmub_rb_cmd_lsdma { 2068 struct dmub_cmd_header header; 2069 struct dmub_cmd_lsdma_data lsdma_data; 2070 }; 2071 2072 struct dmub_optc_state_v2 { 2073 uint32_t v_total_min; 2074 uint32_t v_total_max; 2075 uint32_t v_total_mid; 2076 uint32_t v_total_mid_frame_num; 2077 uint8_t program_manual_trigger; 2078 uint8_t tg_inst; 2079 uint8_t pad[2]; 2080 }; 2081 2082 struct dmub_optc_position { 2083 uint32_t vpos; 2084 uint32_t hpos; 2085 uint32_t frame; 2086 }; 2087 2088 struct dmub_rb_cmd_fams2_drr_update { 2089 struct dmub_cmd_header header; 2090 struct dmub_optc_state_v2 dmub_optc_state_req; 2091 }; 2092 2093 /* HW and FW global configuration data for FAMS2 */ 2094 /* FAMS2 types and structs */ 2095 enum fams2_stream_type { 2096 FAMS2_STREAM_TYPE_NONE = 0, 2097 FAMS2_STREAM_TYPE_VBLANK = 1, 2098 FAMS2_STREAM_TYPE_VACTIVE = 2, 2099 FAMS2_STREAM_TYPE_DRR = 3, 2100 FAMS2_STREAM_TYPE_SUBVP = 4, 2101 }; 2102 2103 /* static stream state */ 2104 struct dmub_fams2_legacy_stream_static_state { 2105 uint8_t vactive_det_fill_delay_otg_vlines; 2106 uint8_t programming_delay_otg_vlines; 2107 }; //v0 2108 2109 struct dmub_fams2_subvp_stream_static_state { 2110 uint16_t vratio_numerator; 2111 uint16_t vratio_denominator; 2112 uint16_t phantom_vtotal; 2113 uint16_t phantom_vactive; 2114 union { 2115 struct { 2116 uint8_t is_multi_planar : 1; 2117 uint8_t is_yuv420 : 1; 2118 } bits; 2119 uint8_t all; 2120 } config; 2121 uint8_t programming_delay_otg_vlines; 2122 uint8_t prefetch_to_mall_otg_vlines; 2123 uint8_t phantom_otg_inst; 2124 uint8_t phantom_pipe_mask; 2125 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2126 }; //v0 2127 2128 struct dmub_fams2_drr_stream_static_state { 2129 uint16_t nom_stretched_vtotal; 2130 uint8_t programming_delay_otg_vlines; 2131 uint8_t only_stretch_if_required; 2132 uint8_t pad[2]; 2133 }; //v0 2134 2135 struct dmub_fams2_cmd_legacy_stream_static_state { 2136 uint16_t vactive_det_fill_delay_otg_vlines; 2137 uint16_t programming_delay_otg_vlines; 2138 }; //v1 2139 2140 struct dmub_fams2_cmd_subvp_stream_static_state { 2141 uint16_t vratio_numerator; 2142 uint16_t vratio_denominator; 2143 uint16_t phantom_vtotal; 2144 uint16_t phantom_vactive; 2145 uint16_t programming_delay_otg_vlines; 2146 uint16_t prefetch_to_mall_otg_vlines; 2147 union { 2148 struct { 2149 uint8_t is_multi_planar : 1; 2150 uint8_t is_yuv420 : 1; 2151 } bits; 2152 uint8_t all; 2153 } config; 2154 uint8_t phantom_otg_inst; 2155 uint8_t phantom_pipe_mask; 2156 uint8_t pad0; 2157 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2158 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2159 }; //v1 2160 2161 struct dmub_fams2_cmd_drr_stream_static_state { 2162 uint16_t nom_stretched_vtotal; 2163 uint16_t programming_delay_otg_vlines; 2164 uint8_t only_stretch_if_required; 2165 uint8_t pad[3]; 2166 }; //v1 2167 2168 union dmub_fams2_stream_static_sub_state { 2169 struct dmub_fams2_legacy_stream_static_state legacy; 2170 struct dmub_fams2_subvp_stream_static_state subvp; 2171 struct dmub_fams2_drr_stream_static_state drr; 2172 }; //v0 2173 2174 union dmub_fams2_cmd_stream_static_sub_state { 2175 COMMON_STREAM_STATIC_SUB_STATE 2176 }; //v1 2177 2178 union dmub_fams2_stream_static_sub_state_v2 { 2179 COMMON_STREAM_STATIC_SUB_STATE 2180 }; //v2 2181 2182 struct dmub_fams2_stream_static_state { 2183 enum fams2_stream_type type; 2184 uint32_t otg_vline_time_ns; 2185 uint32_t otg_vline_time_ticks; 2186 uint16_t htotal; 2187 uint16_t vtotal; // nominal vtotal 2188 uint16_t vblank_start; 2189 uint16_t vblank_end; 2190 uint16_t max_vtotal; 2191 uint16_t allow_start_otg_vline; 2192 uint16_t allow_end_otg_vline; 2193 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2194 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2195 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2196 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2197 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2198 union { 2199 struct { 2200 uint8_t is_drr: 1; // stream is DRR enabled 2201 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2202 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2203 } bits; 2204 uint8_t all; 2205 } config; 2206 uint8_t otg_inst; 2207 uint8_t pipe_mask; // pipe mask for the whole config 2208 uint8_t num_planes; 2209 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2210 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2211 union dmub_fams2_stream_static_sub_state sub_state; 2212 }; //v0 2213 2214 struct dmub_fams2_cmd_stream_static_base_state { 2215 enum fams2_stream_type type; 2216 uint32_t otg_vline_time_ns; 2217 uint32_t otg_vline_time_ticks; 2218 uint16_t htotal; 2219 uint16_t vtotal; // nominal vtotal 2220 uint16_t vblank_start; 2221 uint16_t vblank_end; 2222 uint16_t max_vtotal; 2223 uint16_t allow_start_otg_vline; 2224 uint16_t allow_end_otg_vline; 2225 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2226 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2227 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2228 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2229 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2230 union { 2231 struct { 2232 uint8_t is_drr : 1; // stream is DRR enabled 2233 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2234 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2235 } bits; 2236 uint8_t all; 2237 } config; 2238 uint8_t otg_inst; 2239 uint8_t pipe_mask; // pipe mask for the whole config 2240 uint8_t num_planes; 2241 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2242 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2243 }; //v1 2244 2245 struct dmub_fams2_stream_static_state_v1 { 2246 struct dmub_fams2_cmd_stream_static_base_state base; 2247 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2248 }; //v1 2249 2250 /** 2251 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2252 * p-state request to allow latency 2253 */ 2254 enum dmub_fams2_allow_delay_check_mode { 2255 /* No check for request to allow delay */ 2256 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2257 /* Check for request to allow delay */ 2258 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2259 /* Check for prepare to allow delay */ 2260 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2261 }; 2262 2263 union dmub_fams2_global_feature_config { 2264 struct { 2265 uint32_t enable: 1; 2266 uint32_t enable_ppt_check: 1; 2267 uint32_t enable_stall_recovery: 1; 2268 uint32_t enable_debug: 1; 2269 uint32_t enable_offload_flip: 1; 2270 uint32_t enable_visual_confirm: 1; 2271 uint32_t allow_delay_check_mode: 2; 2272 uint32_t reserved: 24; 2273 } bits; 2274 uint32_t all; 2275 }; 2276 2277 struct dmub_cmd_fams2_global_config { 2278 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2279 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2280 uint32_t num_streams; 2281 union dmub_fams2_global_feature_config features; 2282 uint32_t recovery_timeout_us; 2283 uint32_t hwfq_flip_programming_delay_us; 2284 }; 2285 2286 union dmub_cmd_fams2_config { 2287 struct dmub_cmd_fams2_global_config global; 2288 struct dmub_fams2_stream_static_state stream; //v0 2289 union { 2290 struct dmub_fams2_cmd_stream_static_base_state base; 2291 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2292 } stream_v1; //v1 2293 }; 2294 2295 struct dmub_fams2_config_v2 { 2296 struct dmub_cmd_fams2_global_config global; 2297 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2298 }; 2299 2300 /** 2301 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2302 */ 2303 struct dmub_rb_cmd_fams2 { 2304 struct dmub_cmd_header header; 2305 union dmub_cmd_fams2_config config; 2306 }; 2307 2308 /** 2309 * Indirect buffer descriptor 2310 */ 2311 struct dmub_ib_data { 2312 union dmub_addr src; // location of indirect buffer in memory 2313 uint16_t size; // indirect buffer size in bytes 2314 }; 2315 2316 /** 2317 * DMUB rb command definition for commands passed over indirect buffer 2318 */ 2319 struct dmub_rb_cmd_ib { 2320 struct dmub_cmd_header header; 2321 struct dmub_ib_data ib_data; 2322 }; 2323 2324 /** 2325 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2326 */ 2327 enum dmub_cmd_idle_opt_type { 2328 /** 2329 * DCN hardware restore. 2330 */ 2331 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2332 2333 /** 2334 * DCN hardware save. 2335 */ 2336 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2337 2338 /** 2339 * DCN hardware notify idle. 2340 */ 2341 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2342 2343 /** 2344 * DCN hardware notify power state. 2345 */ 2346 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2347 2348 /** 2349 * DCN notify to release HW. 2350 */ 2351 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2352 }; 2353 2354 /** 2355 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2356 */ 2357 struct dmub_rb_cmd_idle_opt_dcn_restore { 2358 struct dmub_cmd_header header; /**< header */ 2359 }; 2360 2361 /** 2362 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2363 */ 2364 struct dmub_dcn_notify_idle_cntl_data { 2365 uint8_t driver_idle; 2366 uint8_t skip_otg_disable; 2367 uint8_t reserved[58]; 2368 }; 2369 2370 /** 2371 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2372 */ 2373 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2374 struct dmub_cmd_header header; /**< header */ 2375 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2376 }; 2377 2378 /** 2379 * enum dmub_idle_opt_dc_power_state - DC power states. 2380 */ 2381 enum dmub_idle_opt_dc_power_state { 2382 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2383 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2384 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2385 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2386 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2387 }; 2388 2389 /** 2390 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2391 */ 2392 struct dmub_idle_opt_set_dc_power_state_data { 2393 uint8_t power_state; /**< power state */ 2394 uint8_t pad[3]; /**< padding */ 2395 }; 2396 2397 /** 2398 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2399 */ 2400 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2401 struct dmub_cmd_header header; /**< header */ 2402 struct dmub_idle_opt_set_dc_power_state_data data; 2403 }; 2404 2405 /** 2406 * struct dmub_clocks - Clock update notification. 2407 */ 2408 struct dmub_clocks { 2409 uint32_t dispclk_khz; /**< dispclk kHz */ 2410 uint32_t dppclk_khz; /**< dppclk kHz */ 2411 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2412 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2413 }; 2414 2415 /** 2416 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2417 */ 2418 enum dmub_cmd_clk_mgr_type { 2419 /** 2420 * Notify DMCUB of clock update. 2421 */ 2422 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2423 }; 2424 2425 /** 2426 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2427 */ 2428 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2429 struct dmub_cmd_header header; /**< header */ 2430 struct dmub_clocks clocks; /**< clock data */ 2431 }; 2432 2433 /** 2434 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2435 */ 2436 struct dmub_cmd_digx_encoder_control_data { 2437 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2438 }; 2439 2440 /** 2441 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2442 */ 2443 struct dmub_rb_cmd_digx_encoder_control { 2444 struct dmub_cmd_header header; /**< header */ 2445 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2446 }; 2447 2448 /** 2449 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2450 */ 2451 struct dmub_cmd_set_pixel_clock_data { 2452 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2453 }; 2454 2455 /** 2456 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2457 */ 2458 struct dmub_rb_cmd_set_pixel_clock { 2459 struct dmub_cmd_header header; /**< header */ 2460 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2461 }; 2462 2463 /** 2464 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2465 */ 2466 struct dmub_cmd_enable_disp_power_gating_data { 2467 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2468 }; 2469 2470 /** 2471 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2472 */ 2473 struct dmub_rb_cmd_enable_disp_power_gating { 2474 struct dmub_cmd_header header; /**< header */ 2475 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2476 }; 2477 2478 /** 2479 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2480 */ 2481 struct dmub_dig_transmitter_control_data_v1_7 { 2482 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2483 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2484 union { 2485 uint8_t digmode; /**< enum atom_encode_mode_def */ 2486 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2487 } mode_laneset; 2488 uint8_t lanenum; /**< Number of lanes */ 2489 union { 2490 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2491 } symclk_units; 2492 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2493 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2494 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2495 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2496 uint8_t reserved1; /**< For future use */ 2497 uint8_t skip_phy_ssc_reduction; 2498 uint8_t reserved2[2]; /**< For future use */ 2499 uint32_t reserved3[11]; /**< For future use */ 2500 }; 2501 2502 /** 2503 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2504 */ 2505 union dmub_cmd_dig1_transmitter_control_data { 2506 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2507 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2508 }; 2509 2510 /** 2511 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2512 */ 2513 struct dmub_rb_cmd_dig1_transmitter_control { 2514 struct dmub_cmd_header header; /**< header */ 2515 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2516 }; 2517 2518 /** 2519 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2520 */ 2521 struct dmub_rb_cmd_domain_control_data { 2522 uint8_t inst : 6; /**< DOMAIN instance to control */ 2523 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2524 uint8_t reserved[3]; /**< Reserved for future use */ 2525 }; 2526 2527 /** 2528 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2529 */ 2530 struct dmub_rb_cmd_domain_control { 2531 struct dmub_cmd_header header; /**< header */ 2532 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2533 }; 2534 2535 /** 2536 * DPIA tunnel command parameters. 2537 */ 2538 struct dmub_cmd_dig_dpia_control_data { 2539 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2540 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2541 union { 2542 uint8_t digmode; /** enum atom_encode_mode_def */ 2543 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2544 } mode_laneset; 2545 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2546 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2547 uint8_t hpdsel; /** =0: HPD is not assigned */ 2548 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2549 uint8_t dpia_id; /** Index of DPIA */ 2550 uint8_t fec_rdy : 1; 2551 uint8_t reserved : 7; 2552 uint32_t reserved1; 2553 }; 2554 2555 /** 2556 * DMUB command for DPIA tunnel control. 2557 */ 2558 struct dmub_rb_cmd_dig1_dpia_control { 2559 struct dmub_cmd_header header; 2560 struct dmub_cmd_dig_dpia_control_data dpia_control; 2561 }; 2562 2563 /** 2564 * SET_CONFIG Command Payload (deprecated) 2565 */ 2566 struct set_config_cmd_payload { 2567 uint8_t msg_type; /* set config message type */ 2568 uint8_t msg_data; /* set config message data */ 2569 }; 2570 2571 /** 2572 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2573 */ 2574 struct dmub_cmd_set_config_control_data { 2575 struct set_config_cmd_payload cmd_pkt; 2576 uint8_t instance; /* DPIA instance */ 2577 uint8_t immed_status; /* Immediate status returned in case of error */ 2578 }; 2579 2580 /** 2581 * SET_CONFIG Request Command Payload 2582 */ 2583 struct set_config_request_cmd_payload { 2584 uint8_t instance; /* DPIA instance */ 2585 uint8_t immed_status; /* Immediate status returned in case of error */ 2586 uint8_t msg_type; /* set config message type */ 2587 uint8_t reserved; 2588 uint32_t msg_data; /* set config message data */ 2589 }; 2590 2591 /** 2592 * DMUB command structure for SET_CONFIG command. 2593 */ 2594 struct dmub_rb_cmd_set_config_access { 2595 struct dmub_cmd_header header; /* header */ 2596 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2597 }; 2598 2599 /** 2600 * DMUB command structure for SET_CONFIG request command. 2601 */ 2602 struct dmub_rb_cmd_set_config_request { 2603 struct dmub_cmd_header header; /* header */ 2604 struct set_config_request_cmd_payload payload; /* set config request payload */ 2605 }; 2606 2607 /** 2608 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2609 */ 2610 struct dmub_cmd_mst_alloc_slots_control_data { 2611 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2612 uint8_t instance; /* DPIA instance */ 2613 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2614 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2615 }; 2616 2617 /** 2618 * DMUB command structure for SET_ command. 2619 */ 2620 struct dmub_rb_cmd_set_mst_alloc_slots { 2621 struct dmub_cmd_header header; /* header */ 2622 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2623 }; 2624 2625 /** 2626 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2627 */ 2628 struct dmub_cmd_tps_notification_data { 2629 uint8_t instance; /* DPIA instance */ 2630 uint8_t tps; /* requested training pattern */ 2631 uint8_t reserved1; 2632 uint8_t reserved2; 2633 }; 2634 2635 /** 2636 * DMUB command structure for SET_TPS_NOTIFICATION command. 2637 */ 2638 struct dmub_rb_cmd_set_tps_notification { 2639 struct dmub_cmd_header header; /* header */ 2640 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2641 }; 2642 2643 /** 2644 * DMUB command structure for DPIA HPD int enable control. 2645 */ 2646 struct dmub_rb_cmd_dpia_hpd_int_enable { 2647 struct dmub_cmd_header header; /* header */ 2648 uint32_t enable; /* dpia hpd interrupt enable */ 2649 }; 2650 2651 /** 2652 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2653 */ 2654 struct dmub_rb_cmd_dpphy_init { 2655 struct dmub_cmd_header header; /**< header */ 2656 uint8_t reserved[60]; /**< reserved bits */ 2657 }; 2658 2659 /** 2660 * enum dp_aux_request_action - DP AUX request command listing. 2661 * 2662 * 4 AUX request command bits are shifted to high nibble. 2663 */ 2664 enum dp_aux_request_action { 2665 /** I2C-over-AUX write request */ 2666 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2667 /** I2C-over-AUX read request */ 2668 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2669 /** I2C-over-AUX write status request */ 2670 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2671 /** I2C-over-AUX write request with MOT=1 */ 2672 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2673 /** I2C-over-AUX read request with MOT=1 */ 2674 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2675 /** I2C-over-AUX write status request with MOT=1 */ 2676 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2677 /** Native AUX write request */ 2678 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2679 /** Native AUX read request */ 2680 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2681 }; 2682 2683 /** 2684 * enum aux_return_code_type - DP AUX process return code listing. 2685 */ 2686 enum aux_return_code_type { 2687 /** AUX process succeeded */ 2688 AUX_RET_SUCCESS = 0, 2689 /** AUX process failed with unknown reason */ 2690 AUX_RET_ERROR_UNKNOWN, 2691 /** AUX process completed with invalid reply */ 2692 AUX_RET_ERROR_INVALID_REPLY, 2693 /** AUX process timed out */ 2694 AUX_RET_ERROR_TIMEOUT, 2695 /** HPD was low during AUX process */ 2696 AUX_RET_ERROR_HPD_DISCON, 2697 /** Failed to acquire AUX engine */ 2698 AUX_RET_ERROR_ENGINE_ACQUIRE, 2699 /** AUX request not supported */ 2700 AUX_RET_ERROR_INVALID_OPERATION, 2701 /** AUX process not available */ 2702 AUX_RET_ERROR_PROTOCOL_ERROR, 2703 }; 2704 2705 /** 2706 * enum aux_channel_type - DP AUX channel type listing. 2707 */ 2708 enum aux_channel_type { 2709 /** AUX thru Legacy DP AUX */ 2710 AUX_CHANNEL_LEGACY_DDC, 2711 /** AUX thru DPIA DP tunneling */ 2712 AUX_CHANNEL_DPIA 2713 }; 2714 2715 /** 2716 * struct aux_transaction_parameters - DP AUX request transaction data 2717 */ 2718 struct aux_transaction_parameters { 2719 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2720 uint8_t action; /**< enum dp_aux_request_action */ 2721 uint8_t length; /**< DP AUX request data length */ 2722 uint8_t reserved; /**< For future use */ 2723 uint32_t address; /**< DP AUX address */ 2724 uint8_t data[16]; /**< DP AUX write data */ 2725 }; 2726 2727 /** 2728 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2729 */ 2730 struct dmub_cmd_dp_aux_control_data { 2731 uint8_t instance; /**< AUX instance or DPIA instance */ 2732 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2733 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2734 uint8_t reserved0; /**< For future use */ 2735 uint16_t timeout; /**< timeout time in us */ 2736 uint16_t reserved1; /**< For future use */ 2737 enum aux_channel_type type; /**< enum aux_channel_type */ 2738 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2739 }; 2740 2741 /** 2742 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2743 */ 2744 struct dmub_rb_cmd_dp_aux_access { 2745 /** 2746 * Command header. 2747 */ 2748 struct dmub_cmd_header header; 2749 /** 2750 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2751 */ 2752 struct dmub_cmd_dp_aux_control_data aux_control; 2753 }; 2754 2755 /** 2756 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2757 */ 2758 struct dmub_rb_cmd_outbox1_enable { 2759 /** 2760 * Command header. 2761 */ 2762 struct dmub_cmd_header header; 2763 /** 2764 * enable: 0x0 -> disable outbox1 notification (default value) 2765 * 0x1 -> enable outbox1 notification 2766 */ 2767 uint32_t enable; 2768 }; 2769 2770 /* DP AUX Reply command - OutBox Cmd */ 2771 /** 2772 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2773 */ 2774 struct aux_reply_data { 2775 /** 2776 * Aux cmd 2777 */ 2778 uint8_t command; 2779 /** 2780 * Aux reply data length (max: 16 bytes) 2781 */ 2782 uint8_t length; 2783 /** 2784 * Alignment only 2785 */ 2786 uint8_t pad[2]; 2787 /** 2788 * Aux reply data 2789 */ 2790 uint8_t data[16]; 2791 }; 2792 2793 /** 2794 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2795 */ 2796 struct aux_reply_control_data { 2797 /** 2798 * Reserved for future use 2799 */ 2800 uint32_t handle; 2801 /** 2802 * Aux Instance 2803 */ 2804 uint8_t instance; 2805 /** 2806 * Aux transaction result: definition in enum aux_return_code_type 2807 */ 2808 uint8_t result; 2809 /** 2810 * Alignment only 2811 */ 2812 uint16_t pad; 2813 }; 2814 2815 /** 2816 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2817 */ 2818 struct dmub_rb_cmd_dp_aux_reply { 2819 /** 2820 * Command header. 2821 */ 2822 struct dmub_cmd_header header; 2823 /** 2824 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2825 */ 2826 struct aux_reply_control_data control; 2827 /** 2828 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2829 */ 2830 struct aux_reply_data reply_data; 2831 }; 2832 2833 /* DP HPD Notify command - OutBox Cmd */ 2834 /** 2835 * DP HPD Type 2836 */ 2837 enum dp_hpd_type { 2838 /** 2839 * Normal DP HPD 2840 */ 2841 DP_HPD = 0, 2842 /** 2843 * DP HPD short pulse 2844 */ 2845 DP_IRQ = 1, 2846 /** 2847 * Failure to acquire DP HPD state 2848 */ 2849 DP_NONE_HPD = 2 2850 }; 2851 2852 /** 2853 * DP HPD Status 2854 */ 2855 enum dp_hpd_status { 2856 /** 2857 * DP_HPD status low 2858 */ 2859 DP_HPD_UNPLUG = 0, 2860 /** 2861 * DP_HPD status high 2862 */ 2863 DP_HPD_PLUG 2864 }; 2865 2866 /** 2867 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2868 */ 2869 struct dp_hpd_data { 2870 /** 2871 * DP HPD instance 2872 */ 2873 uint8_t instance; 2874 /** 2875 * HPD type 2876 */ 2877 uint8_t hpd_type; 2878 /** 2879 * HPD status: only for type: DP_HPD to indicate status 2880 */ 2881 uint8_t hpd_status; 2882 /** 2883 * Alignment only 2884 */ 2885 uint8_t pad; 2886 }; 2887 2888 /** 2889 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2890 */ 2891 struct dmub_rb_cmd_dp_hpd_notify { 2892 /** 2893 * Command header. 2894 */ 2895 struct dmub_cmd_header header; 2896 /** 2897 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2898 */ 2899 struct dp_hpd_data hpd_data; 2900 }; 2901 2902 /** 2903 * Definition of a SET_CONFIG reply from DPOA. 2904 */ 2905 enum set_config_status { 2906 SET_CONFIG_PENDING = 0, 2907 SET_CONFIG_ACK_RECEIVED, 2908 SET_CONFIG_RX_TIMEOUT, 2909 SET_CONFIG_UNKNOWN_ERROR, 2910 }; 2911 2912 /** 2913 * Definition of a set_config reply 2914 */ 2915 struct set_config_reply_control_data { 2916 uint8_t instance; /* DPIA Instance */ 2917 uint8_t status; /* Set Config reply */ 2918 uint16_t pad; /* Alignment */ 2919 }; 2920 2921 /** 2922 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 2923 */ 2924 struct dmub_rb_cmd_dp_set_config_reply { 2925 struct dmub_cmd_header header; 2926 struct set_config_reply_control_data set_config_reply_control; 2927 }; 2928 2929 /** 2930 * Definition of a DPIA notification header 2931 */ 2932 struct dpia_notification_header { 2933 uint8_t instance; /**< DPIA Instance */ 2934 uint8_t reserved[3]; 2935 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 2936 }; 2937 2938 /** 2939 * Definition of the common data struct of DPIA notification 2940 */ 2941 struct dpia_notification_common { 2942 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 2943 - sizeof(struct dpia_notification_header)]; 2944 }; 2945 2946 /** 2947 * Definition of a DPIA notification data 2948 */ 2949 struct dpia_bw_allocation_notify_data { 2950 union { 2951 struct { 2952 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 2953 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 2954 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 2955 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 2956 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 2957 uint16_t reserved: 11; /**< Reserved */ 2958 } bits; 2959 2960 uint16_t flags; 2961 }; 2962 2963 uint8_t cm_id; /**< CM ID */ 2964 uint8_t group_id; /**< Group ID */ 2965 uint8_t granularity; /**< BW Allocation Granularity */ 2966 uint8_t estimated_bw; /**< Estimated_BW */ 2967 uint8_t allocated_bw; /**< Allocated_BW */ 2968 uint8_t reserved; 2969 }; 2970 2971 /** 2972 * union dpia_notify_data_type - DPIA Notification in Outbox command 2973 */ 2974 union dpia_notification_data { 2975 /** 2976 * DPIA Notification for common data struct 2977 */ 2978 struct dpia_notification_common common_data; 2979 2980 /** 2981 * DPIA Notification for DP BW Allocation support 2982 */ 2983 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 2984 }; 2985 2986 /** 2987 * Definition of a DPIA notification payload 2988 */ 2989 struct dpia_notification_payload { 2990 struct dpia_notification_header header; 2991 union dpia_notification_data data; /**< DPIA notification payload data */ 2992 }; 2993 2994 /** 2995 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 2996 */ 2997 struct dmub_rb_cmd_dpia_notification { 2998 struct dmub_cmd_header header; /**< DPIA notification header */ 2999 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3000 }; 3001 3002 /** 3003 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3004 */ 3005 struct dmub_cmd_hpd_state_query_data { 3006 uint8_t instance; /**< HPD instance or DPIA instance */ 3007 uint8_t result; /**< For returning HPD state */ 3008 uint16_t pad; /** < Alignment */ 3009 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3010 enum aux_return_code_type status; /**< for returning the status of command */ 3011 }; 3012 3013 /** 3014 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3015 */ 3016 struct dmub_rb_cmd_query_hpd_state { 3017 /** 3018 * Command header. 3019 */ 3020 struct dmub_cmd_header header; 3021 /** 3022 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3023 */ 3024 struct dmub_cmd_hpd_state_query_data data; 3025 }; 3026 3027 /** 3028 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3029 */ 3030 struct dmub_rb_cmd_hpd_sense_notify_data { 3031 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3032 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3033 }; 3034 3035 /** 3036 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3037 */ 3038 struct dmub_rb_cmd_hpd_sense_notify { 3039 struct dmub_cmd_header header; /**< header */ 3040 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3041 }; 3042 3043 /* 3044 * Command IDs should be treated as stable ABI. 3045 * Do not reuse or modify IDs. 3046 */ 3047 3048 /** 3049 * PSR command sub-types. 3050 */ 3051 enum dmub_cmd_psr_type { 3052 /** 3053 * Set PSR version support. 3054 */ 3055 DMUB_CMD__PSR_SET_VERSION = 0, 3056 /** 3057 * Copy driver-calculated parameters to PSR state. 3058 */ 3059 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3060 /** 3061 * Enable PSR. 3062 */ 3063 DMUB_CMD__PSR_ENABLE = 2, 3064 3065 /** 3066 * Disable PSR. 3067 */ 3068 DMUB_CMD__PSR_DISABLE = 3, 3069 3070 /** 3071 * Set PSR level. 3072 * PSR level is a 16-bit value dicated by driver that 3073 * will enable/disable different functionality. 3074 */ 3075 DMUB_CMD__PSR_SET_LEVEL = 4, 3076 3077 /** 3078 * Forces PSR enabled until an explicit PSR disable call. 3079 */ 3080 DMUB_CMD__PSR_FORCE_STATIC = 5, 3081 /** 3082 * Set vtotal in psr active for FreeSync PSR. 3083 */ 3084 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3085 /** 3086 * Set PSR power option 3087 */ 3088 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3089 }; 3090 3091 /** 3092 * Different PSR residency modes. 3093 * Different modes change the definition of PSR residency. 3094 */ 3095 enum psr_residency_mode { 3096 PSR_RESIDENCY_MODE_PHY = 0, 3097 PSR_RESIDENCY_MODE_ALPM, 3098 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3099 /* Do not add below. */ 3100 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3101 }; 3102 3103 enum dmub_cmd_fams_type { 3104 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3105 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3106 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3107 /** 3108 * For SubVP set manual trigger in FW because it 3109 * triggers DRR_UPDATE_PENDING which SubVP relies 3110 * on (for any SubVP cases that use a DRR display) 3111 */ 3112 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3113 DMUB_CMD__FAMS2_CONFIG = 4, 3114 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3115 DMUB_CMD__FAMS2_FLIP = 6, 3116 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3117 }; 3118 3119 /** 3120 * PSR versions. 3121 */ 3122 enum psr_version { 3123 /** 3124 * PSR version 1. 3125 */ 3126 PSR_VERSION_1 = 0, 3127 /** 3128 * Freesync PSR SU. 3129 */ 3130 PSR_VERSION_SU_1 = 1, 3131 /** 3132 * PSR not supported. 3133 */ 3134 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3135 }; 3136 3137 /** 3138 * PHY Link rate for DP. 3139 */ 3140 enum phy_link_rate { 3141 /** 3142 * not supported. 3143 */ 3144 PHY_RATE_UNKNOWN = 0, 3145 /** 3146 * Rate_1 (RBR) - 1.62 Gbps/Lane 3147 */ 3148 PHY_RATE_162 = 1, 3149 /** 3150 * Rate_2 - 2.16 Gbps/Lane 3151 */ 3152 PHY_RATE_216 = 2, 3153 /** 3154 * Rate_3 - 2.43 Gbps/Lane 3155 */ 3156 PHY_RATE_243 = 3, 3157 /** 3158 * Rate_4 (HBR) - 2.70 Gbps/Lane 3159 */ 3160 PHY_RATE_270 = 4, 3161 /** 3162 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3163 */ 3164 PHY_RATE_324 = 5, 3165 /** 3166 * Rate_6 - 4.32 Gbps/Lane 3167 */ 3168 PHY_RATE_432 = 6, 3169 /** 3170 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3171 */ 3172 PHY_RATE_540 = 7, 3173 /** 3174 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3175 */ 3176 PHY_RATE_810 = 8, 3177 /** 3178 * UHBR10 - 10.0 Gbps/Lane 3179 */ 3180 PHY_RATE_1000 = 9, 3181 /** 3182 * UHBR13.5 - 13.5 Gbps/Lane 3183 */ 3184 PHY_RATE_1350 = 10, 3185 /** 3186 * UHBR10 - 20.0 Gbps/Lane 3187 */ 3188 PHY_RATE_2000 = 11, 3189 3190 PHY_RATE_675 = 12, 3191 /** 3192 * Rate 12 - 6.75 Gbps/Lane 3193 */ 3194 }; 3195 3196 /** 3197 * enum dmub_phy_fsm_state - PHY FSM states. 3198 * PHY FSM state to transit to during PSR enable/disable. 3199 */ 3200 enum dmub_phy_fsm_state { 3201 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3202 DMUB_PHY_FSM_RESET, 3203 DMUB_PHY_FSM_RESET_RELEASED, 3204 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3205 DMUB_PHY_FSM_INITIALIZED, 3206 DMUB_PHY_FSM_CALIBRATED, 3207 DMUB_PHY_FSM_CALIBRATED_LP, 3208 DMUB_PHY_FSM_CALIBRATED_PG, 3209 DMUB_PHY_FSM_POWER_DOWN, 3210 DMUB_PHY_FSM_PLL_EN, 3211 DMUB_PHY_FSM_TX_EN, 3212 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3213 DMUB_PHY_FSM_FAST_LP, 3214 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3215 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3216 DMUB_PHY_FSM_P2_PLL_OFF, 3217 DMUB_PHY_FSM_P2_PLL_ON, 3218 }; 3219 3220 /** 3221 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3222 */ 3223 struct dmub_cmd_psr_copy_settings_data { 3224 /** 3225 * Flags that can be set by driver to change some PSR behaviour. 3226 */ 3227 union dmub_psr_debug_flags debug; 3228 /** 3229 * 16-bit value dicated by driver that will enable/disable different functionality. 3230 */ 3231 uint16_t psr_level; 3232 /** 3233 * DPP HW instance. 3234 */ 3235 uint8_t dpp_inst; 3236 /** 3237 * MPCC HW instance. 3238 * Not used in dmub fw, 3239 * dmub fw will get active opp by reading odm registers. 3240 */ 3241 uint8_t mpcc_inst; 3242 /** 3243 * OPP HW instance. 3244 * Not used in dmub fw, 3245 * dmub fw will get active opp by reading odm registers. 3246 */ 3247 uint8_t opp_inst; 3248 /** 3249 * OTG HW instance. 3250 */ 3251 uint8_t otg_inst; 3252 /** 3253 * DIG FE HW instance. 3254 */ 3255 uint8_t digfe_inst; 3256 /** 3257 * DIG BE HW instance. 3258 */ 3259 uint8_t digbe_inst; 3260 /** 3261 * DP PHY HW instance. 3262 */ 3263 uint8_t dpphy_inst; 3264 /** 3265 * AUX HW instance. 3266 */ 3267 uint8_t aux_inst; 3268 /** 3269 * Determines if SMU optimzations are enabled/disabled. 3270 */ 3271 uint8_t smu_optimizations_en; 3272 /** 3273 * Unused. 3274 * TODO: Remove. 3275 */ 3276 uint8_t frame_delay; 3277 /** 3278 * If RFB setup time is greater than the total VBLANK time, 3279 * it is not possible for the sink to capture the video frame 3280 * in the same frame the SDP is sent. In this case, 3281 * the frame capture indication bit should be set and an extra 3282 * static frame should be transmitted to the sink. 3283 */ 3284 uint8_t frame_cap_ind; 3285 /** 3286 * Granularity of Y offset supported by sink. 3287 */ 3288 uint8_t su_y_granularity; 3289 /** 3290 * Indicates whether sink should start capturing 3291 * immediately following active scan line, 3292 * or starting with the 2nd active scan line. 3293 */ 3294 uint8_t line_capture_indication; 3295 /** 3296 * Multi-display optimizations are implemented on certain ASICs. 3297 */ 3298 uint8_t multi_disp_optimizations_en; 3299 /** 3300 * The last possible line SDP may be transmitted without violating 3301 * the RFB setup time or entering the active video frame. 3302 */ 3303 uint16_t init_sdp_deadline; 3304 /** 3305 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3306 */ 3307 uint8_t rate_control_caps ; 3308 /* 3309 * Force PSRSU always doing full frame update 3310 */ 3311 uint8_t force_ffu_mode; 3312 /** 3313 * Length of each horizontal line in us. 3314 */ 3315 uint32_t line_time_in_us; 3316 /** 3317 * FEC enable status in driver 3318 */ 3319 uint8_t fec_enable_status; 3320 /** 3321 * FEC re-enable delay when PSR exit. 3322 * unit is 100us, range form 0~255(0xFF). 3323 */ 3324 uint8_t fec_enable_delay_in100us; 3325 /** 3326 * PSR control version. 3327 */ 3328 uint8_t cmd_version; 3329 /** 3330 * Panel Instance. 3331 * Panel instance to identify which psr_state to use 3332 * Currently the support is only for 0 or 1 3333 */ 3334 uint8_t panel_inst; 3335 /* 3336 * DSC enable status in driver 3337 */ 3338 uint8_t dsc_enable_status; 3339 /* 3340 * Use FSM state for PSR power up/down 3341 */ 3342 uint8_t use_phy_fsm; 3343 /** 3344 * frame delay for frame re-lock 3345 */ 3346 uint8_t relock_delay_frame_cnt; 3347 /** 3348 * esd recovery indicate. 3349 */ 3350 uint8_t esd_recovery; 3351 /** 3352 * DSC Slice height. 3353 */ 3354 uint16_t dsc_slice_height; 3355 /** 3356 * Some panels request main link off before xth vertical line 3357 */ 3358 uint16_t poweroff_before_vertical_line; 3359 /** 3360 * Some panels cannot handle idle pattern during PSR entry. 3361 * To power down phy before disable stream to avoid sending 3362 * idle pattern. 3363 */ 3364 uint8_t power_down_phy_before_disable_stream; 3365 }; 3366 3367 /** 3368 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3369 */ 3370 struct dmub_rb_cmd_psr_copy_settings { 3371 /** 3372 * Command header. 3373 */ 3374 struct dmub_cmd_header header; 3375 /** 3376 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3377 */ 3378 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3379 }; 3380 3381 /** 3382 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3383 */ 3384 struct dmub_cmd_psr_set_level_data { 3385 /** 3386 * 16-bit value dicated by driver that will enable/disable different functionality. 3387 */ 3388 uint16_t psr_level; 3389 /** 3390 * PSR control version. 3391 */ 3392 uint8_t cmd_version; 3393 /** 3394 * Panel Instance. 3395 * Panel instance to identify which psr_state to use 3396 * Currently the support is only for 0 or 1 3397 */ 3398 uint8_t panel_inst; 3399 }; 3400 3401 /** 3402 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3403 */ 3404 struct dmub_rb_cmd_psr_set_level { 3405 /** 3406 * Command header. 3407 */ 3408 struct dmub_cmd_header header; 3409 /** 3410 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3411 */ 3412 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3413 }; 3414 3415 struct dmub_rb_cmd_psr_enable_data { 3416 /** 3417 * PSR control version. 3418 */ 3419 uint8_t cmd_version; 3420 /** 3421 * Panel Instance. 3422 * Panel instance to identify which psr_state to use 3423 * Currently the support is only for 0 or 1 3424 */ 3425 uint8_t panel_inst; 3426 /** 3427 * Phy state to enter. 3428 * Values to use are defined in dmub_phy_fsm_state 3429 */ 3430 uint8_t phy_fsm_state; 3431 /** 3432 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3433 * Set this using enum phy_link_rate. 3434 * This does not support HDMI/DP2 for now. 3435 */ 3436 uint8_t phy_rate; 3437 }; 3438 3439 /** 3440 * Definition of a DMUB_CMD__PSR_ENABLE command. 3441 * PSR enable/disable is controlled using the sub_type. 3442 */ 3443 struct dmub_rb_cmd_psr_enable { 3444 /** 3445 * Command header. 3446 */ 3447 struct dmub_cmd_header header; 3448 3449 struct dmub_rb_cmd_psr_enable_data data; 3450 }; 3451 3452 /** 3453 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3454 */ 3455 struct dmub_cmd_psr_set_version_data { 3456 /** 3457 * PSR version that FW should implement. 3458 */ 3459 enum psr_version version; 3460 /** 3461 * PSR control version. 3462 */ 3463 uint8_t cmd_version; 3464 /** 3465 * Panel Instance. 3466 * Panel instance to identify which psr_state to use 3467 * Currently the support is only for 0 or 1 3468 */ 3469 uint8_t panel_inst; 3470 /** 3471 * Explicit padding to 4 byte boundary. 3472 */ 3473 uint8_t pad[2]; 3474 }; 3475 3476 /** 3477 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3478 */ 3479 struct dmub_rb_cmd_psr_set_version { 3480 /** 3481 * Command header. 3482 */ 3483 struct dmub_cmd_header header; 3484 /** 3485 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3486 */ 3487 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3488 }; 3489 3490 struct dmub_cmd_psr_force_static_data { 3491 /** 3492 * PSR control version. 3493 */ 3494 uint8_t cmd_version; 3495 /** 3496 * Panel Instance. 3497 * Panel instance to identify which psr_state to use 3498 * Currently the support is only for 0 or 1 3499 */ 3500 uint8_t panel_inst; 3501 /** 3502 * Explicit padding to 4 byte boundary. 3503 */ 3504 uint8_t pad[2]; 3505 }; 3506 3507 /** 3508 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3509 */ 3510 struct dmub_rb_cmd_psr_force_static { 3511 /** 3512 * Command header. 3513 */ 3514 struct dmub_cmd_header header; 3515 /** 3516 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3517 */ 3518 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3519 }; 3520 3521 /** 3522 * PSR SU debug flags. 3523 */ 3524 union dmub_psr_su_debug_flags { 3525 /** 3526 * PSR SU debug flags. 3527 */ 3528 struct { 3529 /** 3530 * Update dirty rect in SW only. 3531 */ 3532 uint8_t update_dirty_rect_only : 1; 3533 /** 3534 * Reset the cursor/plane state before processing the call. 3535 */ 3536 uint8_t reset_state : 1; 3537 } bitfields; 3538 3539 /** 3540 * Union for debug flags. 3541 */ 3542 uint32_t u32All; 3543 }; 3544 3545 /** 3546 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3547 * This triggers a selective update for PSR SU. 3548 */ 3549 struct dmub_cmd_update_dirty_rect_data { 3550 /** 3551 * Dirty rects from OS. 3552 */ 3553 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3554 /** 3555 * PSR SU debug flags. 3556 */ 3557 union dmub_psr_su_debug_flags debug_flags; 3558 /** 3559 * OTG HW instance. 3560 */ 3561 uint8_t pipe_idx; 3562 /** 3563 * Number of dirty rects. 3564 */ 3565 uint8_t dirty_rect_count; 3566 /** 3567 * PSR control version. 3568 */ 3569 uint8_t cmd_version; 3570 /** 3571 * Panel Instance. 3572 * Panel instance to identify which psr_state to use 3573 * Currently the support is only for 0 or 1 3574 */ 3575 uint8_t panel_inst; 3576 }; 3577 3578 /** 3579 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3580 */ 3581 struct dmub_rb_cmd_update_dirty_rect { 3582 /** 3583 * Command header. 3584 */ 3585 struct dmub_cmd_header header; 3586 /** 3587 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3588 */ 3589 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3590 }; 3591 3592 /** 3593 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3594 */ 3595 union dmub_reg_cursor_control_cfg { 3596 struct { 3597 uint32_t cur_enable: 1; 3598 uint32_t reser0: 3; 3599 uint32_t cur_2x_magnify: 1; 3600 uint32_t reser1: 3; 3601 uint32_t mode: 3; 3602 uint32_t reser2: 5; 3603 uint32_t pitch: 2; 3604 uint32_t reser3: 6; 3605 uint32_t line_per_chunk: 5; 3606 uint32_t reser4: 3; 3607 } bits; 3608 uint32_t raw; 3609 }; 3610 struct dmub_cursor_position_cache_hubp { 3611 union dmub_reg_cursor_control_cfg cur_ctl; 3612 union dmub_reg_position_cfg { 3613 struct { 3614 uint32_t cur_x_pos: 16; 3615 uint32_t cur_y_pos: 16; 3616 } bits; 3617 uint32_t raw; 3618 } position; 3619 union dmub_reg_hot_spot_cfg { 3620 struct { 3621 uint32_t hot_x: 16; 3622 uint32_t hot_y: 16; 3623 } bits; 3624 uint32_t raw; 3625 } hot_spot; 3626 union dmub_reg_dst_offset_cfg { 3627 struct { 3628 uint32_t dst_x_offset: 13; 3629 uint32_t reserved: 19; 3630 } bits; 3631 uint32_t raw; 3632 } dst_offset; 3633 }; 3634 3635 union dmub_reg_cur0_control_cfg { 3636 struct { 3637 uint32_t cur0_enable: 1; 3638 uint32_t expansion_mode: 1; 3639 uint32_t reser0: 1; 3640 uint32_t cur0_rom_en: 1; 3641 uint32_t mode: 3; 3642 uint32_t reserved: 25; 3643 } bits; 3644 uint32_t raw; 3645 }; 3646 struct dmub_cursor_position_cache_dpp { 3647 union dmub_reg_cur0_control_cfg cur0_ctl; 3648 }; 3649 struct dmub_cursor_position_cfg { 3650 struct dmub_cursor_position_cache_hubp pHubp; 3651 struct dmub_cursor_position_cache_dpp pDpp; 3652 uint8_t pipe_idx; 3653 /* 3654 * Padding is required. To be 4 Bytes Aligned. 3655 */ 3656 uint8_t padding[3]; 3657 }; 3658 3659 struct dmub_cursor_attribute_cache_hubp { 3660 uint32_t SURFACE_ADDR_HIGH; 3661 uint32_t SURFACE_ADDR; 3662 union dmub_reg_cursor_control_cfg cur_ctl; 3663 union dmub_reg_cursor_size_cfg { 3664 struct { 3665 uint32_t width: 16; 3666 uint32_t height: 16; 3667 } bits; 3668 uint32_t raw; 3669 } size; 3670 union dmub_reg_cursor_settings_cfg { 3671 struct { 3672 uint32_t dst_y_offset: 8; 3673 uint32_t chunk_hdl_adjust: 2; 3674 uint32_t reserved: 22; 3675 } bits; 3676 uint32_t raw; 3677 } settings; 3678 }; 3679 struct dmub_cursor_attribute_cache_dpp { 3680 union dmub_reg_cur0_control_cfg cur0_ctl; 3681 }; 3682 struct dmub_cursor_attributes_cfg { 3683 struct dmub_cursor_attribute_cache_hubp aHubp; 3684 struct dmub_cursor_attribute_cache_dpp aDpp; 3685 }; 3686 3687 struct dmub_cmd_update_cursor_payload0 { 3688 /** 3689 * Cursor dirty rects. 3690 */ 3691 struct dmub_rect cursor_rect; 3692 /** 3693 * PSR SU debug flags. 3694 */ 3695 union dmub_psr_su_debug_flags debug_flags; 3696 /** 3697 * Cursor enable/disable. 3698 */ 3699 uint8_t enable; 3700 /** 3701 * OTG HW instance. 3702 */ 3703 uint8_t pipe_idx; 3704 /** 3705 * PSR control version. 3706 */ 3707 uint8_t cmd_version; 3708 /** 3709 * Panel Instance. 3710 * Panel instance to identify which psr_state to use 3711 * Currently the support is only for 0 or 1 3712 */ 3713 uint8_t panel_inst; 3714 /** 3715 * Cursor Position Register. 3716 * Registers contains Hubp & Dpp modules 3717 */ 3718 struct dmub_cursor_position_cfg position_cfg; 3719 }; 3720 3721 struct dmub_cmd_update_cursor_payload1 { 3722 struct dmub_cursor_attributes_cfg attribute_cfg; 3723 }; 3724 3725 union dmub_cmd_update_cursor_info_data { 3726 struct dmub_cmd_update_cursor_payload0 payload0; 3727 struct dmub_cmd_update_cursor_payload1 payload1; 3728 }; 3729 /** 3730 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3731 */ 3732 struct dmub_rb_cmd_update_cursor_info { 3733 /** 3734 * Command header. 3735 */ 3736 struct dmub_cmd_header header; 3737 /** 3738 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3739 */ 3740 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3741 }; 3742 3743 /** 3744 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3745 */ 3746 struct dmub_cmd_psr_set_vtotal_data { 3747 /** 3748 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3749 */ 3750 uint16_t psr_vtotal_idle; 3751 /** 3752 * PSR control version. 3753 */ 3754 uint8_t cmd_version; 3755 /** 3756 * Panel Instance. 3757 * Panel instance to identify which psr_state to use 3758 * Currently the support is only for 0 or 1 3759 */ 3760 uint8_t panel_inst; 3761 /* 3762 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3763 */ 3764 uint16_t psr_vtotal_su; 3765 /** 3766 * Explicit padding to 4 byte boundary. 3767 */ 3768 uint8_t pad2[2]; 3769 }; 3770 3771 /** 3772 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3773 */ 3774 struct dmub_rb_cmd_psr_set_vtotal { 3775 /** 3776 * Command header. 3777 */ 3778 struct dmub_cmd_header header; 3779 /** 3780 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3781 */ 3782 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3783 }; 3784 3785 /** 3786 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3787 */ 3788 struct dmub_cmd_psr_set_power_opt_data { 3789 /** 3790 * PSR control version. 3791 */ 3792 uint8_t cmd_version; 3793 /** 3794 * Panel Instance. 3795 * Panel instance to identify which psr_state to use 3796 * Currently the support is only for 0 or 1 3797 */ 3798 uint8_t panel_inst; 3799 /** 3800 * Explicit padding to 4 byte boundary. 3801 */ 3802 uint8_t pad[2]; 3803 /** 3804 * PSR power option 3805 */ 3806 uint32_t power_opt; 3807 }; 3808 3809 /** 3810 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3811 */ 3812 struct dmub_rb_cmd_psr_set_power_opt { 3813 /** 3814 * Command header. 3815 */ 3816 struct dmub_cmd_header header; 3817 /** 3818 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3819 */ 3820 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3821 }; 3822 3823 enum dmub_alpm_mode { 3824 ALPM_AUXWAKE = 0, 3825 ALPM_AUXLESS = 1, 3826 ALPM_UNSUPPORTED = 2, 3827 }; 3828 3829 /** 3830 * Definition of Replay Residency GPINT command. 3831 * Bit[0] - Residency mode for Revision 0 3832 * Bit[1] - Enable/Disable state 3833 * Bit[2-3] - Revision number 3834 * Bit[4-7] - Residency mode for Revision 1 3835 * Bit[8] - Panel instance 3836 * Bit[9-15] - Reserved 3837 */ 3838 3839 enum pr_residency_mode { 3840 PR_RESIDENCY_MODE_PHY = 0x0, 3841 PR_RESIDENCY_MODE_ALPM, 3842 PR_RESIDENCY_MODE_IPS2, 3843 PR_RESIDENCY_MODE_FRAME_CNT, 3844 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3845 }; 3846 3847 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3848 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3849 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3850 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3851 3852 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3853 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3854 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3855 3856 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3857 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3858 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3859 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3860 3861 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3862 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3863 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3864 3865 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3866 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3867 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3868 3869 /** 3870 * Definition of a replay_state. 3871 */ 3872 enum replay_state { 3873 REPLAY_STATE_0 = 0x0, 3874 REPLAY_STATE_1 = 0x10, 3875 REPLAY_STATE_1A = 0x11, 3876 REPLAY_STATE_2 = 0x20, 3877 REPLAY_STATE_2A = 0x21, 3878 REPLAY_STATE_3 = 0x30, 3879 REPLAY_STATE_3INIT = 0x31, 3880 REPLAY_STATE_4 = 0x40, 3881 REPLAY_STATE_4A = 0x41, 3882 REPLAY_STATE_4B = 0x42, 3883 REPLAY_STATE_4C = 0x43, 3884 REPLAY_STATE_4D = 0x44, 3885 REPLAY_STATE_4E = 0x45, 3886 REPLAY_STATE_4B_LOCKED = 0x4A, 3887 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3888 REPLAY_STATE_5 = 0x50, 3889 REPLAY_STATE_5A = 0x51, 3890 REPLAY_STATE_5B = 0x52, 3891 REPLAY_STATE_5A_LOCKED = 0x5A, 3892 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3893 REPLAY_STATE_6 = 0x60, 3894 REPLAY_STATE_6A = 0x61, 3895 REPLAY_STATE_6B = 0x62, 3896 REPLAY_STATE_INVALID = 0xFF, 3897 }; 3898 3899 /** 3900 * Replay command sub-types. 3901 */ 3902 enum dmub_cmd_replay_type { 3903 /** 3904 * Copy driver-calculated parameters to REPLAY state. 3905 */ 3906 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3907 /** 3908 * Enable REPLAY. 3909 */ 3910 DMUB_CMD__REPLAY_ENABLE = 1, 3911 /** 3912 * Set Replay power option. 3913 */ 3914 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3915 /** 3916 * Set coasting vtotal. 3917 */ 3918 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 3919 /** 3920 * Set power opt and coasting vtotal. 3921 */ 3922 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 3923 /** 3924 * Set disabled iiming sync. 3925 */ 3926 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 3927 /** 3928 * Set Residency Frameupdate Timer. 3929 */ 3930 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 3931 /** 3932 * Set pseudo vtotal 3933 */ 3934 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 3935 /** 3936 * Set adaptive sync sdp enabled 3937 */ 3938 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 3939 /** 3940 * Set Replay General command. 3941 */ 3942 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 3943 }; 3944 3945 /** 3946 * Replay general command sub-types. 3947 */ 3948 enum dmub_cmd_replay_general_subtype { 3949 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 3950 /** 3951 * TODO: For backward compatible, allow new command only. 3952 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 3953 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 3954 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 3955 */ 3956 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 3957 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 3958 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 3959 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 3960 }; 3961 3962 struct dmub_alpm_auxless_data { 3963 uint16_t lfps_setup_ns; 3964 uint16_t lfps_period_ns; 3965 uint16_t lfps_silence_ns; 3966 uint16_t lfps_t1_t2_override_us; 3967 short lfps_t1_t2_offset_us; 3968 uint8_t lttpr_count; 3969 }; 3970 3971 /** 3972 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 3973 */ 3974 struct dmub_cmd_replay_copy_settings_data { 3975 /** 3976 * Flags that can be set by driver to change some replay behaviour. 3977 */ 3978 union replay_debug_flags debug; 3979 3980 /** 3981 * @flags: Flags used to determine feature functionality. 3982 */ 3983 union replay_hw_flags flags; 3984 3985 /** 3986 * DPP HW instance. 3987 */ 3988 uint8_t dpp_inst; 3989 /** 3990 * OTG HW instance. 3991 */ 3992 uint8_t otg_inst; 3993 /** 3994 * DIG FE HW instance. 3995 */ 3996 uint8_t digfe_inst; 3997 /** 3998 * DIG BE HW instance. 3999 */ 4000 uint8_t digbe_inst; 4001 /** 4002 * AUX HW instance. 4003 */ 4004 uint8_t aux_inst; 4005 /** 4006 * Panel Instance. 4007 * Panel isntance to identify which psr_state to use 4008 * Currently the support is only for 0 or 1 4009 */ 4010 uint8_t panel_inst; 4011 /** 4012 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4013 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4014 */ 4015 uint8_t pixel_deviation_per_line; 4016 /** 4017 * @max_deviation_line: The max number of deviation line that can keep the timing 4018 * synchronized between the Source and Sink during Replay normal sleep mode. 4019 */ 4020 uint8_t max_deviation_line; 4021 /** 4022 * Length of each horizontal line in ns. 4023 */ 4024 uint32_t line_time_in_ns; 4025 /** 4026 * PHY instance. 4027 */ 4028 uint8_t dpphy_inst; 4029 /** 4030 * Determines if SMU optimzations are enabled/disabled. 4031 */ 4032 uint8_t smu_optimizations_en; 4033 /** 4034 * Determines if timing sync are enabled/disabled. 4035 */ 4036 uint8_t replay_timing_sync_supported; 4037 /* 4038 * Use FSM state for Replay power up/down 4039 */ 4040 uint8_t use_phy_fsm; 4041 /** 4042 * Use for AUX-less ALPM LFPS wake operation 4043 */ 4044 struct dmub_alpm_auxless_data auxless_alpm_data; 4045 }; 4046 4047 /** 4048 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4049 */ 4050 struct dmub_rb_cmd_replay_copy_settings { 4051 /** 4052 * Command header. 4053 */ 4054 struct dmub_cmd_header header; 4055 /** 4056 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4057 */ 4058 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4059 }; 4060 4061 /** 4062 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4063 */ 4064 enum replay_enable { 4065 /** 4066 * Disable REPLAY. 4067 */ 4068 REPLAY_DISABLE = 0, 4069 /** 4070 * Enable REPLAY. 4071 */ 4072 REPLAY_ENABLE = 1, 4073 }; 4074 4075 /** 4076 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4077 */ 4078 struct dmub_rb_cmd_replay_enable_data { 4079 /** 4080 * Replay enable or disable. 4081 */ 4082 uint8_t enable; 4083 /** 4084 * Panel Instance. 4085 * Panel isntance to identify which replay_state to use 4086 * Currently the support is only for 0 or 1 4087 */ 4088 uint8_t panel_inst; 4089 /** 4090 * Phy state to enter. 4091 * Values to use are defined in dmub_phy_fsm_state 4092 */ 4093 uint8_t phy_fsm_state; 4094 /** 4095 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4096 * Set this using enum phy_link_rate. 4097 * This does not support HDMI/DP2 for now. 4098 */ 4099 uint8_t phy_rate; 4100 }; 4101 4102 /** 4103 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4104 * Replay enable/disable is controlled using action in data. 4105 */ 4106 struct dmub_rb_cmd_replay_enable { 4107 /** 4108 * Command header. 4109 */ 4110 struct dmub_cmd_header header; 4111 4112 struct dmub_rb_cmd_replay_enable_data data; 4113 }; 4114 4115 /** 4116 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4117 */ 4118 struct dmub_cmd_replay_set_power_opt_data { 4119 /** 4120 * Panel Instance. 4121 * Panel isntance to identify which replay_state to use 4122 * Currently the support is only for 0 or 1 4123 */ 4124 uint8_t panel_inst; 4125 /** 4126 * Explicit padding to 4 byte boundary. 4127 */ 4128 uint8_t pad[3]; 4129 /** 4130 * REPLAY power option 4131 */ 4132 uint32_t power_opt; 4133 }; 4134 4135 /** 4136 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4137 */ 4138 struct dmub_cmd_replay_set_timing_sync_data { 4139 /** 4140 * Panel Instance. 4141 * Panel isntance to identify which replay_state to use 4142 * Currently the support is only for 0 or 1 4143 */ 4144 uint8_t panel_inst; 4145 /** 4146 * REPLAY set_timing_sync 4147 */ 4148 uint8_t timing_sync_supported; 4149 /** 4150 * Explicit padding to 4 byte boundary. 4151 */ 4152 uint8_t pad[2]; 4153 }; 4154 4155 /** 4156 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4157 */ 4158 struct dmub_cmd_replay_set_pseudo_vtotal { 4159 /** 4160 * Panel Instance. 4161 * Panel isntance to identify which replay_state to use 4162 * Currently the support is only for 0 or 1 4163 */ 4164 uint8_t panel_inst; 4165 /** 4166 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4167 */ 4168 uint16_t vtotal; 4169 /** 4170 * Explicit padding to 4 byte boundary. 4171 */ 4172 uint8_t pad; 4173 }; 4174 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4175 /** 4176 * Panel Instance. 4177 * Panel isntance to identify which replay_state to use 4178 * Currently the support is only for 0 or 1 4179 */ 4180 uint8_t panel_inst; 4181 /** 4182 * enabled: set adaptive sync sdp enabled 4183 */ 4184 uint8_t force_disabled; 4185 4186 uint8_t pad[2]; 4187 }; 4188 struct dmub_cmd_replay_set_general_cmd_data { 4189 /** 4190 * Panel Instance. 4191 * Panel isntance to identify which replay_state to use 4192 * Currently the support is only for 0 or 1 4193 */ 4194 uint8_t panel_inst; 4195 /** 4196 * subtype: replay general cmd sub type 4197 */ 4198 uint8_t subtype; 4199 4200 uint8_t pad[2]; 4201 /** 4202 * config data with param1 and param2 4203 */ 4204 uint32_t param1; 4205 4206 uint32_t param2; 4207 }; 4208 4209 /** 4210 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4211 */ 4212 struct dmub_rb_cmd_replay_set_power_opt { 4213 /** 4214 * Command header. 4215 */ 4216 struct dmub_cmd_header header; 4217 /** 4218 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4219 */ 4220 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4221 }; 4222 4223 /** 4224 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4225 */ 4226 struct dmub_cmd_replay_set_coasting_vtotal_data { 4227 /** 4228 * 16-bit value dicated by driver that indicates the coasting vtotal. 4229 */ 4230 uint16_t coasting_vtotal; 4231 /** 4232 * REPLAY control version. 4233 */ 4234 uint8_t cmd_version; 4235 /** 4236 * Panel Instance. 4237 * Panel isntance to identify which replay_state to use 4238 * Currently the support is only for 0 or 1 4239 */ 4240 uint8_t panel_inst; 4241 /** 4242 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4243 */ 4244 uint16_t coasting_vtotal_high; 4245 /** 4246 * Explicit padding to 4 byte boundary. 4247 */ 4248 uint8_t pad[2]; 4249 }; 4250 4251 /** 4252 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4253 */ 4254 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4255 /** 4256 * Command header. 4257 */ 4258 struct dmub_cmd_header header; 4259 /** 4260 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4261 */ 4262 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4263 }; 4264 4265 /** 4266 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4267 */ 4268 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4269 /** 4270 * Command header. 4271 */ 4272 struct dmub_cmd_header header; 4273 /** 4274 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4275 */ 4276 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4277 /** 4278 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4279 */ 4280 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4281 }; 4282 4283 /** 4284 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4285 */ 4286 struct dmub_rb_cmd_replay_set_timing_sync { 4287 /** 4288 * Command header. 4289 */ 4290 struct dmub_cmd_header header; 4291 /** 4292 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4293 */ 4294 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4295 }; 4296 4297 /** 4298 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4299 */ 4300 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4301 /** 4302 * Command header. 4303 */ 4304 struct dmub_cmd_header header; 4305 /** 4306 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4307 */ 4308 struct dmub_cmd_replay_set_pseudo_vtotal data; 4309 }; 4310 4311 /** 4312 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4313 */ 4314 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4315 /** 4316 * Command header. 4317 */ 4318 struct dmub_cmd_header header; 4319 /** 4320 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4321 */ 4322 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4323 }; 4324 4325 /** 4326 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4327 */ 4328 struct dmub_rb_cmd_replay_set_general_cmd { 4329 /** 4330 * Command header. 4331 */ 4332 struct dmub_cmd_header header; 4333 /** 4334 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4335 */ 4336 struct dmub_cmd_replay_set_general_cmd_data data; 4337 }; 4338 4339 /** 4340 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4341 */ 4342 struct dmub_cmd_replay_frameupdate_timer_data { 4343 /** 4344 * Panel Instance. 4345 * Panel isntance to identify which replay_state to use 4346 * Currently the support is only for 0 or 1 4347 */ 4348 uint8_t panel_inst; 4349 /** 4350 * Replay Frameupdate Timer Enable or not 4351 */ 4352 uint8_t enable; 4353 /** 4354 * REPLAY force reflash frame update number 4355 */ 4356 uint16_t frameupdate_count; 4357 }; 4358 /** 4359 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4360 */ 4361 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4362 /** 4363 * Command header. 4364 */ 4365 struct dmub_cmd_header header; 4366 /** 4367 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4368 */ 4369 struct dmub_cmd_replay_frameupdate_timer_data data; 4370 }; 4371 4372 /** 4373 * Definition union of replay command set 4374 */ 4375 union dmub_replay_cmd_set { 4376 /** 4377 * Panel Instance. 4378 * Panel isntance to identify which replay_state to use 4379 * Currently the support is only for 0 or 1 4380 */ 4381 uint8_t panel_inst; 4382 /** 4383 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4384 */ 4385 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4386 /** 4387 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4388 */ 4389 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4390 /** 4391 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4392 */ 4393 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4394 /** 4395 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4396 */ 4397 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4398 /** 4399 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4400 */ 4401 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4402 }; 4403 4404 /** 4405 * Set of HW components that can be locked. 4406 * 4407 * Note: If updating with more HW components, fields 4408 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4409 */ 4410 union dmub_hw_lock_flags { 4411 /** 4412 * Set of HW components that can be locked. 4413 */ 4414 struct { 4415 /** 4416 * Lock/unlock OTG master update lock. 4417 */ 4418 uint8_t lock_pipe : 1; 4419 /** 4420 * Lock/unlock cursor. 4421 */ 4422 uint8_t lock_cursor : 1; 4423 /** 4424 * Lock/unlock global update lock. 4425 */ 4426 uint8_t lock_dig : 1; 4427 /** 4428 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4429 */ 4430 uint8_t triple_buffer_lock : 1; 4431 } bits; 4432 4433 /** 4434 * Union for HW Lock flags. 4435 */ 4436 uint8_t u8All; 4437 }; 4438 4439 /** 4440 * Instances of HW to be locked. 4441 * 4442 * Note: If updating with more HW components, fields 4443 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4444 */ 4445 struct dmub_hw_lock_inst_flags { 4446 /** 4447 * OTG HW instance for OTG master update lock. 4448 */ 4449 uint8_t otg_inst; 4450 /** 4451 * OPP instance for cursor lock. 4452 */ 4453 uint8_t opp_inst; 4454 /** 4455 * OTG HW instance for global update lock. 4456 * TODO: Remove, and re-use otg_inst. 4457 */ 4458 uint8_t dig_inst; 4459 /** 4460 * Explicit pad to 4 byte boundary. 4461 */ 4462 uint8_t pad; 4463 }; 4464 4465 /** 4466 * Clients that can acquire the HW Lock Manager. 4467 * 4468 * Note: If updating with more clients, fields in 4469 * dmub_inbox0_cmd_lock_hw must be updated to match. 4470 */ 4471 enum hw_lock_client { 4472 /** 4473 * Driver is the client of HW Lock Manager. 4474 */ 4475 HW_LOCK_CLIENT_DRIVER = 0, 4476 /** 4477 * PSR SU is the client of HW Lock Manager. 4478 */ 4479 HW_LOCK_CLIENT_PSR_SU = 1, 4480 HW_LOCK_CLIENT_SUBVP = 3, 4481 /** 4482 * Replay is the client of HW Lock Manager. 4483 */ 4484 HW_LOCK_CLIENT_REPLAY = 4, 4485 HW_LOCK_CLIENT_FAMS2 = 5, 4486 /** 4487 * Invalid client. 4488 */ 4489 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4490 }; 4491 4492 /** 4493 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4494 */ 4495 struct dmub_cmd_lock_hw_data { 4496 /** 4497 * Specifies the client accessing HW Lock Manager. 4498 */ 4499 enum hw_lock_client client; 4500 /** 4501 * HW instances to be locked. 4502 */ 4503 struct dmub_hw_lock_inst_flags inst_flags; 4504 /** 4505 * Which components to be locked. 4506 */ 4507 union dmub_hw_lock_flags hw_locks; 4508 /** 4509 * Specifies lock/unlock. 4510 */ 4511 uint8_t lock; 4512 /** 4513 * HW can be unlocked separately from releasing the HW Lock Mgr. 4514 * This flag is set if the client wishes to release the object. 4515 */ 4516 uint8_t should_release; 4517 /** 4518 * Explicit padding to 4 byte boundary. 4519 */ 4520 uint8_t pad; 4521 }; 4522 4523 /** 4524 * Definition of a DMUB_CMD__HW_LOCK command. 4525 * Command is used by driver and FW. 4526 */ 4527 struct dmub_rb_cmd_lock_hw { 4528 /** 4529 * Command header. 4530 */ 4531 struct dmub_cmd_header header; 4532 /** 4533 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4534 */ 4535 struct dmub_cmd_lock_hw_data lock_hw_data; 4536 }; 4537 4538 /** 4539 * ABM command sub-types. 4540 */ 4541 enum dmub_cmd_abm_type { 4542 /** 4543 * Initialize parameters for ABM algorithm. 4544 * Data is passed through an indirect buffer. 4545 */ 4546 DMUB_CMD__ABM_INIT_CONFIG = 0, 4547 /** 4548 * Set OTG and panel HW instance. 4549 */ 4550 DMUB_CMD__ABM_SET_PIPE = 1, 4551 /** 4552 * Set user requested backklight level. 4553 */ 4554 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4555 /** 4556 * Set ABM operating/aggression level. 4557 */ 4558 DMUB_CMD__ABM_SET_LEVEL = 3, 4559 /** 4560 * Set ambient light level. 4561 */ 4562 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4563 /** 4564 * Enable/disable fractional duty cycle for backlight PWM. 4565 */ 4566 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4567 4568 /** 4569 * unregister vertical interrupt after steady state is reached 4570 */ 4571 DMUB_CMD__ABM_PAUSE = 6, 4572 4573 /** 4574 * Save and Restore ABM state. On save we save parameters, and 4575 * on restore we update state with passed in data. 4576 */ 4577 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4578 4579 /** 4580 * Query ABM caps. 4581 */ 4582 DMUB_CMD__ABM_QUERY_CAPS = 8, 4583 4584 /** 4585 * Set ABM Events 4586 */ 4587 DMUB_CMD__ABM_SET_EVENT = 9, 4588 4589 /** 4590 * Get the current ACE curve. 4591 */ 4592 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4593 4594 /** 4595 * Get current histogram data 4596 */ 4597 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4598 }; 4599 4600 /** 4601 * LSDMA command sub-types. 4602 */ 4603 enum dmub_cmd_lsdma_type { 4604 /** 4605 * Initialize parameters for LSDMA. 4606 * Ring buffer is mapped to the ring buffer 4607 */ 4608 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4609 /** 4610 * LSDMA copies data from source to destination linearly 4611 */ 4612 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4613 /** 4614 * Send the tiled-to-tiled copy command 4615 */ 4616 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 2, 4617 /** 4618 * Send the poll reg write command 4619 */ 4620 DMUB_CMD__LSDMA_POLL_REG_WRITE = 3, 4621 /** 4622 * Send the pio copy command 4623 */ 4624 DMUB_CMD__LSDMA_PIO_COPY = 4, 4625 /** 4626 * Send the pio constfill command 4627 */ 4628 DMUB_CMD__LSDMA_PIO_CONSTFILL = 5, 4629 }; 4630 4631 struct abm_ace_curve { 4632 /** 4633 * @offsets: ACE curve offsets. 4634 */ 4635 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4636 4637 /** 4638 * @thresholds: ACE curve thresholds. 4639 */ 4640 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4641 4642 /** 4643 * @slopes: ACE curve slopes. 4644 */ 4645 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4646 }; 4647 4648 struct fixed_pt_format { 4649 /** 4650 * @sign_bit: Indicates whether one bit is reserved for the sign. 4651 */ 4652 bool sign_bit; 4653 4654 /** 4655 * @num_int_bits: Number of bits used for integer part. 4656 */ 4657 uint8_t num_int_bits; 4658 4659 /** 4660 * @num_frac_bits: Number of bits used for fractional part. 4661 */ 4662 uint8_t num_frac_bits; 4663 4664 /** 4665 * @pad: Explicit padding to 4 byte boundary. 4666 */ 4667 uint8_t pad; 4668 }; 4669 4670 struct abm_caps { 4671 /** 4672 * @num_hg_bins: Number of histogram bins. 4673 */ 4674 uint8_t num_hg_bins; 4675 4676 /** 4677 * @num_ace_segments: Number of ACE curve segments. 4678 */ 4679 uint8_t num_ace_segments; 4680 4681 /** 4682 * @pad: Explicit padding to 4 byte boundary. 4683 */ 4684 uint8_t pad[2]; 4685 4686 /** 4687 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4688 */ 4689 struct fixed_pt_format ace_thresholds_format; 4690 4691 /** 4692 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4693 */ 4694 struct fixed_pt_format ace_offsets_format; 4695 4696 /** 4697 * @ace_slopes_format: Format of the ACE slopes. 4698 */ 4699 struct fixed_pt_format ace_slopes_format; 4700 }; 4701 4702 /** 4703 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4704 * Requirements: 4705 * - Padded explicitly to 32-bit boundary. 4706 * - Must ensure this structure matches the one on driver-side, 4707 * otherwise it won't be aligned. 4708 */ 4709 struct abm_config_table { 4710 /** 4711 * Gamma curve thresholds, used for crgb conversion. 4712 */ 4713 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4714 /** 4715 * Gamma curve offsets, used for crgb conversion. 4716 */ 4717 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4718 /** 4719 * Gamma curve slopes, used for crgb conversion. 4720 */ 4721 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4722 /** 4723 * Custom backlight curve thresholds. 4724 */ 4725 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4726 /** 4727 * Custom backlight curve offsets. 4728 */ 4729 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4730 /** 4731 * Ambient light thresholds. 4732 */ 4733 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4734 /** 4735 * Minimum programmable backlight. 4736 */ 4737 uint16_t min_abm_backlight; // 122B 4738 /** 4739 * Minimum reduction values. 4740 */ 4741 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4742 /** 4743 * Maximum reduction values. 4744 */ 4745 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4746 /** 4747 * Bright positive gain. 4748 */ 4749 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4750 /** 4751 * Dark negative gain. 4752 */ 4753 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4754 /** 4755 * Hybrid factor. 4756 */ 4757 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4758 /** 4759 * Contrast factor. 4760 */ 4761 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4762 /** 4763 * Deviation gain. 4764 */ 4765 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4766 /** 4767 * Minimum knee. 4768 */ 4769 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4770 /** 4771 * Maximum knee. 4772 */ 4773 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4774 /** 4775 * Unused. 4776 */ 4777 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4778 /** 4779 * Explicit padding to 4 byte boundary. 4780 */ 4781 uint8_t pad3[3]; // 229B 4782 /** 4783 * Backlight ramp reduction. 4784 */ 4785 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4786 /** 4787 * Backlight ramp start. 4788 */ 4789 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4790 }; 4791 4792 /** 4793 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4794 */ 4795 struct dmub_cmd_abm_set_pipe_data { 4796 /** 4797 * OTG HW instance. 4798 */ 4799 uint8_t otg_inst; 4800 4801 /** 4802 * Panel Control HW instance. 4803 */ 4804 uint8_t panel_inst; 4805 4806 /** 4807 * Controls how ABM will interpret a set pipe or set level command. 4808 */ 4809 uint8_t set_pipe_option; 4810 4811 /** 4812 * Unused. 4813 * TODO: Remove. 4814 */ 4815 uint8_t ramping_boundary; 4816 4817 /** 4818 * PwrSeq HW Instance. 4819 */ 4820 uint8_t pwrseq_inst; 4821 4822 /** 4823 * Explicit padding to 4 byte boundary. 4824 */ 4825 uint8_t pad[3]; 4826 }; 4827 4828 /** 4829 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4830 */ 4831 struct dmub_rb_cmd_abm_set_pipe { 4832 /** 4833 * Command header. 4834 */ 4835 struct dmub_cmd_header header; 4836 4837 /** 4838 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4839 */ 4840 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4841 }; 4842 4843 /** 4844 * Type of backlight control method to be used by ABM module 4845 */ 4846 enum dmub_backlight_control_type { 4847 /** 4848 * PWM Backlight control 4849 */ 4850 DMU_BACKLIGHT_CONTROL_PWM = 0, 4851 /** 4852 * VESA Aux-based backlight control 4853 */ 4854 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4855 /** 4856 * AMD DPCD Aux-based backlight control 4857 */ 4858 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4859 }; 4860 4861 /** 4862 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4863 */ 4864 struct dmub_cmd_abm_set_backlight_data { 4865 /** 4866 * Number of frames to ramp to backlight user level. 4867 */ 4868 uint32_t frame_ramp; 4869 4870 /** 4871 * Requested backlight level from user. 4872 */ 4873 uint32_t backlight_user_level; 4874 4875 /** 4876 * ABM control version. 4877 */ 4878 uint8_t version; 4879 4880 /** 4881 * Panel Control HW instance mask. 4882 * Bit 0 is Panel Control HW instance 0. 4883 * Bit 1 is Panel Control HW instance 1. 4884 */ 4885 uint8_t panel_mask; 4886 4887 /** 4888 * AUX HW Instance. 4889 */ 4890 uint8_t aux_inst; 4891 4892 /** 4893 * Explicit padding to 4 byte boundary. 4894 */ 4895 uint8_t pad[1]; 4896 4897 /** 4898 * Backlight control type. 4899 * Value 0 is PWM backlight control. 4900 * Value 1 is VAUX backlight control. 4901 * Value 2 is AMD DPCD AUX backlight control. 4902 */ 4903 enum dmub_backlight_control_type backlight_control_type; 4904 4905 /** 4906 * Minimum luminance in nits. 4907 */ 4908 uint32_t min_luminance; 4909 4910 /** 4911 * Maximum luminance in nits. 4912 */ 4913 uint32_t max_luminance; 4914 4915 /** 4916 * Minimum backlight in pwm. 4917 */ 4918 uint32_t min_backlight_pwm; 4919 4920 /** 4921 * Maximum backlight in pwm. 4922 */ 4923 uint32_t max_backlight_pwm; 4924 }; 4925 4926 /** 4927 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 4928 */ 4929 struct dmub_rb_cmd_abm_set_backlight { 4930 /** 4931 * Command header. 4932 */ 4933 struct dmub_cmd_header header; 4934 4935 /** 4936 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4937 */ 4938 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 4939 }; 4940 4941 /** 4942 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4943 */ 4944 struct dmub_cmd_abm_set_level_data { 4945 /** 4946 * Set current ABM operating/aggression level. 4947 */ 4948 uint32_t level; 4949 4950 /** 4951 * ABM control version. 4952 */ 4953 uint8_t version; 4954 4955 /** 4956 * Panel Control HW instance mask. 4957 * Bit 0 is Panel Control HW instance 0. 4958 * Bit 1 is Panel Control HW instance 1. 4959 */ 4960 uint8_t panel_mask; 4961 4962 /** 4963 * Explicit padding to 4 byte boundary. 4964 */ 4965 uint8_t pad[2]; 4966 }; 4967 4968 /** 4969 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 4970 */ 4971 struct dmub_rb_cmd_abm_set_level { 4972 /** 4973 * Command header. 4974 */ 4975 struct dmub_cmd_header header; 4976 4977 /** 4978 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 4979 */ 4980 struct dmub_cmd_abm_set_level_data abm_set_level_data; 4981 }; 4982 4983 /** 4984 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 4985 */ 4986 struct dmub_cmd_abm_set_ambient_level_data { 4987 /** 4988 * Ambient light sensor reading from OS. 4989 */ 4990 uint32_t ambient_lux; 4991 4992 /** 4993 * ABM control version. 4994 */ 4995 uint8_t version; 4996 4997 /** 4998 * Panel Control HW instance mask. 4999 * Bit 0 is Panel Control HW instance 0. 5000 * Bit 1 is Panel Control HW instance 1. 5001 */ 5002 uint8_t panel_mask; 5003 5004 /** 5005 * Explicit padding to 4 byte boundary. 5006 */ 5007 uint8_t pad[2]; 5008 }; 5009 5010 /** 5011 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5012 */ 5013 struct dmub_rb_cmd_abm_set_ambient_level { 5014 /** 5015 * Command header. 5016 */ 5017 struct dmub_cmd_header header; 5018 5019 /** 5020 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5021 */ 5022 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5023 }; 5024 5025 /** 5026 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5027 */ 5028 struct dmub_cmd_abm_set_pwm_frac_data { 5029 /** 5030 * Enable/disable fractional duty cycle for backlight PWM. 5031 * TODO: Convert to uint8_t. 5032 */ 5033 uint32_t fractional_pwm; 5034 5035 /** 5036 * ABM control version. 5037 */ 5038 uint8_t version; 5039 5040 /** 5041 * Panel Control HW instance mask. 5042 * Bit 0 is Panel Control HW instance 0. 5043 * Bit 1 is Panel Control HW instance 1. 5044 */ 5045 uint8_t panel_mask; 5046 5047 /** 5048 * Explicit padding to 4 byte boundary. 5049 */ 5050 uint8_t pad[2]; 5051 }; 5052 5053 /** 5054 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5055 */ 5056 struct dmub_rb_cmd_abm_set_pwm_frac { 5057 /** 5058 * Command header. 5059 */ 5060 struct dmub_cmd_header header; 5061 5062 /** 5063 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5064 */ 5065 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5066 }; 5067 5068 /** 5069 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5070 */ 5071 struct dmub_cmd_abm_init_config_data { 5072 /** 5073 * Location of indirect buffer used to pass init data to ABM. 5074 */ 5075 union dmub_addr src; 5076 5077 /** 5078 * Indirect buffer length. 5079 */ 5080 uint16_t bytes; 5081 5082 5083 /** 5084 * ABM control version. 5085 */ 5086 uint8_t version; 5087 5088 /** 5089 * Panel Control HW instance mask. 5090 * Bit 0 is Panel Control HW instance 0. 5091 * Bit 1 is Panel Control HW instance 1. 5092 */ 5093 uint8_t panel_mask; 5094 5095 /** 5096 * Explicit padding to 4 byte boundary. 5097 */ 5098 uint8_t pad[2]; 5099 }; 5100 5101 /** 5102 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5103 */ 5104 struct dmub_rb_cmd_abm_init_config { 5105 /** 5106 * Command header. 5107 */ 5108 struct dmub_cmd_header header; 5109 5110 /** 5111 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5112 */ 5113 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5114 }; 5115 5116 /** 5117 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5118 */ 5119 5120 struct dmub_cmd_abm_pause_data { 5121 5122 /** 5123 * Panel Control HW instance mask. 5124 * Bit 0 is Panel Control HW instance 0. 5125 * Bit 1 is Panel Control HW instance 1. 5126 */ 5127 uint8_t panel_mask; 5128 5129 /** 5130 * OTG hw instance 5131 */ 5132 uint8_t otg_inst; 5133 5134 /** 5135 * Enable or disable ABM pause 5136 */ 5137 uint8_t enable; 5138 5139 /** 5140 * Explicit padding to 4 byte boundary. 5141 */ 5142 uint8_t pad[1]; 5143 }; 5144 5145 /** 5146 * Definition of a DMUB_CMD__ABM_PAUSE command. 5147 */ 5148 struct dmub_rb_cmd_abm_pause { 5149 /** 5150 * Command header. 5151 */ 5152 struct dmub_cmd_header header; 5153 5154 /** 5155 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5156 */ 5157 struct dmub_cmd_abm_pause_data abm_pause_data; 5158 }; 5159 5160 /** 5161 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5162 */ 5163 struct dmub_cmd_abm_query_caps_in { 5164 /** 5165 * Panel instance. 5166 */ 5167 uint8_t panel_inst; 5168 5169 /** 5170 * Explicit padding to 4 byte boundary. 5171 */ 5172 uint8_t pad[3]; 5173 }; 5174 5175 /** 5176 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5177 */ 5178 struct dmub_cmd_abm_query_caps_out { 5179 /** 5180 * SW Algorithm caps. 5181 */ 5182 struct abm_caps sw_caps; 5183 5184 /** 5185 * ABM HW caps. 5186 */ 5187 struct abm_caps hw_caps; 5188 }; 5189 5190 /** 5191 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5192 */ 5193 struct dmub_rb_cmd_abm_query_caps { 5194 /** 5195 * Command header. 5196 */ 5197 struct dmub_cmd_header header; 5198 5199 /** 5200 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5201 */ 5202 union { 5203 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5204 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5205 } data; 5206 }; 5207 5208 /** 5209 * enum dmub_abm_ace_curve_type - ACE curve type. 5210 */ 5211 enum dmub_abm_ace_curve_type { 5212 /** 5213 * ACE curve as defined by the SW layer. 5214 */ 5215 ABM_ACE_CURVE_TYPE__SW = 0, 5216 /** 5217 * ACE curve as defined by the SW to HW translation interface layer. 5218 */ 5219 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5220 }; 5221 5222 /** 5223 * enum dmub_abm_histogram_type - Histogram type. 5224 */ 5225 enum dmub_abm_histogram_type { 5226 /** 5227 * ACE curve as defined by the SW layer. 5228 */ 5229 ABM_HISTOGRAM_TYPE__SW = 0, 5230 /** 5231 * ACE curve as defined by the SW to HW translation interface layer. 5232 */ 5233 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5234 }; 5235 5236 /** 5237 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5238 */ 5239 struct dmub_rb_cmd_abm_get_ace_curve { 5240 /** 5241 * Command header. 5242 */ 5243 struct dmub_cmd_header header; 5244 5245 /** 5246 * Address where ACE curve should be copied. 5247 */ 5248 union dmub_addr dest; 5249 5250 /** 5251 * Type of ACE curve being queried. 5252 */ 5253 enum dmub_abm_ace_curve_type ace_type; 5254 5255 /** 5256 * Indirect buffer length. 5257 */ 5258 uint16_t bytes; 5259 5260 /** 5261 * eDP panel instance. 5262 */ 5263 uint8_t panel_inst; 5264 5265 /** 5266 * Explicit padding to 4 byte boundary. 5267 */ 5268 uint8_t pad; 5269 }; 5270 5271 /** 5272 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5273 */ 5274 struct dmub_rb_cmd_abm_get_histogram { 5275 /** 5276 * Command header. 5277 */ 5278 struct dmub_cmd_header header; 5279 5280 /** 5281 * Address where Histogram should be copied. 5282 */ 5283 union dmub_addr dest; 5284 5285 /** 5286 * Type of Histogram being queried. 5287 */ 5288 enum dmub_abm_histogram_type histogram_type; 5289 5290 /** 5291 * Indirect buffer length. 5292 */ 5293 uint16_t bytes; 5294 5295 /** 5296 * eDP panel instance. 5297 */ 5298 uint8_t panel_inst; 5299 5300 /** 5301 * Explicit padding to 4 byte boundary. 5302 */ 5303 uint8_t pad; 5304 }; 5305 5306 /** 5307 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5308 */ 5309 struct dmub_rb_cmd_abm_save_restore { 5310 /** 5311 * Command header. 5312 */ 5313 struct dmub_cmd_header header; 5314 5315 /** 5316 * OTG hw instance 5317 */ 5318 uint8_t otg_inst; 5319 5320 /** 5321 * Enable or disable ABM pause 5322 */ 5323 uint8_t freeze; 5324 5325 /** 5326 * Explicit padding to 4 byte boundary. 5327 */ 5328 uint8_t debug; 5329 5330 /** 5331 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5332 */ 5333 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5334 }; 5335 5336 /** 5337 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5338 */ 5339 5340 struct dmub_cmd_abm_set_event_data { 5341 5342 /** 5343 * VB Scaling Init. Strength Mapping 5344 * Byte 0: 0~255 for VB level 0 5345 * Byte 1: 0~255 for VB level 1 5346 * Byte 2: 0~255 for VB level 2 5347 * Byte 3: 0~255 for VB level 3 5348 */ 5349 uint32_t vb_scaling_strength_mapping; 5350 /** 5351 * VariBright Scaling Enable 5352 */ 5353 uint8_t vb_scaling_enable; 5354 /** 5355 * Panel Control HW instance mask. 5356 * Bit 0 is Panel Control HW instance 0. 5357 * Bit 1 is Panel Control HW instance 1. 5358 */ 5359 uint8_t panel_mask; 5360 5361 /** 5362 * Explicit padding to 4 byte boundary. 5363 */ 5364 uint8_t pad[2]; 5365 }; 5366 5367 /** 5368 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5369 */ 5370 struct dmub_rb_cmd_abm_set_event { 5371 /** 5372 * Command header. 5373 */ 5374 struct dmub_cmd_header header; 5375 5376 /** 5377 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5378 */ 5379 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5380 }; 5381 5382 /** 5383 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5384 */ 5385 struct dmub_cmd_query_feature_caps_data { 5386 /** 5387 * DMUB feature capabilities. 5388 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5389 */ 5390 struct dmub_feature_caps feature_caps; 5391 }; 5392 5393 /** 5394 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5395 */ 5396 struct dmub_rb_cmd_query_feature_caps { 5397 /** 5398 * Command header. 5399 */ 5400 struct dmub_cmd_header header; 5401 /** 5402 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5403 */ 5404 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5405 }; 5406 5407 /** 5408 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5409 */ 5410 struct dmub_cmd_visual_confirm_color_data { 5411 /** 5412 * DMUB visual confirm color 5413 */ 5414 struct dmub_visual_confirm_color visual_confirm_color; 5415 }; 5416 5417 /** 5418 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5419 */ 5420 struct dmub_rb_cmd_get_visual_confirm_color { 5421 /** 5422 * Command header. 5423 */ 5424 struct dmub_cmd_header header; 5425 /** 5426 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5427 */ 5428 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5429 }; 5430 5431 /** 5432 * enum dmub_cmd_panel_cntl_type - Panel control command. 5433 */ 5434 enum dmub_cmd_panel_cntl_type { 5435 /** 5436 * Initializes embedded panel hardware blocks. 5437 */ 5438 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5439 /** 5440 * Queries backlight info for the embedded panel. 5441 */ 5442 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5443 /** 5444 * Sets the PWM Freq as per user's requirement. 5445 */ 5446 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5447 }; 5448 5449 /** 5450 * struct dmub_cmd_panel_cntl_data - Panel control data. 5451 */ 5452 struct dmub_cmd_panel_cntl_data { 5453 uint32_t pwrseq_inst; /**< pwrseq instance */ 5454 uint32_t current_backlight; /* in/out */ 5455 uint32_t bl_pwm_cntl; /* in/out */ 5456 uint32_t bl_pwm_period_cntl; /* in/out */ 5457 uint32_t bl_pwm_ref_div1; /* in/out */ 5458 uint8_t is_backlight_on : 1; /* in/out */ 5459 uint8_t is_powered_on : 1; /* in/out */ 5460 uint8_t padding[3]; 5461 uint32_t bl_pwm_ref_div2; /* in/out */ 5462 uint8_t reserved[4]; 5463 }; 5464 5465 /** 5466 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5467 */ 5468 struct dmub_rb_cmd_panel_cntl { 5469 struct dmub_cmd_header header; /**< header */ 5470 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5471 }; 5472 5473 struct dmub_optc_state { 5474 uint32_t v_total_max; 5475 uint32_t v_total_min; 5476 uint32_t tg_inst; 5477 }; 5478 5479 struct dmub_rb_cmd_drr_update { 5480 struct dmub_cmd_header header; 5481 struct dmub_optc_state dmub_optc_state_req; 5482 }; 5483 5484 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5485 uint32_t pix_clk_100hz; 5486 uint8_t max_ramp_step; 5487 uint8_t pipes; 5488 uint8_t min_refresh_in_hz; 5489 uint8_t pipe_count; 5490 uint8_t pipe_index[4]; 5491 }; 5492 5493 struct dmub_cmd_fw_assisted_mclk_switch_config { 5494 uint8_t fams_enabled; 5495 uint8_t visual_confirm_enabled; 5496 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5497 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5498 }; 5499 5500 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5501 struct dmub_cmd_header header; 5502 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5503 }; 5504 5505 /** 5506 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5507 */ 5508 struct dmub_cmd_lvtma_control_data { 5509 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5510 uint8_t bypass_panel_control_wait; 5511 uint8_t reserved_0[2]; /**< For future use */ 5512 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5513 uint8_t reserved_1[3]; /**< For future use */ 5514 }; 5515 5516 /** 5517 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5518 */ 5519 struct dmub_rb_cmd_lvtma_control { 5520 /** 5521 * Command header. 5522 */ 5523 struct dmub_cmd_header header; 5524 /** 5525 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5526 */ 5527 struct dmub_cmd_lvtma_control_data data; 5528 }; 5529 5530 /** 5531 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5532 */ 5533 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5534 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5535 uint8_t is_usb; /**< is phy is usb */ 5536 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5537 uint8_t is_dp4; /**< is dp in 4 lane */ 5538 }; 5539 5540 /** 5541 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5542 */ 5543 struct dmub_rb_cmd_transmitter_query_dp_alt { 5544 struct dmub_cmd_header header; /**< header */ 5545 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5546 }; 5547 5548 struct phy_test_mode { 5549 uint8_t mode; 5550 uint8_t pat0; 5551 uint8_t pad[2]; 5552 }; 5553 5554 /** 5555 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5556 */ 5557 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5558 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5559 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5560 uint8_t lane_num; /**< Number of lanes */ 5561 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5562 struct phy_test_mode test_mode; 5563 enum dmub_phy_fsm_state state; 5564 uint32_t status; 5565 uint8_t pad; 5566 }; 5567 5568 /** 5569 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5570 */ 5571 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5572 struct dmub_cmd_header header; /**< header */ 5573 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5574 }; 5575 5576 /** 5577 * Maximum number of bytes a chunk sent to DMUB for parsing 5578 */ 5579 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5580 5581 /** 5582 * Represent a chunk of CEA blocks sent to DMUB for parsing 5583 */ 5584 struct dmub_cmd_send_edid_cea { 5585 uint16_t offset; /**< offset into the CEA block */ 5586 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5587 uint16_t cea_total_length; /**< total length of the CEA block */ 5588 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5589 uint8_t pad[3]; /**< padding and for future expansion */ 5590 }; 5591 5592 /** 5593 * Result of VSDB parsing from CEA block 5594 */ 5595 struct dmub_cmd_edid_cea_amd_vsdb { 5596 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5597 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5598 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5599 uint16_t min_frame_rate; /**< Maximum frame rate */ 5600 uint16_t max_frame_rate; /**< Minimum frame rate */ 5601 }; 5602 5603 /** 5604 * Result of sending a CEA chunk 5605 */ 5606 struct dmub_cmd_edid_cea_ack { 5607 uint16_t offset; /**< offset of the chunk into the CEA block */ 5608 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5609 uint8_t pad; /**< padding and for future expansion */ 5610 }; 5611 5612 /** 5613 * Specify whether the result is an ACK/NACK or the parsing has finished 5614 */ 5615 enum dmub_cmd_edid_cea_reply_type { 5616 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5617 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5618 }; 5619 5620 /** 5621 * Definition of a DMUB_CMD__EDID_CEA command. 5622 */ 5623 struct dmub_rb_cmd_edid_cea { 5624 struct dmub_cmd_header header; /**< Command header */ 5625 union dmub_cmd_edid_cea_data { 5626 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5627 struct dmub_cmd_edid_cea_output { /**< output with results */ 5628 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5629 union { 5630 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5631 struct dmub_cmd_edid_cea_ack ack; 5632 }; 5633 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5634 } data; /**< Command data */ 5635 5636 }; 5637 5638 /** 5639 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5640 */ 5641 struct dmub_cmd_cable_id_input { 5642 uint8_t phy_inst; /**< phy inst for cable id data */ 5643 }; 5644 5645 /** 5646 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5647 */ 5648 struct dmub_cmd_cable_id_output { 5649 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5650 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5651 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5652 uint8_t RESERVED :2; /**< reserved means not defined */ 5653 }; 5654 5655 /** 5656 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5657 */ 5658 struct dmub_rb_cmd_get_usbc_cable_id { 5659 struct dmub_cmd_header header; /**< Command header */ 5660 /** 5661 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5662 */ 5663 union dmub_cmd_cable_id_data { 5664 struct dmub_cmd_cable_id_input input; /**< Input */ 5665 struct dmub_cmd_cable_id_output output; /**< Output */ 5666 uint8_t output_raw; /**< Raw data output */ 5667 } data; 5668 }; 5669 5670 enum dmub_cmd_fused_io_sub_type { 5671 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5672 DMUB_CMD__FUSED_IO_ABORT = 1, 5673 }; 5674 5675 enum dmub_cmd_fused_request_type { 5676 FUSED_REQUEST_READ, 5677 FUSED_REQUEST_WRITE, 5678 FUSED_REQUEST_POLL, 5679 }; 5680 5681 enum dmub_cmd_fused_request_status { 5682 FUSED_REQUEST_STATUS_SUCCESS, 5683 FUSED_REQUEST_STATUS_BEGIN, 5684 FUSED_REQUEST_STATUS_SUBMIT, 5685 FUSED_REQUEST_STATUS_REPLY, 5686 FUSED_REQUEST_STATUS_POLL, 5687 FUSED_REQUEST_STATUS_ABORTED, 5688 FUSED_REQUEST_STATUS_FAILED = 0x80, 5689 FUSED_REQUEST_STATUS_INVALID, 5690 FUSED_REQUEST_STATUS_BUSY, 5691 FUSED_REQUEST_STATUS_TIMEOUT, 5692 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5693 }; 5694 5695 struct dmub_cmd_fused_request { 5696 uint8_t status; 5697 uint8_t type : 2; 5698 uint8_t _reserved0 : 3; 5699 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5700 uint8_t identifier; 5701 uint8_t _reserved1; 5702 uint32_t timeout_us; 5703 union dmub_cmd_fused_request_location { 5704 struct dmub_cmd_fused_request_location_i2c { 5705 uint8_t is_aux : 1; // False 5706 uint8_t ddc_line : 3; 5707 uint8_t over_aux : 1; 5708 uint8_t _reserved0 : 3; 5709 uint8_t address; 5710 uint8_t offset; 5711 uint8_t length; 5712 } i2c; 5713 struct dmub_cmd_fused_request_location_aux { 5714 uint32_t is_aux : 1; // True 5715 uint32_t ddc_line : 3; 5716 uint32_t address : 20; 5717 uint32_t length : 8; // Automatically split into 16B transactions 5718 } aux; 5719 } u; 5720 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5721 }; 5722 5723 struct dmub_rb_cmd_fused_io { 5724 struct dmub_cmd_header header; 5725 struct dmub_cmd_fused_request request; 5726 }; 5727 5728 /** 5729 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5730 */ 5731 enum dmub_cmd_secure_display_type { 5732 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5733 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5734 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5735 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5736 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5737 }; 5738 5739 #define MAX_ROI_NUM 2 5740 5741 struct dmub_cmd_roi_info { 5742 uint16_t x_start; 5743 uint16_t x_end; 5744 uint16_t y_start; 5745 uint16_t y_end; 5746 uint8_t otg_id; 5747 uint8_t phy_id; 5748 }; 5749 5750 struct dmub_cmd_roi_window_ctl { 5751 uint16_t x_start; 5752 uint16_t x_end; 5753 uint16_t y_start; 5754 uint16_t y_end; 5755 bool enable; 5756 }; 5757 5758 struct dmub_cmd_roi_ctl_info { 5759 uint8_t otg_id; 5760 uint8_t phy_id; 5761 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5762 }; 5763 5764 /** 5765 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5766 */ 5767 struct dmub_rb_cmd_secure_display { 5768 struct dmub_cmd_header header; 5769 /** 5770 * Data passed from driver to dmub firmware. 5771 */ 5772 struct dmub_cmd_roi_info roi_info; 5773 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5774 }; 5775 5776 /** 5777 * Command type of a DMUB_CMD__PSP command 5778 */ 5779 enum dmub_cmd_psp_type { 5780 DMUB_CMD__PSP_ASSR_ENABLE = 0 5781 }; 5782 5783 /** 5784 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5785 */ 5786 struct dmub_cmd_assr_enable_data { 5787 /** 5788 * ASSR enable or disable. 5789 */ 5790 uint8_t enable; 5791 /** 5792 * PHY port type. 5793 * Indicates eDP / non-eDP port type 5794 */ 5795 uint8_t phy_port_type; 5796 /** 5797 * PHY port ID. 5798 */ 5799 uint8_t phy_port_id; 5800 /** 5801 * Link encoder index. 5802 */ 5803 uint8_t link_enc_index; 5804 /** 5805 * HPO mode. 5806 */ 5807 uint8_t hpo_mode; 5808 5809 /** 5810 * Reserved field. 5811 */ 5812 uint8_t reserved[7]; 5813 }; 5814 5815 /** 5816 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5817 */ 5818 struct dmub_rb_cmd_assr_enable { 5819 /** 5820 * Command header. 5821 */ 5822 struct dmub_cmd_header header; 5823 5824 /** 5825 * Assr data. 5826 */ 5827 struct dmub_cmd_assr_enable_data assr_data; 5828 5829 /** 5830 * Reserved field. 5831 */ 5832 uint32_t reserved[3]; 5833 }; 5834 5835 /** 5836 * union dmub_rb_cmd - DMUB inbox command. 5837 */ 5838 union dmub_rb_cmd { 5839 /** 5840 * Elements shared with all commands. 5841 */ 5842 struct dmub_rb_cmd_common cmd_common; 5843 /** 5844 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 5845 */ 5846 struct dmub_rb_cmd_read_modify_write read_modify_write; 5847 /** 5848 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 5849 */ 5850 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 5851 /** 5852 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 5853 */ 5854 struct dmub_rb_cmd_burst_write burst_write; 5855 /** 5856 * Definition of a DMUB_CMD__REG_REG_WAIT command. 5857 */ 5858 struct dmub_rb_cmd_reg_wait reg_wait; 5859 /** 5860 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 5861 */ 5862 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 5863 /** 5864 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 5865 */ 5866 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 5867 /** 5868 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 5869 */ 5870 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 5871 /** 5872 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 5873 */ 5874 struct dmub_rb_cmd_dpphy_init dpphy_init; 5875 /** 5876 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 5877 */ 5878 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 5879 /** 5880 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 5881 */ 5882 struct dmub_rb_cmd_domain_control domain_control; 5883 /** 5884 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 5885 */ 5886 struct dmub_rb_cmd_psr_set_version psr_set_version; 5887 /** 5888 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 5889 */ 5890 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 5891 /** 5892 * Definition of a DMUB_CMD__PSR_ENABLE command. 5893 */ 5894 struct dmub_rb_cmd_psr_enable psr_enable; 5895 /** 5896 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 5897 */ 5898 struct dmub_rb_cmd_psr_set_level psr_set_level; 5899 /** 5900 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 5901 */ 5902 struct dmub_rb_cmd_psr_force_static psr_force_static; 5903 /** 5904 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 5905 */ 5906 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 5907 /** 5908 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 5909 */ 5910 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 5911 /** 5912 * Definition of a DMUB_CMD__HW_LOCK command. 5913 * Command is used by driver and FW. 5914 */ 5915 struct dmub_rb_cmd_lock_hw lock_hw; 5916 /** 5917 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 5918 */ 5919 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 5920 /** 5921 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 5922 */ 5923 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 5924 /** 5925 * Definition of a DMUB_CMD__PLAT_54186_WA command. 5926 */ 5927 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 5928 /** 5929 * Definition of a DMUB_CMD__MALL command. 5930 */ 5931 struct dmub_rb_cmd_mall mall; 5932 5933 /** 5934 * Definition of a DMUB_CMD__CAB command. 5935 */ 5936 struct dmub_rb_cmd_cab_for_ss cab; 5937 5938 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 5939 5940 /** 5941 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 5942 */ 5943 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 5944 5945 /** 5946 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 5947 */ 5948 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 5949 5950 /** 5951 * Definition of DMUB_CMD__PANEL_CNTL commands. 5952 */ 5953 struct dmub_rb_cmd_panel_cntl panel_cntl; 5954 5955 /** 5956 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 5957 */ 5958 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 5959 5960 /** 5961 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5962 */ 5963 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 5964 5965 /** 5966 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5967 */ 5968 struct dmub_rb_cmd_abm_set_level abm_set_level; 5969 5970 /** 5971 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5972 */ 5973 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 5974 5975 /** 5976 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5977 */ 5978 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 5979 5980 /** 5981 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5982 */ 5983 struct dmub_rb_cmd_abm_init_config abm_init_config; 5984 5985 /** 5986 * Definition of a DMUB_CMD__ABM_PAUSE command. 5987 */ 5988 struct dmub_rb_cmd_abm_pause abm_pause; 5989 5990 /** 5991 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5992 */ 5993 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 5994 5995 /** 5996 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5997 */ 5998 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 5999 6000 /** 6001 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6002 */ 6003 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6004 6005 /** 6006 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6007 */ 6008 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6009 6010 /** 6011 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6012 */ 6013 struct dmub_rb_cmd_abm_set_event abm_set_event; 6014 6015 /** 6016 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6017 */ 6018 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6019 6020 /** 6021 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6022 */ 6023 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6024 6025 /** 6026 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6027 */ 6028 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6029 6030 /** 6031 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6032 */ 6033 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6034 struct dmub_rb_cmd_drr_update drr_update; 6035 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6036 6037 /** 6038 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6039 */ 6040 struct dmub_rb_cmd_lvtma_control lvtma_control; 6041 /** 6042 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6043 */ 6044 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6045 /** 6046 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6047 */ 6048 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6049 /** 6050 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6051 */ 6052 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6053 /** 6054 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6055 */ 6056 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6057 /** 6058 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6059 */ 6060 struct dmub_rb_cmd_set_config_request set_config_request; 6061 /** 6062 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6063 */ 6064 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6065 /** 6066 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6067 */ 6068 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6069 /** 6070 * Definition of a DMUB_CMD__EDID_CEA command. 6071 */ 6072 struct dmub_rb_cmd_edid_cea edid_cea; 6073 /** 6074 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6075 */ 6076 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6077 6078 /** 6079 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6080 */ 6081 struct dmub_rb_cmd_query_hpd_state query_hpd; 6082 /** 6083 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6084 */ 6085 struct dmub_rb_cmd_secure_display secure_display; 6086 6087 /** 6088 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6089 */ 6090 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6091 /** 6092 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6093 */ 6094 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6095 /** 6096 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6097 */ 6098 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6099 /* 6100 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6101 */ 6102 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6103 /** 6104 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6105 */ 6106 struct dmub_rb_cmd_replay_enable replay_enable; 6107 /** 6108 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6109 */ 6110 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6111 /** 6112 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6113 */ 6114 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6115 /** 6116 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6117 */ 6118 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6119 6120 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6121 /** 6122 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6123 */ 6124 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6125 /** 6126 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6127 */ 6128 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6129 /** 6130 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6131 */ 6132 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6133 /** 6134 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6135 */ 6136 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6137 /** 6138 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6139 */ 6140 struct dmub_rb_cmd_assr_enable assr_enable; 6141 6142 struct dmub_rb_cmd_fams2 fams2_config; 6143 6144 struct dmub_rb_cmd_ib ib_fams2_config; 6145 6146 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6147 6148 struct dmub_rb_cmd_fams2_flip fams2_flip; 6149 6150 struct dmub_rb_cmd_fused_io fused_io; 6151 6152 /** 6153 * Definition of a DMUB_CMD__LSDMA command. 6154 */ 6155 struct dmub_rb_cmd_lsdma lsdma; 6156 }; 6157 6158 /** 6159 * union dmub_rb_out_cmd - Outbox command 6160 */ 6161 union dmub_rb_out_cmd { 6162 /** 6163 * Parameters common to every command. 6164 */ 6165 struct dmub_rb_cmd_common cmd_common; 6166 /** 6167 * AUX reply command. 6168 */ 6169 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6170 /** 6171 * HPD notify command. 6172 */ 6173 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6174 /** 6175 * SET_CONFIG reply command. 6176 */ 6177 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6178 /** 6179 * DPIA notification command. 6180 */ 6181 struct dmub_rb_cmd_dpia_notification dpia_notification; 6182 /** 6183 * HPD sense notification command. 6184 */ 6185 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6186 struct dmub_rb_cmd_fused_io fused_io; 6187 }; 6188 #pragma pack(pop) 6189 6190 6191 //============================================================================== 6192 //</DMUB_CMD>=================================================================== 6193 //============================================================================== 6194 //< DMUB_RB>==================================================================== 6195 //============================================================================== 6196 6197 /** 6198 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6199 */ 6200 struct dmub_rb_init_params { 6201 void *ctx; /**< Caller provided context pointer */ 6202 void *base_address; /**< CPU base address for ring's data */ 6203 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6204 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6205 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6206 }; 6207 6208 /** 6209 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6210 */ 6211 struct dmub_rb { 6212 void *base_address; /**< CPU address for the ring's data */ 6213 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6214 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6215 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6216 6217 void *ctx; /**< Caller provided context pointer */ 6218 void *dmub; /**< Pointer to the DMUB interface */ 6219 }; 6220 6221 /** 6222 * @brief Checks if the ringbuffer is empty. 6223 * 6224 * @param rb DMUB Ringbuffer 6225 * @return true if empty 6226 * @return false otherwise 6227 */ 6228 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6229 { 6230 return (rb->wrpt == rb->rptr); 6231 } 6232 6233 /** 6234 * @brief gets number of outstanding requests in the RB 6235 * 6236 * @param rb DMUB Ringbuffer 6237 * @return true if full 6238 */ 6239 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6240 { 6241 uint32_t data_count; 6242 6243 if (rb->wrpt >= rb->rptr) 6244 data_count = rb->wrpt - rb->rptr; 6245 else 6246 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6247 6248 return data_count / DMUB_RB_CMD_SIZE; 6249 } 6250 6251 /** 6252 * @brief gets number of free buffers in the RB 6253 * 6254 * @param rb DMUB Ringbuffer 6255 * @return true if full 6256 */ 6257 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6258 { 6259 uint32_t data_count; 6260 6261 if (rb->wrpt >= rb->rptr) 6262 data_count = rb->wrpt - rb->rptr; 6263 else 6264 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6265 6266 /* +1 because 1 entry is always unusable */ 6267 data_count += DMUB_RB_CMD_SIZE; 6268 6269 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6270 } 6271 6272 /** 6273 * @brief Checks if the ringbuffer is full 6274 * 6275 * @param rb DMUB Ringbuffer 6276 * @return true if full 6277 * @return false otherwise 6278 */ 6279 static inline bool dmub_rb_full(struct dmub_rb *rb) 6280 { 6281 uint32_t data_count; 6282 6283 if (rb->wrpt >= rb->rptr) 6284 data_count = rb->wrpt - rb->rptr; 6285 else 6286 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6287 6288 /* -1 because 1 entry is always unusable */ 6289 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6290 } 6291 6292 /** 6293 * @brief Pushes a command into the ringbuffer 6294 * 6295 * @param rb DMUB ringbuffer 6296 * @param cmd The command to push 6297 * @return true if the ringbuffer was not full 6298 * @return false otherwise 6299 */ 6300 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6301 const union dmub_rb_cmd *cmd) 6302 { 6303 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6304 const uint64_t *src = (const uint64_t *)cmd; 6305 uint8_t i; 6306 6307 if (dmub_rb_full(rb)) 6308 return false; 6309 6310 // copying data 6311 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6312 *dst++ = *src++; 6313 6314 rb->wrpt += DMUB_RB_CMD_SIZE; 6315 6316 if (rb->wrpt >= rb->capacity) 6317 rb->wrpt %= rb->capacity; 6318 6319 return true; 6320 } 6321 6322 /** 6323 * @brief Pushes a command into the DMUB outbox ringbuffer 6324 * 6325 * @param rb DMUB outbox ringbuffer 6326 * @param cmd Outbox command 6327 * @return true if not full 6328 * @return false otherwise 6329 */ 6330 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6331 const union dmub_rb_out_cmd *cmd) 6332 { 6333 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6334 const uint8_t *src = (const uint8_t *)cmd; 6335 6336 if (dmub_rb_full(rb)) 6337 return false; 6338 6339 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6340 6341 rb->wrpt += DMUB_RB_CMD_SIZE; 6342 6343 if (rb->wrpt >= rb->capacity) 6344 rb->wrpt %= rb->capacity; 6345 6346 return true; 6347 } 6348 6349 /** 6350 * @brief Returns the next unprocessed command in the ringbuffer. 6351 * 6352 * @param rb DMUB ringbuffer 6353 * @param cmd The command to return 6354 * @return true if not empty 6355 * @return false otherwise 6356 */ 6357 static inline bool dmub_rb_front(struct dmub_rb *rb, 6358 union dmub_rb_cmd **cmd) 6359 { 6360 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6361 6362 if (dmub_rb_empty(rb)) 6363 return false; 6364 6365 *cmd = (union dmub_rb_cmd *)rb_cmd; 6366 6367 return true; 6368 } 6369 6370 /** 6371 * @brief Determines the next ringbuffer offset. 6372 * 6373 * @param rb DMUB inbox ringbuffer 6374 * @param num_cmds Number of commands 6375 * @param next_rptr The next offset in the ringbuffer 6376 */ 6377 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6378 uint32_t num_cmds, 6379 uint32_t *next_rptr) 6380 { 6381 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6382 6383 if (*next_rptr >= rb->capacity) 6384 *next_rptr %= rb->capacity; 6385 } 6386 6387 /** 6388 * @brief Returns a pointer to a command in the inbox. 6389 * 6390 * @param rb DMUB inbox ringbuffer 6391 * @param cmd The inbox command to return 6392 * @param rptr The ringbuffer offset 6393 * @return true if not empty 6394 * @return false otherwise 6395 */ 6396 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6397 union dmub_rb_cmd **cmd, 6398 uint32_t rptr) 6399 { 6400 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6401 6402 if (dmub_rb_empty(rb)) 6403 return false; 6404 6405 *cmd = (union dmub_rb_cmd *)rb_cmd; 6406 6407 return true; 6408 } 6409 6410 /** 6411 * @brief Returns the next unprocessed command in the outbox. 6412 * 6413 * @param rb DMUB outbox ringbuffer 6414 * @param cmd The outbox command to return 6415 * @return true if not empty 6416 * @return false otherwise 6417 */ 6418 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6419 union dmub_rb_out_cmd *cmd) 6420 { 6421 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6422 uint64_t *dst = (uint64_t *)cmd; 6423 uint8_t i; 6424 6425 if (dmub_rb_empty(rb)) 6426 return false; 6427 6428 // copying data 6429 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6430 *dst++ = *src++; 6431 6432 return true; 6433 } 6434 6435 /** 6436 * @brief Removes the front entry in the ringbuffer. 6437 * 6438 * @param rb DMUB ringbuffer 6439 * @return true if the command was removed 6440 * @return false if there were no commands 6441 */ 6442 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6443 { 6444 if (dmub_rb_empty(rb)) 6445 return false; 6446 6447 rb->rptr += DMUB_RB_CMD_SIZE; 6448 6449 if (rb->rptr >= rb->capacity) 6450 rb->rptr %= rb->capacity; 6451 6452 return true; 6453 } 6454 6455 /** 6456 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6457 * 6458 * Avoids a race condition where DMCUB accesses memory while 6459 * there are still writes in flight to framebuffer. 6460 * 6461 * @param rb DMUB ringbuffer 6462 */ 6463 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6464 { 6465 uint32_t rptr = rb->rptr; 6466 uint32_t wptr = rb->wrpt; 6467 6468 while (rptr != wptr) { 6469 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6470 uint8_t i; 6471 6472 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6473 (void)READ_ONCE(*data++); 6474 6475 rptr += DMUB_RB_CMD_SIZE; 6476 if (rptr >= rb->capacity) 6477 rptr %= rb->capacity; 6478 } 6479 } 6480 6481 /** 6482 * @brief Initializes a DMCUB ringbuffer 6483 * 6484 * @param rb DMUB ringbuffer 6485 * @param init_params initial configuration for the ringbuffer 6486 */ 6487 static inline void dmub_rb_init(struct dmub_rb *rb, 6488 struct dmub_rb_init_params *init_params) 6489 { 6490 rb->base_address = init_params->base_address; 6491 rb->capacity = init_params->capacity; 6492 rb->rptr = init_params->read_ptr; 6493 rb->wrpt = init_params->write_ptr; 6494 } 6495 6496 /** 6497 * @brief Copies output data from in/out commands into the given command. 6498 * 6499 * @param rb DMUB ringbuffer 6500 * @param cmd Command to copy data into 6501 */ 6502 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6503 union dmub_rb_cmd *cmd) 6504 { 6505 // Copy rb entry back into command 6506 uint8_t *rd_ptr = (rb->rptr == 0) ? 6507 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6508 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6509 6510 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6511 } 6512 6513 //============================================================================== 6514 //</DMUB_RB>==================================================================== 6515 //============================================================================== 6516 #endif /* _DMUB_CMD_H_ */ 6517