1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DMUB_CMD_H 27 #define DMUB_CMD_H 28 29 #include <asm/byteorder.h> 30 #include <linux/types.h> 31 #include <linux/string.h> 32 #include <linux/delay.h> 33 34 #include "atomfirmware.h" 35 36 //<DMUB_TYPES>================================================================== 37 /* Basic type definitions. */ 38 39 #ifdef __forceinline 40 #undef __forceinline 41 #endif 42 #define __forceinline inline 43 44 /** 45 * Flag from driver to indicate that ABM should be disabled gradually 46 * by slowly reversing all backlight programming and pixel compensation. 47 */ 48 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0 49 50 /** 51 * Flag from driver to indicate that ABM should be disabled immediately 52 * and undo all backlight programming and pixel compensation. 53 */ 54 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255 55 56 /** 57 * Flag from driver to indicate that ABM should be disabled immediately 58 * and keep the current backlight programming and pixel compensation. 59 */ 60 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254 61 62 /** 63 * Flag from driver to set the current ABM pipe index or ABM operating level. 64 */ 65 #define SET_ABM_PIPE_NORMAL 1 66 67 /** 68 * Number of ambient light levels in ABM algorithm. 69 */ 70 #define NUM_AMBI_LEVEL 5 71 72 /** 73 * Number of operating/aggression levels in ABM algorithm. 74 */ 75 #define NUM_AGGR_LEVEL 4 76 77 /** 78 * Number of segments in the gamma curve. 79 */ 80 #define NUM_POWER_FN_SEGS 8 81 82 /** 83 * Number of segments in the backlight curve. 84 */ 85 #define NUM_BL_CURVE_SEGS 16 86 87 /** 88 * Maximum number of segments in ABM ACE curve. 89 */ 90 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 91 92 /** 93 * Maximum number of bins in ABM histogram. 94 */ 95 #define ABM_MAX_NUM_OF_HG_BINS 64 96 97 /* Maximum number of SubVP streams */ 98 #define DMUB_MAX_SUBVP_STREAMS 2 99 100 /* Define max FPO streams as 4 for now. Current implementation today 101 * only supports 1, but could be more in the future. Reduce array 102 * size to ensure the command size remains less than 64 bytes if 103 * adding new fields. 104 */ 105 #define DMUB_MAX_FPO_STREAMS 4 106 107 /* Define to ensure that the "common" members always appear in the same 108 * order in different structs for back compat purposes 109 */ 110 #define COMMON_STREAM_STATIC_SUB_STATE \ 111 struct dmub_fams2_cmd_legacy_stream_static_state legacy; \ 112 struct dmub_fams2_cmd_subvp_stream_static_state subvp; \ 113 struct dmub_fams2_cmd_drr_stream_static_state drr; 114 115 /* Maximum number of streams on any ASIC. */ 116 #define DMUB_MAX_STREAMS 6 117 118 /* Maximum number of planes on any ASIC. */ 119 #define DMUB_MAX_PLANES 6 120 121 /* Maximum number of phantom planes on any ASIC */ 122 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) 123 124 /* Trace buffer offset for entry */ 125 #define TRACE_BUFFER_ENTRY_OFFSET 16 126 127 /** 128 * Maximum number of dirty rects supported by FW. 129 */ 130 #define DMUB_MAX_DIRTY_RECTS 3 131 132 /** 133 * 134 * PSR control version legacy 135 */ 136 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0 137 /** 138 * PSR control version with multi edp support 139 */ 140 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1 141 142 143 /** 144 * ABM control version legacy 145 */ 146 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0 147 148 /** 149 * ABM control version with multi edp support 150 */ 151 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1 152 153 /** 154 * Physical framebuffer address location, 64-bit. 155 */ 156 #ifndef PHYSICAL_ADDRESS_LOC 157 #define PHYSICAL_ADDRESS_LOC union large_integer 158 #endif 159 160 /** 161 * OS/FW agnostic memcpy 162 */ 163 #ifndef dmub_memcpy 164 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes)) 165 #endif 166 167 /** 168 * OS/FW agnostic memset 169 */ 170 #ifndef dmub_memset 171 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) 172 #endif 173 174 /** 175 * OS/FW agnostic memcmp 176 */ 177 #ifndef dmub_memcmp 178 #define dmub_memcmp(lhs, rhs, bytes) memcmp((lhs), (rhs), (bytes)) 179 #endif 180 181 /** 182 * OS/FW agnostic udelay 183 */ 184 #ifndef dmub_udelay 185 #define dmub_udelay(microseconds) udelay(microseconds) 186 #endif 187 188 #pragma pack(push, 1) 189 #define ABM_NUM_OF_ACE_SEGMENTS 5 190 191 /** 192 * Debug FW state offset 193 */ 194 #define DMUB_DEBUG_FW_STATE_OFFSET 0x300 195 196 union abm_flags { 197 struct { 198 /** 199 * @abm_enabled: Indicates if ABM is enabled. 200 */ 201 unsigned int abm_enabled : 1; 202 203 /** 204 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled. 205 */ 206 unsigned int disable_abm_requested : 1; 207 208 /** 209 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately. 210 */ 211 unsigned int disable_abm_immediately : 1; 212 213 /** 214 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM 215 * to be disabled immediately and keep gain. 216 */ 217 unsigned int disable_abm_immediate_keep_gain : 1; 218 219 /** 220 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled. 221 */ 222 unsigned int fractional_pwm : 1; 223 224 /** 225 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment 226 * of user backlight level. 227 */ 228 unsigned int abm_gradual_bl_change : 1; 229 230 /** 231 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady 232 */ 233 unsigned int abm_new_frame : 1; 234 235 /** 236 * @vb_scaling_enabled: Indicates variBright Scaling Enable 237 */ 238 unsigned int vb_scaling_enabled : 1; 239 } bitfields; 240 241 unsigned int u32All; 242 }; 243 244 struct abm_save_restore { 245 /** 246 * @flags: Misc. ABM flags. 247 */ 248 union abm_flags flags; 249 250 /** 251 * @pause: true: pause ABM and get state 252 * false: unpause ABM after setting state 253 */ 254 uint32_t pause; 255 256 /** 257 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13) 258 */ 259 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS]; 260 261 /** 262 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6) 263 */ 264 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS]; 265 266 /** 267 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6) 268 */ 269 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS]; 270 271 272 /** 273 * @knee_threshold: Current x-position of ACE knee (u0.16). 274 */ 275 uint32_t knee_threshold; 276 /** 277 * @current_gain: Current backlight reduction (u16.16). 278 */ 279 uint32_t current_gain; 280 /** 281 * @curr_bl_level: Current actual backlight level converging to target backlight level. 282 */ 283 uint16_t curr_bl_level; 284 285 /** 286 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user. 287 */ 288 uint16_t curr_user_bl_level; 289 290 }; 291 292 /** 293 * union dmub_addr - DMUB physical/virtual 64-bit address. 294 */ 295 union dmub_addr { 296 struct { 297 uint32_t low_part; /**< Lower 32 bits */ 298 uint32_t high_part; /**< Upper 32 bits */ 299 } u; /*<< Low/high bit access */ 300 uint64_t quad_part; /*<< 64 bit address */ 301 }; 302 303 /* Flattened structure containing SOC BB parameters stored in the VBIOS 304 * It is not practical to store the entire bounding box in VBIOS since the bounding box struct can gain new parameters. 305 * This also prevents alighment issues when new parameters are added to the SoC BB. 306 * The following parameters should be added since these values can't be obtained elsewhere: 307 * -dml2_soc_power_management_parameters 308 * -dml2_soc_vmin_clock_limits 309 */ 310 struct dmub_soc_bb_params { 311 uint32_t dram_clk_change_blackout_ns; 312 uint32_t dram_clk_change_read_only_ns; 313 uint32_t dram_clk_change_write_only_ns; 314 uint32_t fclk_change_blackout_ns; 315 uint32_t g7_ppt_blackout_ns; 316 uint32_t stutter_enter_plus_exit_latency_ns; 317 uint32_t stutter_exit_latency_ns; 318 uint32_t z8_stutter_enter_plus_exit_latency_ns; 319 uint32_t z8_stutter_exit_latency_ns; 320 uint32_t z8_min_idle_time_ns; 321 uint32_t type_b_dram_clk_change_blackout_ns; 322 uint32_t type_b_ppt_blackout_ns; 323 uint32_t vmin_limit_dispclk_khz; 324 uint32_t vmin_limit_dcfclk_khz; 325 uint32_t g7_temperature_read_blackout_ns; 326 }; 327 #pragma pack(pop) 328 329 /** 330 * Dirty rect definition. 331 */ 332 struct dmub_rect { 333 /** 334 * Dirty rect x offset. 335 */ 336 uint32_t x; 337 338 /** 339 * Dirty rect y offset. 340 */ 341 uint32_t y; 342 343 /** 344 * Dirty rect width. 345 */ 346 uint32_t width; 347 348 /** 349 * Dirty rect height. 350 */ 351 uint32_t height; 352 }; 353 354 /** 355 * Flags that can be set by driver to change some PSR behaviour. 356 */ 357 union dmub_psr_debug_flags { 358 /** 359 * Debug flags. 360 */ 361 struct { 362 /** 363 * Enable visual confirm in FW. 364 */ 365 uint32_t visual_confirm : 1; 366 367 /** 368 * Force all selective updates to bw full frame updates. 369 */ 370 uint32_t force_full_frame_update : 1; 371 372 /** 373 * Use HW Lock Mgr object to do HW locking in FW. 374 */ 375 uint32_t use_hw_lock_mgr : 1; 376 377 /** 378 * Use TPS3 signal when restore main link. 379 */ 380 uint32_t force_wakeup_by_tps3 : 1; 381 382 /** 383 * Back to back flip, therefore cannot power down PHY 384 */ 385 uint32_t back_to_back_flip : 1; 386 387 /** 388 * Enable visual confirm for IPS 389 */ 390 uint32_t enable_ips_visual_confirm : 1; 391 } bitfields; 392 393 /** 394 * Union for debug flags. 395 */ 396 uint32_t u32All; 397 }; 398 399 /** 400 * Flags that can be set by driver to change some Replay behaviour. 401 */ 402 union replay_debug_flags { 403 struct { 404 /** 405 * 0x1 (bit 0) 406 * Enable visual confirm in FW. 407 */ 408 uint32_t visual_confirm : 1; 409 410 /** 411 * 0x2 (bit 1) 412 * @skip_crc: Set if need to skip CRC. 413 */ 414 uint32_t skip_crc : 1; 415 416 /** 417 * 0x4 (bit 2) 418 * @force_link_power_on: Force disable ALPM control 419 */ 420 uint32_t force_link_power_on : 1; 421 422 /** 423 * 0x8 (bit 3) 424 * @force_phy_power_on: Force phy power on 425 */ 426 uint32_t force_phy_power_on : 1; 427 428 /** 429 * 0x10 (bit 4) 430 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync 431 */ 432 uint32_t timing_resync_disabled : 1; 433 434 /** 435 * 0x20 (bit 5) 436 * @skip_crtc_disabled: CRTC disable skipped 437 */ 438 uint32_t skip_crtc_disabled : 1; 439 440 /** 441 * 0x40 (bit 6) 442 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode 443 */ 444 uint32_t force_defer_one_frame_update : 1; 445 446 /** 447 * 0x80 (bit 7) 448 * @disable_delay_alpm_on: Force disable delay alpm on 449 */ 450 uint32_t disable_delay_alpm_on : 1; 451 452 /** 453 * 0x100 (bit 8) 454 * @disable_desync_error_check: Force disable desync error check 455 */ 456 uint32_t disable_desync_error_check : 1; 457 458 /** 459 * 0x200 (bit 9) 460 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady 461 */ 462 uint32_t force_self_update_when_abm_non_steady : 1; 463 464 /** 465 * 0x400 (bit 10) 466 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS 467 * If we enter IPS2, the Visual confirm bar will change to yellow 468 */ 469 uint32_t enable_ips_visual_confirm : 1; 470 471 /** 472 * 0x800 (bit 11) 473 * @enable_ips_residency_profiling: Enable IPS residency profiling 474 */ 475 uint32_t enable_ips_residency_profiling : 1; 476 477 /** 478 * 0x1000 (bit 12) 479 * @enable_coasting_vtotal_check: Enable Coasting_vtotal_check 480 */ 481 uint32_t enable_coasting_vtotal_check : 1; 482 /** 483 * 0x2000 (bit 13) 484 * @enable_visual_confirm_debug: Enable Visual Confirm Debug 485 */ 486 uint32_t enable_visual_confirm_debug : 1; 487 488 uint32_t reserved : 18; 489 } bitfields; 490 491 uint32_t u32All; 492 }; 493 494 /** 495 * Flags record error state. 496 */ 497 union replay_visual_confirm_error_state_flags { 498 struct { 499 /** 500 * 0x1 (bit 0) - Desync Error flag. 501 */ 502 uint32_t desync_error : 1; 503 504 /** 505 * 0x2 (bit 1) - State Transition Error flag. 506 */ 507 uint32_t state_transition_error : 1; 508 509 /** 510 * 0x4 (bit 2) - Crc Error flag 511 */ 512 uint32_t crc_error : 1; 513 514 /** 515 * 0x8 (bit 3) - Reserved 516 */ 517 uint32_t reserved_3 : 1; 518 519 /** 520 * 0x10 (bit 4) - Incorrect Coasting vtotal checking --> use debug flag to control DPCD write. 521 * Added new debug flag to control DPCD. 522 */ 523 uint32_t incorrect_vtotal_in_static_screen : 1; 524 525 /** 526 * 0x20 (bit 5) - No doubled Refresh Rate. 527 */ 528 uint32_t no_double_rr : 1; 529 530 /** 531 * Reserved bit 6-7 532 */ 533 uint32_t reserved_6_7 : 2; 534 535 /** 536 * Reserved bit 9-31 537 */ 538 uint32_t reserved_9_31 : 24; 539 } bitfields; 540 541 uint32_t u32All; 542 }; 543 544 union replay_hw_flags { 545 struct { 546 /** 547 * @allow_alpm_fw_standby_mode: To indicate whether the 548 * ALPM FW standby mode is allowed 549 */ 550 uint32_t allow_alpm_fw_standby_mode : 1; 551 552 /* 553 * @dsc_enable_status: DSC enable status in driver 554 */ 555 uint32_t dsc_enable_status : 1; 556 557 /** 558 * @fec_enable_status: receive fec enable/disable status from driver 559 */ 560 uint32_t fec_enable_status : 1; 561 562 /* 563 * @smu_optimizations_en: SMU power optimization. 564 * Only when active display is Replay capable and display enters Replay. 565 * Trigger interrupt to SMU to powerup/down. 566 */ 567 uint32_t smu_optimizations_en : 1; 568 569 /** 570 * @phy_power_state: Indicates current phy power state 571 */ 572 uint32_t phy_power_state : 1; 573 574 /** 575 * @link_power_state: Indicates current link power state 576 */ 577 uint32_t link_power_state : 1; 578 /** 579 * Use TPS3 signal when restore main link. 580 */ 581 uint32_t force_wakeup_by_tps3 : 1; 582 /** 583 * @is_alpm_initialized: Indicates whether ALPM is initialized 584 */ 585 uint32_t is_alpm_initialized : 1; 586 587 /** 588 * @alpm_mode: Indicates ALPM mode selected 589 */ 590 uint32_t alpm_mode : 2; 591 } bitfields; 592 593 uint32_t u32All; 594 }; 595 596 union fw_assisted_mclk_switch_version { 597 struct { 598 uint8_t minor : 5; 599 uint8_t major : 3; 600 }; 601 uint8_t ver; 602 }; 603 604 /** 605 * DMUB feature capabilities. 606 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 607 */ 608 struct dmub_feature_caps { 609 /** 610 * Max PSR version supported by FW. 611 */ 612 uint8_t psr; 613 uint8_t fw_assisted_mclk_switch_ver; 614 uint8_t reserved[4]; 615 uint8_t subvp_psr_support; 616 uint8_t gecc_enable; 617 uint8_t replay_supported; 618 uint8_t replay_reserved[3]; 619 uint8_t abm_aux_backlight_support; 620 }; 621 622 struct dmub_visual_confirm_color { 623 /** 624 * Maximum 10 bits color value 625 */ 626 uint16_t color_r_cr; 627 uint16_t color_g_y; 628 uint16_t color_b_cb; 629 uint16_t panel_inst; 630 }; 631 632 //============================================================================== 633 //</DMUB_TYPES>================================================================= 634 //============================================================================== 635 //< DMUB_META>================================================================== 636 //============================================================================== 637 #pragma pack(push, 1) 638 639 /* Magic value for identifying dmub_fw_meta_info */ 640 #define DMUB_FW_META_MAGIC 0x444D5542 641 642 /* Offset from the end of the file to the dmub_fw_meta_info */ 643 #define DMUB_FW_META_OFFSET 0x24 644 645 /** 646 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization 647 */ 648 union dmub_fw_meta_feature_bits { 649 struct { 650 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ 651 uint32_t reserved : 31; 652 } bits; /**< status bits */ 653 uint32_t all; /**< 32-bit access to status bits */ 654 }; 655 656 /** 657 * struct dmub_fw_meta_info - metadata associated with fw binary 658 * 659 * NOTE: This should be considered a stable API. Fields should 660 * not be repurposed or reordered. New fields should be 661 * added instead to extend the structure. 662 * 663 * @magic_value: magic value identifying DMUB firmware meta info 664 * @fw_region_size: size of the firmware state region 665 * @trace_buffer_size: size of the tracebuffer region 666 * @fw_version: the firmware version information 667 * @dal_fw: 1 if the firmware is DAL 668 * @shared_state_size: size of the shared state region in bytes 669 * @shared_state_features: number of shared state features 670 */ 671 struct dmub_fw_meta_info { 672 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */ 673 uint32_t fw_region_size; /**< size of the firmware state region */ 674 uint32_t trace_buffer_size; /**< size of the tracebuffer region */ 675 uint32_t fw_version; /**< the firmware version information */ 676 uint8_t dal_fw; /**< 1 if the firmware is DAL */ 677 uint8_t reserved[3]; /**< padding bits */ 678 uint32_t shared_state_size; /**< size of the shared state region in bytes */ 679 uint16_t shared_state_features; /**< number of shared state features */ 680 uint16_t reserved2; /**< padding bytes */ 681 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ 682 }; 683 684 /** 685 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes 686 */ 687 union dmub_fw_meta { 688 struct dmub_fw_meta_info info; /**< metadata info */ 689 uint8_t reserved[64]; /**< padding bits */ 690 }; 691 692 #pragma pack(pop) 693 694 //============================================================================== 695 //< DMUB Trace Buffer>================================================================ 696 //============================================================================== 697 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED) 698 /** 699 * dmub_trace_code_t - firmware trace code, 32-bits 700 */ 701 typedef uint32_t dmub_trace_code_t; 702 703 /** 704 * struct dmcub_trace_buf_entry - Firmware trace entry 705 */ 706 struct dmcub_trace_buf_entry { 707 dmub_trace_code_t trace_code; /**< trace code for the event */ 708 uint32_t tick_count; /**< the tick count at time of trace */ 709 uint32_t param0; /**< trace defined parameter 0 */ 710 uint32_t param1; /**< trace defined parameter 1 */ 711 }; 712 #endif 713 714 //============================================================================== 715 //< DMUB_STATUS>================================================================ 716 //============================================================================== 717 718 /** 719 * DMCUB scratch registers can be used to determine firmware status. 720 * Current scratch register usage is as follows: 721 * 722 * SCRATCH0: FW Boot Status register 723 * SCRATCH5: LVTMA Status Register 724 * SCRATCH15: FW Boot Options register 725 */ 726 727 /** 728 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0. 729 */ 730 union dmub_fw_boot_status { 731 struct { 732 uint32_t dal_fw : 1; /**< 1 if DAL FW */ 733 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */ 734 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */ 735 uint32_t restore_required : 1; /**< 1 if driver should call restore */ 736 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */ 737 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */ 738 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */ 739 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */ 740 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */ 741 } bits; /**< status bits */ 742 uint32_t all; /**< 32-bit access to status bits */ 743 }; 744 745 /** 746 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0. 747 */ 748 enum dmub_fw_boot_status_bit { 749 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */ 750 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */ 751 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */ 752 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */ 753 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */ 754 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/ 755 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/ 756 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */ 757 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */ 758 }; 759 760 /* Register bit definition for SCRATCH5 */ 761 union dmub_lvtma_status { 762 struct { 763 uint32_t psp_ok : 1; 764 uint32_t edp_on : 1; 765 uint32_t reserved : 30; 766 } bits; 767 uint32_t all; 768 }; 769 770 enum dmub_lvtma_status_bit { 771 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0), 772 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1), 773 }; 774 775 enum dmub_ips_disable_type { 776 DMUB_IPS_ENABLE = 0, 777 DMUB_IPS_DISABLE_ALL = 1, 778 DMUB_IPS_DISABLE_IPS1 = 2, 779 DMUB_IPS_DISABLE_IPS2 = 3, 780 DMUB_IPS_DISABLE_IPS2_Z10 = 4, 781 DMUB_IPS_DISABLE_DYNAMIC = 5, 782 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6, 783 DMUB_IPS_DISABLE_Z8_RETENTION = 7, 784 }; 785 786 enum dmub_ips_rcg_disable_type { 787 DMUB_IPS_RCG_ENABLE = 0, 788 DMUB_IPS0_RCG_DISABLE = 1, 789 DMUB_IPS1_RCG_DISABLE = 2, 790 DMUB_IPS_RCG_DISABLE = 3 791 }; 792 793 enum dmub_ips_in_vpb_disable_type { 794 DMUB_IPS_VPB_RCG_ONLY = 0, // Legacy behaviour 795 DMUB_IPS_VPB_DISABLE_ALL = 1, 796 DMUB_IPS_VPB_ENABLE_IPS1_AND_RCG = 2, 797 DMUB_IPS_VPB_ENABLE_ALL = 3 // Enable IPS1 Z8, IPS1 and RCG 798 }; 799 800 #define DMUB_IPS1_ALLOW_MASK 0x00000001 801 #define DMUB_IPS2_ALLOW_MASK 0x00000002 802 #define DMUB_IPS1_COMMIT_MASK 0x00000004 803 #define DMUB_IPS2_COMMIT_MASK 0x00000008 804 805 enum dmub_ips_comand_type { 806 /** 807 * Start/stop IPS residency measurements for a given IPS mode 808 */ 809 DMUB_CMD__IPS_RESIDENCY_CNTL = 0, 810 /** 811 * Query IPS residency information for a given IPS mode 812 */ 813 DMUB_CMD__IPS_QUERY_RESIDENCY_INFO = 1, 814 }; 815 816 /** 817 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14 818 */ 819 union dmub_fw_boot_options { 820 struct { 821 uint32_t pemu_env : 1; /**< 1 if PEMU */ 822 uint32_t fpga_env : 1; /**< 1 if FPGA */ 823 uint32_t optimized_init : 1; /**< 1 if optimized init */ 824 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */ 825 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */ 826 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */ 827 uint32_t z10_disable: 1; /**< 1 to disable z10 */ 828 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */ 829 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */ 830 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */ 831 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */ 832 /**< 1 if all root clock gating is enabled and low power memory is enabled*/ 833 uint32_t power_optimization: 1; 834 uint32_t diag_env: 1; /* 1 if diagnostic environment */ 835 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ 836 uint32_t usb4_cm_version: 1; /**< 1 CM support */ 837 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ 838 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ 839 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ 840 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ 841 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ 842 uint32_t ips_disable: 3; /* options to disable ips support*/ 843 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ 844 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */ 845 uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */ 846 uint32_t reserved : 6; /**< reserved */ 847 } bits; /**< boot bits */ 848 uint32_t all; /**< 32-bit access to bits */ 849 }; 850 851 enum dmub_fw_boot_options_bit { 852 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */ 853 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */ 854 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */ 855 }; 856 857 //============================================================================== 858 //< DMUB_SHARED_STATE>========================================================== 859 //============================================================================== 860 861 /** 862 * Shared firmware state between driver and firmware for lockless communication 863 * in situations where the inbox/outbox may be unavailable. 864 * 865 * Each structure *must* be at most 256-bytes in size. The layout allocation is 866 * described below: 867 * 868 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]... 869 */ 870 871 /** 872 * enum dmub_shared_state_feature_id - List of shared state features. 873 */ 874 enum dmub_shared_state_feature_id { 875 DMUB_SHARED_SHARE_FEATURE__INVALID = 0, 876 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1, 877 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2, 878 DMUB_SHARED_SHARE_FEATURE__DEBUG_SETUP = 3, 879 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */ 880 }; 881 882 /** 883 * struct dmub_shared_state_ips_fw - Firmware signals for IPS. 884 */ 885 union dmub_shared_state_ips_fw_signals { 886 struct { 887 uint32_t ips1_commit : 1; /**< 1 if in IPS1 or IPS0 RCG */ 888 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ 889 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ 890 uint32_t detection_required : 1; /**< 1 if detection is required */ 891 uint32_t ips1z8_commit: 1; /**< 1 if in IPS1 Z8 Retention */ 892 uint32_t reserved_bits : 27; /**< Reversed */ 893 } bits; 894 uint32_t all; 895 }; 896 897 /** 898 * struct dmub_shared_state_ips_signals - Firmware signals for IPS. 899 */ 900 union dmub_shared_state_ips_driver_signals { 901 struct { 902 uint32_t allow_pg : 1; /**< 1 if PG is allowed */ 903 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ 904 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ 905 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ 906 uint32_t allow_idle: 1; /**< 1 if driver is allowing idle */ 907 uint32_t allow_ips0_rcg : 1; /**< 1 is IPS0 RCG is allowed */ 908 uint32_t allow_ips1_rcg : 1; /**< 1 is IPS1 RCG is allowed */ 909 uint32_t allow_ips1z8 : 1; /**< 1 is IPS1 Z8 Retention is allowed */ 910 uint32_t allow_dynamic_ips1 : 1; /**< 1 if IPS1 is allowed in dynamic use cases such as VPB */ 911 uint32_t allow_dynamic_ips1_z8: 1; /**< 1 if IPS1 z8 ret is allowed in dynamic use cases such as VPB */ 912 uint32_t reserved_bits : 22; /**< Reversed bits */ 913 } bits; 914 uint32_t all; 915 }; 916 917 /** 918 * IPS FW Version 919 */ 920 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1 921 922 struct dmub_shared_state_debug_setup { 923 union { 924 struct { 925 uint32_t exclude_points[62]; 926 } profile_mode; 927 }; 928 }; 929 930 /** 931 * struct dmub_shared_state_ips_fw - Firmware state for IPS. 932 */ 933 struct dmub_shared_state_ips_fw { 934 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */ 935 uint32_t rcg_entry_count; /**< Entry counter for RCG */ 936 uint32_t rcg_exit_count; /**< Exit counter for RCG */ 937 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */ 938 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */ 939 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */ 940 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */ 941 uint32_t ips1_z8ret_entry_count; /**< Entry counter for IPS1 Z8 Retention */ 942 uint32_t ips1_z8ret_exit_count; /**< Exit counter for IPS1 Z8 Retention */ 943 uint32_t reserved[53]; /**< Reversed, to be updated when adding new fields. */ 944 }; /* 248-bytes, fixed */ 945 946 /** 947 * IPS Driver Version 948 */ 949 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1 950 951 /** 952 * struct dmub_shared_state_ips_driver - Driver state for IPS. 953 */ 954 struct dmub_shared_state_ips_driver { 955 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */ 956 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */ 957 }; /* 248-bytes, fixed */ 958 959 /** 960 * enum dmub_shared_state_feature_common - Generic payload. 961 */ 962 struct dmub_shared_state_feature_common { 963 uint32_t padding[62]; 964 }; /* 248-bytes, fixed */ 965 966 /** 967 * enum dmub_shared_state_feature_header - Feature description. 968 */ 969 struct dmub_shared_state_feature_header { 970 uint16_t id; /**< Feature ID */ 971 uint16_t version; /**< Feature version */ 972 uint32_t reserved; /**< Reserved bytes. */ 973 }; /* 8 bytes, fixed */ 974 975 /** 976 * struct dmub_shared_state_feature_block - Feature block. 977 */ 978 struct dmub_shared_state_feature_block { 979 struct dmub_shared_state_feature_header header; /**< Shared state header. */ 980 union dmub_shared_feature_state_union { 981 struct dmub_shared_state_feature_common common; /**< Generic data */ 982 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */ 983 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */ 984 struct dmub_shared_state_debug_setup debug_setup; /**< Debug setup */ 985 } data; /**< Shared state data. */ 986 }; /* 256-bytes, fixed */ 987 988 /** 989 * Shared state size in bytes. 990 */ 991 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \ 992 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block)) 993 994 //============================================================================== 995 //</DMUB_STATUS>================================================================ 996 //============================================================================== 997 //< DMUB_VBIOS>================================================================= 998 //============================================================================== 999 1000 /* 1001 * enum dmub_cmd_vbios_type - VBIOS commands. 1002 * 1003 * Command IDs should be treated as stable ABI. 1004 * Do not reuse or modify IDs. 1005 */ 1006 enum dmub_cmd_vbios_type { 1007 /** 1008 * Configures the DIG encoder. 1009 */ 1010 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0, 1011 /** 1012 * Controls the PHY. 1013 */ 1014 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1, 1015 /** 1016 * Sets the pixel clock/symbol clock. 1017 */ 1018 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2, 1019 /** 1020 * Enables or disables power gating. 1021 */ 1022 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3, 1023 /** 1024 * Controls embedded panels. 1025 */ 1026 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15, 1027 /** 1028 * Query DP alt status on a transmitter. 1029 */ 1030 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26, 1031 /** 1032 * Control PHY FSM 1033 */ 1034 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29, 1035 /** 1036 * Controls domain power gating 1037 */ 1038 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28, 1039 }; 1040 1041 //============================================================================== 1042 //</DMUB_VBIOS>================================================================= 1043 //============================================================================== 1044 //< DMUB_GPINT>================================================================= 1045 //============================================================================== 1046 1047 /** 1048 * The shifts and masks below may alternatively be used to format and read 1049 * the command register bits. 1050 */ 1051 1052 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF 1053 #define DMUB_GPINT_DATA_PARAM_SHIFT 0 1054 1055 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF 1056 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16 1057 1058 #define DMUB_GPINT_DATA_STATUS_MASK 0xF 1059 #define DMUB_GPINT_DATA_STATUS_SHIFT 28 1060 1061 /** 1062 * Command responses. 1063 */ 1064 1065 /** 1066 * Return response for DMUB_GPINT__STOP_FW command. 1067 */ 1068 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD 1069 1070 /** 1071 * union dmub_gpint_data_register - Format for sending a command via the GPINT. 1072 */ 1073 union dmub_gpint_data_register { 1074 struct { 1075 uint32_t param : 16; /**< 16-bit parameter */ 1076 uint32_t command_code : 12; /**< GPINT command */ 1077 uint32_t status : 4; /**< Command status bit */ 1078 } bits; /**< GPINT bit access */ 1079 uint32_t all; /**< GPINT 32-bit access */ 1080 }; 1081 1082 /* 1083 * enum dmub_gpint_command - GPINT command to DMCUB FW 1084 * 1085 * Command IDs should be treated as stable ABI. 1086 * Do not reuse or modify IDs. 1087 */ 1088 enum dmub_gpint_command { 1089 /** 1090 * Invalid command, ignored. 1091 */ 1092 DMUB_GPINT__INVALID_COMMAND = 0, 1093 /** 1094 * DESC: Queries the firmware version. 1095 * RETURN: Firmware version. 1096 */ 1097 DMUB_GPINT__GET_FW_VERSION = 1, 1098 /** 1099 * DESC: Halts the firmware. 1100 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted 1101 */ 1102 DMUB_GPINT__STOP_FW = 2, 1103 /** 1104 * DESC: Get PSR state from FW. 1105 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value. 1106 */ 1107 DMUB_GPINT__GET_PSR_STATE = 7, 1108 /** 1109 * DESC: Notifies DMCUB of the currently active streams. 1110 * ARGS: Stream mask, 1 bit per active stream index. 1111 */ 1112 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8, 1113 /** 1114 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value. 1115 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1116 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1117 * RETURN: PSR residency in milli-percent. 1118 */ 1119 DMUB_GPINT__PSR_RESIDENCY = 9, 1120 1121 /** 1122 * DESC: Notifies DMCUB detection is done so detection required can be cleared. 1123 */ 1124 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12, 1125 1126 /** 1127 * DESC: Get REPLAY state from FW. 1128 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value. 1129 */ 1130 DMUB_GPINT__GET_REPLAY_STATE = 13, 1131 1132 /** 1133 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value. 1134 * ARGS: We can measure residency from various points. The argument will specify the residency mode. 1135 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY. 1136 * RETURN: REPLAY residency in milli-percent. 1137 */ 1138 DMUB_GPINT__REPLAY_RESIDENCY = 14, 1139 1140 /** 1141 * DESC: Copy bounding box to the host. 1142 * ARGS: Version of bounding box to copy 1143 * RETURN: Result of copying bounding box 1144 */ 1145 DMUB_GPINT__BB_COPY = 96, 1146 1147 /** 1148 * DESC: Updates the host addresses bit48~bit63 for bounding box. 1149 * ARGS: The word3 for the 64 bit address 1150 */ 1151 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, 1152 1153 /** 1154 * DESC: Updates the host addresses bit32~bit47 for bounding box. 1155 * ARGS: The word2 for the 64 bit address 1156 */ 1157 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, 1158 1159 /** 1160 * DESC: Updates the host addresses bit16~bit31 for bounding box. 1161 * ARGS: The word1 for the 64 bit address 1162 */ 1163 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, 1164 1165 /** 1166 * DESC: Updates the host addresses bit0~bit15 for bounding box. 1167 * ARGS: The word0 for the 64 bit address 1168 */ 1169 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, 1170 1171 /** 1172 * DESC: Updates the trace buffer lower 32-bit mask. 1173 * ARGS: The new mask 1174 * RETURN: Lower 32-bit mask. 1175 */ 1176 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101, 1177 1178 /** 1179 * DESC: Updates the trace buffer mask bit0~bit15. 1180 * ARGS: The new mask 1181 * RETURN: Lower 32-bit mask. 1182 */ 1183 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102, 1184 1185 /** 1186 * DESC: Updates the trace buffer mask bit16~bit31. 1187 * ARGS: The new mask 1188 * RETURN: Lower 32-bit mask. 1189 */ 1190 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103, 1191 1192 /** 1193 * DESC: Updates the trace buffer mask bit32~bit47. 1194 * ARGS: The new mask 1195 * RETURN: Lower 32-bit mask. 1196 */ 1197 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114, 1198 1199 /** 1200 * DESC: Updates the trace buffer mask bit48~bit63. 1201 * ARGS: The new mask 1202 * RETURN: Lower 32-bit mask. 1203 */ 1204 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115, 1205 1206 /** 1207 * DESC: Read the trace buffer mask bi0~bit15. 1208 */ 1209 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116, 1210 1211 /** 1212 * DESC: Read the trace buffer mask bit16~bit31. 1213 */ 1214 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117, 1215 1216 /** 1217 * DESC: Read the trace buffer mask bi32~bit47. 1218 */ 1219 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118, 1220 1221 /** 1222 * DESC: Updates the trace buffer mask bit32~bit63. 1223 */ 1224 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, 1225 1226 /** 1227 * DESC: Set IPS residency measurement 1228 * ARGS: 0 - Disable ips measurement 1229 * 1 - Enable ips measurement 1230 */ 1231 DMUB_GPINT__IPS_RESIDENCY = 121, 1232 1233 /** 1234 * DESC: Enable measurements for various task duration 1235 * ARGS: 0 - Disable measurement 1236 * 1 - Enable measurement 1237 */ 1238 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, 1239 1240 /** 1241 * DESC: Gets IPS residency in microseconds 1242 * ARGS: 0 - Return IPS1 residency 1243 * 1 - Return IPS2 residency 1244 * 2 - Return IPS1_RCG residency 1245 * 3 - Return IPS1_ONO2_ON residency 1246 * RETURN: Total residency in microseconds - lower 32 bits 1247 */ 1248 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, 1249 1250 /** 1251 * DESC: Gets IPS1 histogram counts 1252 * ARGS: Bucket index 1253 * RETURN: Total count for the bucket 1254 */ 1255 DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, 1256 1257 /** 1258 * DESC: Gets IPS2 histogram counts 1259 * ARGS: Bucket index 1260 * RETURN: Total count for the bucket 1261 */ 1262 DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, 1263 1264 /** 1265 * DESC: Gets IPS residency 1266 * ARGS: 0 - Return IPS1 residency 1267 * 1 - Return IPS2 residency 1268 * 2 - Return IPS1_RCG residency 1269 * 3 - Return IPS1_ONO2_ON residency 1270 * RETURN: Total residency in milli-percent. 1271 */ 1272 DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, 1273 1274 /** 1275 * DESC: Gets IPS1_RCG histogram counts 1276 * ARGS: Bucket index 1277 * RETURN: Total count for the bucket 1278 */ 1279 DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, 1280 1281 /** 1282 * DESC: Gets IPS1_ONO2_ON histogram counts 1283 * ARGS: Bucket index 1284 * RETURN: Total count for the bucket 1285 */ 1286 DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, 1287 1288 /** 1289 * DESC: Gets IPS entry counter during residency measurement 1290 * ARGS: 0 - Return IPS1 entry counts 1291 * 1 - Return IPS2 entry counts 1292 * 2 - Return IPS1_RCG entry counts 1293 * 3 - Return IPS2_ONO2_ON entry counts 1294 * RETURN: Entry counter for selected IPS mode 1295 */ 1296 DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, 1297 1298 /** 1299 * DESC: Gets IPS inactive residency in microseconds 1300 * ARGS: 0 - Return IPS1_MAX residency 1301 * 1 - Return IPS2 residency 1302 * 2 - Return IPS1_RCG residency 1303 * 3 - Return IPS1_ONO2_ON residency 1304 * RETURN: Total inactive residency in microseconds - lower 32 bits 1305 */ 1306 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, 1307 1308 /** 1309 * DESC: Gets IPS inactive residency in microseconds 1310 * ARGS: 0 - Return IPS1_MAX residency 1311 * 1 - Return IPS2 residency 1312 * 2 - Return IPS1_RCG residency 1313 * 3 - Return IPS1_ONO2_ON residency 1314 * RETURN: Total inactive residency in microseconds - upper 32 bits 1315 */ 1316 DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, 1317 1318 /** 1319 * DESC: Gets IPS residency in microseconds 1320 * ARGS: 0 - Return IPS1 residency 1321 * 1 - Return IPS2 residency 1322 * 2 - Return IPS1_RCG residency 1323 * 3 - Return IPS1_ONO2_ON residency 1324 * RETURN: Total residency in microseconds - upper 32 bits 1325 */ 1326 DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, 1327 /** 1328 * DESC: Setup debug configs. 1329 */ 1330 DMUB_GPINT__SETUP_DEBUG_MODE = 136, 1331 /** 1332 * DESC: Initiates IPS wake sequence. 1333 */ 1334 DMUB_GPINT__IPS_DEBUG_WAKE = 137, 1335 }; 1336 1337 /** 1338 * INBOX0 generic command definition 1339 */ 1340 union dmub_inbox0_cmd_common { 1341 struct { 1342 uint32_t command_code: 8; /**< INBOX0 command code */ 1343 uint32_t param: 24; /**< 24-bit parameter */ 1344 } bits; 1345 uint32_t all; 1346 }; 1347 1348 /** 1349 * INBOX0 hw_lock command definition 1350 */ 1351 union dmub_inbox0_cmd_lock_hw { 1352 struct { 1353 uint32_t command_code: 8; 1354 1355 /* NOTE: Must be have enough bits to match: enum hw_lock_client */ 1356 uint32_t hw_lock_client: 2; 1357 1358 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */ 1359 uint32_t otg_inst: 3; 1360 uint32_t opp_inst: 3; 1361 uint32_t dig_inst: 3; 1362 1363 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */ 1364 uint32_t lock_pipe: 1; 1365 uint32_t lock_cursor: 1; 1366 uint32_t lock_dig: 1; 1367 uint32_t triple_buffer_lock: 1; 1368 1369 uint32_t lock: 1; /**< Lock */ 1370 uint32_t should_release: 1; /**< Release */ 1371 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */ 1372 } bits; 1373 uint32_t all; 1374 }; 1375 1376 union dmub_inbox0_data_register { 1377 union dmub_inbox0_cmd_common inbox0_cmd_common; 1378 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw; 1379 }; 1380 1381 enum dmub_inbox0_command { 1382 /** 1383 * DESC: Invalid command, ignored. 1384 */ 1385 DMUB_INBOX0_CMD__INVALID_COMMAND = 0, 1386 /** 1387 * DESC: Notification to acquire/release HW lock 1388 * ARGS: 1389 */ 1390 DMUB_INBOX0_CMD__HW_LOCK = 1, 1391 }; 1392 //============================================================================== 1393 //</DMUB_GPINT>================================================================= 1394 //============================================================================== 1395 //< DMUB_CMD>=================================================================== 1396 //============================================================================== 1397 1398 /** 1399 * Size in bytes of each DMUB command. 1400 */ 1401 #define DMUB_RB_CMD_SIZE 64 1402 1403 /** 1404 * Maximum number of items in the DMUB ringbuffer. 1405 */ 1406 #define DMUB_RB_MAX_ENTRY 128 1407 1408 /** 1409 * Ringbuffer size in bytes. 1410 */ 1411 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY) 1412 1413 /** 1414 * Maximum number of items in the DMUB REG INBOX0 internal ringbuffer. 1415 */ 1416 #define DMUB_REG_INBOX0_RB_MAX_ENTRY 16 1417 1418 /** 1419 * Ringbuffer size in bytes. 1420 */ 1421 #define DMUB_REG_INBOX0_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_REG_INBOX0_RB_MAX_ENTRY) 1422 1423 /** 1424 * REG_SET mask for reg offload. 1425 */ 1426 #define REG_SET_MASK 0xFFFF 1427 1428 /* 1429 * enum dmub_cmd_type - DMUB inbox command. 1430 * 1431 * Command IDs should be treated as stable ABI. 1432 * Do not reuse or modify IDs. 1433 */ 1434 enum dmub_cmd_type { 1435 /** 1436 * Invalid command. 1437 */ 1438 DMUB_CMD__NULL = 0, 1439 /** 1440 * Read modify write register sequence offload. 1441 */ 1442 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1, 1443 /** 1444 * Field update register sequence offload. 1445 */ 1446 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2, 1447 /** 1448 * Burst write sequence offload. 1449 */ 1450 DMUB_CMD__REG_SEQ_BURST_WRITE = 3, 1451 /** 1452 * Reg wait sequence offload. 1453 */ 1454 DMUB_CMD__REG_REG_WAIT = 4, 1455 /** 1456 * Workaround to avoid HUBP underflow during NV12 playback. 1457 */ 1458 DMUB_CMD__PLAT_54186_WA = 5, 1459 /** 1460 * Command type used to query FW feature caps. 1461 */ 1462 DMUB_CMD__QUERY_FEATURE_CAPS = 6, 1463 /** 1464 * Command type used to get visual confirm color. 1465 */ 1466 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8, 1467 /** 1468 * Command type used for all PSR commands. 1469 */ 1470 DMUB_CMD__PSR = 64, 1471 /** 1472 * Command type used for all MALL commands. 1473 */ 1474 DMUB_CMD__MALL = 65, 1475 /** 1476 * Command type used for all ABM commands. 1477 */ 1478 DMUB_CMD__ABM = 66, 1479 /** 1480 * Command type used to update dirty rects in FW. 1481 */ 1482 DMUB_CMD__UPDATE_DIRTY_RECT = 67, 1483 /** 1484 * Command type used to update cursor info in FW. 1485 */ 1486 DMUB_CMD__UPDATE_CURSOR_INFO = 68, 1487 /** 1488 * Command type used for HW locking in FW. 1489 */ 1490 DMUB_CMD__HW_LOCK = 69, 1491 /** 1492 * Command type used to access DP AUX. 1493 */ 1494 DMUB_CMD__DP_AUX_ACCESS = 70, 1495 /** 1496 * Command type used for OUTBOX1 notification enable 1497 */ 1498 DMUB_CMD__OUTBOX1_ENABLE = 71, 1499 1500 /** 1501 * Command type used for all idle optimization commands. 1502 */ 1503 DMUB_CMD__IDLE_OPT = 72, 1504 /** 1505 * Command type used for all clock manager commands. 1506 */ 1507 DMUB_CMD__CLK_MGR = 73, 1508 /** 1509 * Command type used for all panel control commands. 1510 */ 1511 DMUB_CMD__PANEL_CNTL = 74, 1512 1513 /** 1514 * Command type used for all CAB commands. 1515 */ 1516 DMUB_CMD__CAB_FOR_SS = 75, 1517 1518 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76, 1519 1520 /** 1521 * Command type used for interfacing with DPIA. 1522 */ 1523 DMUB_CMD__DPIA = 77, 1524 /** 1525 * Command type used for EDID CEA parsing 1526 */ 1527 DMUB_CMD__EDID_CEA = 79, 1528 /** 1529 * Command type used for getting usbc cable ID 1530 */ 1531 DMUB_CMD_GET_USBC_CABLE_ID = 81, 1532 /** 1533 * Command type used to query HPD state. 1534 */ 1535 DMUB_CMD__QUERY_HPD_STATE = 82, 1536 /** 1537 * Command type used for all VBIOS interface commands. 1538 */ 1539 /** 1540 * Command type used for all REPLAY commands. 1541 */ 1542 DMUB_CMD__REPLAY = 83, 1543 1544 /** 1545 * Command type used for all SECURE_DISPLAY commands. 1546 */ 1547 DMUB_CMD__SECURE_DISPLAY = 85, 1548 1549 /** 1550 * Command type used to set DPIA HPD interrupt state 1551 */ 1552 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86, 1553 1554 /** 1555 * Command type used for all PSP commands. 1556 */ 1557 DMUB_CMD__PSP = 88, 1558 1559 /** 1560 * Command type used for all Fused IO commands. 1561 */ 1562 DMUB_CMD__FUSED_IO = 89, 1563 1564 /** 1565 * Command type used for all LSDMA commands. 1566 */ 1567 DMUB_CMD__LSDMA = 90, 1568 1569 /** 1570 * Command type use for all IPS commands. 1571 */ 1572 DMUB_CMD__IPS = 91, 1573 1574 DMUB_CMD__VBIOS = 128, 1575 }; 1576 1577 /** 1578 * enum dmub_out_cmd_type - DMUB outbox commands. 1579 */ 1580 enum dmub_out_cmd_type { 1581 /** 1582 * Invalid outbox command, ignored. 1583 */ 1584 DMUB_OUT_CMD__NULL = 0, 1585 /** 1586 * Command type used for DP AUX Reply data notification 1587 */ 1588 DMUB_OUT_CMD__DP_AUX_REPLY = 1, 1589 /** 1590 * Command type used for DP HPD event notification 1591 */ 1592 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2, 1593 /** 1594 * Command type used for SET_CONFIG Reply notification 1595 */ 1596 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3, 1597 /** 1598 * Command type used for USB4 DPIA notification 1599 */ 1600 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5, 1601 /** 1602 * Command type used for HPD redetect notification 1603 */ 1604 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6, 1605 /** 1606 * Command type used for Fused IO notification 1607 */ 1608 DMUB_OUT_CMD__FUSED_IO = 7, 1609 }; 1610 1611 /* DMUB_CMD__DPIA command sub-types. */ 1612 enum dmub_cmd_dpia_type { 1613 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, 1614 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST 1615 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, 1616 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, 1617 DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, 1618 }; 1619 1620 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ 1621 enum dmub_cmd_dpia_notification_type { 1622 DPIA_NOTIFY__BW_ALLOCATION = 0, 1623 }; 1624 1625 #pragma pack(push, 1) 1626 1627 /** 1628 * struct dmub_cmd_header - Common command header fields. 1629 */ 1630 struct dmub_cmd_header { 1631 unsigned int type : 8; /**< command type */ 1632 unsigned int sub_type : 8; /**< command sub type */ 1633 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */ 1634 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */ 1635 unsigned int is_reg_based : 1; /**< 1 if register based mailbox cmd, 0 if FB based cmd */ 1636 unsigned int reserved0 : 5; /**< reserved bits */ 1637 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */ 1638 unsigned int reserved1 : 2; /**< reserved bits */ 1639 }; 1640 1641 /* 1642 * struct dmub_cmd_read_modify_write_sequence - Read modify write 1643 * 1644 * 60 payload bytes can hold up to 5 sets of read modify writes, 1645 * each take 3 dwords. 1646 * 1647 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence) 1648 * 1649 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case 1650 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write 1651 */ 1652 struct dmub_cmd_read_modify_write_sequence { 1653 uint32_t addr; /**< register address */ 1654 uint32_t modify_mask; /**< modify mask */ 1655 uint32_t modify_value; /**< modify value */ 1656 }; 1657 1658 /** 1659 * Maximum number of ops in read modify write sequence. 1660 */ 1661 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5 1662 1663 /** 1664 * struct dmub_cmd_read_modify_write_sequence - Read modify write command. 1665 */ 1666 struct dmub_rb_cmd_read_modify_write { 1667 struct dmub_cmd_header header; /**< command header */ 1668 /** 1669 * Read modify write sequence. 1670 */ 1671 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX]; 1672 }; 1673 1674 /* 1675 * Update a register with specified masks and values sequeunce 1676 * 1677 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword 1678 * 1679 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence) 1680 * 1681 * 1682 * USE CASE: 1683 * 1. auto-increment register where additional read would update pointer and produce wrong result 1684 * 2. toggle a bit without read in the middle 1685 */ 1686 1687 struct dmub_cmd_reg_field_update_sequence { 1688 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */ 1689 uint32_t modify_value; /**< value to update with */ 1690 }; 1691 1692 /** 1693 * Maximum number of ops in field update sequence. 1694 */ 1695 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7 1696 1697 /** 1698 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command. 1699 */ 1700 struct dmub_rb_cmd_reg_field_update_sequence { 1701 struct dmub_cmd_header header; /**< command header */ 1702 uint32_t addr; /**< register address */ 1703 /** 1704 * Field update sequence. 1705 */ 1706 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX]; 1707 }; 1708 1709 1710 /** 1711 * Maximum number of burst write values. 1712 */ 1713 #define DMUB_BURST_WRITE_VALUES__MAX 14 1714 1715 /* 1716 * struct dmub_rb_cmd_burst_write - Burst write 1717 * 1718 * support use case such as writing out LUTs. 1719 * 1720 * 60 payload bytes can hold up to 14 values to write to given address 1721 * 1722 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence) 1723 */ 1724 struct dmub_rb_cmd_burst_write { 1725 struct dmub_cmd_header header; /**< command header */ 1726 uint32_t addr; /**< register start address */ 1727 /** 1728 * Burst write register values. 1729 */ 1730 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX]; 1731 }; 1732 1733 /** 1734 * struct dmub_rb_cmd_common - Common command header 1735 */ 1736 struct dmub_rb_cmd_common { 1737 struct dmub_cmd_header header; /**< command header */ 1738 /** 1739 * Padding to RB_CMD_SIZE 1740 */ 1741 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)]; 1742 }; 1743 1744 /** 1745 * struct dmub_cmd_reg_wait_data - Register wait data 1746 */ 1747 struct dmub_cmd_reg_wait_data { 1748 uint32_t addr; /**< Register address */ 1749 uint32_t mask; /**< Mask for register bits */ 1750 uint32_t condition_field_value; /**< Value to wait for */ 1751 uint32_t time_out_us; /**< Time out for reg wait in microseconds */ 1752 }; 1753 1754 /** 1755 * struct dmub_rb_cmd_reg_wait - Register wait command 1756 */ 1757 struct dmub_rb_cmd_reg_wait { 1758 struct dmub_cmd_header header; /**< Command header */ 1759 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */ 1760 }; 1761 1762 /** 1763 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround 1764 * 1765 * Reprograms surface parameters to avoid underflow. 1766 */ 1767 struct dmub_cmd_PLAT_54186_wa { 1768 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */ 1769 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */ 1770 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */ 1771 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */ 1772 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */ 1773 struct { 1774 uint32_t hubp_inst : 4; /**< HUBP instance */ 1775 uint32_t tmz_surface : 1; /**< TMZ enable or disable */ 1776 uint32_t immediate :1; /**< Immediate flip */ 1777 uint32_t vmid : 4; /**< VMID */ 1778 uint32_t grph_stereo : 1; /**< 1 if stereo */ 1779 uint32_t reserved : 21; /**< Reserved */ 1780 } flip_params; /**< Pageflip parameters */ 1781 uint32_t reserved[9]; /**< Reserved bits */ 1782 }; 1783 1784 /** 1785 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command 1786 */ 1787 struct dmub_rb_cmd_PLAT_54186_wa { 1788 struct dmub_cmd_header header; /**< Command header */ 1789 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */ 1790 }; 1791 1792 /** 1793 * enum dmub_cmd_mall_type - MALL commands 1794 */ 1795 enum dmub_cmd_mall_type { 1796 /** 1797 * Allows display refresh from MALL. 1798 */ 1799 DMUB_CMD__MALL_ACTION_ALLOW = 0, 1800 /** 1801 * Disallows display refresh from MALL. 1802 */ 1803 DMUB_CMD__MALL_ACTION_DISALLOW = 1, 1804 /** 1805 * Cursor copy for MALL. 1806 */ 1807 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2, 1808 /** 1809 * Controls DF requests. 1810 */ 1811 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3, 1812 }; 1813 1814 /** 1815 * struct dmub_rb_cmd_mall - MALL command data. 1816 */ 1817 struct dmub_rb_cmd_mall { 1818 struct dmub_cmd_header header; /**< Common command header */ 1819 union dmub_addr cursor_copy_src; /**< Cursor copy address */ 1820 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */ 1821 uint32_t tmr_delay; /**< Timer delay */ 1822 uint32_t tmr_scale; /**< Timer scale */ 1823 uint16_t cursor_width; /**< Cursor width in pixels */ 1824 uint16_t cursor_pitch; /**< Cursor pitch in pixels */ 1825 uint16_t cursor_height; /**< Cursor height in pixels */ 1826 uint8_t cursor_bpp; /**< Cursor bits per pixel */ 1827 uint8_t debug_bits; /**< Debug bits */ 1828 1829 uint8_t reserved1; /**< Reserved bits */ 1830 uint8_t reserved2; /**< Reserved bits */ 1831 }; 1832 1833 /** 1834 * enum dmub_cmd_cab_type - CAB command data. 1835 */ 1836 enum dmub_cmd_cab_type { 1837 /** 1838 * No idle optimizations (i.e. no CAB) 1839 */ 1840 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0, 1841 /** 1842 * No DCN requests for memory 1843 */ 1844 DMUB_CMD__CAB_NO_DCN_REQ = 1, 1845 /** 1846 * Fit surfaces in CAB (i.e. CAB enable) 1847 */ 1848 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2, 1849 /** 1850 * Do not fit surfaces in CAB (i.e. no CAB) 1851 */ 1852 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3, 1853 }; 1854 1855 /** 1856 * struct dmub_rb_cmd_cab - CAB command data. 1857 */ 1858 struct dmub_rb_cmd_cab_for_ss { 1859 struct dmub_cmd_header header; 1860 uint8_t cab_alloc_ways; /* total number of ways */ 1861 uint8_t debug_bits; /* debug bits */ 1862 }; 1863 1864 /** 1865 * Enum for indicating which MCLK switch mode per pipe 1866 */ 1867 enum mclk_switch_mode { 1868 NONE = 0, 1869 FPO = 1, 1870 SUBVP = 2, 1871 VBLANK = 3, 1872 }; 1873 1874 /* Per pipe struct which stores the MCLK switch mode 1875 * data to be sent to DMUB. 1876 * Named "v2" for now -- once FPO and SUBVP are fully merged 1877 * the type name can be updated 1878 */ 1879 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 { 1880 union { 1881 struct { 1882 uint32_t pix_clk_100hz; 1883 uint16_t main_vblank_start; 1884 uint16_t main_vblank_end; 1885 uint16_t mall_region_lines; 1886 uint16_t prefetch_lines; 1887 uint16_t prefetch_to_mall_start_lines; 1888 uint16_t processing_delay_lines; 1889 uint16_t htotal; // required to calculate line time for multi-display cases 1890 uint16_t vtotal; 1891 uint8_t main_pipe_index; 1892 uint8_t phantom_pipe_index; 1893 /* Since the microschedule is calculated in terms of OTG lines, 1894 * include any scaling factors to make sure when we get accurate 1895 * conversion when programming MALL_START_LINE (which is in terms 1896 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor 1897 * is 1/2 (numerator = 1, denominator = 2). 1898 */ 1899 uint8_t scale_factor_numerator; 1900 uint8_t scale_factor_denominator; 1901 uint8_t is_drr; 1902 uint8_t main_split_pipe_index; 1903 uint8_t phantom_split_pipe_index; 1904 } subvp_data; 1905 1906 struct { 1907 uint32_t pix_clk_100hz; 1908 uint16_t vblank_start; 1909 uint16_t vblank_end; 1910 uint16_t vstartup_start; 1911 uint16_t vtotal; 1912 uint16_t htotal; 1913 uint8_t vblank_pipe_index; 1914 uint8_t padding[1]; 1915 struct { 1916 uint8_t drr_in_use; 1917 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame 1918 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK 1919 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling 1920 uint8_t use_ramping; // Use ramping or not 1921 uint8_t drr_vblank_start_margin; 1922 } drr_info; // DRR considered as part of SubVP + VBLANK case 1923 } vblank_data; 1924 } pipe_config; 1925 1926 /* - subvp_data in the union (pipe_config) takes up 27 bytes. 1927 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only 1928 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state). 1929 */ 1930 uint8_t mode; // enum mclk_switch_mode 1931 }; 1932 1933 /** 1934 * Config data for Sub-VP and FPO 1935 * Named "v2" for now -- once FPO and SUBVP are fully merged 1936 * the type name can be updated 1937 */ 1938 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 { 1939 uint16_t watermark_a_cache; 1940 uint8_t vertical_int_margin_us; 1941 uint8_t pstate_allow_width_us; 1942 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS]; 1943 }; 1944 1945 /** 1946 * DMUB rb command definition for Sub-VP and FPO 1947 * Named "v2" for now -- once FPO and SUBVP are fully merged 1948 * the type name can be updated 1949 */ 1950 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { 1951 struct dmub_cmd_header header; 1952 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; 1953 }; 1954 1955 struct dmub_flip_addr_info { 1956 uint32_t surf_addr_lo; 1957 uint32_t surf_addr_c_lo; 1958 uint32_t meta_addr_lo; 1959 uint32_t meta_addr_c_lo; 1960 uint16_t surf_addr_hi; 1961 uint16_t surf_addr_c_hi; 1962 uint16_t meta_addr_hi; 1963 uint16_t meta_addr_c_hi; 1964 }; 1965 1966 struct dmub_fams2_flip_info { 1967 union { 1968 struct { 1969 uint8_t is_immediate: 1; 1970 } bits; 1971 uint8_t all; 1972 } config; 1973 uint8_t otg_inst; 1974 uint8_t pipe_mask; 1975 uint8_t pad; 1976 struct dmub_flip_addr_info addr_info; 1977 }; 1978 1979 struct dmub_rb_cmd_fams2_flip { 1980 struct dmub_cmd_header header; 1981 struct dmub_fams2_flip_info flip_info; 1982 }; 1983 1984 struct dmub_cmd_lsdma_data { 1985 union { 1986 struct lsdma_init_data { 1987 union dmub_addr gpu_addr_base; 1988 uint32_t ring_size; 1989 } init_data; 1990 struct lsdma_tiled_copy_data { 1991 uint32_t src_addr_lo; 1992 uint32_t src_addr_hi; 1993 1994 uint32_t dst_addr_lo; 1995 uint32_t dst_addr_hi; 1996 1997 uint32_t src_x : 16; 1998 uint32_t src_y : 16; 1999 2000 uint32_t dst_x : 16; 2001 uint32_t dst_y : 16; 2002 2003 uint32_t src_width : 16; 2004 uint32_t src_height : 16; 2005 2006 uint32_t dst_width : 16; 2007 uint32_t dst_height : 16; 2008 2009 uint32_t rect_x : 16; 2010 uint32_t rect_y : 16; 2011 2012 uint32_t src_swizzle_mode : 5; 2013 uint32_t src_mip_max : 5; 2014 uint32_t src_mip_id : 5; 2015 uint32_t dst_mip_max : 5; 2016 uint32_t dst_swizzle_mode : 5; 2017 uint32_t dst_mip_id : 5; 2018 uint32_t tmz : 1; 2019 uint32_t dcc : 1; 2020 2021 uint32_t data_format : 6; 2022 uint32_t padding1 : 4; 2023 uint32_t dst_element_size : 3; 2024 uint32_t num_type : 3; 2025 uint32_t src_element_size : 3; 2026 uint32_t write_compress : 2; 2027 uint32_t cache_policy_dst : 2; 2028 uint32_t cache_policy_src : 2; 2029 uint32_t read_compress : 2; 2030 uint32_t src_dim : 2; 2031 uint32_t dst_dim : 2; 2032 uint32_t max_uncom : 1; 2033 2034 uint32_t max_com : 2; 2035 uint32_t padding : 30; 2036 } tiled_copy_data; 2037 struct lsdma_linear_copy_data { 2038 uint32_t src_lo; 2039 uint32_t src_hi; 2040 2041 uint32_t dst_lo; 2042 uint32_t dst_hi; 2043 2044 uint32_t count : 30; 2045 uint32_t cache_policy_dst : 2; 2046 2047 uint32_t tmz : 1; 2048 uint32_t cache_policy_src : 2; 2049 uint32_t padding : 29; 2050 } linear_copy_data; 2051 struct lsdma_linear_sub_window_copy_data { 2052 uint32_t src_lo; 2053 uint32_t src_hi; 2054 2055 uint32_t dst_lo; 2056 uint32_t dst_hi; 2057 2058 uint32_t src_x : 16; 2059 uint32_t src_y : 16; 2060 2061 uint32_t dst_x : 16; 2062 uint32_t dst_y : 16; 2063 2064 uint32_t rect_x : 16; 2065 uint32_t rect_y : 16; 2066 2067 uint32_t src_pitch : 16; 2068 uint32_t dst_pitch : 16; 2069 2070 uint32_t src_slice_pitch; 2071 uint32_t dst_slice_pitch; 2072 2073 uint32_t tmz : 1; 2074 uint32_t element_size : 3; 2075 uint32_t src_cache_policy : 3; 2076 uint32_t dst_cache_policy : 3; 2077 uint32_t reserved0 : 22; 2078 } linear_sub_window_copy_data; 2079 struct lsdma_reg_write_data { 2080 uint32_t reg_addr; 2081 uint32_t reg_data; 2082 } reg_write_data; 2083 struct lsdma_pio_copy_data { 2084 uint32_t src_lo; 2085 uint32_t src_hi; 2086 2087 uint32_t dst_lo; 2088 uint32_t dst_hi; 2089 2090 union { 2091 struct { 2092 uint32_t byte_count : 26; 2093 uint32_t src_loc : 1; 2094 uint32_t dst_loc : 1; 2095 uint32_t src_addr_inc : 1; 2096 uint32_t dst_addr_inc : 1; 2097 uint32_t overlap_disable : 1; 2098 uint32_t constant_fill : 1; 2099 } fields; 2100 uint32_t raw; 2101 } packet; 2102 } pio_copy_data; 2103 struct lsdma_pio_constfill_data { 2104 uint32_t dst_lo; 2105 uint32_t dst_hi; 2106 2107 union { 2108 struct { 2109 uint32_t byte_count : 26; 2110 uint32_t src_loc : 1; 2111 uint32_t dst_loc : 1; 2112 uint32_t src_addr_inc : 1; 2113 uint32_t dst_addr_inc : 1; 2114 uint32_t overlap_disable : 1; 2115 uint32_t constant_fill : 1; 2116 } fields; 2117 uint32_t raw; 2118 } packet; 2119 2120 uint32_t data; 2121 } pio_constfill_data; 2122 2123 uint32_t all[14]; 2124 } u; 2125 }; 2126 2127 struct dmub_rb_cmd_lsdma { 2128 struct dmub_cmd_header header; 2129 struct dmub_cmd_lsdma_data lsdma_data; 2130 }; 2131 2132 struct dmub_optc_state_v2 { 2133 uint32_t v_total_min; 2134 uint32_t v_total_max; 2135 uint32_t v_total_mid; 2136 uint32_t v_total_mid_frame_num; 2137 uint8_t program_manual_trigger; 2138 uint8_t tg_inst; 2139 uint8_t pad[2]; 2140 }; 2141 2142 struct dmub_optc_position { 2143 uint32_t vpos; 2144 uint32_t hpos; 2145 uint32_t frame; 2146 }; 2147 2148 struct dmub_rb_cmd_fams2_drr_update { 2149 struct dmub_cmd_header header; 2150 struct dmub_optc_state_v2 dmub_optc_state_req; 2151 }; 2152 2153 /* HW and FW global configuration data for FAMS2 */ 2154 /* FAMS2 types and structs */ 2155 enum fams2_stream_type { 2156 FAMS2_STREAM_TYPE_NONE = 0, 2157 FAMS2_STREAM_TYPE_VBLANK = 1, 2158 FAMS2_STREAM_TYPE_VACTIVE = 2, 2159 FAMS2_STREAM_TYPE_DRR = 3, 2160 FAMS2_STREAM_TYPE_SUBVP = 4, 2161 }; 2162 2163 struct dmub_rect16 { 2164 /** 2165 * Dirty rect x offset. 2166 */ 2167 uint16_t x; 2168 2169 /** 2170 * Dirty rect y offset. 2171 */ 2172 uint16_t y; 2173 2174 /** 2175 * Dirty rect width. 2176 */ 2177 uint16_t width; 2178 2179 /** 2180 * Dirty rect height. 2181 */ 2182 uint16_t height; 2183 }; 2184 2185 /* static stream state */ 2186 struct dmub_fams2_legacy_stream_static_state { 2187 uint8_t vactive_det_fill_delay_otg_vlines; 2188 uint8_t programming_delay_otg_vlines; 2189 }; //v0 2190 2191 struct dmub_fams2_subvp_stream_static_state { 2192 uint16_t vratio_numerator; 2193 uint16_t vratio_denominator; 2194 uint16_t phantom_vtotal; 2195 uint16_t phantom_vactive; 2196 union { 2197 struct { 2198 uint8_t is_multi_planar : 1; 2199 uint8_t is_yuv420 : 1; 2200 } bits; 2201 uint8_t all; 2202 } config; 2203 uint8_t programming_delay_otg_vlines; 2204 uint8_t prefetch_to_mall_otg_vlines; 2205 uint8_t phantom_otg_inst; 2206 uint8_t phantom_pipe_mask; 2207 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2208 }; //v0 2209 2210 struct dmub_fams2_drr_stream_static_state { 2211 uint16_t nom_stretched_vtotal; 2212 uint8_t programming_delay_otg_vlines; 2213 uint8_t only_stretch_if_required; 2214 uint8_t pad[2]; 2215 }; //v0 2216 2217 struct dmub_fams2_cmd_legacy_stream_static_state { 2218 uint16_t vactive_det_fill_delay_otg_vlines; 2219 uint16_t programming_delay_otg_vlines; 2220 }; //v1 2221 2222 struct dmub_fams2_cmd_subvp_stream_static_state { 2223 uint16_t vratio_numerator; 2224 uint16_t vratio_denominator; 2225 uint16_t phantom_vtotal; 2226 uint16_t phantom_vactive; 2227 uint16_t programming_delay_otg_vlines; 2228 uint16_t prefetch_to_mall_otg_vlines; 2229 union { 2230 struct { 2231 uint8_t is_multi_planar : 1; 2232 uint8_t is_yuv420 : 1; 2233 } bits; 2234 uint8_t all; 2235 } config; 2236 uint8_t phantom_otg_inst; 2237 uint8_t phantom_pipe_mask; 2238 uint8_t pad0; 2239 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) 2240 uint8_t pad1[4 - (DMUB_MAX_PHANTOM_PLANES % 4)]; 2241 }; //v1 2242 2243 struct dmub_fams2_cmd_drr_stream_static_state { 2244 uint16_t nom_stretched_vtotal; 2245 uint16_t programming_delay_otg_vlines; 2246 uint8_t only_stretch_if_required; 2247 uint8_t pad[3]; 2248 }; //v1 2249 2250 union dmub_fams2_stream_static_sub_state { 2251 struct dmub_fams2_legacy_stream_static_state legacy; 2252 struct dmub_fams2_subvp_stream_static_state subvp; 2253 struct dmub_fams2_drr_stream_static_state drr; 2254 }; //v0 2255 2256 union dmub_fams2_cmd_stream_static_sub_state { 2257 COMMON_STREAM_STATIC_SUB_STATE 2258 }; //v1 2259 2260 union dmub_fams2_stream_static_sub_state_v2 { 2261 COMMON_STREAM_STATIC_SUB_STATE 2262 }; //v2 2263 2264 struct dmub_fams2_stream_static_state { 2265 enum fams2_stream_type type; 2266 uint32_t otg_vline_time_ns; 2267 uint32_t otg_vline_time_ticks; 2268 uint16_t htotal; 2269 uint16_t vtotal; // nominal vtotal 2270 uint16_t vblank_start; 2271 uint16_t vblank_end; 2272 uint16_t max_vtotal; 2273 uint16_t allow_start_otg_vline; 2274 uint16_t allow_end_otg_vline; 2275 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2276 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2277 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution 2278 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2279 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2280 union { 2281 struct { 2282 uint8_t is_drr: 1; // stream is DRR enabled 2283 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal 2284 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2285 } bits; 2286 uint8_t all; 2287 } config; 2288 uint8_t otg_inst; 2289 uint8_t pipe_mask; // pipe mask for the whole config 2290 uint8_t num_planes; 2291 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2292 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2293 union dmub_fams2_stream_static_sub_state sub_state; 2294 }; //v0 2295 2296 struct dmub_fams2_cmd_stream_static_base_state { 2297 enum fams2_stream_type type; 2298 uint32_t otg_vline_time_ns; 2299 uint32_t otg_vline_time_ticks; 2300 uint16_t htotal; 2301 uint16_t vtotal; // nominal vtotal 2302 uint16_t vblank_start; 2303 uint16_t vblank_end; 2304 uint16_t max_vtotal; 2305 uint16_t allow_start_otg_vline; 2306 uint16_t allow_end_otg_vline; 2307 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed 2308 uint16_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start 2309 uint16_t contention_delay_otg_vlines; // time to budget for contention on execution 2310 uint16_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing 2311 uint16_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline 2312 union { 2313 struct { 2314 uint8_t is_drr : 1; // stream is DRR enabled 2315 uint8_t clamp_vtotal_min : 1; // clamp vtotal to min instead of nominal 2316 uint8_t min_ttu_vblank_usable : 1; // if min ttu vblank is above wm, no force pstate is needed in blank 2317 } bits; 2318 uint8_t all; 2319 } config; 2320 uint8_t otg_inst; 2321 uint8_t pipe_mask; // pipe mask for the whole config 2322 uint8_t num_planes; 2323 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) 2324 uint8_t pad[4 - (DMUB_MAX_PLANES % 4)]; 2325 }; //v1 2326 2327 struct dmub_fams2_stream_static_state_v1 { 2328 struct dmub_fams2_cmd_stream_static_base_state base; 2329 union dmub_fams2_stream_static_sub_state_v2 sub_state; 2330 }; //v1 2331 2332 /** 2333 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive 2334 * p-state request to allow latency 2335 */ 2336 enum dmub_fams2_allow_delay_check_mode { 2337 /* No check for request to allow delay */ 2338 FAMS2_ALLOW_DELAY_CHECK_NONE = 0, 2339 /* Check for request to allow delay */ 2340 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, 2341 /* Check for prepare to allow delay */ 2342 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, 2343 }; 2344 2345 union dmub_fams2_global_feature_config { 2346 struct { 2347 uint32_t enable: 1; 2348 uint32_t enable_ppt_check: 1; 2349 uint32_t enable_stall_recovery: 1; 2350 uint32_t enable_debug: 1; 2351 uint32_t enable_offload_flip: 1; 2352 uint32_t enable_visual_confirm: 1; 2353 uint32_t allow_delay_check_mode: 2; 2354 uint32_t reserved: 24; 2355 } bits; 2356 uint32_t all; 2357 }; 2358 2359 struct dmub_cmd_fams2_global_config { 2360 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin 2361 uint32_t lock_wait_time_us; // time to forecast acquisition of lock 2362 uint32_t num_streams; 2363 union dmub_fams2_global_feature_config features; 2364 uint32_t recovery_timeout_us; 2365 uint32_t hwfq_flip_programming_delay_us; 2366 }; 2367 2368 union dmub_cmd_fams2_config { 2369 struct dmub_cmd_fams2_global_config global; 2370 struct dmub_fams2_stream_static_state stream; //v0 2371 union { 2372 struct dmub_fams2_cmd_stream_static_base_state base; 2373 union dmub_fams2_cmd_stream_static_sub_state sub_state; 2374 } stream_v1; //v1 2375 }; 2376 2377 struct dmub_fams2_config_v2 { 2378 struct dmub_cmd_fams2_global_config global; 2379 struct dmub_fams2_stream_static_state_v1 stream_v1[DMUB_MAX_STREAMS]; //v1 2380 }; 2381 2382 /** 2383 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) 2384 */ 2385 struct dmub_rb_cmd_fams2 { 2386 struct dmub_cmd_header header; 2387 union dmub_cmd_fams2_config config; 2388 }; 2389 2390 /** 2391 * Indirect buffer descriptor 2392 */ 2393 struct dmub_ib_data { 2394 union dmub_addr src; // location of indirect buffer in memory 2395 uint16_t size; // indirect buffer size in bytes 2396 }; 2397 2398 /** 2399 * DMUB rb command definition for commands passed over indirect buffer 2400 */ 2401 struct dmub_rb_cmd_ib { 2402 struct dmub_cmd_header header; 2403 struct dmub_ib_data ib_data; 2404 }; 2405 2406 /** 2407 * enum dmub_cmd_idle_opt_type - Idle optimization command type. 2408 */ 2409 enum dmub_cmd_idle_opt_type { 2410 /** 2411 * DCN hardware restore. 2412 */ 2413 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0, 2414 2415 /** 2416 * DCN hardware save. 2417 */ 2418 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1, 2419 2420 /** 2421 * DCN hardware notify idle. 2422 */ 2423 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, 2424 2425 /** 2426 * DCN hardware notify power state. 2427 */ 2428 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, 2429 2430 /** 2431 * DCN notify to release HW. 2432 */ 2433 DMUB_CMD__IDLE_OPT_RELEASE_HW = 4, 2434 }; 2435 2436 /** 2437 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data. 2438 */ 2439 struct dmub_rb_cmd_idle_opt_dcn_restore { 2440 struct dmub_cmd_header header; /**< header */ 2441 }; 2442 2443 /** 2444 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2445 */ 2446 struct dmub_dcn_notify_idle_cntl_data { 2447 uint8_t driver_idle; 2448 uint8_t skip_otg_disable; 2449 uint8_t reserved[58]; 2450 }; 2451 2452 /** 2453 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 2454 */ 2455 struct dmub_rb_cmd_idle_opt_dcn_notify_idle { 2456 struct dmub_cmd_header header; /**< header */ 2457 struct dmub_dcn_notify_idle_cntl_data cntl_data; 2458 }; 2459 2460 /** 2461 * enum dmub_idle_opt_dc_power_state - DC power states. 2462 */ 2463 enum dmub_idle_opt_dc_power_state { 2464 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, 2465 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, 2466 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, 2467 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, 2468 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, 2469 }; 2470 2471 /** 2472 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2473 */ 2474 struct dmub_idle_opt_set_dc_power_state_data { 2475 uint8_t power_state; /**< power state */ 2476 uint8_t pad[3]; /**< padding */ 2477 }; 2478 2479 /** 2480 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 2481 */ 2482 struct dmub_rb_cmd_idle_opt_set_dc_power_state { 2483 struct dmub_cmd_header header; /**< header */ 2484 struct dmub_idle_opt_set_dc_power_state_data data; 2485 }; 2486 2487 /** 2488 * struct dmub_clocks - Clock update notification. 2489 */ 2490 struct dmub_clocks { 2491 uint32_t dispclk_khz; /**< dispclk kHz */ 2492 uint32_t dppclk_khz; /**< dppclk kHz */ 2493 uint32_t dcfclk_khz; /**< dcfclk kHz */ 2494 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ 2495 }; 2496 2497 /** 2498 * enum dmub_cmd_clk_mgr_type - Clock manager commands. 2499 */ 2500 enum dmub_cmd_clk_mgr_type { 2501 /** 2502 * Notify DMCUB of clock update. 2503 */ 2504 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0, 2505 }; 2506 2507 /** 2508 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification. 2509 */ 2510 struct dmub_rb_cmd_clk_mgr_notify_clocks { 2511 struct dmub_cmd_header header; /**< header */ 2512 struct dmub_clocks clocks; /**< clock data */ 2513 }; 2514 2515 /** 2516 * struct dmub_cmd_digx_encoder_control_data - Encoder control data. 2517 */ 2518 struct dmub_cmd_digx_encoder_control_data { 2519 union dig_encoder_control_parameters_v1_5 dig; /**< payload */ 2520 }; 2521 2522 /** 2523 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command. 2524 */ 2525 struct dmub_rb_cmd_digx_encoder_control { 2526 struct dmub_cmd_header header; /**< header */ 2527 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */ 2528 }; 2529 2530 /** 2531 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data. 2532 */ 2533 struct dmub_cmd_set_pixel_clock_data { 2534 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */ 2535 }; 2536 2537 /** 2538 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command. 2539 */ 2540 struct dmub_rb_cmd_set_pixel_clock { 2541 struct dmub_cmd_header header; /**< header */ 2542 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */ 2543 }; 2544 2545 /** 2546 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating. 2547 */ 2548 struct dmub_cmd_enable_disp_power_gating_data { 2549 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */ 2550 }; 2551 2552 /** 2553 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command. 2554 */ 2555 struct dmub_rb_cmd_enable_disp_power_gating { 2556 struct dmub_cmd_header header; /**< header */ 2557 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */ 2558 }; 2559 2560 /** 2561 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control. 2562 */ 2563 struct dmub_dig_transmitter_control_data_v1_7 { 2564 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 2565 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */ 2566 union { 2567 uint8_t digmode; /**< enum atom_encode_mode_def */ 2568 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ 2569 } mode_laneset; 2570 uint8_t lanenum; /**< Number of lanes */ 2571 union { 2572 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ 2573 } symclk_units; 2574 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ 2575 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ 2576 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ 2577 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ 2578 uint8_t reserved1; /**< For future use */ 2579 uint8_t skip_phy_ssc_reduction; 2580 uint8_t reserved2[2]; /**< For future use */ 2581 uint32_t reserved3[11]; /**< For future use */ 2582 }; 2583 2584 /** 2585 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data. 2586 */ 2587 union dmub_cmd_dig1_transmitter_control_data { 2588 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */ 2589 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */ 2590 }; 2591 2592 /** 2593 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command. 2594 */ 2595 struct dmub_rb_cmd_dig1_transmitter_control { 2596 struct dmub_cmd_header header; /**< header */ 2597 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */ 2598 }; 2599 2600 /** 2601 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control 2602 */ 2603 struct dmub_rb_cmd_domain_control_data { 2604 uint8_t inst : 6; /**< DOMAIN instance to control */ 2605 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */ 2606 uint8_t reserved[3]; /**< Reserved for future use */ 2607 }; 2608 2609 /** 2610 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating 2611 */ 2612 struct dmub_rb_cmd_domain_control { 2613 struct dmub_cmd_header header; /**< header */ 2614 struct dmub_rb_cmd_domain_control_data data; /**< payload */ 2615 }; 2616 2617 /** 2618 * DPIA tunnel command parameters. 2619 */ 2620 struct dmub_cmd_dig_dpia_control_data { 2621 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */ 2622 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */ 2623 union { 2624 uint8_t digmode; /** enum atom_encode_mode_def */ 2625 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */ 2626 } mode_laneset; 2627 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */ 2628 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */ 2629 uint8_t hpdsel; /** =0: HPD is not assigned */ 2630 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */ 2631 uint8_t dpia_id; /** Index of DPIA */ 2632 uint8_t fec_rdy : 1; 2633 uint8_t reserved : 7; 2634 uint32_t reserved1; 2635 }; 2636 2637 /** 2638 * DMUB command for DPIA tunnel control. 2639 */ 2640 struct dmub_rb_cmd_dig1_dpia_control { 2641 struct dmub_cmd_header header; 2642 struct dmub_cmd_dig_dpia_control_data dpia_control; 2643 }; 2644 2645 /** 2646 * SET_CONFIG Command Payload (deprecated) 2647 */ 2648 struct set_config_cmd_payload { 2649 uint8_t msg_type; /* set config message type */ 2650 uint8_t msg_data; /* set config message data */ 2651 }; 2652 2653 /** 2654 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) 2655 */ 2656 struct dmub_cmd_set_config_control_data { 2657 struct set_config_cmd_payload cmd_pkt; 2658 uint8_t instance; /* DPIA instance */ 2659 uint8_t immed_status; /* Immediate status returned in case of error */ 2660 }; 2661 2662 /** 2663 * SET_CONFIG Request Command Payload 2664 */ 2665 struct set_config_request_cmd_payload { 2666 uint8_t instance; /* DPIA instance */ 2667 uint8_t immed_status; /* Immediate status returned in case of error */ 2668 uint8_t msg_type; /* set config message type */ 2669 uint8_t reserved; 2670 uint32_t msg_data; /* set config message data */ 2671 }; 2672 2673 /** 2674 * DMUB command structure for SET_CONFIG command. 2675 */ 2676 struct dmub_rb_cmd_set_config_access { 2677 struct dmub_cmd_header header; /* header */ 2678 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ 2679 }; 2680 2681 /** 2682 * DMUB command structure for SET_CONFIG request command. 2683 */ 2684 struct dmub_rb_cmd_set_config_request { 2685 struct dmub_cmd_header header; /* header */ 2686 struct set_config_request_cmd_payload payload; /* set config request payload */ 2687 }; 2688 2689 /** 2690 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 2691 */ 2692 struct dmub_cmd_mst_alloc_slots_control_data { 2693 uint8_t mst_alloc_slots; /* mst slots to be allotted */ 2694 uint8_t instance; /* DPIA instance */ 2695 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */ 2696 uint8_t mst_slots_in_use; /* returns slots in use for error cases */ 2697 }; 2698 2699 /** 2700 * DMUB command structure for SET_ command. 2701 */ 2702 struct dmub_rb_cmd_set_mst_alloc_slots { 2703 struct dmub_cmd_header header; /* header */ 2704 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ 2705 }; 2706 2707 /** 2708 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. 2709 */ 2710 struct dmub_cmd_tps_notification_data { 2711 uint8_t instance; /* DPIA instance */ 2712 uint8_t tps; /* requested training pattern */ 2713 uint8_t reserved1; 2714 uint8_t reserved2; 2715 }; 2716 2717 /** 2718 * DMUB command structure for SET_TPS_NOTIFICATION command. 2719 */ 2720 struct dmub_rb_cmd_set_tps_notification { 2721 struct dmub_cmd_header header; /* header */ 2722 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ 2723 }; 2724 2725 /** 2726 * DMUB command structure for DPIA HPD int enable control. 2727 */ 2728 struct dmub_rb_cmd_dpia_hpd_int_enable { 2729 struct dmub_cmd_header header; /* header */ 2730 uint32_t enable; /* dpia hpd interrupt enable */ 2731 }; 2732 2733 /** 2734 * struct dmub_rb_cmd_dpphy_init - DPPHY init. 2735 */ 2736 struct dmub_rb_cmd_dpphy_init { 2737 struct dmub_cmd_header header; /**< header */ 2738 uint8_t reserved[60]; /**< reserved bits */ 2739 }; 2740 2741 /** 2742 * enum dp_aux_request_action - DP AUX request command listing. 2743 * 2744 * 4 AUX request command bits are shifted to high nibble. 2745 */ 2746 enum dp_aux_request_action { 2747 /** I2C-over-AUX write request */ 2748 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00, 2749 /** I2C-over-AUX read request */ 2750 DP_AUX_REQ_ACTION_I2C_READ = 0x10, 2751 /** I2C-over-AUX write status request */ 2752 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20, 2753 /** I2C-over-AUX write request with MOT=1 */ 2754 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40, 2755 /** I2C-over-AUX read request with MOT=1 */ 2756 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50, 2757 /** I2C-over-AUX write status request with MOT=1 */ 2758 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60, 2759 /** Native AUX write request */ 2760 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80, 2761 /** Native AUX read request */ 2762 DP_AUX_REQ_ACTION_DPCD_READ = 0x90 2763 }; 2764 2765 /** 2766 * enum aux_return_code_type - DP AUX process return code listing. 2767 */ 2768 enum aux_return_code_type { 2769 /** AUX process succeeded */ 2770 AUX_RET_SUCCESS = 0, 2771 /** AUX process failed with unknown reason */ 2772 AUX_RET_ERROR_UNKNOWN, 2773 /** AUX process completed with invalid reply */ 2774 AUX_RET_ERROR_INVALID_REPLY, 2775 /** AUX process timed out */ 2776 AUX_RET_ERROR_TIMEOUT, 2777 /** HPD was low during AUX process */ 2778 AUX_RET_ERROR_HPD_DISCON, 2779 /** Failed to acquire AUX engine */ 2780 AUX_RET_ERROR_ENGINE_ACQUIRE, 2781 /** AUX request not supported */ 2782 AUX_RET_ERROR_INVALID_OPERATION, 2783 /** AUX process not available */ 2784 AUX_RET_ERROR_PROTOCOL_ERROR, 2785 }; 2786 2787 /** 2788 * enum aux_channel_type - DP AUX channel type listing. 2789 */ 2790 enum aux_channel_type { 2791 /** AUX thru Legacy DP AUX */ 2792 AUX_CHANNEL_LEGACY_DDC, 2793 /** AUX thru DPIA DP tunneling */ 2794 AUX_CHANNEL_DPIA 2795 }; 2796 2797 /** 2798 * struct aux_transaction_parameters - DP AUX request transaction data 2799 */ 2800 struct aux_transaction_parameters { 2801 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */ 2802 uint8_t action; /**< enum dp_aux_request_action */ 2803 uint8_t length; /**< DP AUX request data length */ 2804 uint8_t reserved; /**< For future use */ 2805 uint32_t address; /**< DP AUX address */ 2806 uint8_t data[16]; /**< DP AUX write data */ 2807 }; 2808 2809 /** 2810 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2811 */ 2812 struct dmub_cmd_dp_aux_control_data { 2813 uint8_t instance; /**< AUX instance or DPIA instance */ 2814 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */ 2815 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */ 2816 uint8_t reserved0; /**< For future use */ 2817 uint16_t timeout; /**< timeout time in us */ 2818 uint16_t reserved1; /**< For future use */ 2819 enum aux_channel_type type; /**< enum aux_channel_type */ 2820 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */ 2821 }; 2822 2823 /** 2824 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 2825 */ 2826 struct dmub_rb_cmd_dp_aux_access { 2827 /** 2828 * Command header. 2829 */ 2830 struct dmub_cmd_header header; 2831 /** 2832 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command. 2833 */ 2834 struct dmub_cmd_dp_aux_control_data aux_control; 2835 }; 2836 2837 /** 2838 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 2839 */ 2840 struct dmub_rb_cmd_outbox1_enable { 2841 /** 2842 * Command header. 2843 */ 2844 struct dmub_cmd_header header; 2845 /** 2846 * enable: 0x0 -> disable outbox1 notification (default value) 2847 * 0x1 -> enable outbox1 notification 2848 */ 2849 uint32_t enable; 2850 }; 2851 2852 /* DP AUX Reply command - OutBox Cmd */ 2853 /** 2854 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2855 */ 2856 struct aux_reply_data { 2857 /** 2858 * Aux cmd 2859 */ 2860 uint8_t command; 2861 /** 2862 * Aux reply data length (max: 16 bytes) 2863 */ 2864 uint8_t length; 2865 /** 2866 * Alignment only 2867 */ 2868 uint8_t pad[2]; 2869 /** 2870 * Aux reply data 2871 */ 2872 uint8_t data[16]; 2873 }; 2874 2875 /** 2876 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2877 */ 2878 struct aux_reply_control_data { 2879 /** 2880 * Reserved for future use 2881 */ 2882 uint32_t handle; 2883 /** 2884 * Aux Instance 2885 */ 2886 uint8_t instance; 2887 /** 2888 * Aux transaction result: definition in enum aux_return_code_type 2889 */ 2890 uint8_t result; 2891 /** 2892 * Alignment only 2893 */ 2894 uint16_t pad; 2895 }; 2896 2897 /** 2898 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command. 2899 */ 2900 struct dmub_rb_cmd_dp_aux_reply { 2901 /** 2902 * Command header. 2903 */ 2904 struct dmub_cmd_header header; 2905 /** 2906 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2907 */ 2908 struct aux_reply_control_data control; 2909 /** 2910 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command. 2911 */ 2912 struct aux_reply_data reply_data; 2913 }; 2914 2915 /* DP HPD Notify command - OutBox Cmd */ 2916 /** 2917 * DP HPD Type 2918 */ 2919 enum dp_hpd_type { 2920 /** 2921 * Normal DP HPD 2922 */ 2923 DP_HPD = 0, 2924 /** 2925 * DP HPD short pulse 2926 */ 2927 DP_IRQ = 1, 2928 /** 2929 * Failure to acquire DP HPD state 2930 */ 2931 DP_NONE_HPD = 2 2932 }; 2933 2934 /** 2935 * DP HPD Status 2936 */ 2937 enum dp_hpd_status { 2938 /** 2939 * DP_HPD status low 2940 */ 2941 DP_HPD_UNPLUG = 0, 2942 /** 2943 * DP_HPD status high 2944 */ 2945 DP_HPD_PLUG 2946 }; 2947 2948 /** 2949 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2950 */ 2951 struct dp_hpd_data { 2952 /** 2953 * DP HPD instance 2954 */ 2955 uint8_t instance; 2956 /** 2957 * HPD type 2958 */ 2959 uint8_t hpd_type; 2960 /** 2961 * HPD status: only for type: DP_HPD to indicate status 2962 */ 2963 uint8_t hpd_status; 2964 /** 2965 * Alignment only 2966 */ 2967 uint8_t pad; 2968 }; 2969 2970 /** 2971 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2972 */ 2973 struct dmub_rb_cmd_dp_hpd_notify { 2974 /** 2975 * Command header. 2976 */ 2977 struct dmub_cmd_header header; 2978 /** 2979 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command. 2980 */ 2981 struct dp_hpd_data hpd_data; 2982 }; 2983 2984 /** 2985 * Definition of a SET_CONFIG reply from DPOA. 2986 */ 2987 enum set_config_status { 2988 SET_CONFIG_PENDING = 0, 2989 SET_CONFIG_ACK_RECEIVED, 2990 SET_CONFIG_RX_TIMEOUT, 2991 SET_CONFIG_UNKNOWN_ERROR, 2992 }; 2993 2994 /** 2995 * Definition of a set_config reply 2996 */ 2997 struct set_config_reply_control_data { 2998 uint8_t instance; /* DPIA Instance */ 2999 uint8_t status; /* Set Config reply */ 3000 uint16_t pad; /* Alignment */ 3001 }; 3002 3003 /** 3004 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command. 3005 */ 3006 struct dmub_rb_cmd_dp_set_config_reply { 3007 struct dmub_cmd_header header; 3008 struct set_config_reply_control_data set_config_reply_control; 3009 }; 3010 3011 /** 3012 * Definition of a DPIA notification header 3013 */ 3014 struct dpia_notification_header { 3015 uint8_t instance; /**< DPIA Instance */ 3016 uint8_t reserved[3]; 3017 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */ 3018 }; 3019 3020 /** 3021 * Definition of the common data struct of DPIA notification 3022 */ 3023 struct dpia_notification_common { 3024 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header) 3025 - sizeof(struct dpia_notification_header)]; 3026 }; 3027 3028 /** 3029 * Definition of a DPIA notification data 3030 */ 3031 struct dpia_bw_allocation_notify_data { 3032 union { 3033 struct { 3034 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */ 3035 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */ 3036 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */ 3037 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */ 3038 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */ 3039 uint16_t reserved: 11; /**< Reserved */ 3040 } bits; 3041 3042 uint16_t flags; 3043 }; 3044 3045 uint8_t cm_id; /**< CM ID */ 3046 uint8_t group_id; /**< Group ID */ 3047 uint8_t granularity; /**< BW Allocation Granularity */ 3048 uint8_t estimated_bw; /**< Estimated_BW */ 3049 uint8_t allocated_bw; /**< Allocated_BW */ 3050 uint8_t reserved; 3051 }; 3052 3053 /** 3054 * union dpia_notify_data_type - DPIA Notification in Outbox command 3055 */ 3056 union dpia_notification_data { 3057 /** 3058 * DPIA Notification for common data struct 3059 */ 3060 struct dpia_notification_common common_data; 3061 3062 /** 3063 * DPIA Notification for DP BW Allocation support 3064 */ 3065 struct dpia_bw_allocation_notify_data dpia_bw_alloc; 3066 }; 3067 3068 /** 3069 * Definition of a DPIA notification payload 3070 */ 3071 struct dpia_notification_payload { 3072 struct dpia_notification_header header; 3073 union dpia_notification_data data; /**< DPIA notification payload data */ 3074 }; 3075 3076 /** 3077 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command. 3078 */ 3079 struct dmub_rb_cmd_dpia_notification { 3080 struct dmub_cmd_header header; /**< DPIA notification header */ 3081 struct dpia_notification_payload payload; /**< DPIA notification payload */ 3082 }; 3083 3084 /** 3085 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3086 */ 3087 struct dmub_cmd_hpd_state_query_data { 3088 uint8_t instance; /**< HPD instance or DPIA instance */ 3089 uint8_t result; /**< For returning HPD state */ 3090 uint16_t pad; /** < Alignment */ 3091 enum aux_channel_type ch_type; /**< enum aux_channel_type */ 3092 enum aux_return_code_type status; /**< for returning the status of command */ 3093 }; 3094 3095 /** 3096 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 3097 */ 3098 struct dmub_rb_cmd_query_hpd_state { 3099 /** 3100 * Command header. 3101 */ 3102 struct dmub_cmd_header header; 3103 /** 3104 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command. 3105 */ 3106 struct dmub_cmd_hpd_state_query_data data; 3107 }; 3108 3109 /** 3110 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data. 3111 */ 3112 struct dmub_rb_cmd_hpd_sense_notify_data { 3113 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */ 3114 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */ 3115 }; 3116 3117 /** 3118 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command. 3119 */ 3120 struct dmub_rb_cmd_hpd_sense_notify { 3121 struct dmub_cmd_header header; /**< header */ 3122 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */ 3123 }; 3124 3125 /* 3126 * Command IDs should be treated as stable ABI. 3127 * Do not reuse or modify IDs. 3128 */ 3129 3130 /** 3131 * PSR command sub-types. 3132 */ 3133 enum dmub_cmd_psr_type { 3134 /** 3135 * Set PSR version support. 3136 */ 3137 DMUB_CMD__PSR_SET_VERSION = 0, 3138 /** 3139 * Copy driver-calculated parameters to PSR state. 3140 */ 3141 DMUB_CMD__PSR_COPY_SETTINGS = 1, 3142 /** 3143 * Enable PSR. 3144 */ 3145 DMUB_CMD__PSR_ENABLE = 2, 3146 3147 /** 3148 * Disable PSR. 3149 */ 3150 DMUB_CMD__PSR_DISABLE = 3, 3151 3152 /** 3153 * Set PSR level. 3154 * PSR level is a 16-bit value dicated by driver that 3155 * will enable/disable different functionality. 3156 */ 3157 DMUB_CMD__PSR_SET_LEVEL = 4, 3158 3159 /** 3160 * Forces PSR enabled until an explicit PSR disable call. 3161 */ 3162 DMUB_CMD__PSR_FORCE_STATIC = 5, 3163 /** 3164 * Set vtotal in psr active for FreeSync PSR. 3165 */ 3166 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6, 3167 /** 3168 * Set PSR power option 3169 */ 3170 DMUB_CMD__SET_PSR_POWER_OPT = 7, 3171 }; 3172 3173 /** 3174 * Different PSR residency modes. 3175 * Different modes change the definition of PSR residency. 3176 */ 3177 enum psr_residency_mode { 3178 PSR_RESIDENCY_MODE_PHY = 0, 3179 PSR_RESIDENCY_MODE_ALPM, 3180 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3181 /* Do not add below. */ 3182 PSR_RESIDENCY_MODE_LAST_ELEMENT, 3183 }; 3184 3185 enum dmub_cmd_fams_type { 3186 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0, 3187 DMUB_CMD__FAMS_DRR_UPDATE = 1, 3188 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd 3189 /** 3190 * For SubVP set manual trigger in FW because it 3191 * triggers DRR_UPDATE_PENDING which SubVP relies 3192 * on (for any SubVP cases that use a DRR display) 3193 */ 3194 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, 3195 DMUB_CMD__FAMS2_CONFIG = 4, 3196 DMUB_CMD__FAMS2_DRR_UPDATE = 5, 3197 DMUB_CMD__FAMS2_FLIP = 6, 3198 DMUB_CMD__FAMS2_IB_CONFIG = 7, 3199 }; 3200 3201 /** 3202 * PSR versions. 3203 */ 3204 enum psr_version { 3205 /** 3206 * PSR version 1. 3207 */ 3208 PSR_VERSION_1 = 0, 3209 /** 3210 * Freesync PSR SU. 3211 */ 3212 PSR_VERSION_SU_1 = 1, 3213 /** 3214 * PSR not supported. 3215 */ 3216 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide 3217 }; 3218 3219 /** 3220 * PHY Link rate for DP. 3221 */ 3222 enum phy_link_rate { 3223 /** 3224 * not supported. 3225 */ 3226 PHY_RATE_UNKNOWN = 0, 3227 /** 3228 * Rate_1 (RBR) - 1.62 Gbps/Lane 3229 */ 3230 PHY_RATE_162 = 1, 3231 /** 3232 * Rate_2 - 2.16 Gbps/Lane 3233 */ 3234 PHY_RATE_216 = 2, 3235 /** 3236 * Rate_3 - 2.43 Gbps/Lane 3237 */ 3238 PHY_RATE_243 = 3, 3239 /** 3240 * Rate_4 (HBR) - 2.70 Gbps/Lane 3241 */ 3242 PHY_RATE_270 = 4, 3243 /** 3244 * Rate_5 (RBR2)- 3.24 Gbps/Lane 3245 */ 3246 PHY_RATE_324 = 5, 3247 /** 3248 * Rate_6 - 4.32 Gbps/Lane 3249 */ 3250 PHY_RATE_432 = 6, 3251 /** 3252 * Rate_7 (HBR2)- 5.40 Gbps/Lane 3253 */ 3254 PHY_RATE_540 = 7, 3255 /** 3256 * Rate_8 (HBR3)- 8.10 Gbps/Lane 3257 */ 3258 PHY_RATE_810 = 8, 3259 /** 3260 * UHBR10 - 10.0 Gbps/Lane 3261 */ 3262 PHY_RATE_1000 = 9, 3263 /** 3264 * UHBR13.5 - 13.5 Gbps/Lane 3265 */ 3266 PHY_RATE_1350 = 10, 3267 /** 3268 * UHBR10 - 20.0 Gbps/Lane 3269 */ 3270 PHY_RATE_2000 = 11, 3271 3272 PHY_RATE_675 = 12, 3273 /** 3274 * Rate 12 - 6.75 Gbps/Lane 3275 */ 3276 }; 3277 3278 /** 3279 * enum dmub_phy_fsm_state - PHY FSM states. 3280 * PHY FSM state to transit to during PSR enable/disable. 3281 */ 3282 enum dmub_phy_fsm_state { 3283 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0, 3284 DMUB_PHY_FSM_RESET, 3285 DMUB_PHY_FSM_RESET_RELEASED, 3286 DMUB_PHY_FSM_SRAM_LOAD_DONE, 3287 DMUB_PHY_FSM_INITIALIZED, 3288 DMUB_PHY_FSM_CALIBRATED, 3289 DMUB_PHY_FSM_CALIBRATED_LP, 3290 DMUB_PHY_FSM_CALIBRATED_PG, 3291 DMUB_PHY_FSM_POWER_DOWN, 3292 DMUB_PHY_FSM_PLL_EN, 3293 DMUB_PHY_FSM_TX_EN, 3294 DMUB_PHY_FSM_TX_EN_TEST_MODE, 3295 DMUB_PHY_FSM_FAST_LP, 3296 DMUB_PHY_FSM_P2_PLL_OFF_CPM, 3297 DMUB_PHY_FSM_P2_PLL_OFF_PG, 3298 DMUB_PHY_FSM_P2_PLL_OFF, 3299 DMUB_PHY_FSM_P2_PLL_ON, 3300 }; 3301 3302 /** 3303 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3304 */ 3305 struct dmub_cmd_psr_copy_settings_data { 3306 /** 3307 * Flags that can be set by driver to change some PSR behaviour. 3308 */ 3309 union dmub_psr_debug_flags debug; 3310 /** 3311 * 16-bit value dicated by driver that will enable/disable different functionality. 3312 */ 3313 uint16_t psr_level; 3314 /** 3315 * DPP HW instance. 3316 */ 3317 uint8_t dpp_inst; 3318 /** 3319 * MPCC HW instance. 3320 * Not used in dmub fw, 3321 * dmub fw will get active opp by reading odm registers. 3322 */ 3323 uint8_t mpcc_inst; 3324 /** 3325 * OPP HW instance. 3326 * Not used in dmub fw, 3327 * dmub fw will get active opp by reading odm registers. 3328 */ 3329 uint8_t opp_inst; 3330 /** 3331 * OTG HW instance. 3332 */ 3333 uint8_t otg_inst; 3334 /** 3335 * DIG FE HW instance. 3336 */ 3337 uint8_t digfe_inst; 3338 /** 3339 * DIG BE HW instance. 3340 */ 3341 uint8_t digbe_inst; 3342 /** 3343 * DP PHY HW instance. 3344 */ 3345 uint8_t dpphy_inst; 3346 /** 3347 * AUX HW instance. 3348 */ 3349 uint8_t aux_inst; 3350 /** 3351 * Determines if SMU optimzations are enabled/disabled. 3352 */ 3353 uint8_t smu_optimizations_en; 3354 /** 3355 * Unused. 3356 * TODO: Remove. 3357 */ 3358 uint8_t frame_delay; 3359 /** 3360 * If RFB setup time is greater than the total VBLANK time, 3361 * it is not possible for the sink to capture the video frame 3362 * in the same frame the SDP is sent. In this case, 3363 * the frame capture indication bit should be set and an extra 3364 * static frame should be transmitted to the sink. 3365 */ 3366 uint8_t frame_cap_ind; 3367 /** 3368 * Granularity of Y offset supported by sink. 3369 */ 3370 uint8_t su_y_granularity; 3371 /** 3372 * Indicates whether sink should start capturing 3373 * immediately following active scan line, 3374 * or starting with the 2nd active scan line. 3375 */ 3376 uint8_t line_capture_indication; 3377 /** 3378 * Multi-display optimizations are implemented on certain ASICs. 3379 */ 3380 uint8_t multi_disp_optimizations_en; 3381 /** 3382 * The last possible line SDP may be transmitted without violating 3383 * the RFB setup time or entering the active video frame. 3384 */ 3385 uint16_t init_sdp_deadline; 3386 /** 3387 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities 3388 */ 3389 uint8_t rate_control_caps ; 3390 /* 3391 * Force PSRSU always doing full frame update 3392 */ 3393 uint8_t force_ffu_mode; 3394 /** 3395 * Length of each horizontal line in us. 3396 */ 3397 uint32_t line_time_in_us; 3398 /** 3399 * FEC enable status in driver 3400 */ 3401 uint8_t fec_enable_status; 3402 /** 3403 * FEC re-enable delay when PSR exit. 3404 * unit is 100us, range form 0~255(0xFF). 3405 */ 3406 uint8_t fec_enable_delay_in100us; 3407 /** 3408 * PSR control version. 3409 */ 3410 uint8_t cmd_version; 3411 /** 3412 * Panel Instance. 3413 * Panel instance to identify which psr_state to use 3414 * Currently the support is only for 0 or 1 3415 */ 3416 uint8_t panel_inst; 3417 /* 3418 * DSC enable status in driver 3419 */ 3420 uint8_t dsc_enable_status; 3421 /* 3422 * Use FSM state for PSR power up/down 3423 */ 3424 uint8_t use_phy_fsm; 3425 /** 3426 * frame delay for frame re-lock 3427 */ 3428 uint8_t relock_delay_frame_cnt; 3429 /** 3430 * esd recovery indicate. 3431 */ 3432 uint8_t esd_recovery; 3433 /** 3434 * DSC Slice height. 3435 */ 3436 uint16_t dsc_slice_height; 3437 /** 3438 * Some panels request main link off before xth vertical line 3439 */ 3440 uint16_t poweroff_before_vertical_line; 3441 /** 3442 * Some panels cannot handle idle pattern during PSR entry. 3443 * To power down phy before disable stream to avoid sending 3444 * idle pattern. 3445 */ 3446 uint8_t power_down_phy_before_disable_stream; 3447 }; 3448 3449 /** 3450 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 3451 */ 3452 struct dmub_rb_cmd_psr_copy_settings { 3453 /** 3454 * Command header. 3455 */ 3456 struct dmub_cmd_header header; 3457 /** 3458 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command. 3459 */ 3460 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data; 3461 }; 3462 3463 /** 3464 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command. 3465 */ 3466 struct dmub_cmd_psr_set_level_data { 3467 /** 3468 * 16-bit value dicated by driver that will enable/disable different functionality. 3469 */ 3470 uint16_t psr_level; 3471 /** 3472 * PSR control version. 3473 */ 3474 uint8_t cmd_version; 3475 /** 3476 * Panel Instance. 3477 * Panel instance to identify which psr_state to use 3478 * Currently the support is only for 0 or 1 3479 */ 3480 uint8_t panel_inst; 3481 }; 3482 3483 /** 3484 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3485 */ 3486 struct dmub_rb_cmd_psr_set_level { 3487 /** 3488 * Command header. 3489 */ 3490 struct dmub_cmd_header header; 3491 /** 3492 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 3493 */ 3494 struct dmub_cmd_psr_set_level_data psr_set_level_data; 3495 }; 3496 3497 struct dmub_rb_cmd_psr_enable_data { 3498 /** 3499 * PSR control version. 3500 */ 3501 uint8_t cmd_version; 3502 /** 3503 * Panel Instance. 3504 * Panel instance to identify which psr_state to use 3505 * Currently the support is only for 0 or 1 3506 */ 3507 uint8_t panel_inst; 3508 /** 3509 * Phy state to enter. 3510 * Values to use are defined in dmub_phy_fsm_state 3511 */ 3512 uint8_t phy_fsm_state; 3513 /** 3514 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 3515 * Set this using enum phy_link_rate. 3516 * This does not support HDMI/DP2 for now. 3517 */ 3518 uint8_t phy_rate; 3519 }; 3520 3521 /** 3522 * Definition of a DMUB_CMD__PSR_ENABLE command. 3523 * PSR enable/disable is controlled using the sub_type. 3524 */ 3525 struct dmub_rb_cmd_psr_enable { 3526 /** 3527 * Command header. 3528 */ 3529 struct dmub_cmd_header header; 3530 3531 struct dmub_rb_cmd_psr_enable_data data; 3532 }; 3533 3534 /** 3535 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3536 */ 3537 struct dmub_cmd_psr_set_version_data { 3538 /** 3539 * PSR version that FW should implement. 3540 */ 3541 enum psr_version version; 3542 /** 3543 * PSR control version. 3544 */ 3545 uint8_t cmd_version; 3546 /** 3547 * Panel Instance. 3548 * Panel instance to identify which psr_state to use 3549 * Currently the support is only for 0 or 1 3550 */ 3551 uint8_t panel_inst; 3552 /** 3553 * Explicit padding to 4 byte boundary. 3554 */ 3555 uint8_t pad[2]; 3556 }; 3557 3558 /** 3559 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 3560 */ 3561 struct dmub_rb_cmd_psr_set_version { 3562 /** 3563 * Command header. 3564 */ 3565 struct dmub_cmd_header header; 3566 /** 3567 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command. 3568 */ 3569 struct dmub_cmd_psr_set_version_data psr_set_version_data; 3570 }; 3571 3572 struct dmub_cmd_psr_force_static_data { 3573 /** 3574 * PSR control version. 3575 */ 3576 uint8_t cmd_version; 3577 /** 3578 * Panel Instance. 3579 * Panel instance to identify which psr_state to use 3580 * Currently the support is only for 0 or 1 3581 */ 3582 uint8_t panel_inst; 3583 /** 3584 * Explicit padding to 4 byte boundary. 3585 */ 3586 uint8_t pad[2]; 3587 }; 3588 3589 /** 3590 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 3591 */ 3592 struct dmub_rb_cmd_psr_force_static { 3593 /** 3594 * Command header. 3595 */ 3596 struct dmub_cmd_header header; 3597 /** 3598 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command. 3599 */ 3600 struct dmub_cmd_psr_force_static_data psr_force_static_data; 3601 }; 3602 3603 /** 3604 * PSR SU debug flags. 3605 */ 3606 union dmub_psr_su_debug_flags { 3607 /** 3608 * PSR SU debug flags. 3609 */ 3610 struct { 3611 /** 3612 * Update dirty rect in SW only. 3613 */ 3614 uint8_t update_dirty_rect_only : 1; 3615 /** 3616 * Reset the cursor/plane state before processing the call. 3617 */ 3618 uint8_t reset_state : 1; 3619 } bitfields; 3620 3621 /** 3622 * Union for debug flags. 3623 */ 3624 uint32_t u32All; 3625 }; 3626 3627 /** 3628 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3629 * This triggers a selective update for PSR SU. 3630 */ 3631 struct dmub_cmd_update_dirty_rect_data { 3632 /** 3633 * Dirty rects from OS. 3634 */ 3635 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS]; 3636 /** 3637 * PSR SU debug flags. 3638 */ 3639 union dmub_psr_su_debug_flags debug_flags; 3640 /** 3641 * OTG HW instance. 3642 */ 3643 uint8_t pipe_idx; 3644 /** 3645 * Number of dirty rects. 3646 */ 3647 uint8_t dirty_rect_count; 3648 /** 3649 * PSR control version. 3650 */ 3651 uint8_t cmd_version; 3652 /** 3653 * Panel Instance. 3654 * Panel instance to identify which psr_state to use 3655 * Currently the support is only for 0 or 1 3656 */ 3657 uint8_t panel_inst; 3658 }; 3659 3660 /** 3661 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 3662 */ 3663 struct dmub_rb_cmd_update_dirty_rect { 3664 /** 3665 * Command header. 3666 */ 3667 struct dmub_cmd_header header; 3668 /** 3669 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command. 3670 */ 3671 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data; 3672 }; 3673 3674 /** 3675 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3676 */ 3677 union dmub_reg_cursor_control_cfg { 3678 struct { 3679 uint32_t cur_enable: 1; 3680 uint32_t reser0: 3; 3681 uint32_t cur_2x_magnify: 1; 3682 uint32_t reser1: 3; 3683 uint32_t mode: 3; 3684 uint32_t reser2: 5; 3685 uint32_t pitch: 2; 3686 uint32_t reser3: 6; 3687 uint32_t line_per_chunk: 5; 3688 uint32_t reser4: 3; 3689 } bits; 3690 uint32_t raw; 3691 }; 3692 struct dmub_cursor_position_cache_hubp { 3693 union dmub_reg_cursor_control_cfg cur_ctl; 3694 union dmub_reg_position_cfg { 3695 struct { 3696 uint32_t cur_x_pos: 16; 3697 uint32_t cur_y_pos: 16; 3698 } bits; 3699 uint32_t raw; 3700 } position; 3701 union dmub_reg_hot_spot_cfg { 3702 struct { 3703 uint32_t hot_x: 16; 3704 uint32_t hot_y: 16; 3705 } bits; 3706 uint32_t raw; 3707 } hot_spot; 3708 union dmub_reg_dst_offset_cfg { 3709 struct { 3710 uint32_t dst_x_offset: 13; 3711 uint32_t reserved: 19; 3712 } bits; 3713 uint32_t raw; 3714 } dst_offset; 3715 }; 3716 3717 union dmub_reg_cur0_control_cfg { 3718 struct { 3719 uint32_t cur0_enable: 1; 3720 uint32_t expansion_mode: 1; 3721 uint32_t reser0: 1; 3722 uint32_t cur0_rom_en: 1; 3723 uint32_t mode: 3; 3724 uint32_t reserved: 25; 3725 } bits; 3726 uint32_t raw; 3727 }; 3728 struct dmub_cursor_position_cache_dpp { 3729 union dmub_reg_cur0_control_cfg cur0_ctl; 3730 }; 3731 struct dmub_cursor_position_cfg { 3732 struct dmub_cursor_position_cache_hubp pHubp; 3733 struct dmub_cursor_position_cache_dpp pDpp; 3734 uint8_t pipe_idx; 3735 /* 3736 * Padding is required. To be 4 Bytes Aligned. 3737 */ 3738 uint8_t padding[3]; 3739 }; 3740 3741 struct dmub_cursor_attribute_cache_hubp { 3742 uint32_t SURFACE_ADDR_HIGH; 3743 uint32_t SURFACE_ADDR; 3744 union dmub_reg_cursor_control_cfg cur_ctl; 3745 union dmub_reg_cursor_size_cfg { 3746 struct { 3747 uint32_t width: 16; 3748 uint32_t height: 16; 3749 } bits; 3750 uint32_t raw; 3751 } size; 3752 union dmub_reg_cursor_settings_cfg { 3753 struct { 3754 uint32_t dst_y_offset: 8; 3755 uint32_t chunk_hdl_adjust: 2; 3756 uint32_t reserved: 22; 3757 } bits; 3758 uint32_t raw; 3759 } settings; 3760 }; 3761 struct dmub_cursor_attribute_cache_dpp { 3762 union dmub_reg_cur0_control_cfg cur0_ctl; 3763 }; 3764 struct dmub_cursor_attributes_cfg { 3765 struct dmub_cursor_attribute_cache_hubp aHubp; 3766 struct dmub_cursor_attribute_cache_dpp aDpp; 3767 }; 3768 3769 struct dmub_cmd_update_cursor_payload0 { 3770 /** 3771 * Cursor dirty rects. 3772 */ 3773 struct dmub_rect cursor_rect; 3774 /** 3775 * PSR SU debug flags. 3776 */ 3777 union dmub_psr_su_debug_flags debug_flags; 3778 /** 3779 * Cursor enable/disable. 3780 */ 3781 uint8_t enable; 3782 /** 3783 * OTG HW instance. 3784 */ 3785 uint8_t pipe_idx; 3786 /** 3787 * PSR control version. 3788 */ 3789 uint8_t cmd_version; 3790 /** 3791 * Panel Instance. 3792 * Panel instance to identify which psr_state to use 3793 * Currently the support is only for 0 or 1 3794 */ 3795 uint8_t panel_inst; 3796 /** 3797 * Cursor Position Register. 3798 * Registers contains Hubp & Dpp modules 3799 */ 3800 struct dmub_cursor_position_cfg position_cfg; 3801 }; 3802 3803 struct dmub_cmd_update_cursor_payload1 { 3804 struct dmub_cursor_attributes_cfg attribute_cfg; 3805 }; 3806 3807 union dmub_cmd_update_cursor_info_data { 3808 struct dmub_cmd_update_cursor_payload0 payload0; 3809 struct dmub_cmd_update_cursor_payload1 payload1; 3810 }; 3811 /** 3812 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 3813 */ 3814 struct dmub_rb_cmd_update_cursor_info { 3815 /** 3816 * Command header. 3817 */ 3818 struct dmub_cmd_header header; 3819 /** 3820 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command. 3821 */ 3822 union dmub_cmd_update_cursor_info_data update_cursor_info_data; 3823 }; 3824 3825 /** 3826 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3827 */ 3828 struct dmub_cmd_psr_set_vtotal_data { 3829 /** 3830 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle.. 3831 */ 3832 uint16_t psr_vtotal_idle; 3833 /** 3834 * PSR control version. 3835 */ 3836 uint8_t cmd_version; 3837 /** 3838 * Panel Instance. 3839 * Panel instance to identify which psr_state to use 3840 * Currently the support is only for 0 or 1 3841 */ 3842 uint8_t panel_inst; 3843 /* 3844 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU. 3845 */ 3846 uint16_t psr_vtotal_su; 3847 /** 3848 * Explicit padding to 4 byte boundary. 3849 */ 3850 uint8_t pad2[2]; 3851 }; 3852 3853 /** 3854 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3855 */ 3856 struct dmub_rb_cmd_psr_set_vtotal { 3857 /** 3858 * Command header. 3859 */ 3860 struct dmub_cmd_header header; 3861 /** 3862 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 3863 */ 3864 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data; 3865 }; 3866 3867 /** 3868 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command. 3869 */ 3870 struct dmub_cmd_psr_set_power_opt_data { 3871 /** 3872 * PSR control version. 3873 */ 3874 uint8_t cmd_version; 3875 /** 3876 * Panel Instance. 3877 * Panel instance to identify which psr_state to use 3878 * Currently the support is only for 0 or 1 3879 */ 3880 uint8_t panel_inst; 3881 /** 3882 * Explicit padding to 4 byte boundary. 3883 */ 3884 uint8_t pad[2]; 3885 /** 3886 * PSR power option 3887 */ 3888 uint32_t power_opt; 3889 }; 3890 3891 /** 3892 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3893 */ 3894 struct dmub_rb_cmd_psr_set_power_opt { 3895 /** 3896 * Command header. 3897 */ 3898 struct dmub_cmd_header header; 3899 /** 3900 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 3901 */ 3902 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data; 3903 }; 3904 3905 enum dmub_alpm_mode { 3906 ALPM_AUXWAKE = 0, 3907 ALPM_AUXLESS = 1, 3908 ALPM_UNSUPPORTED = 2, 3909 }; 3910 3911 /** 3912 * Definition of Replay Residency GPINT command. 3913 * Bit[0] - Residency mode for Revision 0 3914 * Bit[1] - Enable/Disable state 3915 * Bit[2-3] - Revision number 3916 * Bit[4-7] - Residency mode for Revision 1 3917 * Bit[8] - Panel instance 3918 * Bit[9-15] - Reserved 3919 */ 3920 3921 enum pr_residency_mode { 3922 PR_RESIDENCY_MODE_PHY = 0x0, 3923 PR_RESIDENCY_MODE_ALPM, 3924 PR_RESIDENCY_MODE_IPS2, 3925 PR_RESIDENCY_MODE_FRAME_CNT, 3926 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD, 3927 }; 3928 3929 #define REPLAY_RESIDENCY_MODE_SHIFT (0) 3930 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1) 3931 #define REPLAY_RESIDENCY_REVISION_SHIFT (2) 3932 #define REPLAY_RESIDENCY_MODE2_SHIFT (4) 3933 3934 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3935 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT) 3936 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT) 3937 3938 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT) 3939 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT) 3940 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT) 3941 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT) 3942 3943 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3944 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3945 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT) 3946 3947 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT) 3948 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT) 3949 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT) 3950 3951 /** 3952 * Definition of a replay_state. 3953 */ 3954 enum replay_state { 3955 REPLAY_STATE_0 = 0x0, 3956 REPLAY_STATE_1 = 0x10, 3957 REPLAY_STATE_1A = 0x11, 3958 REPLAY_STATE_2 = 0x20, 3959 REPLAY_STATE_2A = 0x21, 3960 REPLAY_STATE_3 = 0x30, 3961 REPLAY_STATE_3INIT = 0x31, 3962 REPLAY_STATE_4 = 0x40, 3963 REPLAY_STATE_4A = 0x41, 3964 REPLAY_STATE_4B = 0x42, 3965 REPLAY_STATE_4C = 0x43, 3966 REPLAY_STATE_4D = 0x44, 3967 REPLAY_STATE_4E = 0x45, 3968 REPLAY_STATE_4B_LOCKED = 0x4A, 3969 REPLAY_STATE_4C_UNLOCKED = 0x4B, 3970 REPLAY_STATE_5 = 0x50, 3971 REPLAY_STATE_5A = 0x51, 3972 REPLAY_STATE_5B = 0x52, 3973 REPLAY_STATE_5A_LOCKED = 0x5A, 3974 REPLAY_STATE_5B_UNLOCKED = 0x5B, 3975 REPLAY_STATE_6 = 0x60, 3976 REPLAY_STATE_6A = 0x61, 3977 REPLAY_STATE_6B = 0x62, 3978 REPLAY_STATE_INVALID = 0xFF, 3979 }; 3980 3981 /** 3982 * Replay command sub-types. 3983 */ 3984 enum dmub_cmd_replay_type { 3985 /** 3986 * Copy driver-calculated parameters to REPLAY state. 3987 */ 3988 DMUB_CMD__REPLAY_COPY_SETTINGS = 0, 3989 /** 3990 * Enable REPLAY. 3991 */ 3992 DMUB_CMD__REPLAY_ENABLE = 1, 3993 /** 3994 * Set Replay power option. 3995 */ 3996 DMUB_CMD__SET_REPLAY_POWER_OPT = 2, 3997 /** 3998 * Set coasting vtotal. 3999 */ 4000 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3, 4001 /** 4002 * Set power opt and coasting vtotal. 4003 */ 4004 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4, 4005 /** 4006 * Set disabled iiming sync. 4007 */ 4008 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5, 4009 /** 4010 * Set Residency Frameupdate Timer. 4011 */ 4012 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6, 4013 /** 4014 * Set pseudo vtotal 4015 */ 4016 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7, 4017 /** 4018 * Set adaptive sync sdp enabled 4019 */ 4020 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8, 4021 /** 4022 * Set Replay General command. 4023 */ 4024 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16, 4025 }; 4026 4027 /** 4028 * Replay general command sub-types. 4029 */ 4030 enum dmub_cmd_replay_general_subtype { 4031 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1, 4032 /** 4033 * TODO: For backward compatible, allow new command only. 4034 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED, 4035 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER, 4036 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL, 4037 */ 4038 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP, 4039 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION, 4040 REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS, 4041 REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE, 4042 }; 4043 4044 struct dmub_alpm_auxless_data { 4045 uint16_t lfps_setup_ns; 4046 uint16_t lfps_period_ns; 4047 uint16_t lfps_silence_ns; 4048 uint16_t lfps_t1_t2_override_us; 4049 short lfps_t1_t2_offset_us; 4050 uint8_t lttpr_count; 4051 /* 4052 * Padding to align structure to 4 byte boundary. 4053 */ 4054 uint8_t pad[1]; 4055 }; 4056 4057 /** 4058 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4059 */ 4060 struct dmub_cmd_replay_copy_settings_data { 4061 /** 4062 * Flags that can be set by driver to change some replay behaviour. 4063 */ 4064 union replay_debug_flags debug; 4065 4066 /** 4067 * @flags: Flags used to determine feature functionality. 4068 */ 4069 union replay_hw_flags flags; 4070 4071 /** 4072 * DPP HW instance. 4073 */ 4074 uint8_t dpp_inst; 4075 /** 4076 * OTG HW instance. 4077 */ 4078 uint8_t otg_inst; 4079 /** 4080 * DIG FE HW instance. 4081 */ 4082 uint8_t digfe_inst; 4083 /** 4084 * DIG BE HW instance. 4085 */ 4086 uint8_t digbe_inst; 4087 /** 4088 * AUX HW instance. 4089 */ 4090 uint8_t aux_inst; 4091 /** 4092 * Panel Instance. 4093 * Panel isntance to identify which psr_state to use 4094 * Currently the support is only for 0 or 1 4095 */ 4096 uint8_t panel_inst; 4097 /** 4098 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare 4099 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode 4100 */ 4101 uint8_t pixel_deviation_per_line; 4102 /** 4103 * @max_deviation_line: The max number of deviation line that can keep the timing 4104 * synchronized between the Source and Sink during Replay normal sleep mode. 4105 */ 4106 uint8_t max_deviation_line; 4107 /** 4108 * Length of each horizontal line in ns. 4109 */ 4110 uint32_t line_time_in_ns; 4111 /** 4112 * PHY instance. 4113 */ 4114 uint8_t dpphy_inst; 4115 /** 4116 * Determines if SMU optimzations are enabled/disabled. 4117 */ 4118 uint8_t smu_optimizations_en; 4119 /** 4120 * Determines if timing sync are enabled/disabled. 4121 */ 4122 uint8_t replay_timing_sync_supported; 4123 /* 4124 * Use FSM state for Replay power up/down 4125 */ 4126 uint8_t use_phy_fsm; 4127 /** 4128 * Use for AUX-less ALPM LFPS wake operation 4129 */ 4130 struct dmub_alpm_auxless_data auxless_alpm_data; 4131 /** 4132 * @hpo_stream_enc_inst: HPO stream encoder instance 4133 */ 4134 uint8_t hpo_stream_enc_inst; 4135 /** 4136 * @hpo_link_enc_inst: HPO link encoder instance 4137 */ 4138 uint8_t hpo_link_enc_inst; 4139 /** 4140 * @pad: Align structure to 4 byte boundary. 4141 */ 4142 uint8_t pad[2]; 4143 }; 4144 4145 /** 4146 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4147 */ 4148 struct dmub_rb_cmd_replay_copy_settings { 4149 /** 4150 * Command header. 4151 */ 4152 struct dmub_cmd_header header; 4153 /** 4154 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command. 4155 */ 4156 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data; 4157 }; 4158 4159 /** 4160 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable 4161 */ 4162 enum replay_enable { 4163 /** 4164 * Disable REPLAY. 4165 */ 4166 REPLAY_DISABLE = 0, 4167 /** 4168 * Enable REPLAY. 4169 */ 4170 REPLAY_ENABLE = 1, 4171 }; 4172 4173 /** 4174 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command. 4175 */ 4176 struct dmub_rb_cmd_replay_enable_data { 4177 /** 4178 * Replay enable or disable. 4179 */ 4180 uint8_t enable; 4181 /** 4182 * Panel Instance. 4183 * Panel isntance to identify which replay_state to use 4184 * Currently the support is only for 0 or 1 4185 */ 4186 uint8_t panel_inst; 4187 /** 4188 * Phy state to enter. 4189 * Values to use are defined in dmub_phy_fsm_state 4190 */ 4191 uint8_t phy_fsm_state; 4192 /** 4193 * Phy rate for DP - RBR/HBR/HBR2/HBR3. 4194 * Set this using enum phy_link_rate. 4195 * This does not support HDMI/DP2 for now. 4196 */ 4197 uint8_t phy_rate; 4198 /** 4199 * @hpo_stream_enc_inst: HPO stream encoder instance 4200 */ 4201 uint8_t hpo_stream_enc_inst; 4202 /** 4203 * @hpo_link_enc_inst: HPO link encoder instance 4204 */ 4205 uint8_t hpo_link_enc_inst; 4206 /** 4207 * @pad: Align structure to 4 byte boundary. 4208 */ 4209 uint8_t pad[2]; 4210 }; 4211 4212 /** 4213 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 4214 * Replay enable/disable is controlled using action in data. 4215 */ 4216 struct dmub_rb_cmd_replay_enable { 4217 /** 4218 * Command header. 4219 */ 4220 struct dmub_cmd_header header; 4221 4222 struct dmub_rb_cmd_replay_enable_data data; 4223 }; 4224 4225 /** 4226 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4227 */ 4228 struct dmub_cmd_replay_set_power_opt_data { 4229 /** 4230 * Panel Instance. 4231 * Panel isntance to identify which replay_state to use 4232 * Currently the support is only for 0 or 1 4233 */ 4234 uint8_t panel_inst; 4235 /** 4236 * Explicit padding to 4 byte boundary. 4237 */ 4238 uint8_t pad[3]; 4239 /** 4240 * REPLAY power option 4241 */ 4242 uint32_t power_opt; 4243 }; 4244 4245 /** 4246 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4247 */ 4248 struct dmub_cmd_replay_set_timing_sync_data { 4249 /** 4250 * Panel Instance. 4251 * Panel isntance to identify which replay_state to use 4252 * Currently the support is only for 0 or 1 4253 */ 4254 uint8_t panel_inst; 4255 /** 4256 * REPLAY set_timing_sync 4257 */ 4258 uint8_t timing_sync_supported; 4259 /** 4260 * Explicit padding to 4 byte boundary. 4261 */ 4262 uint8_t pad[2]; 4263 }; 4264 4265 /** 4266 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4267 */ 4268 struct dmub_cmd_replay_set_pseudo_vtotal { 4269 /** 4270 * Panel Instance. 4271 * Panel isntance to identify which replay_state to use 4272 * Currently the support is only for 0 or 1 4273 */ 4274 uint8_t panel_inst; 4275 /** 4276 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal 4277 */ 4278 uint16_t vtotal; 4279 /** 4280 * Explicit padding to 4 byte boundary. 4281 */ 4282 uint8_t pad; 4283 }; 4284 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data { 4285 /** 4286 * Panel Instance. 4287 * Panel isntance to identify which replay_state to use 4288 * Currently the support is only for 0 or 1 4289 */ 4290 uint8_t panel_inst; 4291 /** 4292 * enabled: set adaptive sync sdp enabled 4293 */ 4294 uint8_t force_disabled; 4295 4296 uint8_t pad[2]; 4297 }; 4298 struct dmub_cmd_replay_set_general_cmd_data { 4299 /** 4300 * Panel Instance. 4301 * Panel isntance to identify which replay_state to use 4302 * Currently the support is only for 0 or 1 4303 */ 4304 uint8_t panel_inst; 4305 /** 4306 * subtype: replay general cmd sub type 4307 */ 4308 uint8_t subtype; 4309 4310 uint8_t pad[2]; 4311 /** 4312 * config data with param1 and param2 4313 */ 4314 uint32_t param1; 4315 4316 uint32_t param2; 4317 }; 4318 4319 /** 4320 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4321 */ 4322 struct dmub_rb_cmd_replay_set_power_opt { 4323 /** 4324 * Command header. 4325 */ 4326 struct dmub_cmd_header header; 4327 /** 4328 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4329 */ 4330 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4331 }; 4332 4333 /** 4334 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4335 */ 4336 struct dmub_cmd_replay_set_coasting_vtotal_data { 4337 /** 4338 * 16-bit value dicated by driver that indicates the coasting vtotal. 4339 */ 4340 uint16_t coasting_vtotal; 4341 /** 4342 * REPLAY control version. 4343 */ 4344 uint8_t cmd_version; 4345 /** 4346 * Panel Instance. 4347 * Panel isntance to identify which replay_state to use 4348 * Currently the support is only for 0 or 1 4349 */ 4350 uint8_t panel_inst; 4351 /** 4352 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part. 4353 */ 4354 uint16_t coasting_vtotal_high; 4355 /** 4356 * Explicit padding to 4 byte boundary. 4357 */ 4358 uint8_t pad[2]; 4359 }; 4360 4361 /** 4362 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4363 */ 4364 struct dmub_rb_cmd_replay_set_coasting_vtotal { 4365 /** 4366 * Command header. 4367 */ 4368 struct dmub_cmd_header header; 4369 /** 4370 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4371 */ 4372 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4373 }; 4374 4375 /** 4376 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 4377 */ 4378 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal { 4379 /** 4380 * Command header. 4381 */ 4382 struct dmub_cmd_header header; 4383 /** 4384 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4385 */ 4386 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data; 4387 /** 4388 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 4389 */ 4390 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data; 4391 }; 4392 4393 /** 4394 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4395 */ 4396 struct dmub_rb_cmd_replay_set_timing_sync { 4397 /** 4398 * Command header. 4399 */ 4400 struct dmub_cmd_header header; 4401 /** 4402 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command. 4403 */ 4404 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data; 4405 }; 4406 4407 /** 4408 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4409 */ 4410 struct dmub_rb_cmd_replay_set_pseudo_vtotal { 4411 /** 4412 * Command header. 4413 */ 4414 struct dmub_cmd_header header; 4415 /** 4416 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 4417 */ 4418 struct dmub_cmd_replay_set_pseudo_vtotal data; 4419 }; 4420 4421 /** 4422 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4423 */ 4424 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp { 4425 /** 4426 * Command header. 4427 */ 4428 struct dmub_cmd_header header; 4429 /** 4430 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 4431 */ 4432 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data; 4433 }; 4434 4435 /** 4436 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4437 */ 4438 struct dmub_rb_cmd_replay_set_general_cmd { 4439 /** 4440 * Command header. 4441 */ 4442 struct dmub_cmd_header header; 4443 /** 4444 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 4445 */ 4446 struct dmub_cmd_replay_set_general_cmd_data data; 4447 }; 4448 4449 /** 4450 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 4451 */ 4452 struct dmub_cmd_replay_frameupdate_timer_data { 4453 /** 4454 * Panel Instance. 4455 * Panel isntance to identify which replay_state to use 4456 * Currently the support is only for 0 or 1 4457 */ 4458 uint8_t panel_inst; 4459 /** 4460 * Replay Frameupdate Timer Enable or not 4461 */ 4462 uint8_t enable; 4463 /** 4464 * REPLAY force reflash frame update number 4465 */ 4466 uint16_t frameupdate_count; 4467 }; 4468 /** 4469 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER 4470 */ 4471 struct dmub_rb_cmd_replay_set_frameupdate_timer { 4472 /** 4473 * Command header. 4474 */ 4475 struct dmub_cmd_header header; 4476 /** 4477 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 4478 */ 4479 struct dmub_cmd_replay_frameupdate_timer_data data; 4480 }; 4481 4482 /** 4483 * Definition union of replay command set 4484 */ 4485 union dmub_replay_cmd_set { 4486 /** 4487 * Panel Instance. 4488 * Panel isntance to identify which replay_state to use 4489 * Currently the support is only for 0 or 1 4490 */ 4491 uint8_t panel_inst; 4492 /** 4493 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data. 4494 */ 4495 struct dmub_cmd_replay_set_timing_sync_data sync_data; 4496 /** 4497 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data. 4498 */ 4499 struct dmub_cmd_replay_frameupdate_timer_data timer_data; 4500 /** 4501 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data. 4502 */ 4503 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data; 4504 /** 4505 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data. 4506 */ 4507 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data; 4508 /** 4509 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data. 4510 */ 4511 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data; 4512 }; 4513 4514 /** 4515 * Set of HW components that can be locked. 4516 * 4517 * Note: If updating with more HW components, fields 4518 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4519 */ 4520 union dmub_hw_lock_flags { 4521 /** 4522 * Set of HW components that can be locked. 4523 */ 4524 struct { 4525 /** 4526 * Lock/unlock OTG master update lock. 4527 */ 4528 uint8_t lock_pipe : 1; 4529 /** 4530 * Lock/unlock cursor. 4531 */ 4532 uint8_t lock_cursor : 1; 4533 /** 4534 * Lock/unlock global update lock. 4535 */ 4536 uint8_t lock_dig : 1; 4537 /** 4538 * Triple buffer lock requires additional hw programming to usual OTG master lock. 4539 */ 4540 uint8_t triple_buffer_lock : 1; 4541 } bits; 4542 4543 /** 4544 * Union for HW Lock flags. 4545 */ 4546 uint8_t u8All; 4547 }; 4548 4549 /** 4550 * Instances of HW to be locked. 4551 * 4552 * Note: If updating with more HW components, fields 4553 * in dmub_inbox0_cmd_lock_hw must be updated to match. 4554 */ 4555 struct dmub_hw_lock_inst_flags { 4556 /** 4557 * OTG HW instance for OTG master update lock. 4558 */ 4559 uint8_t otg_inst; 4560 /** 4561 * OPP instance for cursor lock. 4562 */ 4563 uint8_t opp_inst; 4564 /** 4565 * OTG HW instance for global update lock. 4566 * TODO: Remove, and re-use otg_inst. 4567 */ 4568 uint8_t dig_inst; 4569 /** 4570 * Explicit pad to 4 byte boundary. 4571 */ 4572 uint8_t pad; 4573 }; 4574 4575 /** 4576 * Clients that can acquire the HW Lock Manager. 4577 * 4578 * Note: If updating with more clients, fields in 4579 * dmub_inbox0_cmd_lock_hw must be updated to match. 4580 */ 4581 enum hw_lock_client { 4582 /** 4583 * Driver is the client of HW Lock Manager. 4584 */ 4585 HW_LOCK_CLIENT_DRIVER = 0, 4586 /** 4587 * PSR SU is the client of HW Lock Manager. 4588 */ 4589 HW_LOCK_CLIENT_PSR_SU = 1, 4590 HW_LOCK_CLIENT_SUBVP = 3, 4591 /** 4592 * Replay is the client of HW Lock Manager. 4593 */ 4594 HW_LOCK_CLIENT_REPLAY = 4, 4595 HW_LOCK_CLIENT_FAMS2 = 5, 4596 /** 4597 * Invalid client. 4598 */ 4599 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF, 4600 }; 4601 4602 /** 4603 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4604 */ 4605 struct dmub_cmd_lock_hw_data { 4606 /** 4607 * Specifies the client accessing HW Lock Manager. 4608 */ 4609 enum hw_lock_client client; 4610 /** 4611 * HW instances to be locked. 4612 */ 4613 struct dmub_hw_lock_inst_flags inst_flags; 4614 /** 4615 * Which components to be locked. 4616 */ 4617 union dmub_hw_lock_flags hw_locks; 4618 /** 4619 * Specifies lock/unlock. 4620 */ 4621 uint8_t lock; 4622 /** 4623 * HW can be unlocked separately from releasing the HW Lock Mgr. 4624 * This flag is set if the client wishes to release the object. 4625 */ 4626 uint8_t should_release; 4627 /** 4628 * Explicit padding to 4 byte boundary. 4629 */ 4630 uint8_t pad; 4631 }; 4632 4633 /** 4634 * Definition of a DMUB_CMD__HW_LOCK command. 4635 * Command is used by driver and FW. 4636 */ 4637 struct dmub_rb_cmd_lock_hw { 4638 /** 4639 * Command header. 4640 */ 4641 struct dmub_cmd_header header; 4642 /** 4643 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command. 4644 */ 4645 struct dmub_cmd_lock_hw_data lock_hw_data; 4646 }; 4647 4648 /** 4649 * ABM command sub-types. 4650 */ 4651 enum dmub_cmd_abm_type { 4652 /** 4653 * Initialize parameters for ABM algorithm. 4654 * Data is passed through an indirect buffer. 4655 */ 4656 DMUB_CMD__ABM_INIT_CONFIG = 0, 4657 /** 4658 * Set OTG and panel HW instance. 4659 */ 4660 DMUB_CMD__ABM_SET_PIPE = 1, 4661 /** 4662 * Set user requested backklight level. 4663 */ 4664 DMUB_CMD__ABM_SET_BACKLIGHT = 2, 4665 /** 4666 * Set ABM operating/aggression level. 4667 */ 4668 DMUB_CMD__ABM_SET_LEVEL = 3, 4669 /** 4670 * Set ambient light level. 4671 */ 4672 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4, 4673 /** 4674 * Enable/disable fractional duty cycle for backlight PWM. 4675 */ 4676 DMUB_CMD__ABM_SET_PWM_FRAC = 5, 4677 4678 /** 4679 * unregister vertical interrupt after steady state is reached 4680 */ 4681 DMUB_CMD__ABM_PAUSE = 6, 4682 4683 /** 4684 * Save and Restore ABM state. On save we save parameters, and 4685 * on restore we update state with passed in data. 4686 */ 4687 DMUB_CMD__ABM_SAVE_RESTORE = 7, 4688 4689 /** 4690 * Query ABM caps. 4691 */ 4692 DMUB_CMD__ABM_QUERY_CAPS = 8, 4693 4694 /** 4695 * Set ABM Events 4696 */ 4697 DMUB_CMD__ABM_SET_EVENT = 9, 4698 4699 /** 4700 * Get the current ACE curve. 4701 */ 4702 DMUB_CMD__ABM_GET_ACE_CURVE = 10, 4703 4704 /** 4705 * Get current histogram data 4706 */ 4707 DMUB_CMD__ABM_GET_HISTOGRAM_DATA = 11, 4708 }; 4709 4710 /** 4711 * LSDMA command sub-types. 4712 */ 4713 enum dmub_cmd_lsdma_type { 4714 /** 4715 * Initialize parameters for LSDMA. 4716 * Ring buffer is mapped to the ring buffer 4717 */ 4718 DMUB_CMD__LSDMA_INIT_CONFIG = 0, 4719 /** 4720 * LSDMA copies data from source to destination linearly 4721 */ 4722 DMUB_CMD__LSDMA_LINEAR_COPY = 1, 4723 /** 4724 * LSDMA copies data from source to destination linearly in sub window 4725 */ 4726 DMUB_CMD__LSDMA_LINEAR_SUB_WINDOW_COPY = 2, 4727 /** 4728 * Send the tiled-to-tiled copy command 4729 */ 4730 DMUB_CMD__LSDMA_TILED_TO_TILED_COPY = 3, 4731 /** 4732 * Send the poll reg write command 4733 */ 4734 DMUB_CMD__LSDMA_POLL_REG_WRITE = 4, 4735 /** 4736 * Send the pio copy command 4737 */ 4738 DMUB_CMD__LSDMA_PIO_COPY = 5, 4739 /** 4740 * Send the pio constfill command 4741 */ 4742 DMUB_CMD__LSDMA_PIO_CONSTFILL = 6, 4743 }; 4744 4745 struct abm_ace_curve { 4746 /** 4747 * @offsets: ACE curve offsets. 4748 */ 4749 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4750 4751 /** 4752 * @thresholds: ACE curve thresholds. 4753 */ 4754 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4755 4756 /** 4757 * @slopes: ACE curve slopes. 4758 */ 4759 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; 4760 }; 4761 4762 struct fixed_pt_format { 4763 /** 4764 * @sign_bit: Indicates whether one bit is reserved for the sign. 4765 */ 4766 bool sign_bit; 4767 4768 /** 4769 * @num_int_bits: Number of bits used for integer part. 4770 */ 4771 uint8_t num_int_bits; 4772 4773 /** 4774 * @num_frac_bits: Number of bits used for fractional part. 4775 */ 4776 uint8_t num_frac_bits; 4777 4778 /** 4779 * @pad: Explicit padding to 4 byte boundary. 4780 */ 4781 uint8_t pad; 4782 }; 4783 4784 struct abm_caps { 4785 /** 4786 * @num_hg_bins: Number of histogram bins. 4787 */ 4788 uint8_t num_hg_bins; 4789 4790 /** 4791 * @num_ace_segments: Number of ACE curve segments. 4792 */ 4793 uint8_t num_ace_segments; 4794 4795 /** 4796 * @pad: Explicit padding to 4 byte boundary. 4797 */ 4798 uint8_t pad[2]; 4799 4800 /** 4801 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. 4802 */ 4803 struct fixed_pt_format ace_thresholds_format; 4804 4805 /** 4806 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. 4807 */ 4808 struct fixed_pt_format ace_offsets_format; 4809 4810 /** 4811 * @ace_slopes_format: Format of the ACE slopes. 4812 */ 4813 struct fixed_pt_format ace_slopes_format; 4814 }; 4815 4816 /** 4817 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer. 4818 * Requirements: 4819 * - Padded explicitly to 32-bit boundary. 4820 * - Must ensure this structure matches the one on driver-side, 4821 * otherwise it won't be aligned. 4822 */ 4823 struct abm_config_table { 4824 /** 4825 * Gamma curve thresholds, used for crgb conversion. 4826 */ 4827 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B 4828 /** 4829 * Gamma curve offsets, used for crgb conversion. 4830 */ 4831 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B 4832 /** 4833 * Gamma curve slopes, used for crgb conversion. 4834 */ 4835 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B 4836 /** 4837 * Custom backlight curve thresholds. 4838 */ 4839 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B 4840 /** 4841 * Custom backlight curve offsets. 4842 */ 4843 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B 4844 /** 4845 * Ambient light thresholds. 4846 */ 4847 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B 4848 /** 4849 * Minimum programmable backlight. 4850 */ 4851 uint16_t min_abm_backlight; // 122B 4852 /** 4853 * Minimum reduction values. 4854 */ 4855 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B 4856 /** 4857 * Maximum reduction values. 4858 */ 4859 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B 4860 /** 4861 * Bright positive gain. 4862 */ 4863 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B 4864 /** 4865 * Dark negative gain. 4866 */ 4867 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B 4868 /** 4869 * Hybrid factor. 4870 */ 4871 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B 4872 /** 4873 * Contrast factor. 4874 */ 4875 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B 4876 /** 4877 * Deviation gain. 4878 */ 4879 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B 4880 /** 4881 * Minimum knee. 4882 */ 4883 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B 4884 /** 4885 * Maximum knee. 4886 */ 4887 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B 4888 /** 4889 * Unused. 4890 */ 4891 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B 4892 /** 4893 * Explicit padding to 4 byte boundary. 4894 */ 4895 uint8_t pad3[3]; // 229B 4896 /** 4897 * Backlight ramp reduction. 4898 */ 4899 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B 4900 /** 4901 * Backlight ramp start. 4902 */ 4903 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B 4904 }; 4905 4906 /** 4907 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4908 */ 4909 struct dmub_cmd_abm_set_pipe_data { 4910 /** 4911 * OTG HW instance. 4912 */ 4913 uint8_t otg_inst; 4914 4915 /** 4916 * Panel Control HW instance. 4917 */ 4918 uint8_t panel_inst; 4919 4920 /** 4921 * Controls how ABM will interpret a set pipe or set level command. 4922 */ 4923 uint8_t set_pipe_option; 4924 4925 /** 4926 * Unused. 4927 * TODO: Remove. 4928 */ 4929 uint8_t ramping_boundary; 4930 4931 /** 4932 * PwrSeq HW Instance. 4933 */ 4934 uint8_t pwrseq_inst; 4935 4936 /** 4937 * Explicit padding to 4 byte boundary. 4938 */ 4939 uint8_t pad[3]; 4940 }; 4941 4942 /** 4943 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 4944 */ 4945 struct dmub_rb_cmd_abm_set_pipe { 4946 /** 4947 * Command header. 4948 */ 4949 struct dmub_cmd_header header; 4950 4951 /** 4952 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command. 4953 */ 4954 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data; 4955 }; 4956 4957 /** 4958 * Type of backlight control method to be used by ABM module 4959 */ 4960 enum dmub_backlight_control_type { 4961 /** 4962 * PWM Backlight control 4963 */ 4964 DMU_BACKLIGHT_CONTROL_PWM = 0, 4965 /** 4966 * VESA Aux-based backlight control 4967 */ 4968 DMU_BACKLIGHT_CONTROL_VESA_AUX = 1, 4969 /** 4970 * AMD DPCD Aux-based backlight control 4971 */ 4972 DMU_BACKLIGHT_CONTROL_AMD_AUX = 2, 4973 }; 4974 4975 /** 4976 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 4977 */ 4978 struct dmub_cmd_abm_set_backlight_data { 4979 /** 4980 * Number of frames to ramp to backlight user level. 4981 */ 4982 uint32_t frame_ramp; 4983 4984 /** 4985 * Requested backlight level from user. 4986 */ 4987 uint32_t backlight_user_level; 4988 4989 /** 4990 * ABM control version. 4991 */ 4992 uint8_t version; 4993 4994 /** 4995 * Panel Control HW instance mask. 4996 * Bit 0 is Panel Control HW instance 0. 4997 * Bit 1 is Panel Control HW instance 1. 4998 */ 4999 uint8_t panel_mask; 5000 5001 /** 5002 * AUX HW Instance. 5003 */ 5004 uint8_t aux_inst; 5005 5006 /** 5007 * Explicit padding to 4 byte boundary. 5008 */ 5009 uint8_t pad[1]; 5010 5011 /** 5012 * Backlight control type. 5013 * Value 0 is PWM backlight control. 5014 * Value 1 is VAUX backlight control. 5015 * Value 2 is AMD DPCD AUX backlight control. 5016 */ 5017 enum dmub_backlight_control_type backlight_control_type; 5018 5019 /** 5020 * Minimum luminance in nits. 5021 */ 5022 uint32_t min_luminance; 5023 5024 /** 5025 * Maximum luminance in nits. 5026 */ 5027 uint32_t max_luminance; 5028 5029 /** 5030 * Minimum backlight in pwm. 5031 */ 5032 uint32_t min_backlight_pwm; 5033 5034 /** 5035 * Maximum backlight in pwm. 5036 */ 5037 uint32_t max_backlight_pwm; 5038 }; 5039 5040 /** 5041 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 5042 */ 5043 struct dmub_rb_cmd_abm_set_backlight { 5044 /** 5045 * Command header. 5046 */ 5047 struct dmub_cmd_header header; 5048 5049 /** 5050 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command. 5051 */ 5052 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data; 5053 }; 5054 5055 /** 5056 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5057 */ 5058 struct dmub_cmd_abm_set_level_data { 5059 /** 5060 * Set current ABM operating/aggression level. 5061 */ 5062 uint32_t level; 5063 5064 /** 5065 * ABM control version. 5066 */ 5067 uint8_t version; 5068 5069 /** 5070 * Panel Control HW instance mask. 5071 * Bit 0 is Panel Control HW instance 0. 5072 * Bit 1 is Panel Control HW instance 1. 5073 */ 5074 uint8_t panel_mask; 5075 5076 /** 5077 * Explicit padding to 4 byte boundary. 5078 */ 5079 uint8_t pad[2]; 5080 }; 5081 5082 /** 5083 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 5084 */ 5085 struct dmub_rb_cmd_abm_set_level { 5086 /** 5087 * Command header. 5088 */ 5089 struct dmub_cmd_header header; 5090 5091 /** 5092 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command. 5093 */ 5094 struct dmub_cmd_abm_set_level_data abm_set_level_data; 5095 }; 5096 5097 /** 5098 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5099 */ 5100 struct dmub_cmd_abm_set_ambient_level_data { 5101 /** 5102 * Ambient light sensor reading from OS. 5103 */ 5104 uint32_t ambient_lux; 5105 5106 /** 5107 * ABM control version. 5108 */ 5109 uint8_t version; 5110 5111 /** 5112 * Panel Control HW instance mask. 5113 * Bit 0 is Panel Control HW instance 0. 5114 * Bit 1 is Panel Control HW instance 1. 5115 */ 5116 uint8_t panel_mask; 5117 5118 /** 5119 * Explicit padding to 4 byte boundary. 5120 */ 5121 uint8_t pad[2]; 5122 }; 5123 5124 /** 5125 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5126 */ 5127 struct dmub_rb_cmd_abm_set_ambient_level { 5128 /** 5129 * Command header. 5130 */ 5131 struct dmub_cmd_header header; 5132 5133 /** 5134 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 5135 */ 5136 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data; 5137 }; 5138 5139 /** 5140 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5141 */ 5142 struct dmub_cmd_abm_set_pwm_frac_data { 5143 /** 5144 * Enable/disable fractional duty cycle for backlight PWM. 5145 * TODO: Convert to uint8_t. 5146 */ 5147 uint32_t fractional_pwm; 5148 5149 /** 5150 * ABM control version. 5151 */ 5152 uint8_t version; 5153 5154 /** 5155 * Panel Control HW instance mask. 5156 * Bit 0 is Panel Control HW instance 0. 5157 * Bit 1 is Panel Control HW instance 1. 5158 */ 5159 uint8_t panel_mask; 5160 5161 /** 5162 * Explicit padding to 4 byte boundary. 5163 */ 5164 uint8_t pad[2]; 5165 }; 5166 5167 /** 5168 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 5169 */ 5170 struct dmub_rb_cmd_abm_set_pwm_frac { 5171 /** 5172 * Command header. 5173 */ 5174 struct dmub_cmd_header header; 5175 5176 /** 5177 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command. 5178 */ 5179 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data; 5180 }; 5181 5182 /** 5183 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5184 */ 5185 struct dmub_cmd_abm_init_config_data { 5186 /** 5187 * Location of indirect buffer used to pass init data to ABM. 5188 */ 5189 union dmub_addr src; 5190 5191 /** 5192 * Indirect buffer length. 5193 */ 5194 uint16_t bytes; 5195 5196 5197 /** 5198 * ABM control version. 5199 */ 5200 uint8_t version; 5201 5202 /** 5203 * Panel Control HW instance mask. 5204 * Bit 0 is Panel Control HW instance 0. 5205 * Bit 1 is Panel Control HW instance 1. 5206 */ 5207 uint8_t panel_mask; 5208 5209 /** 5210 * Explicit padding to 4 byte boundary. 5211 */ 5212 uint8_t pad[2]; 5213 }; 5214 5215 /** 5216 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 5217 */ 5218 struct dmub_rb_cmd_abm_init_config { 5219 /** 5220 * Command header. 5221 */ 5222 struct dmub_cmd_header header; 5223 5224 /** 5225 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5226 */ 5227 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5228 }; 5229 5230 /** 5231 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5232 */ 5233 5234 struct dmub_cmd_abm_pause_data { 5235 5236 /** 5237 * Panel Control HW instance mask. 5238 * Bit 0 is Panel Control HW instance 0. 5239 * Bit 1 is Panel Control HW instance 1. 5240 */ 5241 uint8_t panel_mask; 5242 5243 /** 5244 * OTG hw instance 5245 */ 5246 uint8_t otg_inst; 5247 5248 /** 5249 * Enable or disable ABM pause 5250 */ 5251 uint8_t enable; 5252 5253 /** 5254 * Explicit padding to 4 byte boundary. 5255 */ 5256 uint8_t pad[1]; 5257 }; 5258 5259 /** 5260 * Definition of a DMUB_CMD__ABM_PAUSE command. 5261 */ 5262 struct dmub_rb_cmd_abm_pause { 5263 /** 5264 * Command header. 5265 */ 5266 struct dmub_cmd_header header; 5267 5268 /** 5269 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command. 5270 */ 5271 struct dmub_cmd_abm_pause_data abm_pause_data; 5272 }; 5273 5274 /** 5275 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. 5276 */ 5277 struct dmub_cmd_abm_query_caps_in { 5278 /** 5279 * Panel instance. 5280 */ 5281 uint8_t panel_inst; 5282 5283 /** 5284 * Explicit padding to 4 byte boundary. 5285 */ 5286 uint8_t pad[3]; 5287 }; 5288 5289 /** 5290 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5291 */ 5292 struct dmub_cmd_abm_query_caps_out { 5293 /** 5294 * SW Algorithm caps. 5295 */ 5296 struct abm_caps sw_caps; 5297 5298 /** 5299 * ABM HW caps. 5300 */ 5301 struct abm_caps hw_caps; 5302 }; 5303 5304 /** 5305 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 5306 */ 5307 struct dmub_rb_cmd_abm_query_caps { 5308 /** 5309 * Command header. 5310 */ 5311 struct dmub_cmd_header header; 5312 5313 /** 5314 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. 5315 */ 5316 union { 5317 struct dmub_cmd_abm_query_caps_in abm_query_caps_in; 5318 struct dmub_cmd_abm_query_caps_out abm_query_caps_out; 5319 } data; 5320 }; 5321 5322 /** 5323 * enum dmub_abm_ace_curve_type - ACE curve type. 5324 */ 5325 enum dmub_abm_ace_curve_type { 5326 /** 5327 * ACE curve as defined by the SW layer. 5328 */ 5329 ABM_ACE_CURVE_TYPE__SW = 0, 5330 /** 5331 * ACE curve as defined by the SW to HW translation interface layer. 5332 */ 5333 ABM_ACE_CURVE_TYPE__SW_IF = 1, 5334 }; 5335 5336 /** 5337 * enum dmub_abm_histogram_type - Histogram type. 5338 */ 5339 enum dmub_abm_histogram_type { 5340 /** 5341 * ACE curve as defined by the SW layer. 5342 */ 5343 ABM_HISTOGRAM_TYPE__SW = 0, 5344 /** 5345 * ACE curve as defined by the SW to HW translation interface layer. 5346 */ 5347 ABM_HISTOGRAM_TYPE__SW_IF = 1, 5348 }; 5349 5350 /** 5351 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 5352 */ 5353 struct dmub_rb_cmd_abm_get_ace_curve { 5354 /** 5355 * Command header. 5356 */ 5357 struct dmub_cmd_header header; 5358 5359 /** 5360 * Address where ACE curve should be copied. 5361 */ 5362 union dmub_addr dest; 5363 5364 /** 5365 * Type of ACE curve being queried. 5366 */ 5367 enum dmub_abm_ace_curve_type ace_type; 5368 5369 /** 5370 * Indirect buffer length. 5371 */ 5372 uint16_t bytes; 5373 5374 /** 5375 * eDP panel instance. 5376 */ 5377 uint8_t panel_inst; 5378 5379 /** 5380 * Explicit padding to 4 byte boundary. 5381 */ 5382 uint8_t pad; 5383 }; 5384 5385 /** 5386 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 5387 */ 5388 struct dmub_rb_cmd_abm_get_histogram { 5389 /** 5390 * Command header. 5391 */ 5392 struct dmub_cmd_header header; 5393 5394 /** 5395 * Address where Histogram should be copied. 5396 */ 5397 union dmub_addr dest; 5398 5399 /** 5400 * Type of Histogram being queried. 5401 */ 5402 enum dmub_abm_histogram_type histogram_type; 5403 5404 /** 5405 * Indirect buffer length. 5406 */ 5407 uint16_t bytes; 5408 5409 /** 5410 * eDP panel instance. 5411 */ 5412 uint8_t panel_inst; 5413 5414 /** 5415 * Explicit padding to 4 byte boundary. 5416 */ 5417 uint8_t pad; 5418 }; 5419 5420 /** 5421 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 5422 */ 5423 struct dmub_rb_cmd_abm_save_restore { 5424 /** 5425 * Command header. 5426 */ 5427 struct dmub_cmd_header header; 5428 5429 /** 5430 * OTG hw instance 5431 */ 5432 uint8_t otg_inst; 5433 5434 /** 5435 * Enable or disable ABM pause 5436 */ 5437 uint8_t freeze; 5438 5439 /** 5440 * Explicit padding to 4 byte boundary. 5441 */ 5442 uint8_t debug; 5443 5444 /** 5445 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command. 5446 */ 5447 struct dmub_cmd_abm_init_config_data abm_init_config_data; 5448 }; 5449 5450 /** 5451 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5452 */ 5453 5454 struct dmub_cmd_abm_set_event_data { 5455 5456 /** 5457 * VB Scaling Init. Strength Mapping 5458 * Byte 0: 0~255 for VB level 0 5459 * Byte 1: 0~255 for VB level 1 5460 * Byte 2: 0~255 for VB level 2 5461 * Byte 3: 0~255 for VB level 3 5462 */ 5463 uint32_t vb_scaling_strength_mapping; 5464 /** 5465 * VariBright Scaling Enable 5466 */ 5467 uint8_t vb_scaling_enable; 5468 /** 5469 * Panel Control HW instance mask. 5470 * Bit 0 is Panel Control HW instance 0. 5471 * Bit 1 is Panel Control HW instance 1. 5472 */ 5473 uint8_t panel_mask; 5474 5475 /** 5476 * Explicit padding to 4 byte boundary. 5477 */ 5478 uint8_t pad[2]; 5479 }; 5480 5481 /** 5482 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 5483 */ 5484 struct dmub_rb_cmd_abm_set_event { 5485 /** 5486 * Command header. 5487 */ 5488 struct dmub_cmd_header header; 5489 5490 /** 5491 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. 5492 */ 5493 struct dmub_cmd_abm_set_event_data abm_set_event_data; 5494 }; 5495 5496 /** 5497 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5498 */ 5499 struct dmub_cmd_query_feature_caps_data { 5500 /** 5501 * DMUB feature capabilities. 5502 * After DMUB init, driver will query FW capabilities prior to enabling certain features. 5503 */ 5504 struct dmub_feature_caps feature_caps; 5505 }; 5506 5507 /** 5508 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 5509 */ 5510 struct dmub_rb_cmd_query_feature_caps { 5511 /** 5512 * Command header. 5513 */ 5514 struct dmub_cmd_header header; 5515 /** 5516 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. 5517 */ 5518 struct dmub_cmd_query_feature_caps_data query_feature_caps_data; 5519 }; 5520 5521 /** 5522 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5523 */ 5524 struct dmub_cmd_visual_confirm_color_data { 5525 /** 5526 * DMUB visual confirm color 5527 */ 5528 struct dmub_visual_confirm_color visual_confirm_color; 5529 }; 5530 5531 /** 5532 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5533 */ 5534 struct dmub_rb_cmd_get_visual_confirm_color { 5535 /** 5536 * Command header. 5537 */ 5538 struct dmub_cmd_header header; 5539 /** 5540 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 5541 */ 5542 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data; 5543 }; 5544 5545 /** 5546 * enum dmub_cmd_panel_cntl_type - Panel control command. 5547 */ 5548 enum dmub_cmd_panel_cntl_type { 5549 /** 5550 * Initializes embedded panel hardware blocks. 5551 */ 5552 DMUB_CMD__PANEL_CNTL_HW_INIT = 0, 5553 /** 5554 * Queries backlight info for the embedded panel. 5555 */ 5556 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1, 5557 /** 5558 * Sets the PWM Freq as per user's requirement. 5559 */ 5560 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2, 5561 }; 5562 5563 /** 5564 * struct dmub_cmd_panel_cntl_data - Panel control data. 5565 */ 5566 struct dmub_cmd_panel_cntl_data { 5567 uint32_t pwrseq_inst; /**< pwrseq instance */ 5568 uint32_t current_backlight; /* in/out */ 5569 uint32_t bl_pwm_cntl; /* in/out */ 5570 uint32_t bl_pwm_period_cntl; /* in/out */ 5571 uint32_t bl_pwm_ref_div1; /* in/out */ 5572 uint8_t is_backlight_on : 1; /* in/out */ 5573 uint8_t is_powered_on : 1; /* in/out */ 5574 uint8_t padding[3]; 5575 uint32_t bl_pwm_ref_div2; /* in/out */ 5576 uint8_t reserved[4]; 5577 }; 5578 5579 /** 5580 * struct dmub_rb_cmd_panel_cntl - Panel control command. 5581 */ 5582 struct dmub_rb_cmd_panel_cntl { 5583 struct dmub_cmd_header header; /**< header */ 5584 struct dmub_cmd_panel_cntl_data data; /**< payload */ 5585 }; 5586 5587 struct dmub_optc_state { 5588 uint32_t v_total_max; 5589 uint32_t v_total_min; 5590 uint32_t tg_inst; 5591 }; 5592 5593 struct dmub_rb_cmd_drr_update { 5594 struct dmub_cmd_header header; 5595 struct dmub_optc_state dmub_optc_state_req; 5596 }; 5597 5598 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data { 5599 uint32_t pix_clk_100hz; 5600 uint8_t max_ramp_step; 5601 uint8_t pipes; 5602 uint8_t min_refresh_in_hz; 5603 uint8_t pipe_count; 5604 uint8_t pipe_index[4]; 5605 }; 5606 5607 struct dmub_cmd_fw_assisted_mclk_switch_config { 5608 uint8_t fams_enabled; 5609 uint8_t visual_confirm_enabled; 5610 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive 5611 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS]; 5612 }; 5613 5614 struct dmub_rb_cmd_fw_assisted_mclk_switch { 5615 struct dmub_cmd_header header; 5616 struct dmub_cmd_fw_assisted_mclk_switch_config config_data; 5617 }; 5618 5619 /** 5620 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5621 */ 5622 struct dmub_cmd_lvtma_control_data { 5623 uint8_t uc_pwr_action; /**< LVTMA_ACTION */ 5624 uint8_t bypass_panel_control_wait; 5625 uint8_t reserved_0[2]; /**< For future use */ 5626 uint8_t pwrseq_inst; /**< LVTMA control instance */ 5627 uint8_t reserved_1[3]; /**< For future use */ 5628 }; 5629 5630 /** 5631 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5632 */ 5633 struct dmub_rb_cmd_lvtma_control { 5634 /** 5635 * Command header. 5636 */ 5637 struct dmub_cmd_header header; 5638 /** 5639 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 5640 */ 5641 struct dmub_cmd_lvtma_control_data data; 5642 }; 5643 5644 /** 5645 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5646 */ 5647 struct dmub_rb_cmd_transmitter_query_dp_alt_data { 5648 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5649 uint8_t is_usb; /**< is phy is usb */ 5650 uint8_t is_dp_alt_disable; /**< is dp alt disable */ 5651 uint8_t is_dp4; /**< is dp in 4 lane */ 5652 }; 5653 5654 /** 5655 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 5656 */ 5657 struct dmub_rb_cmd_transmitter_query_dp_alt { 5658 struct dmub_cmd_header header; /**< header */ 5659 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */ 5660 }; 5661 5662 struct phy_test_mode { 5663 uint8_t mode; 5664 uint8_t pat0; 5665 uint8_t pad[2]; 5666 }; 5667 5668 /** 5669 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5670 */ 5671 struct dmub_rb_cmd_transmitter_set_phy_fsm_data { 5672 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */ 5673 uint8_t mode; /**< HDMI/DP/DP2 etc */ 5674 uint8_t lane_num; /**< Number of lanes */ 5675 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */ 5676 struct phy_test_mode test_mode; 5677 enum dmub_phy_fsm_state state; 5678 uint32_t status; 5679 uint8_t pad; 5680 }; 5681 5682 /** 5683 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 5684 */ 5685 struct dmub_rb_cmd_transmitter_set_phy_fsm { 5686 struct dmub_cmd_header header; /**< header */ 5687 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */ 5688 }; 5689 5690 /** 5691 * Maximum number of bytes a chunk sent to DMUB for parsing 5692 */ 5693 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8 5694 5695 /** 5696 * Represent a chunk of CEA blocks sent to DMUB for parsing 5697 */ 5698 struct dmub_cmd_send_edid_cea { 5699 uint16_t offset; /**< offset into the CEA block */ 5700 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */ 5701 uint16_t cea_total_length; /**< total length of the CEA block */ 5702 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */ 5703 uint8_t pad[3]; /**< padding and for future expansion */ 5704 }; 5705 5706 /** 5707 * Result of VSDB parsing from CEA block 5708 */ 5709 struct dmub_cmd_edid_cea_amd_vsdb { 5710 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */ 5711 uint8_t freesync_supported; /**< 1 if Freesync is supported */ 5712 uint16_t amd_vsdb_version; /**< AMD VSDB version */ 5713 uint16_t min_frame_rate; /**< Maximum frame rate */ 5714 uint16_t max_frame_rate; /**< Minimum frame rate */ 5715 }; 5716 5717 /** 5718 * Result of sending a CEA chunk 5719 */ 5720 struct dmub_cmd_edid_cea_ack { 5721 uint16_t offset; /**< offset of the chunk into the CEA block */ 5722 uint8_t success; /**< 1 if this sending of chunk succeeded */ 5723 uint8_t pad; /**< padding and for future expansion */ 5724 }; 5725 5726 /** 5727 * Specify whether the result is an ACK/NACK or the parsing has finished 5728 */ 5729 enum dmub_cmd_edid_cea_reply_type { 5730 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */ 5731 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */ 5732 }; 5733 5734 /** 5735 * Definition of a DMUB_CMD__EDID_CEA command. 5736 */ 5737 struct dmub_rb_cmd_edid_cea { 5738 struct dmub_cmd_header header; /**< Command header */ 5739 union dmub_cmd_edid_cea_data { 5740 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */ 5741 struct dmub_cmd_edid_cea_output { /**< output with results */ 5742 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */ 5743 union { 5744 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb; 5745 struct dmub_cmd_edid_cea_ack ack; 5746 }; 5747 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */ 5748 } data; /**< Command data */ 5749 5750 }; 5751 5752 /** 5753 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command. 5754 */ 5755 struct dmub_cmd_cable_id_input { 5756 uint8_t phy_inst; /**< phy inst for cable id data */ 5757 }; 5758 5759 /** 5760 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command. 5761 */ 5762 struct dmub_cmd_cable_id_output { 5763 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */ 5764 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */ 5765 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */ 5766 uint8_t RESERVED :2; /**< reserved means not defined */ 5767 }; 5768 5769 /** 5770 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command 5771 */ 5772 struct dmub_rb_cmd_get_usbc_cable_id { 5773 struct dmub_cmd_header header; /**< Command header */ 5774 /** 5775 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command. 5776 */ 5777 union dmub_cmd_cable_id_data { 5778 struct dmub_cmd_cable_id_input input; /**< Input */ 5779 struct dmub_cmd_cable_id_output output; /**< Output */ 5780 uint8_t output_raw; /**< Raw data output */ 5781 } data; 5782 }; 5783 5784 enum dmub_cmd_fused_io_sub_type { 5785 DMUB_CMD__FUSED_IO_EXECUTE = 0, 5786 DMUB_CMD__FUSED_IO_ABORT = 1, 5787 }; 5788 5789 enum dmub_cmd_fused_request_type { 5790 FUSED_REQUEST_READ, 5791 FUSED_REQUEST_WRITE, 5792 FUSED_REQUEST_POLL, 5793 }; 5794 5795 enum dmub_cmd_fused_request_status { 5796 FUSED_REQUEST_STATUS_SUCCESS, 5797 FUSED_REQUEST_STATUS_BEGIN, 5798 FUSED_REQUEST_STATUS_SUBMIT, 5799 FUSED_REQUEST_STATUS_REPLY, 5800 FUSED_REQUEST_STATUS_POLL, 5801 FUSED_REQUEST_STATUS_ABORTED, 5802 FUSED_REQUEST_STATUS_FAILED = 0x80, 5803 FUSED_REQUEST_STATUS_INVALID, 5804 FUSED_REQUEST_STATUS_BUSY, 5805 FUSED_REQUEST_STATUS_TIMEOUT, 5806 FUSED_REQUEST_STATUS_POLL_TIMEOUT, 5807 }; 5808 5809 struct dmub_cmd_fused_request { 5810 uint8_t status; 5811 uint8_t type : 2; 5812 uint8_t _reserved0 : 3; 5813 uint8_t poll_mask_msb : 3; // Number of MSB to zero out from last byte before comparing 5814 uint8_t identifier; 5815 uint8_t _reserved1; 5816 uint32_t timeout_us; 5817 union dmub_cmd_fused_request_location { 5818 struct dmub_cmd_fused_request_location_i2c { 5819 uint8_t is_aux : 1; // False 5820 uint8_t ddc_line : 3; 5821 uint8_t over_aux : 1; 5822 uint8_t _reserved0 : 3; 5823 uint8_t address; 5824 uint8_t offset; 5825 uint8_t length; 5826 } i2c; 5827 struct dmub_cmd_fused_request_location_aux { 5828 uint32_t is_aux : 1; // True 5829 uint32_t ddc_line : 3; 5830 uint32_t address : 20; 5831 uint32_t length : 8; // Automatically split into 16B transactions 5832 } aux; 5833 } u; 5834 uint8_t buffer[0x30]; // Read: out, write: in, poll: expected 5835 }; 5836 5837 struct dmub_rb_cmd_fused_io { 5838 struct dmub_cmd_header header; 5839 struct dmub_cmd_fused_request request; 5840 }; 5841 5842 /** 5843 * Command type of a DMUB_CMD__SECURE_DISPLAY command 5844 */ 5845 enum dmub_cmd_secure_display_type { 5846 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */ 5847 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE, 5848 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY, 5849 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_STOP_UPDATE, 5850 DMUB_CMD__SECURE_DISPLAY_MULTIPLE_CRC_WIN_NOTIFY 5851 }; 5852 5853 #define MAX_ROI_NUM 2 5854 5855 struct dmub_cmd_roi_info { 5856 uint16_t x_start; 5857 uint16_t x_end; 5858 uint16_t y_start; 5859 uint16_t y_end; 5860 uint8_t otg_id; 5861 uint8_t phy_id; 5862 }; 5863 5864 struct dmub_cmd_roi_window_ctl { 5865 uint16_t x_start; 5866 uint16_t x_end; 5867 uint16_t y_start; 5868 uint16_t y_end; 5869 bool enable; 5870 }; 5871 5872 struct dmub_cmd_roi_ctl_info { 5873 uint8_t otg_id; 5874 uint8_t phy_id; 5875 struct dmub_cmd_roi_window_ctl roi_ctl[MAX_ROI_NUM]; 5876 }; 5877 5878 /** 5879 * Definition of a DMUB_CMD__SECURE_DISPLAY command 5880 */ 5881 struct dmub_rb_cmd_secure_display { 5882 struct dmub_cmd_header header; 5883 /** 5884 * Data passed from driver to dmub firmware. 5885 */ 5886 struct dmub_cmd_roi_info roi_info; 5887 struct dmub_cmd_roi_ctl_info mul_roi_ctl; 5888 }; 5889 5890 /** 5891 * Command type of a DMUB_CMD__PSP command 5892 */ 5893 enum dmub_cmd_psp_type { 5894 DMUB_CMD__PSP_ASSR_ENABLE = 0 5895 }; 5896 5897 /** 5898 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command. 5899 */ 5900 struct dmub_cmd_assr_enable_data { 5901 /** 5902 * ASSR enable or disable. 5903 */ 5904 uint8_t enable; 5905 /** 5906 * PHY port type. 5907 * Indicates eDP / non-eDP port type 5908 */ 5909 uint8_t phy_port_type; 5910 /** 5911 * PHY port ID. 5912 */ 5913 uint8_t phy_port_id; 5914 /** 5915 * Link encoder index. 5916 */ 5917 uint8_t link_enc_index; 5918 /** 5919 * HPO mode. 5920 */ 5921 uint8_t hpo_mode; 5922 5923 /** 5924 * Reserved field. 5925 */ 5926 uint8_t reserved[7]; 5927 }; 5928 5929 /** 5930 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 5931 */ 5932 struct dmub_rb_cmd_assr_enable { 5933 /** 5934 * Command header. 5935 */ 5936 struct dmub_cmd_header header; 5937 5938 /** 5939 * Assr data. 5940 */ 5941 struct dmub_cmd_assr_enable_data assr_data; 5942 5943 /** 5944 * Reserved field. 5945 */ 5946 uint32_t reserved[3]; 5947 }; 5948 5949 /** 5950 * Current definition of "ips_mode" from driver 5951 */ 5952 enum ips_residency_mode { 5953 IPS_RESIDENCY__IPS1_MAX, 5954 IPS_RESIDENCY__IPS2, 5955 IPS_RESIDENCY__IPS1_RCG, 5956 IPS_RESIDENCY__IPS1_ONO2_ON, 5957 IPS_RESIDENCY__IPS1_Z8_RETENTION, 5958 }; 5959 5960 #define NUM_IPS_HISTOGRAM_BUCKETS 16 5961 5962 /** 5963 * IPS residency statistics to be sent to driver - subset of struct dmub_ips_residency_stats 5964 */ 5965 struct dmub_ips_residency_info { 5966 uint32_t residency_millipercent; 5967 uint32_t entry_counter; 5968 uint32_t histogram[NUM_IPS_HISTOGRAM_BUCKETS]; 5969 uint64_t total_time_us; 5970 uint64_t total_inactive_time_us; 5971 }; 5972 5973 /** 5974 * Data passed from driver to FW in a DMUB_CMD__IPS_RESIDENCY_CNTL command. 5975 */ 5976 struct dmub_cmd_ips_residency_cntl_data { 5977 uint8_t panel_inst; 5978 uint8_t start_measurement; 5979 uint8_t padding[2]; // align to 4-byte boundary 5980 }; 5981 5982 struct dmub_rb_cmd_ips_residency_cntl { 5983 struct dmub_cmd_header header; 5984 struct dmub_cmd_ips_residency_cntl_data cntl_data; 5985 }; 5986 5987 /** 5988 * Data passed from FW to driver in a DMUB_CMD__IPS_QUERY_RESIDENCY_INFO command. 5989 */ 5990 struct dmub_cmd_ips_query_residency_info_data { 5991 union dmub_addr dest; 5992 uint32_t size; 5993 uint32_t ips_mode; 5994 uint8_t panel_inst; 5995 uint8_t padding[3]; // align to 4-byte boundary 5996 }; 5997 5998 struct dmub_rb_cmd_ips_query_residency_info { 5999 struct dmub_cmd_header header; 6000 struct dmub_cmd_ips_query_residency_info_data info_data; 6001 }; 6002 6003 /** 6004 * union dmub_rb_cmd - DMUB inbox command. 6005 */ 6006 union dmub_rb_cmd { 6007 /** 6008 * Elements shared with all commands. 6009 */ 6010 struct dmub_rb_cmd_common cmd_common; 6011 /** 6012 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command. 6013 */ 6014 struct dmub_rb_cmd_read_modify_write read_modify_write; 6015 /** 6016 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command. 6017 */ 6018 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq; 6019 /** 6020 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command. 6021 */ 6022 struct dmub_rb_cmd_burst_write burst_write; 6023 /** 6024 * Definition of a DMUB_CMD__REG_REG_WAIT command. 6025 */ 6026 struct dmub_rb_cmd_reg_wait reg_wait; 6027 /** 6028 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command. 6029 */ 6030 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control; 6031 /** 6032 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command. 6033 */ 6034 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock; 6035 /** 6036 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command. 6037 */ 6038 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating; 6039 /** 6040 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command. 6041 */ 6042 struct dmub_rb_cmd_dpphy_init dpphy_init; 6043 /** 6044 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command. 6045 */ 6046 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control; 6047 /** 6048 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command. 6049 */ 6050 struct dmub_rb_cmd_domain_control domain_control; 6051 /** 6052 * Definition of a DMUB_CMD__PSR_SET_VERSION command. 6053 */ 6054 struct dmub_rb_cmd_psr_set_version psr_set_version; 6055 /** 6056 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command. 6057 */ 6058 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings; 6059 /** 6060 * Definition of a DMUB_CMD__PSR_ENABLE command. 6061 */ 6062 struct dmub_rb_cmd_psr_enable psr_enable; 6063 /** 6064 * Definition of a DMUB_CMD__PSR_SET_LEVEL command. 6065 */ 6066 struct dmub_rb_cmd_psr_set_level psr_set_level; 6067 /** 6068 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command. 6069 */ 6070 struct dmub_rb_cmd_psr_force_static psr_force_static; 6071 /** 6072 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command. 6073 */ 6074 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect; 6075 /** 6076 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command. 6077 */ 6078 struct dmub_rb_cmd_update_cursor_info update_cursor_info; 6079 /** 6080 * Definition of a DMUB_CMD__HW_LOCK command. 6081 * Command is used by driver and FW. 6082 */ 6083 struct dmub_rb_cmd_lock_hw lock_hw; 6084 /** 6085 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command. 6086 */ 6087 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal; 6088 /** 6089 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command. 6090 */ 6091 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt; 6092 /** 6093 * Definition of a DMUB_CMD__PLAT_54186_WA command. 6094 */ 6095 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa; 6096 /** 6097 * Definition of a DMUB_CMD__MALL command. 6098 */ 6099 struct dmub_rb_cmd_mall mall; 6100 6101 /** 6102 * Definition of a DMUB_CMD__CAB command. 6103 */ 6104 struct dmub_rb_cmd_cab_for_ss cab; 6105 6106 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2; 6107 6108 /** 6109 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command. 6110 */ 6111 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore; 6112 6113 /** 6114 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command. 6115 */ 6116 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks; 6117 6118 /** 6119 * Definition of DMUB_CMD__PANEL_CNTL commands. 6120 */ 6121 struct dmub_rb_cmd_panel_cntl panel_cntl; 6122 6123 /** 6124 * Definition of a DMUB_CMD__ABM_SET_PIPE command. 6125 */ 6126 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe; 6127 6128 /** 6129 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command. 6130 */ 6131 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight; 6132 6133 /** 6134 * Definition of a DMUB_CMD__ABM_SET_LEVEL command. 6135 */ 6136 struct dmub_rb_cmd_abm_set_level abm_set_level; 6137 6138 /** 6139 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command. 6140 */ 6141 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level; 6142 6143 /** 6144 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command. 6145 */ 6146 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac; 6147 6148 /** 6149 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command. 6150 */ 6151 struct dmub_rb_cmd_abm_init_config abm_init_config; 6152 6153 /** 6154 * Definition of a DMUB_CMD__ABM_PAUSE command. 6155 */ 6156 struct dmub_rb_cmd_abm_pause abm_pause; 6157 6158 /** 6159 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. 6160 */ 6161 struct dmub_rb_cmd_abm_save_restore abm_save_restore; 6162 6163 /** 6164 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. 6165 */ 6166 struct dmub_rb_cmd_abm_query_caps abm_query_caps; 6167 6168 /** 6169 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command. 6170 */ 6171 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve; 6172 6173 /** 6174 * Definition of a DMUB_CMD__ABM_GET_HISTOGRAM command. 6175 */ 6176 struct dmub_rb_cmd_abm_get_histogram abm_get_histogram; 6177 6178 /** 6179 * Definition of a DMUB_CMD__ABM_SET_EVENT command. 6180 */ 6181 struct dmub_rb_cmd_abm_set_event abm_set_event; 6182 6183 /** 6184 * Definition of a DMUB_CMD__DP_AUX_ACCESS command. 6185 */ 6186 struct dmub_rb_cmd_dp_aux_access dp_aux_access; 6187 6188 /** 6189 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command. 6190 */ 6191 struct dmub_rb_cmd_outbox1_enable outbox1_enable; 6192 6193 /** 6194 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command. 6195 */ 6196 struct dmub_rb_cmd_query_feature_caps query_feature_caps; 6197 6198 /** 6199 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command. 6200 */ 6201 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color; 6202 struct dmub_rb_cmd_drr_update drr_update; 6203 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch; 6204 6205 /** 6206 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command. 6207 */ 6208 struct dmub_rb_cmd_lvtma_control lvtma_control; 6209 /** 6210 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command. 6211 */ 6212 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt; 6213 /** 6214 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command. 6215 */ 6216 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm; 6217 /** 6218 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command. 6219 */ 6220 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control; 6221 /** 6222 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6223 */ 6224 struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) 6225 /** 6226 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. 6227 */ 6228 struct dmub_rb_cmd_set_config_request set_config_request; 6229 /** 6230 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. 6231 */ 6232 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; 6233 /** 6234 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. 6235 */ 6236 struct dmub_rb_cmd_set_tps_notification set_tps_notification; 6237 /** 6238 * Definition of a DMUB_CMD__EDID_CEA command. 6239 */ 6240 struct dmub_rb_cmd_edid_cea edid_cea; 6241 /** 6242 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command. 6243 */ 6244 struct dmub_rb_cmd_get_usbc_cable_id cable_id; 6245 6246 /** 6247 * Definition of a DMUB_CMD__QUERY_HPD_STATE command. 6248 */ 6249 struct dmub_rb_cmd_query_hpd_state query_hpd; 6250 /** 6251 * Definition of a DMUB_CMD__SECURE_DISPLAY command. 6252 */ 6253 struct dmub_rb_cmd_secure_display secure_display; 6254 6255 /** 6256 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command. 6257 */ 6258 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable; 6259 /** 6260 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. 6261 */ 6262 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; 6263 /** 6264 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. 6265 */ 6266 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; 6267 /* 6268 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. 6269 */ 6270 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings; 6271 /** 6272 * Definition of a DMUB_CMD__REPLAY_ENABLE command. 6273 */ 6274 struct dmub_rb_cmd_replay_enable replay_enable; 6275 /** 6276 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command. 6277 */ 6278 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt; 6279 /** 6280 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command. 6281 */ 6282 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal; 6283 /** 6284 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command. 6285 */ 6286 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal; 6287 6288 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync; 6289 /** 6290 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command. 6291 */ 6292 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer; 6293 /** 6294 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command. 6295 */ 6296 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal; 6297 /** 6298 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command. 6299 */ 6300 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp; 6301 /** 6302 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command. 6303 */ 6304 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd; 6305 /** 6306 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. 6307 */ 6308 struct dmub_rb_cmd_assr_enable assr_enable; 6309 6310 struct dmub_rb_cmd_fams2 fams2_config; 6311 6312 struct dmub_rb_cmd_ib ib_fams2_config; 6313 6314 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; 6315 6316 struct dmub_rb_cmd_fams2_flip fams2_flip; 6317 6318 struct dmub_rb_cmd_fused_io fused_io; 6319 6320 /** 6321 * Definition of a DMUB_CMD__LSDMA command. 6322 */ 6323 struct dmub_rb_cmd_lsdma lsdma; 6324 6325 struct dmub_rb_cmd_ips_residency_cntl ips_residency_cntl; 6326 6327 struct dmub_rb_cmd_ips_query_residency_info ips_query_residency_info; 6328 }; 6329 6330 /** 6331 * union dmub_rb_out_cmd - Outbox command 6332 */ 6333 union dmub_rb_out_cmd { 6334 /** 6335 * Parameters common to every command. 6336 */ 6337 struct dmub_rb_cmd_common cmd_common; 6338 /** 6339 * AUX reply command. 6340 */ 6341 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply; 6342 /** 6343 * HPD notify command. 6344 */ 6345 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify; 6346 /** 6347 * SET_CONFIG reply command. 6348 */ 6349 struct dmub_rb_cmd_dp_set_config_reply set_config_reply; 6350 /** 6351 * DPIA notification command. 6352 */ 6353 struct dmub_rb_cmd_dpia_notification dpia_notification; 6354 /** 6355 * HPD sense notification command. 6356 */ 6357 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify; 6358 struct dmub_rb_cmd_fused_io fused_io; 6359 }; 6360 #pragma pack(pop) 6361 6362 6363 //============================================================================== 6364 //</DMUB_CMD>=================================================================== 6365 //============================================================================== 6366 //< DMUB_RB>==================================================================== 6367 //============================================================================== 6368 6369 /** 6370 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer 6371 */ 6372 struct dmub_rb_init_params { 6373 void *ctx; /**< Caller provided context pointer */ 6374 void *base_address; /**< CPU base address for ring's data */ 6375 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6376 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */ 6377 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */ 6378 }; 6379 6380 /** 6381 * struct dmub_rb - Inbox or outbox DMUB ringbuffer 6382 */ 6383 struct dmub_rb { 6384 void *base_address; /**< CPU address for the ring's data */ 6385 uint32_t rptr; /**< Read pointer for consumer in bytes */ 6386 uint32_t wrpt; /**< Write pointer for producer in bytes */ 6387 uint32_t capacity; /**< Ringbuffer capacity in bytes */ 6388 6389 void *ctx; /**< Caller provided context pointer */ 6390 void *dmub; /**< Pointer to the DMUB interface */ 6391 }; 6392 6393 /** 6394 * @brief Checks if the ringbuffer is empty. 6395 * 6396 * @param rb DMUB Ringbuffer 6397 * @return true if empty 6398 * @return false otherwise 6399 */ 6400 static inline bool dmub_rb_empty(struct dmub_rb *rb) 6401 { 6402 return (rb->wrpt == rb->rptr); 6403 } 6404 6405 /** 6406 * @brief gets number of outstanding requests in the RB 6407 * 6408 * @param rb DMUB Ringbuffer 6409 * @return true if full 6410 */ 6411 static inline uint32_t dmub_rb_num_outstanding(struct dmub_rb *rb) 6412 { 6413 uint32_t data_count; 6414 6415 if (rb->wrpt >= rb->rptr) 6416 data_count = rb->wrpt - rb->rptr; 6417 else 6418 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6419 6420 return data_count / DMUB_RB_CMD_SIZE; 6421 } 6422 6423 /** 6424 * @brief gets number of free buffers in the RB 6425 * 6426 * @param rb DMUB Ringbuffer 6427 * @return true if full 6428 */ 6429 static inline uint32_t dmub_rb_num_free(struct dmub_rb *rb) 6430 { 6431 uint32_t data_count; 6432 6433 if (rb->wrpt >= rb->rptr) 6434 data_count = rb->wrpt - rb->rptr; 6435 else 6436 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6437 6438 /* +1 because 1 entry is always unusable */ 6439 data_count += DMUB_RB_CMD_SIZE; 6440 6441 return (rb->capacity - data_count) / DMUB_RB_CMD_SIZE; 6442 } 6443 6444 /** 6445 * @brief Checks if the ringbuffer is full 6446 * 6447 * @param rb DMUB Ringbuffer 6448 * @return true if full 6449 * @return false otherwise 6450 */ 6451 static inline bool dmub_rb_full(struct dmub_rb *rb) 6452 { 6453 uint32_t data_count; 6454 6455 if (rb->wrpt >= rb->rptr) 6456 data_count = rb->wrpt - rb->rptr; 6457 else 6458 data_count = rb->capacity - (rb->rptr - rb->wrpt); 6459 6460 /* -1 because 1 entry is always unusable */ 6461 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE)); 6462 } 6463 6464 /** 6465 * @brief Pushes a command into the ringbuffer 6466 * 6467 * @param rb DMUB ringbuffer 6468 * @param cmd The command to push 6469 * @return true if the ringbuffer was not full 6470 * @return false otherwise 6471 */ 6472 static inline bool dmub_rb_push_front(struct dmub_rb *rb, 6473 const union dmub_rb_cmd *cmd) 6474 { 6475 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt); 6476 const uint64_t *src = (const uint64_t *)cmd; 6477 uint8_t i; 6478 6479 if (dmub_rb_full(rb)) 6480 return false; 6481 6482 // copying data 6483 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6484 *dst++ = *src++; 6485 6486 rb->wrpt += DMUB_RB_CMD_SIZE; 6487 6488 if (rb->wrpt >= rb->capacity) 6489 rb->wrpt %= rb->capacity; 6490 6491 return true; 6492 } 6493 6494 /** 6495 * @brief Pushes a command into the DMUB outbox ringbuffer 6496 * 6497 * @param rb DMUB outbox ringbuffer 6498 * @param cmd Outbox command 6499 * @return true if not full 6500 * @return false otherwise 6501 */ 6502 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb, 6503 const union dmub_rb_out_cmd *cmd) 6504 { 6505 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt; 6506 const uint8_t *src = (const uint8_t *)cmd; 6507 6508 if (dmub_rb_full(rb)) 6509 return false; 6510 6511 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE); 6512 6513 rb->wrpt += DMUB_RB_CMD_SIZE; 6514 6515 if (rb->wrpt >= rb->capacity) 6516 rb->wrpt %= rb->capacity; 6517 6518 return true; 6519 } 6520 6521 /** 6522 * @brief Returns the next unprocessed command in the ringbuffer. 6523 * 6524 * @param rb DMUB ringbuffer 6525 * @param cmd The command to return 6526 * @return true if not empty 6527 * @return false otherwise 6528 */ 6529 static inline bool dmub_rb_front(struct dmub_rb *rb, 6530 union dmub_rb_cmd **cmd) 6531 { 6532 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr; 6533 6534 if (dmub_rb_empty(rb)) 6535 return false; 6536 6537 *cmd = (union dmub_rb_cmd *)rb_cmd; 6538 6539 return true; 6540 } 6541 6542 /** 6543 * @brief Determines the next ringbuffer offset. 6544 * 6545 * @param rb DMUB inbox ringbuffer 6546 * @param num_cmds Number of commands 6547 * @param next_rptr The next offset in the ringbuffer 6548 */ 6549 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb, 6550 uint32_t num_cmds, 6551 uint32_t *next_rptr) 6552 { 6553 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds; 6554 6555 if (*next_rptr >= rb->capacity) 6556 *next_rptr %= rb->capacity; 6557 } 6558 6559 /** 6560 * @brief Returns a pointer to a command in the inbox. 6561 * 6562 * @param rb DMUB inbox ringbuffer 6563 * @param cmd The inbox command to return 6564 * @param rptr The ringbuffer offset 6565 * @return true if not empty 6566 * @return false otherwise 6567 */ 6568 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb, 6569 union dmub_rb_cmd **cmd, 6570 uint32_t rptr) 6571 { 6572 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr; 6573 6574 if (dmub_rb_empty(rb)) 6575 return false; 6576 6577 *cmd = (union dmub_rb_cmd *)rb_cmd; 6578 6579 return true; 6580 } 6581 6582 /** 6583 * @brief Returns the next unprocessed command in the outbox. 6584 * 6585 * @param rb DMUB outbox ringbuffer 6586 * @param cmd The outbox command to return 6587 * @return true if not empty 6588 * @return false otherwise 6589 */ 6590 static inline bool dmub_rb_out_front(struct dmub_rb *rb, 6591 union dmub_rb_out_cmd *cmd) 6592 { 6593 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr); 6594 uint64_t *dst = (uint64_t *)cmd; 6595 uint8_t i; 6596 6597 if (dmub_rb_empty(rb)) 6598 return false; 6599 6600 // copying data 6601 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6602 *dst++ = *src++; 6603 6604 return true; 6605 } 6606 6607 /** 6608 * @brief Removes the front entry in the ringbuffer. 6609 * 6610 * @param rb DMUB ringbuffer 6611 * @return true if the command was removed 6612 * @return false if there were no commands 6613 */ 6614 static inline bool dmub_rb_pop_front(struct dmub_rb *rb) 6615 { 6616 if (dmub_rb_empty(rb)) 6617 return false; 6618 6619 rb->rptr += DMUB_RB_CMD_SIZE; 6620 6621 if (rb->rptr >= rb->capacity) 6622 rb->rptr %= rb->capacity; 6623 6624 return true; 6625 } 6626 6627 /** 6628 * @brief Flushes commands in the ringbuffer to framebuffer memory. 6629 * 6630 * Avoids a race condition where DMCUB accesses memory while 6631 * there are still writes in flight to framebuffer. 6632 * 6633 * @param rb DMUB ringbuffer 6634 */ 6635 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb) 6636 { 6637 uint32_t rptr = rb->rptr; 6638 uint32_t wptr = rb->wrpt; 6639 6640 while (rptr != wptr) { 6641 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr); 6642 uint8_t i; 6643 6644 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++) 6645 (void)READ_ONCE(*data++); 6646 6647 rptr += DMUB_RB_CMD_SIZE; 6648 if (rptr >= rb->capacity) 6649 rptr %= rb->capacity; 6650 } 6651 } 6652 6653 /** 6654 * @brief Initializes a DMCUB ringbuffer 6655 * 6656 * @param rb DMUB ringbuffer 6657 * @param init_params initial configuration for the ringbuffer 6658 */ 6659 static inline void dmub_rb_init(struct dmub_rb *rb, 6660 struct dmub_rb_init_params *init_params) 6661 { 6662 rb->base_address = init_params->base_address; 6663 rb->capacity = init_params->capacity; 6664 rb->rptr = init_params->read_ptr; 6665 rb->wrpt = init_params->write_ptr; 6666 } 6667 6668 /** 6669 * @brief Copies output data from in/out commands into the given command. 6670 * 6671 * @param rb DMUB ringbuffer 6672 * @param cmd Command to copy data into 6673 */ 6674 static inline void dmub_rb_get_return_data(struct dmub_rb *rb, 6675 union dmub_rb_cmd *cmd) 6676 { 6677 // Copy rb entry back into command 6678 uint8_t *rd_ptr = (rb->rptr == 0) ? 6679 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE : 6680 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE; 6681 6682 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); 6683 } 6684 6685 //============================================================================== 6686 //</DMUB_RB>==================================================================== 6687 //============================================================================== 6688 #endif /* _DMUB_CMD_H_ */ 6689